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[mirror_ubuntu-zesty-kernel.git] / drivers / misc / cxl / pci.c
1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
18 #include <linux/of.h>
19 #include <linux/delay.h>
20 #include <asm/opal.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pnv-pci.h>
23 #include <asm/io.h>
24 #include <asm/reg.h>
25
26 #include "cxl.h"
27 #include <misc/cxl.h>
28
29
30 #define CXL_PCI_VSEC_ID 0x1280
31 #define CXL_VSEC_MIN_SIZE 0x80
32
33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43 #define CXL_STATUS_SECOND_PORT 0x80
44 #define CXL_STATUS_MSI_X_FULL 0x40
45 #define CXL_STATUS_MSI_X_SINGLE 0x20
46 #define CXL_STATUS_FLASH_RW 0x08
47 #define CXL_STATUS_FLASH_RO 0x04
48 #define CXL_STATUS_LOADABLE_AFU 0x02
49 #define CXL_STATUS_LOADABLE_PSL 0x01
50 /* If we see these features we won't try to use the card */
51 #define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60 #define CXL_VSEC_PROTOCOL_MASK 0xe0
61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
62 #define CXL_VSEC_PROTOCOL_512TB 0x40
63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
74
75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93 /* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
120
121 static const struct pci_device_id cxl_pci_tbl[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126 { PCI_DEVICE_CLASS(0x120000, ~0), },
127
128 { }
129 };
130 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
131
132
133 /*
134 * Mostly using these wrappers to avoid confusion:
135 * priv 1 is BAR2, while priv 2 is BAR0
136 */
137 static inline resource_size_t p1_base(struct pci_dev *dev)
138 {
139 return pci_resource_start(dev, 2);
140 }
141
142 static inline resource_size_t p1_size(struct pci_dev *dev)
143 {
144 return pci_resource_len(dev, 2);
145 }
146
147 static inline resource_size_t p2_base(struct pci_dev *dev)
148 {
149 return pci_resource_start(dev, 0);
150 }
151
152 static inline resource_size_t p2_size(struct pci_dev *dev)
153 {
154 return pci_resource_len(dev, 0);
155 }
156
157 static int find_cxl_vsec(struct pci_dev *dev)
158 {
159 int vsec = 0;
160 u16 val;
161
162 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
163 pci_read_config_word(dev, vsec + 0x4, &val);
164 if (val == CXL_PCI_VSEC_ID)
165 return vsec;
166 }
167 return 0;
168
169 }
170
171 static void dump_cxl_config_space(struct pci_dev *dev)
172 {
173 int vsec;
174 u32 val;
175
176 dev_info(&dev->dev, "dump_cxl_config_space\n");
177
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
179 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
181 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
183 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
185 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
187 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
189 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
190
191 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
192 p1_base(dev), p1_size(dev));
193 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
194 p2_base(dev), p2_size(dev));
195 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
196 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
197
198 if (!(vsec = find_cxl_vsec(dev)))
199 return;
200
201 #define show_reg(name, what) \
202 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
203
204 pci_read_config_dword(dev, vsec + 0x0, &val);
205 show_reg("Cap ID", (val >> 0) & 0xffff);
206 show_reg("Cap Ver", (val >> 16) & 0xf);
207 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
208 pci_read_config_dword(dev, vsec + 0x4, &val);
209 show_reg("VSEC ID", (val >> 0) & 0xffff);
210 show_reg("VSEC Rev", (val >> 16) & 0xf);
211 show_reg("VSEC Length", (val >> 20) & 0xfff);
212 pci_read_config_dword(dev, vsec + 0x8, &val);
213 show_reg("Num AFUs", (val >> 0) & 0xff);
214 show_reg("Status", (val >> 8) & 0xff);
215 show_reg("Mode Control", (val >> 16) & 0xff);
216 show_reg("Reserved", (val >> 24) & 0xff);
217 pci_read_config_dword(dev, vsec + 0xc, &val);
218 show_reg("PSL Rev", (val >> 0) & 0xffff);
219 show_reg("CAIA Ver", (val >> 16) & 0xffff);
220 pci_read_config_dword(dev, vsec + 0x10, &val);
221 show_reg("Base Image Rev", (val >> 0) & 0xffff);
222 show_reg("Reserved", (val >> 16) & 0x0fff);
223 show_reg("Image Control", (val >> 28) & 0x3);
224 show_reg("Reserved", (val >> 30) & 0x1);
225 show_reg("Image Loaded", (val >> 31) & 0x1);
226
227 pci_read_config_dword(dev, vsec + 0x14, &val);
228 show_reg("Reserved", val);
229 pci_read_config_dword(dev, vsec + 0x18, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x1c, &val);
232 show_reg("Reserved", val);
233
234 pci_read_config_dword(dev, vsec + 0x20, &val);
235 show_reg("AFU Descriptor Offset", val);
236 pci_read_config_dword(dev, vsec + 0x24, &val);
237 show_reg("AFU Descriptor Size", val);
238 pci_read_config_dword(dev, vsec + 0x28, &val);
239 show_reg("Problem State Offset", val);
240 pci_read_config_dword(dev, vsec + 0x2c, &val);
241 show_reg("Problem State Size", val);
242
243 pci_read_config_dword(dev, vsec + 0x30, &val);
244 show_reg("Reserved", val);
245 pci_read_config_dword(dev, vsec + 0x34, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x38, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x3c, &val);
250 show_reg("Reserved", val);
251
252 pci_read_config_dword(dev, vsec + 0x40, &val);
253 show_reg("PSL Programming Port", val);
254 pci_read_config_dword(dev, vsec + 0x44, &val);
255 show_reg("PSL Programming Control", val);
256
257 pci_read_config_dword(dev, vsec + 0x48, &val);
258 show_reg("Reserved", val);
259 pci_read_config_dword(dev, vsec + 0x4c, &val);
260 show_reg("Reserved", val);
261
262 pci_read_config_dword(dev, vsec + 0x50, &val);
263 show_reg("Flash Address Register", val);
264 pci_read_config_dword(dev, vsec + 0x54, &val);
265 show_reg("Flash Size Register", val);
266 pci_read_config_dword(dev, vsec + 0x58, &val);
267 show_reg("Flash Status/Control Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Data Port", val);
270
271 #undef show_reg
272 }
273
274 static void dump_afu_descriptor(struct cxl_afu *afu)
275 {
276 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
277 int i;
278
279 #define show_reg(name, what) \
280 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
281
282 val = AFUD_READ_INFO(afu);
283 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
284 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
285 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
286 show_reg("req_prog_mode", val & 0xffffULL);
287 afu_cr_num = AFUD_NUM_CRS(val);
288
289 val = AFUD_READ(afu, 0x8);
290 show_reg("Reserved", val);
291 val = AFUD_READ(afu, 0x10);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x18);
294 show_reg("Reserved", val);
295
296 val = AFUD_READ_CR(afu);
297 show_reg("Reserved", (val >> (63-7)) & 0xff);
298 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
299 afu_cr_len = AFUD_CR_LEN(val) * 256;
300
301 val = AFUD_READ_CR_OFF(afu);
302 afu_cr_off = val;
303 show_reg("AFU_CR_offset", val);
304
305 val = AFUD_READ_PPPSA(afu);
306 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
307 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
308
309 val = AFUD_READ_PPPSA_OFF(afu);
310 show_reg("PerProcessPSA_offset", val);
311
312 val = AFUD_READ_EB(afu);
313 show_reg("Reserved", (val >> (63-7)) & 0xff);
314 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
315
316 val = AFUD_READ_EB_OFF(afu);
317 show_reg("AFU_EB_offset", val);
318
319 for (i = 0; i < afu_cr_num; i++) {
320 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
321 show_reg("CR Vendor", val & 0xffff);
322 show_reg("CR Device", (val >> 16) & 0xffff);
323 }
324 #undef show_reg
325 }
326
327 #define P8_CAPP_UNIT0_ID 0xBA
328 #define P8_CAPP_UNIT1_ID 0XBE
329 #define P9_CAPP_UNIT0_ID 0xC0
330 #define P9_CAPP_UNIT1_ID 0xE0
331
332 static int get_phb_index(struct device_node *np, u32 *phb_index)
333 {
334 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
335 return -ENODEV;
336 return 0;
337 }
338
339 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
340 {
341 /*
342 * POWER 8:
343 * - For chips other than POWER8NVL, we only have CAPP 0,
344 * irrespective of which PHB is used.
345 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
346 * CAPP 1 is attached to PHB1.
347 */
348 if (cxl_is_power8()) {
349 if (!pvr_version_is(PVR_POWER8NVL))
350 return P8_CAPP_UNIT0_ID;
351
352 if (phb_index == 0)
353 return P8_CAPP_UNIT0_ID;
354
355 if (phb_index == 1)
356 return P8_CAPP_UNIT1_ID;
357 }
358
359 /*
360 * POWER 9:
361 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
362 * PEC1 (PHB1 - PHB2). No capi mode
363 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
364 */
365 if (cxl_is_power9()) {
366 if (phb_index == 0)
367 return P9_CAPP_UNIT0_ID;
368
369 if (phb_index == 3)
370 return P9_CAPP_UNIT1_ID;
371 }
372
373 return 0;
374 }
375
376 static int calc_capp_routing(struct pci_dev *dev, u64 *chipid,
377 u32 *phb_index, u64 *capp_unit_id)
378 {
379 int rc;
380 struct device_node *np;
381 const __be32 *prop;
382
383 if (!(np = pnv_pci_get_phb_node(dev)))
384 return -ENODEV;
385
386 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
387 np = of_get_next_parent(np);
388 if (!np)
389 return -ENODEV;
390
391 *chipid = be32_to_cpup(prop);
392
393 rc = get_phb_index(np, phb_index);
394 if (rc) {
395 pr_err("cxl: invalid phb index\n");
396 return rc;
397 }
398
399 *capp_unit_id = get_capp_unit_id(np, *phb_index);
400 of_node_put(np);
401 if (!*capp_unit_id) {
402 pr_err("cxl: invalid capp unit id\n");
403 return -ENODEV;
404 }
405
406 return 0;
407 }
408
409 static int init_implementation_adapter_regs_psl9(struct cxl *adapter, struct pci_dev *dev)
410 {
411 u64 xsl_dsnctl, psl_fircntl;
412 u64 chipid;
413 u32 phb_index;
414 u64 capp_unit_id;
415 int rc;
416
417 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
418 if (rc)
419 return rc;
420
421 /*
422 * CAPI Identifier bits [0:7]
423 * bit 61:60 MSI bits --> 0
424 * bit 59 TVT selector --> 0
425 */
426
427 /*
428 * Tell XSL where to route data to.
429 * The field chipid should match the PHB CAPI_CMPM register
430 */
431 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
432 xsl_dsnctl |= (capp_unit_id << (63-15));
433
434 /* nMMU_ID Defaults to: b’000001001’*/
435 xsl_dsnctl |= ((u64)0x09 << (63-28));
436
437 if (cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1)) {
438 /*
439 * Used to identify CAPI packets which should be sorted into
440 * the Non-Blocking queues by the PHB. This field should match
441 * the PHB PBL_NBW_CMPM register
442 * nbwind=0x03, bits [57:58], must include capi indicator.
443 * Not supported on P9 DD1.
444 */
445 xsl_dsnctl |= ((u64)0x03 << (63-47));
446
447 /*
448 * Upper 16b address bits of ASB_Notify messages sent to the
449 * system. Need to match the PHB’s ASN Compare/Mask Register.
450 * Not supported on P9 DD1.
451 */
452 xsl_dsnctl |= ((u64)0x04 << (63-55));
453 }
454
455 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
456
457 /* Set fir_cntl to recommended value for production env */
458 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
459 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
460 psl_fircntl |= 0x1ULL; /* ce_thresh */
461 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
462
463 /* vccredits=0x1 pcklat=0x4 */
464 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
465
466 /*
467 * For debugging with trace arrays.
468 * Configure RX trace 0 segmented mode.
469 * Configure CT trace 0 segmented mode.
470 * Configure LA0 trace 0 segmented mode.
471 * Configure LA1 trace 0 segmented mode.
472 */
473 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
474 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
475 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
476 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
477
478 /*
479 * A response to an ASB_Notify request is returned by the
480 * system as an MMIO write to the address defined in
481 * the PSL_TNR_ADDR register
482 */
483 /* PSL_TNR_ADDR */
484
485 /* NORST */
486 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
487
488 /* allocate the apc machines */
489 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
490
491 /* Disable vc dd1 fix */
492 if ((cxl_is_power9() && cpu_has_feature(CPU_FTR_POWER9_DD1)))
493 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
494
495 return 0;
496 }
497
498 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
499 {
500 u64 psl_dsnctl, psl_fircntl;
501 u64 chipid;
502 u32 phb_index;
503 u64 capp_unit_id;
504 int rc;
505
506 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
507 if (rc)
508 return rc;
509
510 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
511 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
512 /* Tell PSL where to route data to */
513 psl_dsnctl |= (chipid << (63-5));
514 psl_dsnctl |= (capp_unit_id << (63-13));
515
516 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
517 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
518 /* snoop write mask */
519 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
520 /* set fir_cntl to recommended value for production env */
521 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
522 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
523 psl_fircntl |= 0x1ULL; /* ce_thresh */
524 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
525 /* for debugging with trace arrays */
526 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
527
528 return 0;
529 }
530
531 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
532 {
533 u64 xsl_dsnctl;
534 u64 chipid;
535 u32 phb_index;
536 u64 capp_unit_id;
537 int rc;
538
539 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
540 if (rc)
541 return rc;
542
543 /* Tell XSL where to route data to */
544 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
545 xsl_dsnctl |= (capp_unit_id << (63-13));
546 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
547
548 return 0;
549 }
550
551 /* PSL & XSL */
552 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
553 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
554 /* For the PSL this is a multiple for 0 < n <= 7: */
555 #define PSL_2048_250MHZ_CYCLES 1
556
557 static void write_timebase_ctrl_psl9(struct cxl *adapter)
558 {
559 cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
560 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
561 }
562
563 static void write_timebase_ctrl_psl8(struct cxl *adapter)
564 {
565 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
566 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
567 }
568
569 /* XSL */
570 #define TBSYNC_ENA (1ULL << 63)
571 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
572 #define XSL_2000_CLOCKS 1
573 #define XSL_4000_CLOCKS 2
574 #define XSL_8000_CLOCKS 3
575
576 static void write_timebase_ctrl_xsl(struct cxl *adapter)
577 {
578 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
579 TBSYNC_ENA |
580 TBSYNC_CAL(3) |
581 TBSYNC_CNT(XSL_4000_CLOCKS));
582 }
583
584 static u64 timebase_read_psl9(struct cxl *adapter)
585 {
586 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
587 }
588
589 static u64 timebase_read_psl8(struct cxl *adapter)
590 {
591 return cxl_p1_read(adapter, CXL_PSL_Timebase);
592 }
593
594 static u64 timebase_read_xsl(struct cxl *adapter)
595 {
596 return cxl_p1_read(adapter, CXL_XSL_Timebase);
597 }
598
599 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
600 {
601 u64 psl_tb;
602 int delta;
603 unsigned int retry = 0;
604 struct device_node *np;
605
606 adapter->psl_timebase_synced = false;
607
608 if (!(np = pnv_pci_get_phb_node(dev)))
609 return;
610
611 /* Do not fail when CAPP timebase sync is not supported by OPAL */
612 of_node_get(np);
613 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
614 of_node_put(np);
615 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
616 return;
617 }
618 of_node_put(np);
619
620 /*
621 * Setup PSL Timebase Control and Status register
622 * with the recommended Timebase Sync Count value
623 */
624 adapter->native->sl_ops->write_timebase_ctrl(adapter);
625
626 /* Enable PSL Timebase */
627 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
628 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
629
630 /* Wait until CORE TB and PSL TB difference <= 16usecs */
631 do {
632 msleep(1);
633 if (retry++ > 5) {
634 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
635 return;
636 }
637 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
638 delta = mftb() - psl_tb;
639 if (delta < 0)
640 delta = -delta;
641 } while (tb_to_ns(delta) > 16000);
642
643 adapter->psl_timebase_synced = true;
644 return;
645 }
646
647 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
648 {
649 return 0;
650 }
651
652 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
653 {
654 /* read/write masks for this slice */
655 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
656 /* APC read/write masks for this slice */
657 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
658 /* for debugging with trace arrays */
659 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
660 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
661
662 return 0;
663 }
664
665 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
666 unsigned int virq)
667 {
668 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
669
670 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
671 }
672
673 int cxl_update_image_control(struct cxl *adapter)
674 {
675 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
676 int rc;
677 int vsec;
678 u8 image_state;
679
680 if (!(vsec = find_cxl_vsec(dev))) {
681 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
682 return -ENODEV;
683 }
684
685 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
686 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
687 return rc;
688 }
689
690 if (adapter->perst_loads_image)
691 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
692 else
693 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
694
695 if (adapter->perst_select_user)
696 image_state |= CXL_VSEC_PERST_SELECT_USER;
697 else
698 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
699
700 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
701 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
702 return rc;
703 }
704
705 return 0;
706 }
707
708 int cxl_pci_alloc_one_irq(struct cxl *adapter)
709 {
710 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
711
712 return pnv_cxl_alloc_hwirqs(dev, 1);
713 }
714
715 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
716 {
717 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
718
719 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
720 }
721
722 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
723 struct cxl *adapter, unsigned int num)
724 {
725 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
726
727 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
728 }
729
730 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
731 struct cxl *adapter)
732 {
733 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
734
735 pnv_cxl_release_hwirq_ranges(irqs, dev);
736 }
737
738 static int setup_cxl_bars(struct pci_dev *dev)
739 {
740 /* Safety check in case we get backported to < 3.17 without M64 */
741 if ((p1_base(dev) < 0x100000000ULL) ||
742 (p2_base(dev) < 0x100000000ULL)) {
743 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
744 return -ENODEV;
745 }
746
747 /*
748 * BAR 4/5 has a special meaning for CXL and must be programmed with a
749 * special value corresponding to the CXL protocol address range.
750 * For POWER 8/9 that means bits 48:49 must be set to 10
751 */
752 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
753 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
754
755 return 0;
756 }
757
758 #ifdef CONFIG_CXL_BIMODAL
759
760 struct cxl_switch_work {
761 struct pci_dev *dev;
762 struct work_struct work;
763 int vsec;
764 int mode;
765 };
766
767 static void switch_card_to_cxl(struct work_struct *work)
768 {
769 struct cxl_switch_work *switch_work =
770 container_of(work, struct cxl_switch_work, work);
771 struct pci_dev *dev = switch_work->dev;
772 struct pci_bus *bus = dev->bus;
773 struct pci_controller *hose = pci_bus_to_host(bus);
774 struct pci_dev *bridge;
775 struct pnv_php_slot *php_slot;
776 unsigned int devfn;
777 u8 val;
778 int rc;
779
780 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
781 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
782 bus_list);
783 if (!bridge) {
784 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
785 goto err_dev_put;
786 }
787
788 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
789 if (!php_slot) {
790 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
791 "information. You may need to upgrade "
792 "skiboot. Aborting.\n");
793 goto err_dev_put;
794 }
795
796 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
797 if (rc) {
798 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
799 goto err_dev_put;
800 }
801 devfn = dev->devfn;
802
803 /* Release the reference obtained in cxl_check_and_switch_mode() */
804 pci_dev_put(dev);
805
806 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
807 pci_lock_rescan_remove();
808 pci_hp_remove_devices(bridge->subordinate);
809 pci_unlock_rescan_remove();
810
811 /* Switch the CXL protocol on the card */
812 if (switch_work->mode == CXL_BIMODE_CXL) {
813 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
814 val &= ~CXL_VSEC_PROTOCOL_MASK;
815 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
816 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
817 if (rc) {
818 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
819 " on real PHB, aborting\n");
820 goto err_free_work;
821 }
822 } else {
823 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
824 goto err_free_work;
825 }
826
827 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
828 if (rc) {
829 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
830 goto err_free_work;
831 }
832
833 /*
834 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
835 * we must wait 100ms after this mode switch before touching PCIe config
836 * space.
837 */
838 msleep(100);
839
840 /*
841 * Hot reset to cause the card to come back in cxl mode. A
842 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
843 * in skiboot, so we use a hot reset instead.
844 *
845 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
846 * guaranteed to sit directly under the root port, and setting the reset
847 * state on a device directly under the root port is equivalent to doing
848 * it on the root port iself.
849 */
850 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
851 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
852 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
853
854 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
855 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
856 if (rc) {
857 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
858 goto err_free_work;
859 }
860
861 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
862 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
863 if (rc) {
864 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
865 goto err_free_work;
866 }
867
868 pci_lock_rescan_remove();
869 pci_hp_add_devices(bridge->subordinate);
870 pci_unlock_rescan_remove();
871
872 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
873 kfree(switch_work);
874 return;
875
876 err_dev_put:
877 /* Release the reference obtained in cxl_check_and_switch_mode() */
878 pci_dev_put(dev);
879 err_free_work:
880 kfree(switch_work);
881 }
882
883 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
884 {
885 struct cxl_switch_work *work;
886 u8 val;
887 int rc;
888
889 if (!cpu_has_feature(CPU_FTR_HVMODE))
890 return -ENODEV;
891
892 if (!vsec) {
893 vsec = find_cxl_vsec(dev);
894 if (!vsec) {
895 dev_info(&dev->dev, "CXL VSEC not found\n");
896 return -ENODEV;
897 }
898 }
899
900 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
901 if (rc) {
902 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
903 return rc;
904 }
905
906 if (mode == CXL_BIMODE_PCI) {
907 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
908 dev_info(&dev->dev, "Card is already in PCI mode\n");
909 return 0;
910 }
911 /*
912 * TODO: Before it's safe to switch the card back to PCI mode
913 * we need to disable the CAPP and make sure any cachelines the
914 * card holds have been flushed out. Needs skiboot support.
915 */
916 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
917 return -EIO;
918 }
919
920 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
921 dev_info(&dev->dev, "Card is already in CXL mode\n");
922 return 0;
923 }
924
925 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
926 "to switch to CXL mode\n");
927
928 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
929 if (!work)
930 return -ENOMEM;
931
932 pci_dev_get(dev);
933 work->dev = dev;
934 work->vsec = vsec;
935 work->mode = mode;
936 INIT_WORK(&work->work, switch_card_to_cxl);
937
938 schedule_work(&work->work);
939
940 /*
941 * We return a failure now to abort the driver init. Once the
942 * link has been cycled and the card is in cxl mode we will
943 * come back (possibly using the generic cxl driver), but
944 * return success as the card should then be in cxl mode.
945 *
946 * TODO: What if the card comes back in PCI mode even after
947 * the switch? Don't want to spin endlessly.
948 */
949 return -EBUSY;
950 }
951 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
952
953 #endif /* CONFIG_CXL_BIMODAL */
954
955 static int setup_cxl_protocol_area(struct pci_dev *dev)
956 {
957 u8 val;
958 int rc;
959 int vsec = find_cxl_vsec(dev);
960
961 if (!vsec) {
962 dev_info(&dev->dev, "CXL VSEC not found\n");
963 return -ENODEV;
964 }
965
966 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
967 if (rc) {
968 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
969 return rc;
970 }
971
972 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
973 dev_err(&dev->dev, "Card not in CAPI mode!\n");
974 return -EIO;
975 }
976
977 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
978 val &= ~CXL_VSEC_PROTOCOL_MASK;
979 val |= CXL_VSEC_PROTOCOL_256TB;
980 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
981 if (rc) {
982 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
983 return rc;
984 }
985 }
986
987 return 0;
988 }
989
990 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
991 {
992 u64 p1n_base, p2n_base, afu_desc;
993 const u64 p1n_size = 0x100;
994 const u64 p2n_size = 0x1000;
995
996 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
997 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
998 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
999 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1000
1001 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1002 goto err;
1003 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1004 goto err1;
1005 if (afu_desc) {
1006 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1007 goto err2;
1008 }
1009
1010 return 0;
1011 err2:
1012 iounmap(afu->p2n_mmio);
1013 err1:
1014 iounmap(afu->native->p1n_mmio);
1015 err:
1016 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1017 return -ENOMEM;
1018 }
1019
1020 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1021 {
1022 if (afu->p2n_mmio) {
1023 iounmap(afu->p2n_mmio);
1024 afu->p2n_mmio = NULL;
1025 }
1026 if (afu->native->p1n_mmio) {
1027 iounmap(afu->native->p1n_mmio);
1028 afu->native->p1n_mmio = NULL;
1029 }
1030 if (afu->native->afu_desc_mmio) {
1031 iounmap(afu->native->afu_desc_mmio);
1032 afu->native->afu_desc_mmio = NULL;
1033 }
1034 }
1035
1036 void cxl_pci_release_afu(struct device *dev)
1037 {
1038 struct cxl_afu *afu = to_cxl_afu(dev);
1039
1040 pr_devel("%s\n", __func__);
1041
1042 idr_destroy(&afu->contexts_idr);
1043 cxl_release_spa(afu);
1044
1045 kfree(afu->native);
1046 kfree(afu);
1047 }
1048
1049 /* Expects AFU struct to have recently been zeroed out */
1050 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1051 {
1052 u64 val;
1053
1054 val = AFUD_READ_INFO(afu);
1055 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1056 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1057 afu->crs_num = AFUD_NUM_CRS(val);
1058
1059 if (AFUD_AFU_DIRECTED(val))
1060 afu->modes_supported |= CXL_MODE_DIRECTED;
1061 if (AFUD_DEDICATED_PROCESS(val))
1062 afu->modes_supported |= CXL_MODE_DEDICATED;
1063 if (AFUD_TIME_SLICED(val))
1064 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1065
1066 val = AFUD_READ_PPPSA(afu);
1067 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1068 afu->psa = AFUD_PPPSA_PSA(val);
1069 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1070 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1071
1072 val = AFUD_READ_CR(afu);
1073 afu->crs_len = AFUD_CR_LEN(val) * 256;
1074 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1075
1076
1077 /* eb_len is in multiple of 4K */
1078 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1079 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1080
1081 /* eb_off is 4K aligned so lower 12 bits are always zero */
1082 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1083 dev_warn(&afu->dev,
1084 "Invalid AFU error buffer offset %Lx\n",
1085 afu->eb_offset);
1086 dev_info(&afu->dev,
1087 "Ignoring AFU error buffer in the descriptor\n");
1088 /* indicate that no afu buffer exists */
1089 afu->eb_len = 0;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1096 {
1097 int i, rc;
1098 u32 val;
1099
1100 if (afu->psa && afu->adapter->ps_size <
1101 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1102 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1103 return -ENODEV;
1104 }
1105
1106 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1107 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1108
1109 for (i = 0; i < afu->crs_num; i++) {
1110 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1111 if (rc || val == 0) {
1112 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1113 return -EINVAL;
1114 }
1115 }
1116
1117 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1118 /*
1119 * We could also check this for the dedicated process model
1120 * since the architecture indicates it should be set to 1, but
1121 * in that case we ignore the value and I'd rather not risk
1122 * breaking any existing dedicated process AFUs that left it as
1123 * 0 (not that I'm aware of any). It is clearly an error for an
1124 * AFU directed AFU to set this to 0, and would have previously
1125 * triggered a bug resulting in the maximum not being enforced
1126 * at all since idr_alloc treats 0 as no maximum.
1127 */
1128 dev_err(&afu->dev, "AFU does not support any processes\n");
1129 return -EINVAL;
1130 }
1131
1132 return 0;
1133 }
1134
1135 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1136 {
1137 u64 reg;
1138
1139 /*
1140 * Clear out any regs that contain either an IVTE or address or may be
1141 * waiting on an acknowledgment to try to be a bit safer as we bring
1142 * it online
1143 */
1144 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1145 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1146 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1147 if (cxl_ops->afu_reset(afu))
1148 return -EIO;
1149 if (cxl_afu_disable(afu))
1150 return -EIO;
1151 if (cxl_psl_purge(afu))
1152 return -EIO;
1153 }
1154 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1155 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1156 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1157 if (reg) {
1158 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1159 if (reg & CXL_PSL9_DSISR_An_TF)
1160 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1161 else
1162 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1163 }
1164 if (afu->adapter->native->sl_ops->register_serr_irq) {
1165 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1166 if (reg) {
1167 if (reg & ~0x000000007fffffff)
1168 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1169 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1170 }
1171 }
1172 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1173 if (reg) {
1174 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1175 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1176 }
1177
1178 return 0;
1179 }
1180
1181 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1182 {
1183 u64 reg;
1184
1185 /*
1186 * Clear out any regs that contain either an IVTE or address or may be
1187 * waiting on an acknowledgement to try to be a bit safer as we bring
1188 * it online
1189 */
1190 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1191 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1192 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1193 if (cxl_ops->afu_reset(afu))
1194 return -EIO;
1195 if (cxl_afu_disable(afu))
1196 return -EIO;
1197 if (cxl_psl_purge(afu))
1198 return -EIO;
1199 }
1200 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1201 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1202 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1203 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1204 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1205 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1206 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1207 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1208 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1209 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1210 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1211 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1212 if (reg) {
1213 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1214 if (reg & CXL_PSL_DSISR_TRANS)
1215 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1216 else
1217 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1218 }
1219 if (afu->adapter->native->sl_ops->register_serr_irq) {
1220 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1221 if (reg) {
1222 if (reg & ~0xffff)
1223 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1224 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1225 }
1226 }
1227 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1228 if (reg) {
1229 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1230 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1231 }
1232
1233 return 0;
1234 }
1235
1236 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1237 /*
1238 * afu_eb_read:
1239 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1240 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1241 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1242 */
1243 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1244 loff_t off, size_t count)
1245 {
1246 loff_t aligned_start, aligned_end;
1247 size_t aligned_length;
1248 void *tbuf;
1249 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1250
1251 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1252 return 0;
1253
1254 /* calculate aligned read window */
1255 count = min((size_t)(afu->eb_len - off), count);
1256 aligned_start = round_down(off, 8);
1257 aligned_end = round_up(off + count, 8);
1258 aligned_length = aligned_end - aligned_start;
1259
1260 /* max we can copy in one read is PAGE_SIZE */
1261 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1262 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1263 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1264 }
1265
1266 /* use bounce buffer for copy */
1267 tbuf = (void *)__get_free_page(GFP_TEMPORARY);
1268 if (!tbuf)
1269 return -ENOMEM;
1270
1271 /* perform aligned read from the mmio region */
1272 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1273 memcpy(buf, tbuf + (off & 0x7), count);
1274
1275 free_page((unsigned long)tbuf);
1276
1277 return count;
1278 }
1279
1280 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1281 {
1282 int rc;
1283
1284 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1285 return rc;
1286
1287 if (adapter->native->sl_ops->sanitise_afu_regs) {
1288 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1289 if (rc)
1290 goto err1;
1291 }
1292
1293 /* We need to reset the AFU before we can read the AFU descriptor */
1294 if ((rc = cxl_ops->afu_reset(afu)))
1295 goto err1;
1296
1297 if (cxl_verbose)
1298 dump_afu_descriptor(afu);
1299
1300 if ((rc = cxl_read_afu_descriptor(afu)))
1301 goto err1;
1302
1303 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1304 goto err1;
1305
1306 if (adapter->native->sl_ops->afu_regs_init)
1307 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1308 goto err1;
1309
1310 if (adapter->native->sl_ops->register_serr_irq)
1311 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1312 goto err1;
1313
1314 if ((rc = cxl_native_register_psl_irq(afu)))
1315 goto err2;
1316
1317 atomic_set(&afu->configured_state, 0);
1318 return 0;
1319
1320 err2:
1321 if (adapter->native->sl_ops->release_serr_irq)
1322 adapter->native->sl_ops->release_serr_irq(afu);
1323 err1:
1324 pci_unmap_slice_regs(afu);
1325 return rc;
1326 }
1327
1328 static void pci_deconfigure_afu(struct cxl_afu *afu)
1329 {
1330 /*
1331 * It's okay to deconfigure when AFU is already locked, otherwise wait
1332 * until there are no readers
1333 */
1334 if (atomic_read(&afu->configured_state) != -1) {
1335 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1336 schedule();
1337 }
1338 cxl_native_release_psl_irq(afu);
1339 if (afu->adapter->native->sl_ops->release_serr_irq)
1340 afu->adapter->native->sl_ops->release_serr_irq(afu);
1341 pci_unmap_slice_regs(afu);
1342 }
1343
1344 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1345 {
1346 struct cxl_afu *afu;
1347 int rc = -ENOMEM;
1348
1349 afu = cxl_alloc_afu(adapter, slice);
1350 if (!afu)
1351 return -ENOMEM;
1352
1353 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1354 if (!afu->native)
1355 goto err_free_afu;
1356
1357 mutex_init(&afu->native->spa_mutex);
1358
1359 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1360 if (rc)
1361 goto err_free_native;
1362
1363 rc = pci_configure_afu(afu, adapter, dev);
1364 if (rc)
1365 goto err_free_native;
1366
1367 /* Don't care if this fails */
1368 cxl_debugfs_afu_add(afu);
1369
1370 /*
1371 * After we call this function we must not free the afu directly, even
1372 * if it returns an error!
1373 */
1374 if ((rc = cxl_register_afu(afu)))
1375 goto err_put1;
1376
1377 if ((rc = cxl_sysfs_afu_add(afu)))
1378 goto err_put1;
1379
1380 adapter->afu[afu->slice] = afu;
1381
1382 if ((rc = cxl_pci_vphb_add(afu)))
1383 dev_info(&afu->dev, "Can't register vPHB\n");
1384
1385 return 0;
1386
1387 err_put1:
1388 pci_deconfigure_afu(afu);
1389 cxl_debugfs_afu_remove(afu);
1390 device_unregister(&afu->dev);
1391 return rc;
1392
1393 err_free_native:
1394 kfree(afu->native);
1395 err_free_afu:
1396 kfree(afu);
1397 return rc;
1398
1399 }
1400
1401 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1402 {
1403 pr_devel("%s\n", __func__);
1404
1405 if (!afu)
1406 return;
1407
1408 cxl_pci_vphb_remove(afu);
1409 cxl_sysfs_afu_remove(afu);
1410 cxl_debugfs_afu_remove(afu);
1411
1412 spin_lock(&afu->adapter->afu_list_lock);
1413 afu->adapter->afu[afu->slice] = NULL;
1414 spin_unlock(&afu->adapter->afu_list_lock);
1415
1416 cxl_context_detach_all(afu);
1417 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1418
1419 pci_deconfigure_afu(afu);
1420 device_unregister(&afu->dev);
1421 }
1422
1423 int cxl_pci_reset(struct cxl *adapter)
1424 {
1425 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1426 int rc;
1427
1428 if (adapter->perst_same_image) {
1429 dev_warn(&dev->dev,
1430 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1431 return -EINVAL;
1432 }
1433
1434 dev_info(&dev->dev, "CXL reset\n");
1435
1436 /*
1437 * The adapter is about to be reset, so ignore errors.
1438 * Not supported on P9 DD1
1439 */
1440 if ((cxl_is_power8()) ||
1441 ((cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1))))
1442 cxl_data_cache_flush(adapter);
1443
1444 /* pcie_warm_reset requests a fundamental pci reset which includes a
1445 * PERST assert/deassert. PERST triggers a loading of the image
1446 * if "user" or "factory" is selected in sysfs */
1447 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1448 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1449 return rc;
1450 }
1451
1452 return rc;
1453 }
1454
1455 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1456 {
1457 if (pci_request_region(dev, 2, "priv 2 regs"))
1458 goto err1;
1459 if (pci_request_region(dev, 0, "priv 1 regs"))
1460 goto err2;
1461
1462 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1463 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1464
1465 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1466 goto err3;
1467
1468 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1469 goto err4;
1470
1471 return 0;
1472
1473 err4:
1474 iounmap(adapter->native->p1_mmio);
1475 adapter->native->p1_mmio = NULL;
1476 err3:
1477 pci_release_region(dev, 0);
1478 err2:
1479 pci_release_region(dev, 2);
1480 err1:
1481 return -ENOMEM;
1482 }
1483
1484 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1485 {
1486 if (adapter->native->p1_mmio) {
1487 iounmap(adapter->native->p1_mmio);
1488 adapter->native->p1_mmio = NULL;
1489 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1490 }
1491 if (adapter->native->p2_mmio) {
1492 iounmap(adapter->native->p2_mmio);
1493 adapter->native->p2_mmio = NULL;
1494 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1495 }
1496 }
1497
1498 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1499 {
1500 int vsec;
1501 u32 afu_desc_off, afu_desc_size;
1502 u32 ps_off, ps_size;
1503 u16 vseclen;
1504 u8 image_state;
1505
1506 if (!(vsec = find_cxl_vsec(dev))) {
1507 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1508 return -ENODEV;
1509 }
1510
1511 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1512 if (vseclen < CXL_VSEC_MIN_SIZE) {
1513 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1514 return -EINVAL;
1515 }
1516
1517 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1518 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1519 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1520 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1521 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1522 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1523 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1524 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1525 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1526
1527 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1528 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1529 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1530 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1531 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1532
1533 /* Convert everything to bytes, because there is NO WAY I'd look at the
1534 * code a month later and forget what units these are in ;-) */
1535 adapter->native->ps_off = ps_off * 64 * 1024;
1536 adapter->ps_size = ps_size * 64 * 1024;
1537 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1538 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1539
1540 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1541 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1542
1543 return 0;
1544 }
1545
1546 /*
1547 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1548 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1549 * reported. Mask this error in the Uncorrectable Error Mask Register.
1550 *
1551 * The upper nibble of the PSL revision is used to distinguish between
1552 * different cards. The affected ones have it set to 0.
1553 */
1554 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1555 {
1556 int aer;
1557 u32 data;
1558
1559 if (adapter->psl_rev & 0xf000)
1560 return;
1561 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1562 return;
1563 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1564 if (data & PCI_ERR_UNC_MALF_TLP)
1565 if (data & PCI_ERR_UNC_INTN)
1566 return;
1567 data |= PCI_ERR_UNC_MALF_TLP;
1568 data |= PCI_ERR_UNC_INTN;
1569 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1570 }
1571
1572 static bool cxl_compatible_caia_version(struct cxl *adapter)
1573 {
1574 if (cxl_is_power8() && (adapter->caia_major == 1))
1575 return true;
1576
1577 if (cxl_is_power9() && (adapter->caia_major == 2))
1578 return true;
1579
1580 return false;
1581 }
1582
1583 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1584 {
1585 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1586 return -EBUSY;
1587
1588 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1589 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1590 return -EINVAL;
1591 }
1592
1593 if (!cxl_compatible_caia_version(adapter)) {
1594 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1595 adapter->caia_major);
1596 return -ENODEV;
1597 }
1598
1599 if (!adapter->slices) {
1600 /* Once we support dynamic reprogramming we can use the card if
1601 * it supports loadable AFUs */
1602 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1603 return -EINVAL;
1604 }
1605
1606 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1607 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1608 return -EINVAL;
1609 }
1610
1611 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1612 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1613 "available in BAR2: 0x%llx > 0x%llx\n",
1614 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1615 return -EINVAL;
1616 }
1617
1618 return 0;
1619 }
1620
1621 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1622 {
1623 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1624 }
1625
1626 static void cxl_release_adapter(struct device *dev)
1627 {
1628 struct cxl *adapter = to_cxl_adapter(dev);
1629
1630 pr_devel("cxl_release_adapter\n");
1631
1632 cxl_remove_adapter_nr(adapter);
1633
1634 kfree(adapter->native);
1635 kfree(adapter);
1636 }
1637
1638 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1639
1640 static int sanitise_adapter_regs(struct cxl *adapter)
1641 {
1642 int rc = 0;
1643
1644 /* Clear PSL tberror bit by writing 1 to it */
1645 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1646
1647 if (adapter->native->sl_ops->invalidate_all) {
1648 /* do not invalidate ERAT entries when not reloading on PERST */
1649 if (cxl_is_power9() && (adapter->perst_loads_image))
1650 return 0;
1651 rc = adapter->native->sl_ops->invalidate_all(adapter);
1652 }
1653
1654 return rc;
1655 }
1656
1657 /* This should contain *only* operations that can safely be done in
1658 * both creation and recovery.
1659 */
1660 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1661 {
1662 int rc;
1663
1664 adapter->dev.parent = &dev->dev;
1665 adapter->dev.release = cxl_release_adapter;
1666 pci_set_drvdata(dev, adapter);
1667
1668 rc = pci_enable_device(dev);
1669 if (rc) {
1670 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1671 return rc;
1672 }
1673
1674 if ((rc = cxl_read_vsec(adapter, dev)))
1675 return rc;
1676
1677 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1678 return rc;
1679
1680 cxl_fixup_malformed_tlp(adapter, dev);
1681
1682 if ((rc = setup_cxl_bars(dev)))
1683 return rc;
1684
1685 if ((rc = setup_cxl_protocol_area(dev)))
1686 return rc;
1687
1688 if ((rc = cxl_update_image_control(adapter)))
1689 return rc;
1690
1691 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1692 return rc;
1693
1694 if ((rc = sanitise_adapter_regs(adapter)))
1695 goto err;
1696
1697 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1698 goto err;
1699
1700 /* Required for devices using CAPP DMA mode, harmless for others */
1701 pci_set_master(dev);
1702
1703 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1704 goto err;
1705
1706 /* If recovery happened, the last step is to turn on snooping.
1707 * In the non-recovery case this has no effect */
1708 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1709 goto err;
1710
1711 /* Ignore error, adapter init is not dependant on timebase sync */
1712 cxl_setup_psl_timebase(adapter, dev);
1713
1714 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1715 goto err;
1716
1717 /* Release the context lock as adapter is configured */
1718 cxl_adapter_context_unlock(adapter);
1719 return 0;
1720
1721 err:
1722 cxl_unmap_adapter_regs(adapter);
1723 return rc;
1724
1725 }
1726
1727 static void cxl_deconfigure_adapter(struct cxl *adapter)
1728 {
1729 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1730
1731 cxl_native_release_psl_err_irq(adapter);
1732 cxl_unmap_adapter_regs(adapter);
1733
1734 pci_disable_device(pdev);
1735 }
1736
1737 static const struct cxl_service_layer_ops psl9_ops = {
1738 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1739 .invalidate_all = cxl_invalidate_all_psl9,
1740 .afu_regs_init = init_implementation_afu_regs_psl9,
1741 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1742 .register_serr_irq = cxl_native_register_serr_irq,
1743 .release_serr_irq = cxl_native_release_serr_irq,
1744 .handle_interrupt = cxl_irq_psl9,
1745 .fail_irq = cxl_fail_irq_psl,
1746 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1747 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1748 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1749 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1750 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1751 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1752 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1753 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1754 .debugfs_stop_trace = cxl_stop_trace_psl9,
1755 .write_timebase_ctrl = write_timebase_ctrl_psl9,
1756 .timebase_read = timebase_read_psl9,
1757 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1758 .needs_reset_before_disable = true,
1759 };
1760
1761 static const struct cxl_service_layer_ops psl8_ops = {
1762 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1763 .invalidate_all = cxl_invalidate_all_psl8,
1764 .afu_regs_init = init_implementation_afu_regs_psl8,
1765 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1766 .register_serr_irq = cxl_native_register_serr_irq,
1767 .release_serr_irq = cxl_native_release_serr_irq,
1768 .handle_interrupt = cxl_irq_psl8,
1769 .fail_irq = cxl_fail_irq_psl,
1770 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1771 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1772 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1773 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1774 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1775 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1776 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1777 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1778 .debugfs_stop_trace = cxl_stop_trace_psl8,
1779 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1780 .timebase_read = timebase_read_psl8,
1781 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1782 .needs_reset_before_disable = true,
1783 };
1784
1785 static const struct cxl_service_layer_ops xsl_ops = {
1786 .adapter_regs_init = init_implementation_adapter_regs_xsl,
1787 .invalidate_all = cxl_invalidate_all_psl8,
1788 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1789 .handle_interrupt = cxl_irq_psl8,
1790 .fail_irq = cxl_fail_irq_psl,
1791 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1792 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1793 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1794 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1795 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1796 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1797 .timebase_read = timebase_read_xsl,
1798 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1799 };
1800
1801 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1802 {
1803 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1804 /* Mellanox CX-4 */
1805 dev_info(&dev->dev, "Device uses an XSL\n");
1806 adapter->native->sl_ops = &xsl_ops;
1807 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1808 } else {
1809 if (cxl_is_power8()) {
1810 dev_info(&dev->dev, "Device uses a PSL8\n");
1811 adapter->native->sl_ops = &psl8_ops;
1812 } else {
1813 dev_info(&dev->dev, "Device uses a PSL9\n");
1814 adapter->native->sl_ops = &psl9_ops;
1815 }
1816 }
1817 }
1818
1819
1820 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1821 {
1822 struct cxl *adapter;
1823 int rc;
1824
1825 adapter = cxl_alloc_adapter();
1826 if (!adapter)
1827 return ERR_PTR(-ENOMEM);
1828
1829 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1830 if (!adapter->native) {
1831 rc = -ENOMEM;
1832 goto err_release;
1833 }
1834
1835 set_sl_ops(adapter, dev);
1836
1837 /* Set defaults for parameters which need to persist over
1838 * configure/reconfigure
1839 */
1840 adapter->perst_loads_image = true;
1841 adapter->perst_same_image = false;
1842
1843 rc = cxl_configure_adapter(adapter, dev);
1844 if (rc) {
1845 pci_disable_device(dev);
1846 goto err_release;
1847 }
1848
1849 /* Don't care if this one fails: */
1850 cxl_debugfs_adapter_add(adapter);
1851
1852 /*
1853 * After we call this function we must not free the adapter directly,
1854 * even if it returns an error!
1855 */
1856 if ((rc = cxl_register_adapter(adapter)))
1857 goto err_put1;
1858
1859 if ((rc = cxl_sysfs_adapter_add(adapter)))
1860 goto err_put1;
1861
1862 return adapter;
1863
1864 err_put1:
1865 /* This should mirror cxl_remove_adapter, except without the
1866 * sysfs parts
1867 */
1868 cxl_debugfs_adapter_remove(adapter);
1869 cxl_deconfigure_adapter(adapter);
1870 device_unregister(&adapter->dev);
1871 return ERR_PTR(rc);
1872
1873 err_release:
1874 cxl_release_adapter(&adapter->dev);
1875 return ERR_PTR(rc);
1876 }
1877
1878 static void cxl_pci_remove_adapter(struct cxl *adapter)
1879 {
1880 pr_devel("cxl_remove_adapter\n");
1881
1882 cxl_sysfs_adapter_remove(adapter);
1883 cxl_debugfs_adapter_remove(adapter);
1884
1885 /*
1886 * Flush adapter datacache as its about to be removed.
1887 * Not supported on P9 DD1.
1888 */
1889 if ((cxl_is_power8()) ||
1890 ((cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1))))
1891 cxl_data_cache_flush(adapter);
1892
1893 cxl_deconfigure_adapter(adapter);
1894
1895 device_unregister(&adapter->dev);
1896 }
1897
1898 #define CXL_MAX_PCIEX_PARENT 2
1899
1900 static int cxl_slot_is_switched(struct pci_dev *dev)
1901 {
1902 struct device_node *np;
1903 int depth = 0;
1904 const __be32 *prop;
1905
1906 if (!(np = pci_device_to_OF_node(dev))) {
1907 pr_err("cxl: np = NULL\n");
1908 return -ENODEV;
1909 }
1910 of_node_get(np);
1911 while (np) {
1912 np = of_get_next_parent(np);
1913 prop = of_get_property(np, "device_type", NULL);
1914 if (!prop || strcmp((char *)prop, "pciex"))
1915 break;
1916 depth++;
1917 }
1918 of_node_put(np);
1919 return (depth > CXL_MAX_PCIEX_PARENT);
1920 }
1921
1922 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1923 {
1924 if (!cpu_has_feature(CPU_FTR_HVMODE))
1925 return false;
1926
1927 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1928 /*
1929 * CAPP DMA mode is technically supported on regular P8, but
1930 * will EEH if the card attempts to access memory < 4GB, which
1931 * we cannot realistically avoid. We might be able to work
1932 * around the issue, but until then return unsupported:
1933 */
1934 return false;
1935 }
1936
1937 if (cxl_slot_is_switched(dev))
1938 return false;
1939
1940 /*
1941 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1942 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1943 * served basis, which is racy to check from here. If we need to
1944 * support this in future we might need to consider having this
1945 * function effectively reserve it ahead of time.
1946 *
1947 * Currently, the only user of this API is the Mellanox CX4, which is
1948 * only supported on P8NVL due to the above mentioned limitation of
1949 * CAPP DMA mode and therefore does not need to worry about this. If the
1950 * issue with CAPP DMA mode is later worked around on P8 we might need
1951 * to revisit this.
1952 */
1953
1954 return true;
1955 }
1956 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1957
1958
1959 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1960 {
1961 struct cxl *adapter;
1962 int slice;
1963 int rc;
1964
1965 if (cxl_pci_is_vphb_device(dev)) {
1966 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1967 return -ENODEV;
1968 }
1969
1970 if (cxl_slot_is_switched(dev)) {
1971 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1972 return -ENODEV;
1973 }
1974
1975 if (cxl_is_power9() && !radix_enabled()) {
1976 dev_info(&dev->dev, "Only Radix mode supported\n");
1977 return -ENODEV;
1978 }
1979
1980 if (cxl_verbose)
1981 dump_cxl_config_space(dev);
1982
1983 adapter = cxl_pci_init_adapter(dev);
1984 if (IS_ERR(adapter)) {
1985 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1986 return PTR_ERR(adapter);
1987 }
1988
1989 for (slice = 0; slice < adapter->slices; slice++) {
1990 if ((rc = pci_init_afu(adapter, slice, dev))) {
1991 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1992 continue;
1993 }
1994
1995 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1996 if (rc)
1997 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1998 }
1999
2000 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2001 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2002
2003 return 0;
2004 }
2005
2006 static void cxl_remove(struct pci_dev *dev)
2007 {
2008 struct cxl *adapter = pci_get_drvdata(dev);
2009 struct cxl_afu *afu;
2010 int i;
2011
2012 /*
2013 * Lock to prevent someone grabbing a ref through the adapter list as
2014 * we are removing it
2015 */
2016 for (i = 0; i < adapter->slices; i++) {
2017 afu = adapter->afu[i];
2018 cxl_pci_remove_afu(afu);
2019 }
2020 cxl_pci_remove_adapter(adapter);
2021 }
2022
2023 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2024 pci_channel_state_t state)
2025 {
2026 struct pci_dev *afu_dev;
2027 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2028 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2029
2030 /* There should only be one entry, but go through the list
2031 * anyway
2032 */
2033 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2034 if (!afu_dev->driver)
2035 continue;
2036
2037 afu_dev->error_state = state;
2038
2039 if (afu_dev->driver->err_handler)
2040 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2041 state);
2042 /* Disconnect trumps all, NONE trumps NEED_RESET */
2043 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2044 result = PCI_ERS_RESULT_DISCONNECT;
2045 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2046 (result == PCI_ERS_RESULT_NEED_RESET))
2047 result = PCI_ERS_RESULT_NONE;
2048 }
2049 return result;
2050 }
2051
2052 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2053 pci_channel_state_t state)
2054 {
2055 struct cxl *adapter = pci_get_drvdata(pdev);
2056 struct cxl_afu *afu;
2057 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2058 int i;
2059
2060 /* At this point, we could still have an interrupt pending.
2061 * Let's try to get them out of the way before they do
2062 * anything we don't like.
2063 */
2064 schedule();
2065
2066 /* If we're permanently dead, give up. */
2067 if (state == pci_channel_io_perm_failure) {
2068 /* Tell the AFU drivers; but we don't care what they
2069 * say, we're going away.
2070 */
2071 for (i = 0; i < adapter->slices; i++) {
2072 afu = adapter->afu[i];
2073 /* Only participate in EEH if we are on a virtual PHB */
2074 if (afu->phb == NULL)
2075 return PCI_ERS_RESULT_NONE;
2076 cxl_vphb_error_detected(afu, state);
2077 }
2078 return PCI_ERS_RESULT_DISCONNECT;
2079 }
2080
2081 /* Are we reflashing?
2082 *
2083 * If we reflash, we could come back as something entirely
2084 * different, including a non-CAPI card. As such, by default
2085 * we don't participate in the process. We'll be unbound and
2086 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2087 * us!)
2088 *
2089 * However, this isn't the entire story: for reliablity
2090 * reasons, we usually want to reflash the FPGA on PERST in
2091 * order to get back to a more reliable known-good state.
2092 *
2093 * This causes us a bit of a problem: if we reflash we can't
2094 * trust that we'll come back the same - we could have a new
2095 * image and been PERSTed in order to load that
2096 * image. However, most of the time we actually *will* come
2097 * back the same - for example a regular EEH event.
2098 *
2099 * Therefore, we allow the user to assert that the image is
2100 * indeed the same and that we should continue on into EEH
2101 * anyway.
2102 */
2103 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2104 /* TODO take the PHB out of CXL mode */
2105 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2106 return PCI_ERS_RESULT_NONE;
2107 }
2108
2109 /*
2110 * At this point, we want to try to recover. We'll always
2111 * need a complete slot reset: we don't trust any other reset.
2112 *
2113 * Now, we go through each AFU:
2114 * - We send the driver, if bound, an error_detected callback.
2115 * We expect it to clean up, but it can also tell us to give
2116 * up and permanently detach the card. To simplify things, if
2117 * any bound AFU driver doesn't support EEH, we give up on EEH.
2118 *
2119 * - We detach all contexts associated with the AFU. This
2120 * does not free them, but puts them into a CLOSED state
2121 * which causes any the associated files to return useful
2122 * errors to userland. It also unmaps, but does not free,
2123 * any IRQs.
2124 *
2125 * - We clean up our side: releasing and unmapping resources we hold
2126 * so we can wire them up again when the hardware comes back up.
2127 *
2128 * Driver authors should note:
2129 *
2130 * - Any contexts you create in your kernel driver (except
2131 * those associated with anonymous file descriptors) are
2132 * your responsibility to free and recreate. Likewise with
2133 * any attached resources.
2134 *
2135 * - We will take responsibility for re-initialising the
2136 * device context (the one set up for you in
2137 * cxl_pci_enable_device_hook and accessed through
2138 * cxl_get_context). If you've attached IRQs or other
2139 * resources to it, they remains yours to free.
2140 *
2141 * You can call the same functions to release resources as you
2142 * normally would: we make sure that these functions continue
2143 * to work when the hardware is down.
2144 *
2145 * Two examples:
2146 *
2147 * 1) If you normally free all your resources at the end of
2148 * each request, or if you use anonymous FDs, your
2149 * error_detected callback can simply set a flag to tell
2150 * your driver not to start any new calls. You can then
2151 * clear the flag in the resume callback.
2152 *
2153 * 2) If you normally allocate your resources on startup:
2154 * * Set a flag in error_detected as above.
2155 * * Let CXL detach your contexts.
2156 * * In slot_reset, free the old resources and allocate new ones.
2157 * * In resume, clear the flag to allow things to start.
2158 */
2159 for (i = 0; i < adapter->slices; i++) {
2160 afu = adapter->afu[i];
2161
2162 result = cxl_vphb_error_detected(afu, state);
2163
2164 /* Only continue if everyone agrees on NEED_RESET */
2165 if (result != PCI_ERS_RESULT_NEED_RESET)
2166 return result;
2167
2168 cxl_context_detach_all(afu);
2169 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2170 pci_deconfigure_afu(afu);
2171 }
2172 cxl_deconfigure_adapter(adapter);
2173
2174 return result;
2175 }
2176
2177 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2178 {
2179 struct cxl *adapter = pci_get_drvdata(pdev);
2180 struct cxl_afu *afu;
2181 struct cxl_context *ctx;
2182 struct pci_dev *afu_dev;
2183 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2184 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2185 int i;
2186
2187 if (cxl_configure_adapter(adapter, pdev))
2188 goto err;
2189
2190 for (i = 0; i < adapter->slices; i++) {
2191 afu = adapter->afu[i];
2192
2193 if (pci_configure_afu(afu, adapter, pdev))
2194 goto err;
2195
2196 if (cxl_afu_select_best_mode(afu))
2197 goto err;
2198
2199 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2200 /* Reset the device context.
2201 * TODO: make this less disruptive
2202 */
2203 ctx = cxl_get_context(afu_dev);
2204
2205 if (ctx && cxl_release_context(ctx))
2206 goto err;
2207
2208 ctx = cxl_dev_context_init(afu_dev);
2209 if (IS_ERR(ctx))
2210 goto err;
2211
2212 afu_dev->dev.archdata.cxl_ctx = ctx;
2213
2214 if (cxl_ops->afu_check_and_enable(afu))
2215 goto err;
2216
2217 afu_dev->error_state = pci_channel_io_normal;
2218
2219 /* If there's a driver attached, allow it to
2220 * chime in on recovery. Drivers should check
2221 * if everything has come back OK, but
2222 * shouldn't start new work until we call
2223 * their resume function.
2224 */
2225 if (!afu_dev->driver)
2226 continue;
2227
2228 if (afu_dev->driver->err_handler &&
2229 afu_dev->driver->err_handler->slot_reset)
2230 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2231
2232 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2233 result = PCI_ERS_RESULT_DISCONNECT;
2234 }
2235 }
2236 return result;
2237
2238 err:
2239 /* All the bits that happen in both error_detected and cxl_remove
2240 * should be idempotent, so we don't need to worry about leaving a mix
2241 * of unconfigured and reconfigured resources.
2242 */
2243 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2244 return PCI_ERS_RESULT_DISCONNECT;
2245 }
2246
2247 static void cxl_pci_resume(struct pci_dev *pdev)
2248 {
2249 struct cxl *adapter = pci_get_drvdata(pdev);
2250 struct cxl_afu *afu;
2251 struct pci_dev *afu_dev;
2252 int i;
2253
2254 /* Everything is back now. Drivers should restart work now.
2255 * This is not the place to be checking if everything came back up
2256 * properly, because there's no return value: do that in slot_reset.
2257 */
2258 for (i = 0; i < adapter->slices; i++) {
2259 afu = adapter->afu[i];
2260
2261 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2262 if (afu_dev->driver && afu_dev->driver->err_handler &&
2263 afu_dev->driver->err_handler->resume)
2264 afu_dev->driver->err_handler->resume(afu_dev);
2265 }
2266 }
2267 }
2268
2269 static const struct pci_error_handlers cxl_err_handler = {
2270 .error_detected = cxl_pci_error_detected,
2271 .slot_reset = cxl_pci_slot_reset,
2272 .resume = cxl_pci_resume,
2273 };
2274
2275 struct pci_driver cxl_pci_driver = {
2276 .name = "cxl-pci",
2277 .id_table = cxl_pci_tbl,
2278 .probe = cxl_probe,
2279 .remove = cxl_remove,
2280 .shutdown = cxl_remove,
2281 .err_handler = &cxl_err_handler,
2282 };
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