drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hw-me.h"
  24
  25 #include "hbm.h"
  26
  27
  28 /**
  29  * mei_reg_read - Reads 32bit data from the mei device
  30  *
  31  * @dev: the device structure
  32  * @offset: offset from which to read the data
  33  *
  34  * returns register value (u32)
  35  */
  36 static inline u32 mei_reg_read(const struct mei_me_hw *hw,
  37                                unsigned long offset)
  38 {
  39         return ioread32(hw->mem_addr + offset);
  40 }
  41
  42
  43 /**
  44  * mei_reg_write - Writes 32bit data to the mei device
  45  *
  46  * @dev: the device structure
  47  * @offset: offset from which to write the data
  48  * @value: register value to write (u32)
  49  */
  50 static inline void mei_reg_write(const struct mei_me_hw *hw,
  51                                  unsigned long offset, u32 value)
  52 {
  53         iowrite32(value, hw->mem_addr + offset);
  54 }
  55
  56 /**
  57  * mei_mecbrw_read - Reads 32bit data from ME circular buffer
  58  *  read window register
  59  *
  60  * @dev: the device structure
  61  *
  62  * returns ME_CB_RW register value (u32)
  63  */
  64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
  65 {
  66         return mei_reg_read(to_me_hw(dev), ME_CB_RW);
  67 }
  68 /**
  69  * mei_mecsr_read - Reads 32bit data from the ME CSR
  70  *
  71  * @dev: the device structure
  72  *
  73  * returns ME_CSR_HA register value (u32)
  74  */
  75 static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
  76 {
  77         return mei_reg_read(hw, ME_CSR_HA);
  78 }
  79
  80 /**
  81  * mei_hcsr_read - Reads 32bit data from the host CSR
  82  *
  83  * @dev: the device structure
  84  *
  85  * returns H_CSR register value (u32)
  86  */
  87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
  88 {
  89         return mei_reg_read(hw, H_CSR);
  90 }
  91
  92 /**
  93  * mei_hcsr_set - writes H_CSR register to the mei device,
  94  * and ignores the H_IS bit for it is write-one-to-zero.
  95  *
  96  * @dev: the device structure
  97  */
  98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
  99 {
 100         hcsr &= ~H_IS;
 101         mei_reg_write(hw, H_CSR, hcsr);
 102 }
 103
 104
 105 /**
 106  * me_hw_config - configure hw dependent settings
 107  *
 108  * @dev: mei device
 109  */
 110 static void mei_me_hw_config(struct mei_device *dev)
 111 {
 112         u32 hcsr = mei_hcsr_read(to_me_hw(dev));
 113         /* Doesn't change in runtime */
 114         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 115 }
 116 /**
 117  * mei_clear_interrupts - clear and stop interrupts
 118  *
 119  * @dev: the device structure
 120  */
 121 static void mei_me_intr_clear(struct mei_device *dev)
 122 {
 123         struct mei_me_hw *hw = to_me_hw(dev);
 124         u32 hcsr = mei_hcsr_read(hw);
 125         if ((hcsr & H_IS) == H_IS)
 126                 mei_reg_write(hw, H_CSR, hcsr);
 127 }
 128 /**
 129  * mei_me_intr_enable - enables mei device interrupts
 130  *
 131  * @dev: the device structure
 132  */
 133 static void mei_me_intr_enable(struct mei_device *dev)
 134 {
 135         struct mei_me_hw *hw = to_me_hw(dev);
 136         u32 hcsr = mei_hcsr_read(hw);
 137         hcsr |= H_IE;
 138         mei_hcsr_set(hw, hcsr);
 139 }
 140
 141 /**
 142  * mei_disable_interrupts - disables mei device interrupts
 143  *
 144  * @dev: the device structure
 145  */
 146 static void mei_me_intr_disable(struct mei_device *dev)
 147 {
 148         struct mei_me_hw *hw = to_me_hw(dev);
 149         u32 hcsr = mei_hcsr_read(hw);
 150         hcsr  &= ~H_IE;
 151         mei_hcsr_set(hw, hcsr);
 152 }
 153
 154 /**
 155  * mei_me_hw_reset_release - release device from the reset
 156  *
 157  * @dev: the device structure
 158  */
 159 static void mei_me_hw_reset_release(struct mei_device *dev)
 160 {
 161         struct mei_me_hw *hw = to_me_hw(dev);
 162         u32 hcsr = mei_hcsr_read(hw);
 163
 164         hcsr |= H_IG;
 165         hcsr &= ~H_RST;
 166         mei_hcsr_set(hw, hcsr);
 167 }
 168 /**
 169  * mei_me_hw_reset - resets fw via mei csr register.
 170  *
 171  * @dev: the device structure
 172  * @interrupts_enabled: if interrupt should be enabled after reset.
 173  */
 174 static void mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 175 {
 176         struct mei_me_hw *hw = to_me_hw(dev);
 177         u32 hcsr = mei_hcsr_read(hw);
 178
 179         dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
 180
 181         hcsr |= (H_RST | H_IG);
 182
 183         if (intr_enable)
 184                 hcsr |= H_IE;
 185         else
 186                 hcsr |= ~H_IE;
 187
 188         mei_hcsr_set(hw, hcsr);
 189
 190         if (dev->dev_state == MEI_DEV_POWER_DOWN)
 191                 mei_me_hw_reset_release(dev);
 192
 193         dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw));
 194 }
 195
 196 /**
 197  * mei_me_host_set_ready - enable device
 198  *
 199  * @dev - mei device
 200  * returns bool
 201  */
 202
 203 static void mei_me_host_set_ready(struct mei_device *dev)
 204 {
 205         struct mei_me_hw *hw = to_me_hw(dev);
 206         hw->host_hw_state |= H_IE | H_IG | H_RDY;
 207         mei_hcsr_set(hw, hw->host_hw_state);
 208 }
 209 /**
 210  * mei_me_host_is_ready - check whether the host has turned ready
 211  *
 212  * @dev - mei device
 213  * returns bool
 214  */
 215 static bool mei_me_host_is_ready(struct mei_device *dev)
 216 {
 217         struct mei_me_hw *hw = to_me_hw(dev);
 218         hw->host_hw_state = mei_hcsr_read(hw);
 219         return (hw->host_hw_state & H_RDY) == H_RDY;
 220 }
 221
 222 /**
 223  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 224  *
 225  * @dev - mei device
 226  * returns bool
 227  */
 228 static bool mei_me_hw_is_ready(struct mei_device *dev)
 229 {
 230         struct mei_me_hw *hw = to_me_hw(dev);
 231         hw->me_hw_state = mei_mecsr_read(hw);
 232         return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
 233 }
 234
 235 /**
 236  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 237  *
 238  * @dev: the device structure
 239  *
 240  * returns number of filled slots
 241  */
 242 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 243 {
 244         struct mei_me_hw *hw = to_me_hw(dev);
 245         char read_ptr, write_ptr;
 246
 247         hw->host_hw_state = mei_hcsr_read(hw);
 248
 249         read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
 250         write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
 251
 252         return (unsigned char) (write_ptr - read_ptr);
 253 }
 254
 255 /**
 256  * mei_hbuf_is_empty - checks if host buffer is empty.
 257  *
 258  * @dev: the device structure
 259  *
 260  * returns true if empty, false - otherwise.
 261  */
 262 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 263 {
 264         return mei_hbuf_filled_slots(dev) == 0;
 265 }
 266
 267 /**
 268  * mei_me_hbuf_empty_slots - counts write empty slots.
 269  *
 270  * @dev: the device structure
 271  *
 272  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
 273  */
 274 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 275 {
 276         unsigned char filled_slots, empty_slots;
 277
 278         filled_slots = mei_hbuf_filled_slots(dev);
 279         empty_slots = dev->hbuf_depth - filled_slots;
 280
 281         /* check for overflow */
 282         if (filled_slots > dev->hbuf_depth)
 283                 return -EOVERFLOW;
 284
 285         return empty_slots;
 286 }
 287
 288 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 289 {
 290         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 291 }
 292
 293
 294 /**
 295  * mei_write_message - writes a message to mei device.
 296  *
 297  * @dev: the device structure
 298  * @header: mei HECI header of message
 299  * @buf: message payload will be written
 300  *
 301  * This function returns -EIO if write has failed
 302  */
 303 static int mei_me_write_message(struct mei_device *dev,
 304                         struct mei_msg_hdr *header,
 305                         unsigned char *buf)
 306 {
 307         struct mei_me_hw *hw = to_me_hw(dev);
 308         unsigned long rem, dw_cnt;
 309         unsigned long length = header->length;
 310         u32 *reg_buf = (u32 *)buf;
 311         u32 hcsr;
 312         int i;
 313         int empty_slots;
 314
 315         dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 316
 317         empty_slots = mei_hbuf_empty_slots(dev);
 318         dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
 319
 320         dw_cnt = mei_data2slots(length);
 321         if (empty_slots < 0 || dw_cnt > empty_slots)
 322                 return -EIO;
 323
 324         mei_reg_write(hw, H_CB_WW, *((u32 *) header));
 325
 326         for (i = 0; i < length / 4; i++)
 327                 mei_reg_write(hw, H_CB_WW, reg_buf[i]);
 328
 329         rem = length & 0x3;
 330         if (rem > 0) {
 331                 u32 reg = 0;
 332                 memcpy(&reg, &buf[length - rem], rem);
 333                 mei_reg_write(hw, H_CB_WW, reg);
 334         }
 335
 336         hcsr = mei_hcsr_read(hw) | H_IG;
 337         mei_hcsr_set(hw, hcsr);
 338         if (!mei_me_hw_is_ready(dev))
 339                 return -EIO;
 340
 341         return 0;
 342 }
 343
 344 /**
 345  * mei_me_count_full_read_slots - counts read full slots.
 346  *
 347  * @dev: the device structure
 348  *
 349  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
 350  */
 351 static int mei_me_count_full_read_slots(struct mei_device *dev)
 352 {
 353         struct mei_me_hw *hw = to_me_hw(dev);
 354         char read_ptr, write_ptr;
 355         unsigned char buffer_depth, filled_slots;
 356
 357         hw->me_hw_state = mei_mecsr_read(hw);
 358         buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
 359         read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
 360         write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
 361         filled_slots = (unsigned char) (write_ptr - read_ptr);
 362
 363         /* check for overflow */
 364         if (filled_slots > buffer_depth)
 365                 return -EOVERFLOW;
 366
 367         dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
 368         return (int)filled_slots;
 369 }
 370
 371 /**
 372  * mei_me_read_slots - reads a message from mei device.
 373  *
 374  * @dev: the device structure
 375  * @buffer: message buffer will be written
 376  * @buffer_length: message size will be read
 377  */
 378 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 379                     unsigned long buffer_length)
 380 {
 381         struct mei_me_hw *hw = to_me_hw(dev);
 382         u32 *reg_buf = (u32 *)buffer;
 383         u32 hcsr;
 384
 385         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 386                 *reg_buf++ = mei_me_mecbrw_read(dev);
 387
 388         if (buffer_length > 0) {
 389                 u32 reg = mei_me_mecbrw_read(dev);
 390                 memcpy(reg_buf, &reg, buffer_length);
 391         }
 392
 393         hcsr = mei_hcsr_read(hw) | H_IG;
 394         mei_hcsr_set(hw, hcsr);
 395         return 0;
 396 }
 397
 398 /**
 399  * mei_me_irq_quick_handler - The ISR of the MEI device
 400  *
 401  * @irq: The irq number
 402  * @dev_id: pointer to the device structure
 403  *
 404  * returns irqreturn_t
 405  */
 406
 407 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 408 {
 409         struct mei_device *dev = (struct mei_device *) dev_id;
 410         struct mei_me_hw *hw = to_me_hw(dev);
 411         u32 csr_reg = mei_hcsr_read(hw);
 412
 413         if ((csr_reg & H_IS) != H_IS)
 414                 return IRQ_NONE;
 415
 416         /* clear H_IS bit in H_CSR */
 417         mei_reg_write(hw, H_CSR, csr_reg);
 418
 419         return IRQ_WAKE_THREAD;
 420 }
 421
 422 /**
 423  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 424  * processing.
 425  *
 426  * @irq: The irq number
 427  * @dev_id: pointer to the device structure
 428  *
 429  * returns irqreturn_t
 430  *
 431  */
 432 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 433 {
 434         struct mei_device *dev = (struct mei_device *) dev_id;
 435         struct mei_cl_cb complete_list;
 436         struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
 437         struct mei_cl *cl;
 438         s32 slots;
 439         int rets;
 440         bool  bus_message_received;
 441
 442
 443         dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
 444         /* initialize our complete list */
 445         mutex_lock(&dev->device_lock);
 446         mei_io_list_init(&complete_list);
 447
 448         /* Ack the interrupt here
 449          * In case of MSI we don't go through the quick handler */
 450         if (pci_dev_msi_enabled(dev->pdev))
 451                 mei_clear_interrupts(dev);
 452
 453         /* check if ME wants a reset */
 454         if (!mei_hw_is_ready(dev) &&
 455             dev->dev_state != MEI_DEV_RESETING &&
 456             dev->dev_state != MEI_DEV_INITIALIZING) {
 457                 dev_dbg(&dev->pdev->dev, "FW not ready.\n");
 458                 mei_reset(dev, 1);
 459                 mutex_unlock(&dev->device_lock);
 460                 return IRQ_HANDLED;
 461         }
 462
 463         /*  check if we need to start the dev */
 464         if (!mei_host_is_ready(dev)) {
 465                 if (mei_hw_is_ready(dev)) {
 466                         dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
 467
 468                         mei_host_set_ready(dev);
 469
 470                         dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
 471                         /* link is established * start sending messages.  */
 472
 473                         dev->dev_state = MEI_DEV_INIT_CLIENTS;
 474
 475                         mei_hbm_start_req(dev);
 476                         mutex_unlock(&dev->device_lock);
 477                         return IRQ_HANDLED;
 478                 } else {
 479                         dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
 480                         mei_me_hw_reset_release(dev);
 481                         mutex_unlock(&dev->device_lock);
 482                         return IRQ_HANDLED;
 483                 }
 484         }
 485         /* check slots available for reading */
 486         slots = mei_count_full_read_slots(dev);
 487         while (slots > 0) {
 488                 /* we have urgent data to send so break the read */
 489                 if (dev->wr_ext_msg.hdr.length)
 490                         break;
 491                 dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
 492                 dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
 493                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 494                 if (rets)
 495                         goto end;
 496         }
 497         rets = mei_irq_write_handler(dev, &complete_list);
 498 end:
 499         dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
 500         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 501
 502         bus_message_received = false;
 503         if (dev->recvd_msg && waitqueue_active(&dev->wait_recvd_msg)) {
 504                 dev_dbg(&dev->pdev->dev, "received waiting bus message\n");
 505                 bus_message_received = true;
 506         }
 507         mutex_unlock(&dev->device_lock);
 508         if (bus_message_received) {
 509                 dev_dbg(&dev->pdev->dev, "wake up dev->wait_recvd_msg\n");
 510                 wake_up_interruptible(&dev->wait_recvd_msg);
 511                 bus_message_received = false;
 512         }
 513         if (list_empty(&complete_list.list))
 514                 return IRQ_HANDLED;
 515
 516
 517         list_for_each_entry_safe(cb_pos, cb_next, &complete_list.list, list) {
 518                 cl = cb_pos->cl;
 519                 list_del(&cb_pos->list);
 520                 if (cl) {
 521                         if (cl != &dev->iamthif_cl) {
 522                                 dev_dbg(&dev->pdev->dev, "completing call back.\n");
 523                                 mei_irq_complete_handler(cl, cb_pos);
 524                                 cb_pos = NULL;
 525                         } else if (cl == &dev->iamthif_cl) {
 526                                 mei_amthif_complete(dev, cb_pos);
 527                         }
 528                 }
 529         }
 530         return IRQ_HANDLED;
 531 }
 532 static const struct mei_hw_ops mei_me_hw_ops = {
 533
 534         .host_set_ready = mei_me_host_set_ready,
 535         .host_is_ready = mei_me_host_is_ready,
 536
 537         .hw_is_ready = mei_me_hw_is_ready,
 538         .hw_reset = mei_me_hw_reset,
 539         .hw_config  = mei_me_hw_config,
 540
 541         .intr_clear = mei_me_intr_clear,
 542         .intr_enable = mei_me_intr_enable,
 543         .intr_disable = mei_me_intr_disable,
 544
 545         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 546         .hbuf_is_ready = mei_me_hbuf_is_empty,
 547         .hbuf_max_len = mei_me_hbuf_max_len,
 548
 549         .write = mei_me_write_message,
 550
 551         .rdbuf_full_slots = mei_me_count_full_read_slots,
 552         .read_hdr = mei_me_mecbrw_read,
 553         .read = mei_me_read_slots
 554 };
 555
 556 /**
 557  * init_mei_device - allocates and initializes the mei device structure
 558  *
 559  * @pdev: The pci device structure
 560  *
 561  * returns The mei_device_device pointer on success, NULL on failure.
 562  */
 563 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
 564 {
 565         struct mei_device *dev;
 566
 567         dev = kzalloc(sizeof(struct mei_device) +
 568                          sizeof(struct mei_me_hw), GFP_KERNEL);
 569         if (!dev)
 570                 return NULL;
 571
 572         mei_device_init(dev);
 573
 574         INIT_LIST_HEAD(&dev->wd_cl.link);
 575         INIT_LIST_HEAD(&dev->iamthif_cl.link);
 576         mei_io_list_init(&dev->amthif_cmd_list);
 577         mei_io_list_init(&dev->amthif_rd_complete_list);
 578
 579         INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
 580         INIT_WORK(&dev->init_work, mei_host_client_init);
 581
 582         dev->ops = &mei_me_hw_ops;
 583
 584         dev->pdev = pdev;
 585         return dev;
 586 }
 587