1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
16 #include <linux/pm_domain.h>
17 #include <linux/pm_runtime.h>
19 #include <linux/mei.h>
23 #include "hw-me-regs.h"
26 static bool disable_msi
;
27 module_param(disable_msi
, bool, 0);
29 /* mei_pci_tbl - PCI Device ID Table */
30 static const struct pci_device_id mei_me_pci_tbl
[] = {
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ
, MEI_ME_ICH_CFG
)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35
, MEI_ME_ICH_CFG
)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965
, MEI_ME_ICH_CFG
)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965
, MEI_ME_ICH_CFG
)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965
, MEI_ME_ICH_CFG
)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965
, MEI_ME_ICH_CFG
)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35
, MEI_ME_ICH_CFG
)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33
, MEI_ME_ICH_CFG
)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33
, MEI_ME_ICH_CFG
)},
40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38
, MEI_ME_ICH_CFG
)},
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200
, MEI_ME_ICH_CFG
)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6
, MEI_ME_ICH_CFG
)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7
, MEI_ME_ICH_CFG
)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8
, MEI_ME_ICH_CFG
)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9
, MEI_ME_ICH_CFG
)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10
, MEI_ME_ICH_CFG
)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1
, MEI_ME_ICH_CFG
)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2
, MEI_ME_ICH_CFG
)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3
, MEI_ME_ICH_CFG
)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4
, MEI_ME_ICH_CFG
)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1
, MEI_ME_ICH10_CFG
)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2
, MEI_ME_ICH10_CFG
)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3
, MEI_ME_ICH10_CFG
)},
56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4
, MEI_ME_ICH10_CFG
)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1
, MEI_ME_PCH6_CFG
)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2
, MEI_ME_PCH6_CFG
)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1
, MEI_ME_PCH_CPT_PBG_CFG
)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1
, MEI_ME_PCH_CPT_PBG_CFG
)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1
, MEI_ME_PCH7_CFG
)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2
, MEI_ME_PCH7_CFG
)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3
, MEI_ME_PCH7_CFG
)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H
, MEI_ME_PCH8_SPS_4_CFG
)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W
, MEI_ME_PCH8_SPS_4_CFG
)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP
, MEI_ME_PCH8_CFG
)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR
, MEI_ME_PCH8_SPS_4_CFG
)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP
, MEI_ME_PCH8_CFG
)},
70 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2
, MEI_ME_PCH8_CFG
)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT
, MEI_ME_PCH8_CFG
)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2
, MEI_ME_PCH8_CFG
)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3
, MEI_ME_PCH8_ITOUCH_CFG
)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H
, MEI_ME_PCH8_SPS_4_CFG
)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2
, MEI_ME_PCH8_SPS_4_CFG
)},
77 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG
, MEI_ME_PCH12_SPS_4_CFG
)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M
, MEI_ME_PCH8_CFG
)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I
, MEI_ME_PCH8_CFG
)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE
, MEI_ME_PCH8_CFG
)},
84 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK
, MEI_ME_PCH8_CFG
)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP
, MEI_ME_PCH8_CFG
)},
87 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2
, MEI_ME_PCH8_CFG
)},
88 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3
, MEI_ME_PCH8_CFG
)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP
, MEI_ME_PCH12_CFG
)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3
, MEI_ME_PCH8_ITOUCH_CFG
)},
92 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H
, MEI_ME_PCH12_SPS_CFG
)},
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3
, MEI_ME_PCH12_SPS_ITOUCH_CFG
)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP
, MEI_ME_PCH12_CFG
)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3
, MEI_ME_PCH8_ITOUCH_CFG
)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V
, MEI_ME_PCH12_CFG
)},
98 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H
, MEI_ME_PCH12_CFG
)},
99 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3
, MEI_ME_PCH8_ITOUCH_CFG
)},
101 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP
, MEI_ME_PCH12_CFG
)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP
, MEI_ME_PCH15_CFG
)},
104 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H
, MEI_ME_PCH15_SPS_CFG
)},
106 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N
, MEI_ME_PCH15_CFG
)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC
, MEI_ME_PCH15_CFG
)},
109 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4
, MEI_ME_PCH8_CFG
)},
111 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF
, MEI_ME_PCH8_CFG
)},
113 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG
, MEI_ME_PCH15_SPS_CFG
)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S
, MEI_ME_PCH15_CFG
)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP
, MEI_ME_PCH15_CFG
)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P
, MEI_ME_PCH15_CFG
)},
119 /* required last entry */
123 MODULE_DEVICE_TABLE(pci
, mei_me_pci_tbl
);
126 static inline void mei_me_set_pm_domain(struct mei_device
*dev
);
127 static inline void mei_me_unset_pm_domain(struct mei_device
*dev
);
129 static inline void mei_me_set_pm_domain(struct mei_device
*dev
) {}
130 static inline void mei_me_unset_pm_domain(struct mei_device
*dev
) {}
131 #endif /* CONFIG_PM */
133 static int mei_me_read_fws(const struct mei_device
*dev
, int where
, u32
*val
)
135 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
137 return pci_read_config_dword(pdev
, where
, val
);
141 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
143 * @pdev: PCI device structure
144 * @cfg: per generation config
146 * Return: true if ME Interface is valid, false otherwise
148 static bool mei_me_quirk_probe(struct pci_dev
*pdev
,
149 const struct mei_cfg
*cfg
)
151 if (cfg
->quirk_probe
&& cfg
->quirk_probe(pdev
)) {
152 dev_info(&pdev
->dev
, "Device doesn't have valid ME Interface\n");
160 * mei_me_probe - Device Initialization Routine
162 * @pdev: PCI device structure
163 * @ent: entry in kcs_pci_tbl
165 * Return: 0 on success, <0 on failure.
167 static int mei_me_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
169 const struct mei_cfg
*cfg
;
170 struct mei_device
*dev
;
171 struct mei_me_hw
*hw
;
172 unsigned int irqflags
;
175 cfg
= mei_me_get_cfg(ent
->driver_data
);
179 if (!mei_me_quirk_probe(pdev
, cfg
))
183 err
= pcim_enable_device(pdev
);
185 dev_err(&pdev
->dev
, "failed to enable pci device.\n");
188 /* set PCI host mastering */
189 pci_set_master(pdev
);
190 /* pci request regions and mapping IO device memory for mei driver */
191 err
= pcim_iomap_regions(pdev
, BIT(0), KBUILD_MODNAME
);
193 dev_err(&pdev
->dev
, "failed to get pci regions.\n");
197 if (dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) ||
198 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
200 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
202 err
= dma_set_coherent_mask(&pdev
->dev
,
206 dev_err(&pdev
->dev
, "No usable DMA configuration, aborting\n");
210 /* allocates and initializes the mei dev structure */
211 dev
= mei_me_dev_init(&pdev
->dev
, cfg
);
217 hw
->mem_addr
= pcim_iomap_table(pdev
)[0];
218 hw
->read_fws
= mei_me_read_fws
;
221 pci_enable_msi(pdev
);
225 /* request and enable interrupt */
226 irqflags
= pci_dev_msi_enabled(pdev
) ? IRQF_ONESHOT
: IRQF_SHARED
;
228 err
= request_threaded_irq(pdev
->irq
,
229 mei_me_irq_quick_handler
,
230 mei_me_irq_thread_handler
,
231 irqflags
, KBUILD_MODNAME
, dev
);
233 dev_err(&pdev
->dev
, "request_threaded_irq failure. irq = %d\n",
238 if (mei_start(dev
)) {
239 dev_err(&pdev
->dev
, "init hw failure.\n");
244 pm_runtime_set_autosuspend_delay(&pdev
->dev
, MEI_ME_RPM_TIMEOUT
);
245 pm_runtime_use_autosuspend(&pdev
->dev
);
247 err
= mei_register(dev
, &pdev
->dev
);
251 pci_set_drvdata(pdev
, dev
);
254 * MEI requires to resume from runtime suspend mode
255 * in order to perform link reset flow upon system suspend.
257 dev_pm_set_driver_flags(&pdev
->dev
, DPM_FLAG_NO_DIRECT_COMPLETE
);
260 * ME maps runtime suspend/resume to D0i states,
261 * hence we need to go around native PCI runtime service which
262 * eventually brings the device into D3cold/hot state,
263 * but the mei device cannot wake up from D3 unlike from D0i3.
264 * To get around the PCI device native runtime pm,
265 * ME uses runtime pm domain handlers which take precedence
266 * over the driver's pm handlers.
268 mei_me_set_pm_domain(dev
);
270 if (mei_pg_is_enabled(dev
)) {
271 pm_runtime_put_noidle(&pdev
->dev
);
272 if (hw
->d0i3_supported
)
273 pm_runtime_allow(&pdev
->dev
);
276 dev_dbg(&pdev
->dev
, "initialization successful.\n");
283 mei_cancel_work(dev
);
284 mei_disable_interrupts(dev
);
285 free_irq(pdev
->irq
, dev
);
287 dev_err(&pdev
->dev
, "initialization failed.\n");
292 * mei_me_shutdown - Device Removal Routine
294 * @pdev: PCI device structure
296 * mei_me_shutdown is called from the reboot notifier
297 * it's a simplified version of remove so we go down
300 static void mei_me_shutdown(struct pci_dev
*pdev
)
302 struct mei_device
*dev
;
304 dev
= pci_get_drvdata(pdev
);
308 dev_dbg(&pdev
->dev
, "shutdown\n");
311 mei_me_unset_pm_domain(dev
);
313 mei_disable_interrupts(dev
);
314 free_irq(pdev
->irq
, dev
);
318 * mei_me_remove - Device Removal Routine
320 * @pdev: PCI device structure
322 * mei_me_remove is called by the PCI subsystem to alert the driver
323 * that it should release a PCI device.
325 static void mei_me_remove(struct pci_dev
*pdev
)
327 struct mei_device
*dev
;
329 dev
= pci_get_drvdata(pdev
);
333 if (mei_pg_is_enabled(dev
))
334 pm_runtime_get_noresume(&pdev
->dev
);
336 dev_dbg(&pdev
->dev
, "stop\n");
339 mei_me_unset_pm_domain(dev
);
341 mei_disable_interrupts(dev
);
343 free_irq(pdev
->irq
, dev
);
348 #ifdef CONFIG_PM_SLEEP
349 static int mei_me_pci_suspend(struct device
*device
)
351 struct pci_dev
*pdev
= to_pci_dev(device
);
352 struct mei_device
*dev
= pci_get_drvdata(pdev
);
357 dev_dbg(&pdev
->dev
, "suspend\n");
361 mei_disable_interrupts(dev
);
363 free_irq(pdev
->irq
, dev
);
364 pci_disable_msi(pdev
);
369 static int mei_me_pci_resume(struct device
*device
)
371 struct pci_dev
*pdev
= to_pci_dev(device
);
372 struct mei_device
*dev
;
373 unsigned int irqflags
;
376 dev
= pci_get_drvdata(pdev
);
380 pci_enable_msi(pdev
);
382 irqflags
= pci_dev_msi_enabled(pdev
) ? IRQF_ONESHOT
: IRQF_SHARED
;
384 /* request and enable interrupt */
385 err
= request_threaded_irq(pdev
->irq
,
386 mei_me_irq_quick_handler
,
387 mei_me_irq_thread_handler
,
388 irqflags
, KBUILD_MODNAME
, dev
);
391 dev_err(&pdev
->dev
, "request_threaded_irq failed: irq = %d.\n",
396 err
= mei_restart(dev
);
400 /* Start timer if stopped in suspend */
401 schedule_delayed_work(&dev
->timer_work
, HZ
);
405 #endif /* CONFIG_PM_SLEEP */
408 static int mei_me_pm_runtime_idle(struct device
*device
)
410 struct mei_device
*dev
;
412 dev_dbg(device
, "rpm: me: runtime_idle\n");
414 dev
= dev_get_drvdata(device
);
417 if (mei_write_is_idle(dev
))
418 pm_runtime_autosuspend(device
);
423 static int mei_me_pm_runtime_suspend(struct device
*device
)
425 struct mei_device
*dev
;
428 dev_dbg(device
, "rpm: me: runtime suspend\n");
430 dev
= dev_get_drvdata(device
);
434 mutex_lock(&dev
->device_lock
);
436 if (mei_write_is_idle(dev
))
437 ret
= mei_me_pg_enter_sync(dev
);
441 mutex_unlock(&dev
->device_lock
);
443 dev_dbg(device
, "rpm: me: runtime suspend ret=%d\n", ret
);
445 if (ret
&& ret
!= -EAGAIN
)
446 schedule_work(&dev
->reset_work
);
451 static int mei_me_pm_runtime_resume(struct device
*device
)
453 struct mei_device
*dev
;
456 dev_dbg(device
, "rpm: me: runtime resume\n");
458 dev
= dev_get_drvdata(device
);
462 mutex_lock(&dev
->device_lock
);
464 ret
= mei_me_pg_exit_sync(dev
);
466 mutex_unlock(&dev
->device_lock
);
468 dev_dbg(device
, "rpm: me: runtime resume ret = %d\n", ret
);
471 schedule_work(&dev
->reset_work
);
477 * mei_me_set_pm_domain - fill and set pm domain structure for device
481 static inline void mei_me_set_pm_domain(struct mei_device
*dev
)
483 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
485 if (pdev
->dev
.bus
&& pdev
->dev
.bus
->pm
) {
486 dev
->pg_domain
.ops
= *pdev
->dev
.bus
->pm
;
488 dev
->pg_domain
.ops
.runtime_suspend
= mei_me_pm_runtime_suspend
;
489 dev
->pg_domain
.ops
.runtime_resume
= mei_me_pm_runtime_resume
;
490 dev
->pg_domain
.ops
.runtime_idle
= mei_me_pm_runtime_idle
;
492 dev_pm_domain_set(&pdev
->dev
, &dev
->pg_domain
);
497 * mei_me_unset_pm_domain - clean pm domain structure for device
501 static inline void mei_me_unset_pm_domain(struct mei_device
*dev
)
503 /* stop using pm callbacks if any */
504 dev_pm_domain_set(dev
->dev
, NULL
);
507 static const struct dev_pm_ops mei_me_pm_ops
= {
508 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend
,
511 mei_me_pm_runtime_suspend
,
512 mei_me_pm_runtime_resume
,
513 mei_me_pm_runtime_idle
)
516 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
518 #define MEI_ME_PM_OPS NULL
519 #endif /* CONFIG_PM */
521 * PCI driver structure
523 static struct pci_driver mei_me_driver
= {
524 .name
= KBUILD_MODNAME
,
525 .id_table
= mei_me_pci_tbl
,
526 .probe
= mei_me_probe
,
527 .remove
= mei_me_remove
,
528 .shutdown
= mei_me_shutdown
,
529 .driver
.pm
= MEI_ME_PM_OPS
,
530 .driver
.probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
533 module_pci_driver(mei_me_driver
);
535 MODULE_AUTHOR("Intel Corporation");
536 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
537 MODULE_LICENSE("GPL v2");