2 * Host side test driver to test endpoint functionality
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/crc32.h>
21 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/miscdevice.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/random.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/pci_ids.h>
34 #include <linux/pci_regs.h>
36 #include <uapi/linux/pcitest.h>
38 #define DRV_MODULE_NAME "pci-endpoint-test"
40 #define IRQ_TYPE_UNDEFINED -1
41 #define IRQ_TYPE_LEGACY 0
42 #define IRQ_TYPE_MSI 1
43 #define IRQ_TYPE_MSIX 2
45 #define PCI_ENDPOINT_TEST_MAGIC 0x0
47 #define PCI_ENDPOINT_TEST_COMMAND 0x4
48 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
49 #define COMMAND_RAISE_MSI_IRQ BIT(1)
50 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
51 #define COMMAND_READ BIT(3)
52 #define COMMAND_WRITE BIT(4)
53 #define COMMAND_COPY BIT(5)
55 #define PCI_ENDPOINT_TEST_STATUS 0x8
56 #define STATUS_READ_SUCCESS BIT(0)
57 #define STATUS_READ_FAIL BIT(1)
58 #define STATUS_WRITE_SUCCESS BIT(2)
59 #define STATUS_WRITE_FAIL BIT(3)
60 #define STATUS_COPY_SUCCESS BIT(4)
61 #define STATUS_COPY_FAIL BIT(5)
62 #define STATUS_IRQ_RAISED BIT(6)
63 #define STATUS_SRC_ADDR_INVALID BIT(7)
64 #define STATUS_DST_ADDR_INVALID BIT(8)
66 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
67 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
69 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
70 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
72 #define PCI_ENDPOINT_TEST_SIZE 0x1c
73 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
75 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
76 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
78 #define PCI_DEVICE_ID_TI_AM654 0xb00c
80 #define is_am654_pci_dev(pdev) \
81 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
83 static DEFINE_IDA(pci_endpoint_test_ida
);
85 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
89 module_param(no_msi
, bool, 0444);
90 MODULE_PARM_DESC(no_msi
, "Disable MSI interrupt in pci_endpoint_test");
92 static int irq_type
= IRQ_TYPE_MSI
;
93 module_param(irq_type
, int, 0444);
94 MODULE_PARM_DESC(irq_type
, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
105 struct pci_endpoint_test
{
106 struct pci_dev
*pdev
;
108 void __iomem
*bar
[6];
109 struct completion irq_raised
;
112 /* mutex to protect the ioctls */
114 struct miscdevice miscdev
;
115 enum pci_barno test_reg_bar
;
119 struct pci_endpoint_test_data
{
120 enum pci_barno test_reg_bar
;
125 static inline u32
pci_endpoint_test_readl(struct pci_endpoint_test
*test
,
128 return readl(test
->base
+ offset
);
131 static inline void pci_endpoint_test_writel(struct pci_endpoint_test
*test
,
132 u32 offset
, u32 value
)
134 writel(value
, test
->base
+ offset
);
137 static inline u32
pci_endpoint_test_bar_readl(struct pci_endpoint_test
*test
,
140 return readl(test
->bar
[bar
] + offset
);
143 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test
*test
,
144 int bar
, u32 offset
, u32 value
)
146 writel(value
, test
->bar
[bar
] + offset
);
149 static irqreturn_t
pci_endpoint_test_irqhandler(int irq
, void *dev_id
)
151 struct pci_endpoint_test
*test
= dev_id
;
154 reg
= pci_endpoint_test_readl(test
, PCI_ENDPOINT_TEST_STATUS
);
155 if (reg
& STATUS_IRQ_RAISED
) {
156 test
->last_irq
= irq
;
157 complete(&test
->irq_raised
);
158 reg
&= ~STATUS_IRQ_RAISED
;
160 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_STATUS
,
166 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test
*test
)
168 struct pci_dev
*pdev
= test
->pdev
;
170 pci_free_irq_vectors(pdev
);
173 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test
*test
,
177 struct pci_dev
*pdev
= test
->pdev
;
178 struct device
*dev
= &pdev
->dev
;
182 case IRQ_TYPE_LEGACY
:
183 irq
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_LEGACY
);
185 dev_err(dev
, "Failed to get Legacy interrupt\n");
188 irq
= pci_alloc_irq_vectors(pdev
, 1, 32, PCI_IRQ_MSI
);
190 dev_err(dev
, "Failed to get MSI interrupts\n");
193 irq
= pci_alloc_irq_vectors(pdev
, 1, 2048, PCI_IRQ_MSIX
);
195 dev_err(dev
, "Failed to get MSI-X interrupts\n");
198 dev_err(dev
, "Invalid IRQ type selected\n");
205 test
->num_irqs
= irq
;
210 static void pci_endpoint_test_release_irq(struct pci_endpoint_test
*test
)
213 struct pci_dev
*pdev
= test
->pdev
;
214 struct device
*dev
= &pdev
->dev
;
216 for (i
= 0; i
< test
->num_irqs
; i
++)
217 devm_free_irq(dev
, pci_irq_vector(pdev
, i
), test
);
222 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test
*test
)
226 struct pci_dev
*pdev
= test
->pdev
;
227 struct device
*dev
= &pdev
->dev
;
229 for (i
= 0; i
< test
->num_irqs
; i
++) {
230 err
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
),
231 pci_endpoint_test_irqhandler
,
232 IRQF_SHARED
, DRV_MODULE_NAME
, test
);
241 case IRQ_TYPE_LEGACY
:
242 dev_err(dev
, "Failed to request IRQ %d for Legacy\n",
243 pci_irq_vector(pdev
, i
));
246 dev_err(dev
, "Failed to request IRQ %d for MSI %d\n",
247 pci_irq_vector(pdev
, i
),
251 dev_err(dev
, "Failed to request IRQ %d for MSI-X %d\n",
252 pci_irq_vector(pdev
, i
),
260 static bool pci_endpoint_test_bar(struct pci_endpoint_test
*test
,
261 enum pci_barno barno
)
266 struct pci_dev
*pdev
= test
->pdev
;
268 if (!test
->bar
[barno
])
271 size
= pci_resource_len(pdev
, barno
);
273 if (barno
== test
->test_reg_bar
)
276 for (j
= 0; j
< size
; j
+= 4)
277 pci_endpoint_test_bar_writel(test
, barno
, j
, 0xA0A0A0A0);
279 for (j
= 0; j
< size
; j
+= 4) {
280 val
= pci_endpoint_test_bar_readl(test
, barno
, j
);
281 if (val
!= 0xA0A0A0A0)
288 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test
*test
)
292 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_TYPE
,
294 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_NUMBER
, 0);
295 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_COMMAND
,
296 COMMAND_RAISE_LEGACY_IRQ
);
297 val
= wait_for_completion_timeout(&test
->irq_raised
,
298 msecs_to_jiffies(1000));
305 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test
*test
,
306 u16 msi_num
, bool msix
)
309 struct pci_dev
*pdev
= test
->pdev
;
311 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_TYPE
,
312 msix
== false ? IRQ_TYPE_MSI
:
314 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_NUMBER
, msi_num
);
315 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_COMMAND
,
316 msix
== false ? COMMAND_RAISE_MSI_IRQ
:
317 COMMAND_RAISE_MSIX_IRQ
);
318 val
= wait_for_completion_timeout(&test
->irq_raised
,
319 msecs_to_jiffies(1000));
323 if (pci_irq_vector(pdev
, msi_num
- 1) == test
->last_irq
)
329 static bool pci_endpoint_test_copy(struct pci_endpoint_test
*test
, size_t size
)
334 dma_addr_t src_phys_addr
;
335 dma_addr_t dst_phys_addr
;
336 struct pci_dev
*pdev
= test
->pdev
;
337 struct device
*dev
= &pdev
->dev
;
339 dma_addr_t orig_src_phys_addr
;
341 dma_addr_t orig_dst_phys_addr
;
343 size_t alignment
= test
->alignment
;
347 if (size
> SIZE_MAX
- alignment
)
350 if (irq_type
< IRQ_TYPE_LEGACY
|| irq_type
> IRQ_TYPE_MSIX
) {
351 dev_err(dev
, "Invalid IRQ type option\n");
355 orig_src_addr
= dma_alloc_coherent(dev
, size
+ alignment
,
356 &orig_src_phys_addr
, GFP_KERNEL
);
357 if (!orig_src_addr
) {
358 dev_err(dev
, "Failed to allocate source buffer\n");
363 if (alignment
&& !IS_ALIGNED(orig_src_phys_addr
, alignment
)) {
364 src_phys_addr
= PTR_ALIGN(orig_src_phys_addr
, alignment
);
365 offset
= src_phys_addr
- orig_src_phys_addr
;
366 src_addr
= orig_src_addr
+ offset
;
368 src_phys_addr
= orig_src_phys_addr
;
369 src_addr
= orig_src_addr
;
372 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR
,
373 lower_32_bits(src_phys_addr
));
375 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR
,
376 upper_32_bits(src_phys_addr
));
378 get_random_bytes(src_addr
, size
);
379 src_crc32
= crc32_le(~0, src_addr
, size
);
381 orig_dst_addr
= dma_alloc_coherent(dev
, size
+ alignment
,
382 &orig_dst_phys_addr
, GFP_KERNEL
);
383 if (!orig_dst_addr
) {
384 dev_err(dev
, "Failed to allocate destination address\n");
386 goto err_orig_src_addr
;
389 if (alignment
&& !IS_ALIGNED(orig_dst_phys_addr
, alignment
)) {
390 dst_phys_addr
= PTR_ALIGN(orig_dst_phys_addr
, alignment
);
391 offset
= dst_phys_addr
- orig_dst_phys_addr
;
392 dst_addr
= orig_dst_addr
+ offset
;
394 dst_phys_addr
= orig_dst_phys_addr
;
395 dst_addr
= orig_dst_addr
;
398 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_LOWER_DST_ADDR
,
399 lower_32_bits(dst_phys_addr
));
400 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_UPPER_DST_ADDR
,
401 upper_32_bits(dst_phys_addr
));
403 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_SIZE
,
406 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_TYPE
, irq_type
);
407 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_NUMBER
, 1);
408 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_COMMAND
,
411 wait_for_completion(&test
->irq_raised
);
413 dst_crc32
= crc32_le(~0, dst_addr
, size
);
414 if (dst_crc32
== src_crc32
)
417 dma_free_coherent(dev
, size
+ alignment
, orig_dst_addr
,
421 dma_free_coherent(dev
, size
+ alignment
, orig_src_addr
,
428 static bool pci_endpoint_test_write(struct pci_endpoint_test
*test
, size_t size
)
433 dma_addr_t phys_addr
;
434 struct pci_dev
*pdev
= test
->pdev
;
435 struct device
*dev
= &pdev
->dev
;
437 dma_addr_t orig_phys_addr
;
439 size_t alignment
= test
->alignment
;
442 if (size
> SIZE_MAX
- alignment
)
445 if (irq_type
< IRQ_TYPE_LEGACY
|| irq_type
> IRQ_TYPE_MSIX
) {
446 dev_err(dev
, "Invalid IRQ type option\n");
450 orig_addr
= dma_alloc_coherent(dev
, size
+ alignment
, &orig_phys_addr
,
453 dev_err(dev
, "Failed to allocate address\n");
458 if (alignment
&& !IS_ALIGNED(orig_phys_addr
, alignment
)) {
459 phys_addr
= PTR_ALIGN(orig_phys_addr
, alignment
);
460 offset
= phys_addr
- orig_phys_addr
;
461 addr
= orig_addr
+ offset
;
463 phys_addr
= orig_phys_addr
;
467 get_random_bytes(addr
, size
);
469 crc32
= crc32_le(~0, addr
, size
);
470 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_CHECKSUM
,
473 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR
,
474 lower_32_bits(phys_addr
));
475 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR
,
476 upper_32_bits(phys_addr
));
478 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_SIZE
, size
);
480 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_TYPE
, irq_type
);
481 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_NUMBER
, 1);
482 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_COMMAND
,
485 wait_for_completion(&test
->irq_raised
);
487 reg
= pci_endpoint_test_readl(test
, PCI_ENDPOINT_TEST_STATUS
);
488 if (reg
& STATUS_READ_SUCCESS
)
491 dma_free_coherent(dev
, size
+ alignment
, orig_addr
, orig_phys_addr
);
497 static bool pci_endpoint_test_read(struct pci_endpoint_test
*test
, size_t size
)
501 dma_addr_t phys_addr
;
502 struct pci_dev
*pdev
= test
->pdev
;
503 struct device
*dev
= &pdev
->dev
;
505 dma_addr_t orig_phys_addr
;
507 size_t alignment
= test
->alignment
;
510 if (size
> SIZE_MAX
- alignment
)
513 if (irq_type
< IRQ_TYPE_LEGACY
|| irq_type
> IRQ_TYPE_MSIX
) {
514 dev_err(dev
, "Invalid IRQ type option\n");
518 orig_addr
= dma_alloc_coherent(dev
, size
+ alignment
, &orig_phys_addr
,
521 dev_err(dev
, "Failed to allocate destination address\n");
526 if (alignment
&& !IS_ALIGNED(orig_phys_addr
, alignment
)) {
527 phys_addr
= PTR_ALIGN(orig_phys_addr
, alignment
);
528 offset
= phys_addr
- orig_phys_addr
;
529 addr
= orig_addr
+ offset
;
531 phys_addr
= orig_phys_addr
;
535 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_LOWER_DST_ADDR
,
536 lower_32_bits(phys_addr
));
537 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_UPPER_DST_ADDR
,
538 upper_32_bits(phys_addr
));
540 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_SIZE
, size
);
542 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_TYPE
, irq_type
);
543 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_IRQ_NUMBER
, 1);
544 pci_endpoint_test_writel(test
, PCI_ENDPOINT_TEST_COMMAND
,
547 wait_for_completion(&test
->irq_raised
);
549 crc32
= crc32_le(~0, addr
, size
);
550 if (crc32
== pci_endpoint_test_readl(test
, PCI_ENDPOINT_TEST_CHECKSUM
))
553 dma_free_coherent(dev
, size
+ alignment
, orig_addr
, orig_phys_addr
);
558 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test
*test
,
561 struct pci_dev
*pdev
= test
->pdev
;
562 struct device
*dev
= &pdev
->dev
;
564 if (req_irq_type
< IRQ_TYPE_LEGACY
|| req_irq_type
> IRQ_TYPE_MSIX
) {
565 dev_err(dev
, "Invalid IRQ type option\n");
569 if (irq_type
== req_irq_type
)
572 pci_endpoint_test_release_irq(test
);
573 pci_endpoint_test_free_irq_vectors(test
);
575 if (!pci_endpoint_test_alloc_irq_vectors(test
, req_irq_type
))
578 if (!pci_endpoint_test_request_irq(test
))
581 irq_type
= req_irq_type
;
585 pci_endpoint_test_free_irq_vectors(test
);
586 irq_type
= IRQ_TYPE_UNDEFINED
;
590 static long pci_endpoint_test_ioctl(struct file
*file
, unsigned int cmd
,
595 struct pci_endpoint_test
*test
= to_endpoint_test(file
->private_data
);
596 struct pci_dev
*pdev
= test
->pdev
;
598 mutex_lock(&test
->mutex
);
602 if (bar
< 0 || bar
> 5)
604 if (is_am654_pci_dev(pdev
) && bar
== BAR_0
)
606 ret
= pci_endpoint_test_bar(test
, bar
);
608 case PCITEST_LEGACY_IRQ
:
609 ret
= pci_endpoint_test_legacy_irq(test
);
613 ret
= pci_endpoint_test_msi_irq(test
, arg
, cmd
== PCITEST_MSIX
);
616 ret
= pci_endpoint_test_write(test
, arg
);
619 ret
= pci_endpoint_test_read(test
, arg
);
622 ret
= pci_endpoint_test_copy(test
, arg
);
624 case PCITEST_SET_IRQTYPE
:
625 ret
= pci_endpoint_test_set_irq(test
, arg
);
627 case PCITEST_GET_IRQTYPE
:
633 mutex_unlock(&test
->mutex
);
637 static const struct file_operations pci_endpoint_test_fops
= {
638 .owner
= THIS_MODULE
,
639 .unlocked_ioctl
= pci_endpoint_test_ioctl
,
642 static int pci_endpoint_test_probe(struct pci_dev
*pdev
,
643 const struct pci_device_id
*ent
)
650 struct device
*dev
= &pdev
->dev
;
651 struct pci_endpoint_test
*test
;
652 struct pci_endpoint_test_data
*data
;
653 enum pci_barno test_reg_bar
= BAR_0
;
654 struct miscdevice
*misc_device
;
656 if (pci_is_bridge(pdev
))
659 test
= devm_kzalloc(dev
, sizeof(*test
), GFP_KERNEL
);
663 test
->test_reg_bar
= 0;
668 irq_type
= IRQ_TYPE_LEGACY
;
670 data
= (struct pci_endpoint_test_data
*)ent
->driver_data
;
672 test_reg_bar
= data
->test_reg_bar
;
673 test
->test_reg_bar
= test_reg_bar
;
674 test
->alignment
= data
->alignment
;
675 irq_type
= data
->irq_type
;
678 init_completion(&test
->irq_raised
);
679 mutex_init(&test
->mutex
);
681 err
= pci_enable_device(pdev
);
683 dev_err(dev
, "Cannot enable PCI device\n");
687 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
689 dev_err(dev
, "Cannot obtain PCI resources\n");
690 goto err_disable_pdev
;
693 pci_set_master(pdev
);
695 if (!pci_endpoint_test_alloc_irq_vectors(test
, irq_type
))
696 goto err_disable_irq
;
698 if (!pci_endpoint_test_request_irq(test
))
699 goto err_disable_irq
;
701 for (bar
= BAR_0
; bar
<= BAR_5
; bar
++) {
702 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
703 base
= pci_ioremap_bar(pdev
, bar
);
705 dev_err(dev
, "Failed to read BAR%d\n", bar
);
706 WARN_ON(bar
== test_reg_bar
);
708 test
->bar
[bar
] = base
;
712 test
->base
= test
->bar
[test_reg_bar
];
715 dev_err(dev
, "Cannot perform PCI test without BAR%d\n",
720 pci_set_drvdata(pdev
, test
);
722 id
= ida_simple_get(&pci_endpoint_test_ida
, 0, 0, GFP_KERNEL
);
725 dev_err(dev
, "Unable to get id\n");
729 snprintf(name
, sizeof(name
), DRV_MODULE_NAME
".%d", id
);
730 misc_device
= &test
->miscdev
;
731 misc_device
->minor
= MISC_DYNAMIC_MINOR
;
732 misc_device
->name
= kstrdup(name
, GFP_KERNEL
);
733 if (!misc_device
->name
) {
737 misc_device
->fops
= &pci_endpoint_test_fops
,
739 err
= misc_register(misc_device
);
741 dev_err(dev
, "Failed to register device\n");
748 kfree(misc_device
->name
);
751 ida_simple_remove(&pci_endpoint_test_ida
, id
);
754 for (bar
= BAR_0
; bar
<= BAR_5
; bar
++) {
756 pci_iounmap(pdev
, test
->bar
[bar
]);
758 pci_endpoint_test_release_irq(test
);
761 pci_endpoint_test_free_irq_vectors(test
);
762 pci_release_regions(pdev
);
765 pci_disable_device(pdev
);
770 static void pci_endpoint_test_remove(struct pci_dev
*pdev
)
774 struct pci_endpoint_test
*test
= pci_get_drvdata(pdev
);
775 struct miscdevice
*misc_device
= &test
->miscdev
;
777 if (sscanf(misc_device
->name
, DRV_MODULE_NAME
".%d", &id
) != 1)
782 misc_deregister(&test
->miscdev
);
783 kfree(misc_device
->name
);
784 ida_simple_remove(&pci_endpoint_test_ida
, id
);
785 for (bar
= BAR_0
; bar
<= BAR_5
; bar
++) {
787 pci_iounmap(pdev
, test
->bar
[bar
]);
790 pci_endpoint_test_release_irq(test
);
791 pci_endpoint_test_free_irq_vectors(test
);
793 pci_release_regions(pdev
);
794 pci_disable_device(pdev
);
797 static const struct pci_endpoint_test_data am654_data
= {
798 .test_reg_bar
= BAR_2
,
800 .irq_type
= IRQ_TYPE_MSI
,
803 static const struct pci_device_id pci_endpoint_test_tbl
[] = {
804 { PCI_DEVICE(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_DRA74x
) },
805 { PCI_DEVICE(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_DRA72x
) },
806 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE
, 0x81c0) },
807 { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS
, 0xedda) },
808 { PCI_DEVICE(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_AM654
),
809 .driver_data
= (kernel_ulong_t
)&am654_data
813 MODULE_DEVICE_TABLE(pci
, pci_endpoint_test_tbl
);
815 static struct pci_driver pci_endpoint_test_driver
= {
816 .name
= DRV_MODULE_NAME
,
817 .id_table
= pci_endpoint_test_tbl
,
818 .probe
= pci_endpoint_test_probe
,
819 .remove
= pci_endpoint_test_remove
,
821 module_pci_driver(pci_endpoint_test_driver
);
823 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
824 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
825 MODULE_LICENSE("GPL v2");