2 * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/device.h>
42 #include <linux/interrupt.h>
43 #include <linux/dma-mapping.h>
45 #include <linux/mmc/host.h>
46 #include <linux/mmc/protocol.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
51 #include <asm/scatterlist.h>
56 #define DRIVER_NAME "au1xxx-mmc"
58 /* Set this to enable special debugging macros */
59 /* #define MMC_DEBUG */
62 #define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
64 #define DEBUG(fmt, idx, args...)
69 u32 tx_devid
, rx_devid
;
73 } au1xmmc_card_table
[] = {
74 { SD0_BASE
, DSCR_CMD0_SDMS_TX0
, DSCR_CMD0_SDMS_RX0
,
75 BCSR_BOARD_SD0PWR
, BCSR_INT_SD0INSERT
, BCSR_STATUS_SD0WP
},
76 #ifndef CONFIG_MIPS_DB1200
77 { SD1_BASE
, DSCR_CMD0_SDMS_TX1
, DSCR_CMD0_SDMS_RX1
,
78 BCSR_BOARD_DS1PWR
, BCSR_INT_SD1INSERT
, BCSR_STATUS_SD1WP
}
82 #define AU1XMMC_CONTROLLER_COUNT \
83 (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
85 /* This array stores pointers for the hosts (used by the IRQ handler) */
86 struct au1xmmc_host
*au1xmmc_hosts
[AU1XMMC_CONTROLLER_COUNT
];
90 MODULE_PARM(dma
, "i");
91 MODULE_PARM_DESC(dma
, "Use DMA engine for data transfers (0 = disabled)");
94 static inline void IRQ_ON(struct au1xmmc_host
*host
, u32 mask
)
96 u32 val
= au_readl(HOST_CONFIG(host
));
98 au_writel(val
, HOST_CONFIG(host
));
102 static inline void FLUSH_FIFO(struct au1xmmc_host
*host
)
104 u32 val
= au_readl(HOST_CONFIG2(host
));
106 au_writel(val
| SD_CONFIG2_FF
, HOST_CONFIG2(host
));
109 /* SEND_STOP will turn off clock control - this re-enables it */
110 val
&= ~SD_CONFIG2_DF
;
112 au_writel(val
, HOST_CONFIG2(host
));
116 static inline void IRQ_OFF(struct au1xmmc_host
*host
, u32 mask
)
118 u32 val
= au_readl(HOST_CONFIG(host
));
120 au_writel(val
, HOST_CONFIG(host
));
124 static inline void SEND_STOP(struct au1xmmc_host
*host
)
127 /* We know the value of CONFIG2, so avoid a read we don't need */
128 u32 mask
= SD_CONFIG2_EN
;
130 WARN_ON(host
->status
!= HOST_S_DATA
);
131 host
->status
= HOST_S_STOP
;
133 au_writel(mask
| SD_CONFIG2_DF
, HOST_CONFIG2(host
));
136 /* Send the stop commmand */
137 au_writel(STOP_CMD
, HOST_CMD(host
));
140 static void au1xmmc_set_power(struct au1xmmc_host
*host
, int state
)
143 u32 val
= au1xmmc_card_table
[host
->id
].bcsrpwr
;
146 if (state
) bcsr
->board
|= val
;
151 static inline int au1xmmc_card_inserted(struct au1xmmc_host
*host
)
153 return (bcsr
->sig_status
& au1xmmc_card_table
[host
->id
].bcsrstatus
)
157 static inline int au1xmmc_card_readonly(struct au1xmmc_host
*host
)
159 return (bcsr
->status
& au1xmmc_card_table
[host
->id
].wpstatus
)
163 static void au1xmmc_finish_request(struct au1xmmc_host
*host
)
166 struct mmc_request
*mrq
= host
->mrq
;
169 host
->flags
&= HOST_F_ACTIVE
;
175 host
->pio
.offset
= 0;
178 host
->status
= HOST_S_IDLE
;
180 bcsr
->disk_leds
|= (1 << 8);
182 mmc_request_done(host
->mmc
, mrq
);
185 static void au1xmmc_tasklet_finish(unsigned long param
)
187 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) param
;
188 au1xmmc_finish_request(host
);
191 static int au1xmmc_send_command(struct au1xmmc_host
*host
, int wait
,
192 struct mmc_command
*cmd
)
195 u32 mmccmd
= (cmd
->opcode
<< SD_CMD_CI_SHIFT
);
197 switch (mmc_rsp_type(cmd
->flags
)) {
199 mmccmd
|= SD_CMD_RT_1
;
202 mmccmd
|= SD_CMD_RT_1B
;
205 mmccmd
|= SD_CMD_RT_2
;
208 mmccmd
|= SD_CMD_RT_3
;
212 switch(cmd
->opcode
) {
213 case MMC_READ_SINGLE_BLOCK
:
214 case SD_APP_SEND_SCR
:
215 mmccmd
|= SD_CMD_CT_2
;
217 case MMC_READ_MULTIPLE_BLOCK
:
218 mmccmd
|= SD_CMD_CT_4
;
220 case MMC_WRITE_BLOCK
:
221 mmccmd
|= SD_CMD_CT_1
;
224 case MMC_WRITE_MULTIPLE_BLOCK
:
225 mmccmd
|= SD_CMD_CT_3
;
227 case MMC_STOP_TRANSMISSION
:
228 mmccmd
|= SD_CMD_CT_7
;
232 au_writel(cmd
->arg
, HOST_CMDARG(host
));
236 IRQ_OFF(host
, SD_CONFIG_CR
);
238 au_writel((mmccmd
| SD_CMD_GO
), HOST_CMD(host
));
241 /* Wait for the command to go on the line */
244 if (!(au_readl(HOST_CMD(host
)) & SD_CMD_GO
))
248 /* Wait for the command to come back */
251 u32 status
= au_readl(HOST_STATUS(host
));
253 while(!(status
& SD_STATUS_CR
))
254 status
= au_readl(HOST_STATUS(host
));
256 /* Clear the CR status */
257 au_writel(SD_STATUS_CR
, HOST_STATUS(host
));
259 IRQ_ON(host
, SD_CONFIG_CR
);
265 static void au1xmmc_data_complete(struct au1xmmc_host
*host
, u32 status
)
268 struct mmc_request
*mrq
= host
->mrq
;
269 struct mmc_data
*data
;
272 WARN_ON(host
->status
!= HOST_S_DATA
&& host
->status
!= HOST_S_STOP
);
274 if (host
->mrq
== NULL
)
277 data
= mrq
->cmd
->data
;
280 status
= au_readl(HOST_STATUS(host
));
282 /* The transaction is really over when the SD_STATUS_DB bit is clear */
284 while((host
->flags
& HOST_F_XMIT
) && (status
& SD_STATUS_DB
))
285 status
= au_readl(HOST_STATUS(host
));
287 data
->error
= MMC_ERR_NONE
;
288 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
, host
->dma
.dir
);
290 /* Process any errors */
292 crc
= (status
& (SD_STATUS_WC
| SD_STATUS_RC
));
293 if (host
->flags
& HOST_F_XMIT
)
294 crc
|= ((status
& 0x07) == 0x02) ? 0 : 1;
297 data
->error
= MMC_ERR_BADCRC
;
299 /* Clear the CRC bits */
300 au_writel(SD_STATUS_WC
| SD_STATUS_RC
, HOST_STATUS(host
));
302 data
->bytes_xfered
= 0;
304 if (data
->error
== MMC_ERR_NONE
) {
305 if (host
->flags
& HOST_F_DMA
) {
306 u32 chan
= DMA_CHANNEL(host
);
308 chan_tab_t
*c
= *((chan_tab_t
**) chan
);
309 au1x_dma_chan_t
*cp
= c
->chan_ptr
;
310 data
->bytes_xfered
= cp
->ddma_bytecnt
;
314 (data
->blocks
* (1 << data
->blksz_bits
)) -
318 au1xmmc_finish_request(host
);
321 static void au1xmmc_tasklet_data(unsigned long param
)
323 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) param
;
325 u32 status
= au_readl(HOST_STATUS(host
));
326 au1xmmc_data_complete(host
, status
);
329 #define AU1XMMC_MAX_TRANSFER 8
331 static void au1xmmc_send_pio(struct au1xmmc_host
*host
)
334 struct mmc_data
*data
= 0;
335 int sg_len
, max
, count
= 0;
336 unsigned char *sg_ptr
;
338 struct scatterlist
*sg
;
340 data
= host
->mrq
->data
;
342 if (!(host
->flags
& HOST_F_XMIT
))
345 /* This is the pointer to the data buffer */
346 sg
= &data
->sg
[host
->pio
.index
];
347 sg_ptr
= page_address(sg
->page
) + sg
->offset
+ host
->pio
.offset
;
349 /* This is the space left inside the buffer */
350 sg_len
= data
->sg
[host
->pio
.index
].length
- host
->pio
.offset
;
352 /* Check to if we need less then the size of the sg_buffer */
354 max
= (sg_len
> host
->pio
.len
) ? host
->pio
.len
: sg_len
;
355 if (max
> AU1XMMC_MAX_TRANSFER
) max
= AU1XMMC_MAX_TRANSFER
;
357 for(count
= 0; count
< max
; count
++ ) {
360 status
= au_readl(HOST_STATUS(host
));
362 if (!(status
& SD_STATUS_TH
))
367 au_writel((unsigned long) val
, HOST_TXPORT(host
));
371 host
->pio
.len
-= count
;
372 host
->pio
.offset
+= count
;
374 if (count
== sg_len
) {
376 host
->pio
.offset
= 0;
379 if (host
->pio
.len
== 0) {
380 IRQ_OFF(host
, SD_CONFIG_TH
);
382 if (host
->flags
& HOST_F_STOP
)
385 tasklet_schedule(&host
->data_task
);
389 static void au1xmmc_receive_pio(struct au1xmmc_host
*host
)
392 struct mmc_data
*data
= 0;
393 int sg_len
= 0, max
= 0, count
= 0;
394 unsigned char *sg_ptr
= 0;
396 struct scatterlist
*sg
;
398 data
= host
->mrq
->data
;
400 if (!(host
->flags
& HOST_F_RECV
))
405 if (host
->pio
.index
< host
->dma
.len
) {
406 sg
= &data
->sg
[host
->pio
.index
];
407 sg_ptr
= page_address(sg
->page
) + sg
->offset
+ host
->pio
.offset
;
409 /* This is the space left inside the buffer */
410 sg_len
= sg_dma_len(&data
->sg
[host
->pio
.index
]) - host
->pio
.offset
;
412 /* Check to if we need less then the size of the sg_buffer */
413 if (sg_len
< max
) max
= sg_len
;
416 if (max
> AU1XMMC_MAX_TRANSFER
)
417 max
= AU1XMMC_MAX_TRANSFER
;
419 for(count
= 0; count
< max
; count
++ ) {
421 status
= au_readl(HOST_STATUS(host
));
423 if (!(status
& SD_STATUS_NE
))
426 if (status
& SD_STATUS_RC
) {
427 DEBUG("RX CRC Error [%d + %d].\n", host
->id
,
428 host
->pio
.len
, count
);
432 if (status
& SD_STATUS_RO
) {
433 DEBUG("RX Overrun [%d + %d]\n", host
->id
,
434 host
->pio
.len
, count
);
437 else if (status
& SD_STATUS_RU
) {
438 DEBUG("RX Underrun [%d + %d]\n", host
->id
,
439 host
->pio
.len
, count
);
443 val
= au_readl(HOST_RXPORT(host
));
446 *sg_ptr
++ = (unsigned char) (val
& 0xFF);
449 host
->pio
.len
-= count
;
450 host
->pio
.offset
+= count
;
452 if (sg_len
&& count
== sg_len
) {
454 host
->pio
.offset
= 0;
457 if (host
->pio
.len
== 0) {
458 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
459 IRQ_OFF(host
, SD_CONFIG_NE
);
461 if (host
->flags
& HOST_F_STOP
)
464 tasklet_schedule(&host
->data_task
);
468 /* static void au1xmmc_cmd_complete
469 This is called when a command has been completed - grab the response
470 and check for errors. Then start the data transfer if it is indicated.
473 static void au1xmmc_cmd_complete(struct au1xmmc_host
*host
, u32 status
)
476 struct mmc_request
*mrq
= host
->mrq
;
477 struct mmc_command
*cmd
;
484 cmd
->error
= MMC_ERR_NONE
;
486 if (cmd
->flags
& MMC_RSP_PRESENT
) {
487 if (cmd
->flags
& MMC_RSP_136
) {
491 r
[0] = au_readl(host
->iobase
+ SD_RESP3
);
492 r
[1] = au_readl(host
->iobase
+ SD_RESP2
);
493 r
[2] = au_readl(host
->iobase
+ SD_RESP1
);
494 r
[3] = au_readl(host
->iobase
+ SD_RESP0
);
496 /* The CRC is omitted from the response, so really
497 * we only got 120 bytes, but the engine expects
498 * 128 bits, so we have to shift things up
501 for(i
= 0; i
< 4; i
++) {
502 cmd
->resp
[i
] = (r
[i
] & 0x00FFFFFF) << 8;
504 cmd
->resp
[i
] |= (r
[i
+ 1] & 0xFF000000) >> 24;
507 /* Techincally, we should be getting all 48 bits of
508 * the response (SD_RESP1 + SD_RESP2), but because
509 * our response omits the CRC, our data ends up
510 * being shifted 8 bits to the right. In this case,
511 * that means that the OSR data starts at bit 31,
512 * so we can just read RESP0 and return that
514 cmd
->resp
[0] = au_readl(host
->iobase
+ SD_RESP0
);
518 /* Figure out errors */
520 if (status
& (SD_STATUS_SC
| SD_STATUS_WC
| SD_STATUS_RC
))
521 cmd
->error
= MMC_ERR_BADCRC
;
523 trans
= host
->flags
& (HOST_F_XMIT
| HOST_F_RECV
);
525 if (!trans
|| cmd
->error
!= MMC_ERR_NONE
) {
527 IRQ_OFF(host
, SD_CONFIG_TH
| SD_CONFIG_RA
|SD_CONFIG_RF
);
528 tasklet_schedule(&host
->finish_task
);
532 host
->status
= HOST_S_DATA
;
534 if (host
->flags
& HOST_F_DMA
) {
535 u32 channel
= DMA_CHANNEL(host
);
537 /* Start the DMA as soon as the buffer gets something in it */
539 if (host
->flags
& HOST_F_RECV
) {
540 u32 mask
= SD_STATUS_DB
| SD_STATUS_NE
;
542 while((status
& mask
) != mask
)
543 status
= au_readl(HOST_STATUS(host
));
546 au1xxx_dbdma_start(channel
);
550 static void au1xmmc_set_clock(struct au1xmmc_host
*host
, int rate
)
553 unsigned int pbus
= get_au1x00_speed();
554 unsigned int divisor
;
558 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
561 pbus
/= ((au_readl(SYS_POWERCTRL
) & 0x3) + 2);
564 divisor
= ((pbus
/ rate
) / 2) - 1;
566 config
= au_readl(HOST_CONFIG(host
));
568 config
&= ~(SD_CONFIG_DIV
);
569 config
|= (divisor
& SD_CONFIG_DIV
) | SD_CONFIG_DE
;
571 au_writel(config
, HOST_CONFIG(host
));
576 au1xmmc_prepare_data(struct au1xmmc_host
*host
, struct mmc_data
*data
)
579 int datalen
= data
->blocks
* (1 << data
->blksz_bits
);
582 host
->flags
|= HOST_F_DMA
;
584 if (data
->flags
& MMC_DATA_READ
)
585 host
->flags
|= HOST_F_RECV
;
587 host
->flags
|= HOST_F_XMIT
;
590 host
->flags
|= HOST_F_STOP
;
592 host
->dma
.dir
= DMA_BIDIRECTIONAL
;
594 host
->dma
.len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
595 data
->sg_len
, host
->dma
.dir
);
597 if (host
->dma
.len
== 0)
598 return MMC_ERR_TIMEOUT
;
600 au_writel((1 << data
->blksz_bits
) - 1, HOST_BLKSIZE(host
));
602 if (host
->flags
& HOST_F_DMA
) {
604 u32 channel
= DMA_CHANNEL(host
);
606 au1xxx_dbdma_stop(channel
);
608 for(i
= 0; i
< host
->dma
.len
; i
++) {
609 u32 ret
= 0, flags
= DDMA_FLAGS_NOIE
;
610 struct scatterlist
*sg
= &data
->sg
[i
];
611 int sg_len
= sg
->length
;
613 int len
= (datalen
> sg_len
) ? sg_len
: datalen
;
615 if (i
== host
->dma
.len
- 1)
616 flags
= DDMA_FLAGS_IE
;
618 if (host
->flags
& HOST_F_XMIT
){
619 ret
= au1xxx_dbdma_put_source_flags(channel
,
620 (void *) (page_address(sg
->page
) +
625 ret
= au1xxx_dbdma_put_dest_flags(channel
,
626 (void *) (page_address(sg
->page
) +
639 host
->pio
.offset
= 0;
640 host
->pio
.len
= datalen
;
642 if (host
->flags
& HOST_F_XMIT
)
643 IRQ_ON(host
, SD_CONFIG_TH
);
645 IRQ_ON(host
, SD_CONFIG_NE
);
646 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
652 dma_unmap_sg(mmc_dev(host
->mmc
),data
->sg
,data
->sg_len
,host
->dma
.dir
);
653 return MMC_ERR_TIMEOUT
;
656 /* static void au1xmmc_request
657 This actually starts a command or data transaction
660 static void au1xmmc_request(struct mmc_host
* mmc
, struct mmc_request
* mrq
)
663 struct au1xmmc_host
*host
= mmc_priv(mmc
);
664 int ret
= MMC_ERR_NONE
;
666 WARN_ON(irqs_disabled());
667 WARN_ON(host
->status
!= HOST_S_IDLE
);
670 host
->status
= HOST_S_CMD
;
672 bcsr
->disk_leds
&= ~(1 << 8);
676 ret
= au1xmmc_prepare_data(host
, mrq
->data
);
679 if (ret
== MMC_ERR_NONE
)
680 ret
= au1xmmc_send_command(host
, 0, mrq
->cmd
);
682 if (ret
!= MMC_ERR_NONE
) {
683 mrq
->cmd
->error
= ret
;
684 au1xmmc_finish_request(host
);
688 static void au1xmmc_reset_controller(struct au1xmmc_host
*host
)
691 /* Apply the clock */
692 au_writel(SD_ENABLE_CE
, HOST_ENABLE(host
));
695 au_writel(SD_ENABLE_R
| SD_ENABLE_CE
, HOST_ENABLE(host
));
698 au_writel(~0, HOST_STATUS(host
));
701 au_writel(0, HOST_BLKSIZE(host
));
702 au_writel(0x001fffff, HOST_TIMEOUT(host
));
705 au_writel(SD_CONFIG2_EN
, HOST_CONFIG2(host
));
708 au_writel(SD_CONFIG2_EN
| SD_CONFIG2_FF
, HOST_CONFIG2(host
));
711 au_writel(SD_CONFIG2_EN
, HOST_CONFIG2(host
));
714 /* Configure interrupts */
715 au_writel(AU1XMMC_INTERRUPTS
, HOST_CONFIG(host
));
720 static void au1xmmc_set_ios(struct mmc_host
* mmc
, struct mmc_ios
* ios
)
722 struct au1xmmc_host
*host
= mmc_priv(mmc
);
724 DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
725 host
->id
, ios
->power_mode
, ios
->clock
, ios
->vdd
,
728 if (ios
->power_mode
== MMC_POWER_OFF
)
729 au1xmmc_set_power(host
, 0);
730 else if (ios
->power_mode
== MMC_POWER_ON
) {
731 au1xmmc_set_power(host
, 1);
734 if (ios
->clock
&& ios
->clock
!= host
->clock
) {
735 au1xmmc_set_clock(host
, ios
->clock
);
736 host
->clock
= ios
->clock
;
740 static void au1xmmc_dma_callback(int irq
, void *dev_id
, struct pt_regs
*regs
)
742 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) dev_id
;
745 /* Avoid spurious interrupts */
750 if (host
->flags
& HOST_F_STOP
)
753 tasklet_schedule(&host
->data_task
);
756 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
757 #define STATUS_DATA_IN (SD_STATUS_NE)
758 #define STATUS_DATA_OUT (SD_STATUS_TH)
760 static irqreturn_t
au1xmmc_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
766 disable_irq(AU1100_SD_IRQ
);
768 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
769 struct au1xmmc_host
* host
= au1xmmc_hosts
[i
];
772 status
= au_readl(HOST_STATUS(host
));
774 if (host
->mrq
&& (status
& STATUS_TIMEOUT
)) {
775 if (status
& SD_STATUS_RAT
)
776 host
->mrq
->cmd
->error
= MMC_ERR_TIMEOUT
;
778 else if (status
& SD_STATUS_DT
)
779 host
->mrq
->data
->error
= MMC_ERR_TIMEOUT
;
781 /* In PIO mode, interrupts might still be enabled */
782 IRQ_OFF(host
, SD_CONFIG_NE
| SD_CONFIG_TH
);
784 //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
785 tasklet_schedule(&host
->finish_task
);
788 else if (status
& SD_STATUS_DD
) {
790 /* Sometimes we get a DD before a NE in PIO mode */
792 if (!(host
->flags
& HOST_F_DMA
) &&
793 (status
& SD_STATUS_NE
))
794 au1xmmc_receive_pio(host
);
796 au1xmmc_data_complete(host
, status
);
797 //tasklet_schedule(&host->data_task);
801 else if (status
& (SD_STATUS_CR
)) {
802 if (host
->status
== HOST_S_CMD
)
803 au1xmmc_cmd_complete(host
,status
);
805 else if (!(host
->flags
& HOST_F_DMA
)) {
806 if ((host
->flags
& HOST_F_XMIT
) &&
807 (status
& STATUS_DATA_OUT
))
808 au1xmmc_send_pio(host
);
809 else if ((host
->flags
& HOST_F_RECV
) &&
810 (status
& STATUS_DATA_IN
))
811 au1xmmc_receive_pio(host
);
813 else if (status
& 0x203FBC70) {
814 DEBUG("Unhandled status %8.8x\n", host
->id
, status
);
818 au_writel(status
, HOST_STATUS(host
));
824 enable_irq(AU1100_SD_IRQ
);
828 static void au1xmmc_poll_event(unsigned long arg
)
830 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) arg
;
832 int card
= au1xmmc_card_inserted(host
);
833 int controller
= (host
->flags
& HOST_F_ACTIVE
) ? 1 : 0;
835 if (card
!= controller
) {
836 host
->flags
&= ~HOST_F_ACTIVE
;
837 if (card
) host
->flags
|= HOST_F_ACTIVE
;
838 mmc_detect_change(host
->mmc
, 0);
841 if (host
->mrq
!= NULL
) {
842 u32 status
= au_readl(HOST_STATUS(host
));
843 DEBUG("PENDING - %8.8x\n", host
->id
, status
);
846 mod_timer(&host
->timer
, jiffies
+ AU1XMMC_DETECT_TIMEOUT
);
849 static dbdev_tab_t au1xmmc_mem_dbdev
=
851 DSCR_CMD0_ALWAYS
, DEV_FLAGS_ANYUSE
, 0, 8, 0x00000000, 0, 0
854 static void au1xmmc_init_dma(struct au1xmmc_host
*host
)
859 int txid
= au1xmmc_card_table
[host
->id
].tx_devid
;
860 int rxid
= au1xmmc_card_table
[host
->id
].rx_devid
;
862 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
863 of 8 bits. And since devices are shared, we need to create
864 our own to avoid freaking out other devices
867 int memid
= au1xxx_ddma_add_device(&au1xmmc_mem_dbdev
);
869 txchan
= au1xxx_dbdma_chan_alloc(memid
, txid
,
870 au1xmmc_dma_callback
, (void *) host
);
872 rxchan
= au1xxx_dbdma_chan_alloc(rxid
, memid
,
873 au1xmmc_dma_callback
, (void *) host
);
875 au1xxx_dbdma_set_devwidth(txchan
, 8);
876 au1xxx_dbdma_set_devwidth(rxchan
, 8);
878 au1xxx_dbdma_ring_alloc(txchan
, AU1XMMC_DESCRIPTOR_COUNT
);
879 au1xxx_dbdma_ring_alloc(rxchan
, AU1XMMC_DESCRIPTOR_COUNT
);
881 host
->tx_chan
= txchan
;
882 host
->rx_chan
= rxchan
;
885 struct mmc_host_ops au1xmmc_ops
= {
886 .request
= au1xmmc_request
,
887 .set_ios
= au1xmmc_set_ios
,
890 static int au1xmmc_probe(struct device
*dev
)
895 /* THe interrupt is shared among all controllers */
896 ret
= request_irq(AU1100_SD_IRQ
, au1xmmc_irq
, SA_INTERRUPT
, "MMC", 0);
899 printk(DRIVER_NAME
"ERROR: Couldn't get int %d: %d\n",
904 disable_irq(AU1100_SD_IRQ
);
906 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
907 struct mmc_host
*mmc
= mmc_alloc_host(sizeof(struct au1xmmc_host
), dev
);
908 struct au1xmmc_host
*host
= 0;
911 printk(DRIVER_NAME
"ERROR: no mem for host %d\n", i
);
912 au1xmmc_hosts
[i
] = 0;
916 mmc
->ops
= &au1xmmc_ops
;
919 mmc
->f_max
= 24000000;
921 mmc
->max_seg_size
= AU1XMMC_DESCRIPTOR_SIZE
;
922 mmc
->max_phys_segs
= AU1XMMC_DESCRIPTOR_COUNT
;
924 mmc
->ocr_avail
= AU1XMMC_OCR
;
926 host
= mmc_priv(mmc
);
930 host
->iobase
= au1xmmc_card_table
[host
->id
].iobase
;
932 host
->power_mode
= MMC_POWER_OFF
;
934 host
->flags
= au1xmmc_card_inserted(host
) ? HOST_F_ACTIVE
: 0;
935 host
->status
= HOST_S_IDLE
;
937 init_timer(&host
->timer
);
939 host
->timer
.function
= au1xmmc_poll_event
;
940 host
->timer
.data
= (unsigned long) host
;
941 host
->timer
.expires
= jiffies
+ AU1XMMC_DETECT_TIMEOUT
;
943 tasklet_init(&host
->data_task
, au1xmmc_tasklet_data
,
944 (unsigned long) host
);
946 tasklet_init(&host
->finish_task
, au1xmmc_tasklet_finish
,
947 (unsigned long) host
);
949 spin_lock_init(&host
->lock
);
952 au1xmmc_init_dma(host
);
954 au1xmmc_reset_controller(host
);
957 au1xmmc_hosts
[i
] = host
;
959 add_timer(&host
->timer
);
961 printk(KERN_INFO DRIVER_NAME
": MMC Controller %d set up at %8.8X (mode=%s)\n",
962 host
->id
, host
->iobase
, dma
? "dma" : "pio");
965 enable_irq(AU1100_SD_IRQ
);
970 static int au1xmmc_remove(struct device
*dev
)
975 disable_irq(AU1100_SD_IRQ
);
977 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
978 struct au1xmmc_host
*host
= au1xmmc_hosts
[i
];
981 tasklet_kill(&host
->data_task
);
982 tasklet_kill(&host
->finish_task
);
984 del_timer_sync(&host
->timer
);
985 au1xmmc_set_power(host
, 0);
987 mmc_remove_host(host
->mmc
);
989 au1xxx_dbdma_chan_free(host
->tx_chan
);
990 au1xxx_dbdma_chan_free(host
->rx_chan
);
992 au_writel(0x0, HOST_ENABLE(host
));
996 free_irq(AU1100_SD_IRQ
, 0);
1000 static struct device_driver au1xmmc_driver
= {
1001 .name
= DRIVER_NAME
,
1002 .bus
= &platform_bus_type
,
1003 .probe
= au1xmmc_probe
,
1004 .remove
= au1xmmc_remove
,
1009 static int __init
au1xmmc_init(void)
1011 return driver_register(&au1xmmc_driver
);
1014 static void __exit
au1xmmc_exit(void)
1016 driver_unregister(&au1xmmc_driver
);
1019 module_init(au1xmmc_init
);
1020 module_exit(au1xmmc_exit
);
1023 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1024 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1025 MODULE_LICENSE("GPL");