drivers/mmc/host/android-goldfish.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright 2007, Google Inc.
   4  *  Copyright 2012, Intel Inc.
   5  *
   6  *  based on omap.c driver, which was
   7  *  Copyright (C) 2004 Nokia Corporation
   8  *  Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
   9  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
  10  *  Other hacks (DMA, SD, etc) by David Brownell
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/major.h>
  16
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/interrupt.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/fs.h>
  23 #include <linux/errno.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/blkdev.h>
  27 #include <linux/mutex.h>
  28 #include <linux/scatterlist.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sdio.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/card.h>
  33
  34 #include <linux/moduleparam.h>
  35 #include <linux/init.h>
  36 #include <linux/ioport.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/delay.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/timer.h>
  41 #include <linux/clk.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45
  46 #include <asm/types.h>
  47 #include <linux/uaccess.h>
  48
  49 #define DRIVER_NAME "goldfish_mmc"
  50
  51 #define BUFFER_SIZE   16384
  52
  53 #define GOLDFISH_MMC_READ(host, addr)   (readl(host->reg_base + addr))
  54 #define GOLDFISH_MMC_WRITE(host, addr, x)   (writel(x, host->reg_base + addr))
  55
  56 enum {
  57         /* status register */
  58         MMC_INT_STATUS          = 0x00,
  59         /* set this to enable IRQ */
  60         MMC_INT_ENABLE          = 0x04,
  61         /* set this to specify buffer address */
  62         MMC_SET_BUFFER          = 0x08,
  63
  64         /* MMC command number */
  65         MMC_CMD                 = 0x0C,
  66
  67         /* MMC argument */
  68         MMC_ARG                 = 0x10,
  69
  70         /* MMC response (or R2 bits 0 - 31) */
  71         MMC_RESP_0                      = 0x14,
  72
  73         /* MMC R2 response bits 32 - 63 */
  74         MMC_RESP_1                      = 0x18,
  75
  76         /* MMC R2 response bits 64 - 95 */
  77         MMC_RESP_2                      = 0x1C,
  78
  79         /* MMC R2 response bits 96 - 127 */
  80         MMC_RESP_3                      = 0x20,
  81
  82         MMC_BLOCK_LENGTH        = 0x24,
  83         MMC_BLOCK_COUNT         = 0x28,
  84
  85         /* MMC state flags */
  86         MMC_STATE               = 0x2C,
  87
  88         /* MMC_INT_STATUS bits */
  89
  90         MMC_STAT_END_OF_CMD     = 1U << 0,
  91         MMC_STAT_END_OF_DATA    = 1U << 1,
  92         MMC_STAT_STATE_CHANGE   = 1U << 2,
  93         MMC_STAT_CMD_TIMEOUT    = 1U << 3,
  94
  95         /* MMC_STATE bits */
  96         MMC_STATE_INSERTED     = 1U << 0,
  97         MMC_STATE_READ_ONLY    = 1U << 1,
  98 };
  99
 100 /*
 101  * Command types
 102  */
 103 #define OMAP_MMC_CMDTYPE_BC     0
 104 #define OMAP_MMC_CMDTYPE_BCR    1
 105 #define OMAP_MMC_CMDTYPE_AC     2
 106 #define OMAP_MMC_CMDTYPE_ADTC   3
 107
 108
 109 struct goldfish_mmc_host {
 110         struct mmc_request      *mrq;
 111         struct mmc_command      *cmd;
 112         struct mmc_data         *data;
 113         struct mmc_host         *mmc;
 114         struct device           *dev;
 115         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 116         void                    *virt_base;
 117         unsigned int            phys_base;
 118         int                     irq;
 119         unsigned char           bus_mode;
 120         unsigned char           hw_bus_mode;
 121
 122         unsigned int            sg_len;
 123         unsigned                dma_done:1;
 124         unsigned                dma_in_use:1;
 125
 126         void __iomem            *reg_base;
 127 };
 128
 129 static inline int
 130 goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
 131 {
 132         return 0;
 133 }
 134
 135 static ssize_t
 136 goldfish_mmc_show_cover_switch(struct device *dev,
 137                                struct device_attribute *attr, char *buf)
 138 {
 139         struct goldfish_mmc_host *host = dev_get_drvdata(dev);
 140
 141         return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
 142                        "closed");
 143 }
 144
 145 static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
 146
 147 static void
 148 goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
 149 {
 150         u32 cmdreg;
 151         u32 resptype;
 152         u32 cmdtype;
 153
 154         host->cmd = cmd;
 155
 156         resptype = 0;
 157         cmdtype = 0;
 158
 159         /* Our hardware needs to know exact type */
 160         switch (mmc_resp_type(cmd)) {
 161         case MMC_RSP_NONE:
 162                 break;
 163         case MMC_RSP_R1:
 164         case MMC_RSP_R1B:
 165                 /* resp 1, 1b, 6, 7 */
 166                 resptype = 1;
 167                 break;
 168         case MMC_RSP_R2:
 169                 resptype = 2;
 170                 break;
 171         case MMC_RSP_R3:
 172                 resptype = 3;
 173                 break;
 174         default:
 175                 dev_err(mmc_dev(host->mmc),
 176                         "Invalid response type: %04x\n", mmc_resp_type(cmd));
 177                 break;
 178         }
 179
 180         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
 181                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 182         else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
 183                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 184         else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
 185                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 186         else
 187                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 188
 189         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 190
 191         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 192                 cmdreg |= 1 << 6;
 193
 194         if (cmd->flags & MMC_RSP_BUSY)
 195                 cmdreg |= 1 << 11;
 196
 197         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 198                 cmdreg |= 1 << 15;
 199
 200         GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
 201         GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
 202 }
 203
 204 static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
 205                                    struct mmc_data *data)
 206 {
 207         if (host->dma_in_use) {
 208                 enum dma_data_direction dma_data_dir;
 209
 210                 dma_data_dir = mmc_get_dma_dir(data);
 211
 212                 if (dma_data_dir == DMA_FROM_DEVICE) {
 213                         /*
 214                          * We don't really have DMA, so we need
 215                          * to copy from our platform driver buffer
 216                          */
 217                         sg_copy_from_buffer(data->sg, 1, host->virt_base,
 218                                         data->sg->length);
 219                 }
 220                 host->data->bytes_xfered += data->sg->length;
 221                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 222                              dma_data_dir);
 223         }
 224
 225         host->data = NULL;
 226         host->sg_len = 0;
 227
 228         /*
 229          * NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 230          * dozens of requests until the card finishes writing data.
 231          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 232          */
 233
 234         if (!data->stop) {
 235                 host->mrq = NULL;
 236                 mmc_request_done(host->mmc, data->mrq);
 237                 return;
 238         }
 239
 240         goldfish_mmc_start_command(host, data->stop);
 241 }
 242
 243 static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
 244                                      struct mmc_data *data)
 245 {
 246         if (!host->dma_in_use) {
 247                 goldfish_mmc_xfer_done(host, data);
 248                 return;
 249         }
 250         if (host->dma_done)
 251                 goldfish_mmc_xfer_done(host, data);
 252 }
 253
 254 static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
 255                                   struct mmc_command *cmd)
 256 {
 257         host->cmd = NULL;
 258         if (cmd->flags & MMC_RSP_PRESENT) {
 259                 if (cmd->flags & MMC_RSP_136) {
 260                         /* response type 2 */
 261                         cmd->resp[3] =
 262                                 GOLDFISH_MMC_READ(host, MMC_RESP_0);
 263                         cmd->resp[2] =
 264                                 GOLDFISH_MMC_READ(host, MMC_RESP_1);
 265                         cmd->resp[1] =
 266                                 GOLDFISH_MMC_READ(host, MMC_RESP_2);
 267                         cmd->resp[0] =
 268                                 GOLDFISH_MMC_READ(host, MMC_RESP_3);
 269                 } else {
 270                         /* response types 1, 1b, 3, 4, 5, 6 */
 271                         cmd->resp[0] =
 272                                 GOLDFISH_MMC_READ(host, MMC_RESP_0);
 273                 }
 274         }
 275
 276         if (host->data == NULL || cmd->error) {
 277                 host->mrq = NULL;
 278                 mmc_request_done(host->mmc, cmd->mrq);
 279         }
 280 }
 281
 282 static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
 283 {
 284         struct goldfish_mmc_host *host = (struct goldfish_mmc_host *)dev_id;
 285         u16 status;
 286         int end_command = 0;
 287         int end_transfer = 0;
 288         int state_changed = 0;
 289         int cmd_timeout = 0;
 290
 291         while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
 292                 GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
 293
 294                 if (status & MMC_STAT_END_OF_CMD)
 295                         end_command = 1;
 296
 297                 if (status & MMC_STAT_END_OF_DATA)
 298                         end_transfer = 1;
 299
 300                 if (status & MMC_STAT_STATE_CHANGE)
 301                         state_changed = 1;
 302
 303                 if (status & MMC_STAT_CMD_TIMEOUT) {
 304                         end_command = 0;
 305                         cmd_timeout = 1;
 306                 }
 307         }
 308
 309         if (cmd_timeout) {
 310                 struct mmc_request *mrq = host->mrq;
 311                 mrq->cmd->error = -ETIMEDOUT;
 312                 host->mrq = NULL;
 313                 mmc_request_done(host->mmc, mrq);
 314         }
 315
 316         if (end_command)
 317                 goldfish_mmc_cmd_done(host, host->cmd);
 318
 319         if (end_transfer) {
 320                 host->dma_done = 1;
 321                 goldfish_mmc_end_of_data(host, host->data);
 322         } else if (host->data != NULL) {
 323                 /*
 324                  * WORKAROUND -- after porting this driver from 2.6 to 3.4,
 325                  * during device initialization, cases where host->data is
 326                  * non-null but end_transfer is false would occur. Doing
 327                  * nothing in such cases results in no further interrupts,
 328                  * and initialization failure.
 329                  * TODO -- find the real cause.
 330                  */
 331                 host->dma_done = 1;
 332                 goldfish_mmc_end_of_data(host, host->data);
 333         }
 334
 335         if (state_changed) {
 336                 u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
 337                 pr_info("%s: Card detect now %d\n", __func__,
 338                         (state & MMC_STATE_INSERTED));
 339                 mmc_detect_change(host->mmc, 0);
 340         }
 341
 342         if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
 343                 status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
 344                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 345                 if (status != 0) {
 346                         GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
 347                         GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
 348                 }
 349         }
 350
 351         return IRQ_HANDLED;
 352 }
 353
 354 static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
 355                                       struct mmc_request *req)
 356 {
 357         struct mmc_data *data = req->data;
 358         int block_size;
 359         unsigned sg_len;
 360         enum dma_data_direction dma_data_dir;
 361
 362         host->data = data;
 363         if (data == NULL) {
 364                 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
 365                 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
 366                 host->dma_in_use = 0;
 367                 return;
 368         }
 369
 370         block_size = data->blksz;
 371
 372         GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
 373         GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
 374
 375         /*
 376          * Cope with calling layer confusion; it issues "single
 377          * block" writes using multi-block scatterlists.
 378          */
 379         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 380
 381         dma_data_dir = mmc_get_dma_dir(data);
 382
 383         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 384                                   sg_len, dma_data_dir);
 385         host->dma_done = 0;
 386         host->dma_in_use = 1;
 387
 388         if (dma_data_dir == DMA_TO_DEVICE) {
 389                 /*
 390                  * We don't really have DMA, so we need to copy to our
 391                  * platform driver buffer
 392                  */
 393                 sg_copy_to_buffer(data->sg, 1, host->virt_base,
 394                                 data->sg->length);
 395         }
 396 }
 397
 398 static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 399 {
 400         struct goldfish_mmc_host *host = mmc_priv(mmc);
 401
 402         WARN_ON(host->mrq != NULL);
 403
 404         host->mrq = req;
 405         goldfish_mmc_prepare_data(host, req);
 406         goldfish_mmc_start_command(host, req->cmd);
 407
 408         /*
 409          * This is to avoid accidentally being detected as an SDIO card
 410          * in mmc_attach_sdio().
 411          */
 412         if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
 413             req->cmd->flags == (MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR))
 414                 req->cmd->error = -EINVAL;
 415 }
 416
 417 static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 418 {
 419         struct goldfish_mmc_host *host = mmc_priv(mmc);
 420
 421         host->bus_mode = ios->bus_mode;
 422         host->hw_bus_mode = host->bus_mode;
 423 }
 424
 425 static int goldfish_mmc_get_ro(struct mmc_host *mmc)
 426 {
 427         uint32_t state;
 428         struct goldfish_mmc_host *host = mmc_priv(mmc);
 429
 430         state = GOLDFISH_MMC_READ(host, MMC_STATE);
 431         return ((state & MMC_STATE_READ_ONLY) != 0);
 432 }
 433
 434 static const struct mmc_host_ops goldfish_mmc_ops = {
 435         .request        = goldfish_mmc_request,
 436         .set_ios        = goldfish_mmc_set_ios,
 437         .get_ro         = goldfish_mmc_get_ro,
 438 };
 439
 440 static int goldfish_mmc_probe(struct platform_device *pdev)
 441 {
 442         struct mmc_host *mmc;
 443         struct goldfish_mmc_host *host = NULL;
 444         struct resource *res;
 445         int ret = 0;
 446         int irq;
 447         dma_addr_t buf_addr;
 448
 449         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 450         irq = platform_get_irq(pdev, 0);
 451         if (res == NULL || irq < 0)
 452                 return -ENXIO;
 453
 454         mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
 455         if (mmc == NULL) {
 456                 ret = -ENOMEM;
 457                 goto err_alloc_host_failed;
 458         }
 459
 460         host = mmc_priv(mmc);
 461         host->mmc = mmc;
 462
 463         pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
 464         host->reg_base = ioremap(res->start, resource_size(res));
 465         if (host->reg_base == NULL) {
 466                 ret = -ENOMEM;
 467                 goto ioremap_failed;
 468         }
 469         host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 470                                              &buf_addr, GFP_KERNEL);
 471
 472         if (host->virt_base == 0) {
 473                 ret = -ENOMEM;
 474                 goto dma_alloc_failed;
 475         }
 476         host->phys_base = buf_addr;
 477
 478         host->id = pdev->id;
 479         host->irq = irq;
 480
 481         mmc->ops = &goldfish_mmc_ops;
 482         mmc->f_min = 400000;
 483         mmc->f_max = 24000000;
 484         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 485         mmc->caps = MMC_CAP_4_BIT_DATA;
 486
 487         /* Use scatterlist DMA to reduce per-transfer costs.
 488          * NOTE max_seg_size assumption that small blocks aren't
 489          * normally used (except e.g. for reading SD registers).
 490          */
 491         mmc->max_segs = 32;
 492         mmc->max_blk_size = 2048;       /* MMC_BLOCK_LENGTH is 11 bits (+1) */
 493         mmc->max_blk_count = 2048;      /* MMC_BLOCK_COUNT is 11 bits (+1) */
 494         mmc->max_req_size = BUFFER_SIZE;
 495         mmc->max_seg_size = mmc->max_req_size;
 496
 497         ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
 498         if (ret) {
 499                 dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
 500                 goto err_request_irq_failed;
 501         }
 502
 503         host->dev = &pdev->dev;
 504         platform_set_drvdata(pdev, host);
 505
 506         ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
 507         if (ret)
 508                 dev_warn(mmc_dev(host->mmc),
 509                          "Unable to create sysfs attributes\n");
 510
 511         GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
 512         GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
 513                            MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA |
 514                            MMC_STAT_STATE_CHANGE | MMC_STAT_CMD_TIMEOUT);
 515
 516         mmc_add_host(mmc);
 517         return 0;
 518
 519 err_request_irq_failed:
 520         dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
 521                           host->phys_base);
 522 dma_alloc_failed:
 523         iounmap(host->reg_base);
 524 ioremap_failed:
 525         mmc_free_host(host->mmc);
 526 err_alloc_host_failed:
 527         return ret;
 528 }
 529
 530 static int goldfish_mmc_remove(struct platform_device *pdev)
 531 {
 532         struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
 533
 534         BUG_ON(host == NULL);
 535
 536         mmc_remove_host(host->mmc);
 537         free_irq(host->irq, host);
 538         dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
 539         iounmap(host->reg_base);
 540         mmc_free_host(host->mmc);
 541         return 0;
 542 }
 543
 544 static struct platform_driver goldfish_mmc_driver = {
 545         .probe          = goldfish_mmc_probe,
 546         .remove         = goldfish_mmc_remove,
 547         .driver         = {
 548                 .name   = DRIVER_NAME,
 549         },
 550 };
 551
 552 module_platform_driver(goldfish_mmc_driver);
 553 MODULE_LICENSE("GPL v2");