2 * Atmel MultiMedia Card Interface driver
4 * Copyright (C) 2004-2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/types.h>
31 #include <linux/platform_data/atmel.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/sdio.h>
36 #include <mach/atmel-mci.h>
37 #include <linux/atmel-mci.h>
38 #include <linux/atmel_pdc.h>
41 #include <asm/unaligned.h>
43 #include "atmel-mci-regs.h"
45 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
46 #define ATMCI_DMA_THRESHOLD 16
55 enum atmel_mci_state
{
59 STATE_WAITING_NOTBUSY
,
74 struct atmel_mci_caps
{
75 bool has_dma_conf_reg
;
82 bool has_bad_data_ordering
;
83 bool need_reset_after_xfer
;
84 bool need_blksz_mul_4
;
85 bool need_notbusy_for_read_ops
;
88 struct atmel_mci_dma
{
89 struct dma_chan
*chan
;
90 struct dma_async_tx_descriptor
*data_desc
;
94 * struct atmel_mci - MMC controller state shared between all slots
95 * @lock: Spinlock protecting the queue and associated data.
96 * @regs: Pointer to MMIO registers.
97 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
98 * @pio_offset: Offset into the current scatterlist entry.
99 * @buffer: Buffer used if we don't have the r/w proof capability. We
100 * don't have the time to switch pdc buffers so we have to use only
101 * one buffer for the full transaction.
102 * @buf_size: size of the buffer.
103 * @phys_buf_addr: buffer address needed for pdc.
104 * @cur_slot: The slot which is currently using the controller.
105 * @mrq: The request currently being processed on @cur_slot,
106 * or NULL if the controller is idle.
107 * @cmd: The command currently being sent to the card, or NULL.
108 * @data: The data currently being transferred, or NULL if no data
109 * transfer is in progress.
110 * @data_size: just data->blocks * data->blksz.
111 * @dma: DMA client state.
112 * @data_chan: DMA channel being used for the current data transfer.
113 * @cmd_status: Snapshot of SR taken upon completion of the current
114 * command. Only valid when EVENT_CMD_COMPLETE is pending.
115 * @data_status: Snapshot of SR taken upon completion of the current
116 * data transfer. Only valid when EVENT_DATA_COMPLETE or
117 * EVENT_DATA_ERROR is pending.
118 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
120 * @tasklet: Tasklet running the request state machine.
121 * @pending_events: Bitmask of events flagged by the interrupt handler
122 * to be processed by the tasklet.
123 * @completed_events: Bitmask of events which the state machine has
125 * @state: Tasklet state.
126 * @queue: List of slots waiting for access to the controller.
127 * @need_clock_update: Update the clock rate before the next request.
128 * @need_reset: Reset controller before next request.
129 * @timer: Timer to balance the data timeout error flag which cannot rise.
130 * @mode_reg: Value of the MR register.
131 * @cfg_reg: Value of the CFG register.
132 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
133 * rate and timeout calculations.
134 * @mapbase: Physical address of the MMIO registers.
135 * @mck: The peripheral bus clock hooked up to the MMC controller.
136 * @pdev: Platform device associated with the MMC controller.
137 * @slot: Slots sharing this MMC controller.
138 * @caps: MCI capabilities depending on MCI version.
139 * @prepare_data: function to setup MCI before data transfer which
140 * depends on MCI capabilities.
141 * @submit_data: function to start data transfer which depends on MCI
143 * @stop_transfer: function to stop data transfer which depends on MCI
149 * @lock is a softirq-safe spinlock protecting @queue as well as
150 * @cur_slot, @mrq and @state. These must always be updated
151 * at the same time while holding @lock.
153 * @lock also protects mode_reg and need_clock_update since these are
154 * used to synchronize mode register updates with the queue
157 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
158 * and must always be written at the same time as the slot is added to
161 * @pending_events and @completed_events are accessed using atomic bit
162 * operations, so they don't need any locking.
164 * None of the fields touched by the interrupt handler need any
165 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
166 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
167 * interrupts must be disabled and @data_status updated with a
168 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
169 * CMDRDY interrupt must be disabled and @cmd_status updated with a
170 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
171 * bytes_xfered field of @data must be written. This is ensured by
178 struct scatterlist
*sg
;
180 unsigned int pio_offset
;
181 unsigned int *buffer
;
182 unsigned int buf_size
;
183 dma_addr_t buf_phys_addr
;
185 struct atmel_mci_slot
*cur_slot
;
186 struct mmc_request
*mrq
;
187 struct mmc_command
*cmd
;
188 struct mmc_data
*data
;
189 unsigned int data_size
;
191 struct atmel_mci_dma dma
;
192 struct dma_chan
*data_chan
;
193 struct dma_slave_config dma_conf
;
199 struct tasklet_struct tasklet
;
200 unsigned long pending_events
;
201 unsigned long completed_events
;
202 enum atmel_mci_state state
;
203 struct list_head queue
;
205 bool need_clock_update
;
207 struct timer_list timer
;
210 unsigned long bus_hz
;
211 unsigned long mapbase
;
213 struct platform_device
*pdev
;
215 struct atmel_mci_slot
*slot
[ATMCI_MAX_NR_SLOTS
];
217 struct atmel_mci_caps caps
;
219 u32 (*prepare_data
)(struct atmel_mci
*host
, struct mmc_data
*data
);
220 void (*submit_data
)(struct atmel_mci
*host
, struct mmc_data
*data
);
221 void (*stop_transfer
)(struct atmel_mci
*host
);
225 * struct atmel_mci_slot - MMC slot state
226 * @mmc: The mmc_host representing this slot.
227 * @host: The MMC controller this slot is using.
228 * @sdc_reg: Value of SDCR to be written before using this slot.
229 * @sdio_irq: SDIO irq mask for this slot.
230 * @mrq: mmc_request currently being processed or waiting to be
231 * processed, or NULL when the slot is idle.
232 * @queue_node: List node for placing this node in the @queue list of
234 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
235 * @flags: Random state bits associated with the slot.
236 * @detect_pin: GPIO pin used for card detection, or negative if not
238 * @wp_pin: GPIO pin used for card write protect sending, or negative
240 * @detect_is_active_high: The state of the detect pin when it is active.
241 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
243 struct atmel_mci_slot
{
244 struct mmc_host
*mmc
;
245 struct atmel_mci
*host
;
250 struct mmc_request
*mrq
;
251 struct list_head queue_node
;
255 #define ATMCI_CARD_PRESENT 0
256 #define ATMCI_CARD_NEED_INIT 1
257 #define ATMCI_SHUTDOWN 2
261 bool detect_is_active_high
;
263 struct timer_list detect_timer
;
266 #define atmci_test_and_clear_pending(host, event) \
267 test_and_clear_bit(event, &host->pending_events)
268 #define atmci_set_completed(host, event) \
269 set_bit(event, &host->completed_events)
270 #define atmci_set_pending(host, event) \
271 set_bit(event, &host->pending_events)
274 * The debugfs stuff below is mostly optimized away when
275 * CONFIG_DEBUG_FS is not set.
277 static int atmci_req_show(struct seq_file
*s
, void *v
)
279 struct atmel_mci_slot
*slot
= s
->private;
280 struct mmc_request
*mrq
;
281 struct mmc_command
*cmd
;
282 struct mmc_command
*stop
;
283 struct mmc_data
*data
;
285 /* Make sure we get a consistent snapshot */
286 spin_lock_bh(&slot
->host
->lock
);
296 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
297 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
298 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
299 cmd
->resp
[3], cmd
->error
);
301 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
302 data
->bytes_xfered
, data
->blocks
,
303 data
->blksz
, data
->flags
, data
->error
);
306 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
307 stop
->opcode
, stop
->arg
, stop
->flags
,
308 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
309 stop
->resp
[3], stop
->error
);
312 spin_unlock_bh(&slot
->host
->lock
);
317 static int atmci_req_open(struct inode
*inode
, struct file
*file
)
319 return single_open(file
, atmci_req_show
, inode
->i_private
);
322 static const struct file_operations atmci_req_fops
= {
323 .owner
= THIS_MODULE
,
324 .open
= atmci_req_open
,
327 .release
= single_release
,
330 static void atmci_show_status_reg(struct seq_file
*s
,
331 const char *regname
, u32 value
)
333 static const char *sr_bit
[] = {
364 seq_printf(s
, "%s:\t0x%08x", regname
, value
);
365 for (i
= 0; i
< ARRAY_SIZE(sr_bit
); i
++) {
366 if (value
& (1 << i
)) {
368 seq_printf(s
, " %s", sr_bit
[i
]);
370 seq_puts(s
, " UNKNOWN");
376 static int atmci_regs_show(struct seq_file
*s
, void *v
)
378 struct atmel_mci
*host
= s
->private;
383 buf
= kmalloc(ATMCI_REGS_SIZE
, GFP_KERNEL
);
388 * Grab a more or less consistent snapshot. Note that we're
389 * not disabling interrupts, so IMR and SR may not be
392 ret
= clk_prepare_enable(host
->mck
);
396 spin_lock_bh(&host
->lock
);
397 memcpy_fromio(buf
, host
->regs
, ATMCI_REGS_SIZE
);
398 spin_unlock_bh(&host
->lock
);
400 clk_disable_unprepare(host
->mck
);
402 seq_printf(s
, "MR:\t0x%08x%s%s ",
404 buf
[ATMCI_MR
/ 4] & ATMCI_MR_RDPROOF
? " RDPROOF" : "",
405 buf
[ATMCI_MR
/ 4] & ATMCI_MR_WRPROOF
? " WRPROOF" : "");
406 if (host
->caps
.has_odd_clk_div
)
407 seq_printf(s
, "{CLKDIV,CLKODD}=%u\n",
408 ((buf
[ATMCI_MR
/ 4] & 0xff) << 1)
409 | ((buf
[ATMCI_MR
/ 4] >> 16) & 1));
411 seq_printf(s
, "CLKDIV=%u\n",
412 (buf
[ATMCI_MR
/ 4] & 0xff));
413 seq_printf(s
, "DTOR:\t0x%08x\n", buf
[ATMCI_DTOR
/ 4]);
414 seq_printf(s
, "SDCR:\t0x%08x\n", buf
[ATMCI_SDCR
/ 4]);
415 seq_printf(s
, "ARGR:\t0x%08x\n", buf
[ATMCI_ARGR
/ 4]);
416 seq_printf(s
, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
418 buf
[ATMCI_BLKR
/ 4] & 0xffff,
419 (buf
[ATMCI_BLKR
/ 4] >> 16) & 0xffff);
420 if (host
->caps
.has_cstor_reg
)
421 seq_printf(s
, "CSTOR:\t0x%08x\n", buf
[ATMCI_CSTOR
/ 4]);
423 /* Don't read RSPR and RDR; it will consume the data there */
425 atmci_show_status_reg(s
, "SR", buf
[ATMCI_SR
/ 4]);
426 atmci_show_status_reg(s
, "IMR", buf
[ATMCI_IMR
/ 4]);
428 if (host
->caps
.has_dma_conf_reg
) {
431 val
= buf
[ATMCI_DMA
/ 4];
432 seq_printf(s
, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
435 1 << (((val
>> 4) & 3) + 1) : 1,
436 val
& ATMCI_DMAEN
? " DMAEN" : "");
438 if (host
->caps
.has_cfg_reg
) {
441 val
= buf
[ATMCI_CFG
/ 4];
442 seq_printf(s
, "CFG:\t0x%08x%s%s%s%s\n",
444 val
& ATMCI_CFG_FIFOMODE_1DATA
? " FIFOMODE_ONE_DATA" : "",
445 val
& ATMCI_CFG_FERRCTRL_COR
? " FERRCTRL_CLEAR_ON_READ" : "",
446 val
& ATMCI_CFG_HSMODE
? " HSMODE" : "",
447 val
& ATMCI_CFG_LSYNC
? " LSYNC" : "");
456 static int atmci_regs_open(struct inode
*inode
, struct file
*file
)
458 return single_open(file
, atmci_regs_show
, inode
->i_private
);
461 static const struct file_operations atmci_regs_fops
= {
462 .owner
= THIS_MODULE
,
463 .open
= atmci_regs_open
,
466 .release
= single_release
,
469 static void atmci_init_debugfs(struct atmel_mci_slot
*slot
)
471 struct mmc_host
*mmc
= slot
->mmc
;
472 struct atmel_mci
*host
= slot
->host
;
476 root
= mmc
->debugfs_root
;
480 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
487 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
, &atmci_req_fops
);
491 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
495 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
496 (u32
*)&host
->pending_events
);
500 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
501 (u32
*)&host
->completed_events
);
508 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
511 #if defined(CONFIG_OF)
512 static const struct of_device_id atmci_dt_ids
[] = {
513 { .compatible
= "atmel,hsmci" },
517 MODULE_DEVICE_TABLE(of
, atmci_dt_ids
);
519 static struct mci_platform_data
*
520 atmci_of_init(struct platform_device
*pdev
)
522 struct device_node
*np
= pdev
->dev
.of_node
;
523 struct device_node
*cnp
;
524 struct mci_platform_data
*pdata
;
528 dev_err(&pdev
->dev
, "device node not found\n");
529 return ERR_PTR(-EINVAL
);
532 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
534 dev_err(&pdev
->dev
, "could not allocate memory for pdata\n");
535 return ERR_PTR(-ENOMEM
);
538 for_each_child_of_node(np
, cnp
) {
539 if (of_property_read_u32(cnp
, "reg", &slot_id
)) {
540 dev_warn(&pdev
->dev
, "reg property is missing for %s\n",
545 if (slot_id
>= ATMCI_MAX_NR_SLOTS
) {
546 dev_warn(&pdev
->dev
, "can't have more than %d slots\n",
551 if (of_property_read_u32(cnp
, "bus-width",
552 &pdata
->slot
[slot_id
].bus_width
))
553 pdata
->slot
[slot_id
].bus_width
= 1;
555 pdata
->slot
[slot_id
].detect_pin
=
556 of_get_named_gpio(cnp
, "cd-gpios", 0);
558 pdata
->slot
[slot_id
].detect_is_active_high
=
559 of_property_read_bool(cnp
, "cd-inverted");
561 pdata
->slot
[slot_id
].wp_pin
=
562 of_get_named_gpio(cnp
, "wp-gpios", 0);
567 #else /* CONFIG_OF */
568 static inline struct mci_platform_data
*
569 atmci_of_init(struct platform_device
*dev
)
571 return ERR_PTR(-EINVAL
);
575 static inline unsigned int atmci_get_version(struct atmel_mci
*host
)
577 return atmci_readl(host
, ATMCI_VERSION
) & 0x00000fff;
580 static void atmci_timeout_timer(unsigned long data
)
582 struct atmel_mci
*host
;
584 host
= (struct atmel_mci
*)data
;
586 dev_dbg(&host
->pdev
->dev
, "software timeout\n");
588 if (host
->mrq
->cmd
->data
) {
589 host
->mrq
->cmd
->data
->error
= -ETIMEDOUT
;
592 * With some SDIO modules, sometimes DMA transfer hangs. If
593 * stop_transfer() is not called then the DMA request is not
594 * removed, following ones are queued and never computed.
596 if (host
->state
== STATE_DATA_XFER
)
597 host
->stop_transfer(host
);
599 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
602 host
->need_reset
= 1;
603 host
->state
= STATE_END_REQUEST
;
605 tasklet_schedule(&host
->tasklet
);
608 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci
*host
,
612 * It is easier here to use us instead of ns for the timeout,
613 * it prevents from overflows during calculation.
615 unsigned int us
= DIV_ROUND_UP(ns
, 1000);
617 /* Maximum clock frequency is host->bus_hz/2 */
618 return us
* (DIV_ROUND_UP(host
->bus_hz
, 2000000));
621 static void atmci_set_timeout(struct atmel_mci
*host
,
622 struct atmel_mci_slot
*slot
, struct mmc_data
*data
)
624 static unsigned dtomul_to_shift
[] = {
625 0, 4, 7, 8, 10, 12, 16, 20
631 timeout
= atmci_ns_to_clocks(host
, data
->timeout_ns
)
632 + data
->timeout_clks
;
634 for (dtomul
= 0; dtomul
< 8; dtomul
++) {
635 unsigned shift
= dtomul_to_shift
[dtomul
];
636 dtocyc
= (timeout
+ (1 << shift
) - 1) >> shift
;
646 dev_vdbg(&slot
->mmc
->class_dev
, "setting timeout to %u cycles\n",
647 dtocyc
<< dtomul_to_shift
[dtomul
]);
648 atmci_writel(host
, ATMCI_DTOR
, (ATMCI_DTOMUL(dtomul
) | ATMCI_DTOCYC(dtocyc
)));
652 * Return mask with command flags to be enabled for this command.
654 static u32
atmci_prepare_command(struct mmc_host
*mmc
,
655 struct mmc_command
*cmd
)
657 struct mmc_data
*data
;
660 cmd
->error
= -EINPROGRESS
;
662 cmdr
= ATMCI_CMDR_CMDNB(cmd
->opcode
);
664 if (cmd
->flags
& MMC_RSP_PRESENT
) {
665 if (cmd
->flags
& MMC_RSP_136
)
666 cmdr
|= ATMCI_CMDR_RSPTYP_136BIT
;
668 cmdr
|= ATMCI_CMDR_RSPTYP_48BIT
;
672 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
673 * it's too difficult to determine whether this is an ACMD or
674 * not. Better make it 64.
676 cmdr
|= ATMCI_CMDR_MAXLAT_64CYC
;
678 if (mmc
->ios
.bus_mode
== MMC_BUSMODE_OPENDRAIN
)
679 cmdr
|= ATMCI_CMDR_OPDCMD
;
683 cmdr
|= ATMCI_CMDR_START_XFER
;
685 if (cmd
->opcode
== SD_IO_RW_EXTENDED
) {
686 cmdr
|= ATMCI_CMDR_SDIO_BLOCK
;
688 if (data
->flags
& MMC_DATA_STREAM
)
689 cmdr
|= ATMCI_CMDR_STREAM
;
690 else if (data
->blocks
> 1)
691 cmdr
|= ATMCI_CMDR_MULTI_BLOCK
;
693 cmdr
|= ATMCI_CMDR_BLOCK
;
696 if (data
->flags
& MMC_DATA_READ
)
697 cmdr
|= ATMCI_CMDR_TRDIR_READ
;
703 static void atmci_send_command(struct atmel_mci
*host
,
704 struct mmc_command
*cmd
, u32 cmd_flags
)
709 dev_vdbg(&host
->pdev
->dev
,
710 "start command: ARGR=0x%08x CMDR=0x%08x\n",
711 cmd
->arg
, cmd_flags
);
713 atmci_writel(host
, ATMCI_ARGR
, cmd
->arg
);
714 atmci_writel(host
, ATMCI_CMDR
, cmd_flags
);
717 static void atmci_send_stop_cmd(struct atmel_mci
*host
, struct mmc_data
*data
)
719 dev_dbg(&host
->pdev
->dev
, "send stop command\n");
720 atmci_send_command(host
, data
->stop
, host
->stop_cmdr
);
721 atmci_writel(host
, ATMCI_IER
, ATMCI_CMDRDY
);
725 * Configure given PDC buffer taking care of alignement issues.
726 * Update host->data_size and host->sg.
728 static void atmci_pdc_set_single_buf(struct atmel_mci
*host
,
729 enum atmci_xfer_dir dir
, enum atmci_pdc_buf buf_nb
)
731 u32 pointer_reg
, counter_reg
;
732 unsigned int buf_size
;
734 if (dir
== XFER_RECEIVE
) {
735 pointer_reg
= ATMEL_PDC_RPR
;
736 counter_reg
= ATMEL_PDC_RCR
;
738 pointer_reg
= ATMEL_PDC_TPR
;
739 counter_reg
= ATMEL_PDC_TCR
;
742 if (buf_nb
== PDC_SECOND_BUF
) {
743 pointer_reg
+= ATMEL_PDC_SCND_BUF_OFF
;
744 counter_reg
+= ATMEL_PDC_SCND_BUF_OFF
;
747 if (!host
->caps
.has_rwproof
) {
748 buf_size
= host
->buf_size
;
749 atmci_writel(host
, pointer_reg
, host
->buf_phys_addr
);
751 buf_size
= sg_dma_len(host
->sg
);
752 atmci_writel(host
, pointer_reg
, sg_dma_address(host
->sg
));
755 if (host
->data_size
<= buf_size
) {
756 if (host
->data_size
& 0x3) {
757 /* If size is different from modulo 4, transfer bytes */
758 atmci_writel(host
, counter_reg
, host
->data_size
);
759 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
| ATMCI_MR_PDCFBYTE
);
761 /* Else transfer 32-bits words */
762 atmci_writel(host
, counter_reg
, host
->data_size
/ 4);
766 /* We assume the size of a page is 32-bits aligned */
767 atmci_writel(host
, counter_reg
, sg_dma_len(host
->sg
) / 4);
768 host
->data_size
-= sg_dma_len(host
->sg
);
770 host
->sg
= sg_next(host
->sg
);
775 * Configure PDC buffer according to the data size ie configuring one or two
776 * buffers. Don't use this function if you want to configure only the second
777 * buffer. In this case, use atmci_pdc_set_single_buf.
779 static void atmci_pdc_set_both_buf(struct atmel_mci
*host
, int dir
)
781 atmci_pdc_set_single_buf(host
, dir
, PDC_FIRST_BUF
);
783 atmci_pdc_set_single_buf(host
, dir
, PDC_SECOND_BUF
);
787 * Unmap sg lists, called when transfer is finished.
789 static void atmci_pdc_cleanup(struct atmel_mci
*host
)
791 struct mmc_data
*data
= host
->data
;
794 dma_unmap_sg(&host
->pdev
->dev
,
795 data
->sg
, data
->sg_len
,
796 ((data
->flags
& MMC_DATA_WRITE
)
797 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
));
801 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
802 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
803 * interrupt needed for both transfer directions.
805 static void atmci_pdc_complete(struct atmel_mci
*host
)
807 int transfer_size
= host
->data
->blocks
* host
->data
->blksz
;
810 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTDIS
| ATMEL_PDC_TXTDIS
);
812 if ((!host
->caps
.has_rwproof
)
813 && (host
->data
->flags
& MMC_DATA_READ
)) {
814 if (host
->caps
.has_bad_data_ordering
)
815 for (i
= 0; i
< transfer_size
; i
++)
816 host
->buffer
[i
] = swab32(host
->buffer
[i
]);
817 sg_copy_from_buffer(host
->data
->sg
, host
->data
->sg_len
,
818 host
->buffer
, transfer_size
);
821 atmci_pdc_cleanup(host
);
823 dev_dbg(&host
->pdev
->dev
, "(%s) set pending xfer complete\n", __func__
);
824 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
825 tasklet_schedule(&host
->tasklet
);
828 static void atmci_dma_cleanup(struct atmel_mci
*host
)
830 struct mmc_data
*data
= host
->data
;
833 dma_unmap_sg(host
->dma
.chan
->device
->dev
,
834 data
->sg
, data
->sg_len
,
835 ((data
->flags
& MMC_DATA_WRITE
)
836 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
));
840 * This function is called by the DMA driver from tasklet context.
842 static void atmci_dma_complete(void *arg
)
844 struct atmel_mci
*host
= arg
;
845 struct mmc_data
*data
= host
->data
;
847 dev_vdbg(&host
->pdev
->dev
, "DMA complete\n");
849 if (host
->caps
.has_dma_conf_reg
)
850 /* Disable DMA hardware handshaking on MCI */
851 atmci_writel(host
, ATMCI_DMA
, atmci_readl(host
, ATMCI_DMA
) & ~ATMCI_DMAEN
);
853 atmci_dma_cleanup(host
);
856 * If the card was removed, data will be NULL. No point trying
857 * to send the stop command or waiting for NBUSY in this case.
860 dev_dbg(&host
->pdev
->dev
,
861 "(%s) set pending xfer complete\n", __func__
);
862 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
863 tasklet_schedule(&host
->tasklet
);
866 * Regardless of what the documentation says, we have
867 * to wait for NOTBUSY even after block read
870 * When the DMA transfer is complete, the controller
871 * may still be reading the CRC from the card, i.e.
872 * the data transfer is still in progress and we
873 * haven't seen all the potential error bits yet.
875 * The interrupt handler will schedule a different
876 * tasklet to finish things up when the data transfer
877 * is completely done.
879 * We may not complete the mmc request here anyway
880 * because the mmc layer may call back and cause us to
881 * violate the "don't submit new operations from the
882 * completion callback" rule of the dma engine
885 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
890 * Returns a mask of interrupt flags to be enabled after the whole
891 * request has been prepared.
893 static u32
atmci_prepare_data(struct atmel_mci
*host
, struct mmc_data
*data
)
897 data
->error
= -EINPROGRESS
;
900 host
->sg_len
= data
->sg_len
;
902 host
->data_chan
= NULL
;
904 iflags
= ATMCI_DATA_ERROR_FLAGS
;
907 * Errata: MMC data write operation with less than 12
908 * bytes is impossible.
910 * Errata: MCI Transmit Data Register (TDR) FIFO
911 * corruption when length is not multiple of 4.
913 if (data
->blocks
* data
->blksz
< 12
914 || (data
->blocks
* data
->blksz
) & 3)
915 host
->need_reset
= true;
917 host
->pio_offset
= 0;
918 if (data
->flags
& MMC_DATA_READ
)
919 iflags
|= ATMCI_RXRDY
;
921 iflags
|= ATMCI_TXRDY
;
927 * Set interrupt flags and set block length into the MCI mode register even
928 * if this value is also accessible in the MCI block register. It seems to be
929 * necessary before the High Speed MCI version. It also map sg and configure
933 atmci_prepare_data_pdc(struct atmel_mci
*host
, struct mmc_data
*data
)
937 enum dma_data_direction dir
;
940 data
->error
= -EINPROGRESS
;
944 iflags
= ATMCI_DATA_ERROR_FLAGS
;
946 /* Enable pdc mode */
947 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
| ATMCI_MR_PDCMODE
);
949 if (data
->flags
& MMC_DATA_READ
) {
950 dir
= DMA_FROM_DEVICE
;
951 iflags
|= ATMCI_ENDRX
| ATMCI_RXBUFF
;
954 iflags
|= ATMCI_ENDTX
| ATMCI_TXBUFE
| ATMCI_BLKE
;
958 tmp
= atmci_readl(host
, ATMCI_MR
);
960 tmp
|= ATMCI_BLKLEN(data
->blksz
);
961 atmci_writel(host
, ATMCI_MR
, tmp
);
964 host
->data_size
= data
->blocks
* data
->blksz
;
965 sg_len
= dma_map_sg(&host
->pdev
->dev
, data
->sg
, data
->sg_len
, dir
);
967 if ((!host
->caps
.has_rwproof
)
968 && (host
->data
->flags
& MMC_DATA_WRITE
)) {
969 sg_copy_to_buffer(host
->data
->sg
, host
->data
->sg_len
,
970 host
->buffer
, host
->data_size
);
971 if (host
->caps
.has_bad_data_ordering
)
972 for (i
= 0; i
< host
->data_size
; i
++)
973 host
->buffer
[i
] = swab32(host
->buffer
[i
]);
977 atmci_pdc_set_both_buf(host
,
978 ((dir
== DMA_FROM_DEVICE
) ? XFER_RECEIVE
: XFER_TRANSMIT
));
984 atmci_prepare_data_dma(struct atmel_mci
*host
, struct mmc_data
*data
)
986 struct dma_chan
*chan
;
987 struct dma_async_tx_descriptor
*desc
;
988 struct scatterlist
*sg
;
990 enum dma_data_direction direction
;
991 enum dma_transfer_direction slave_dirn
;
996 data
->error
= -EINPROGRESS
;
1002 iflags
= ATMCI_DATA_ERROR_FLAGS
;
1005 * We don't do DMA on "complex" transfers, i.e. with
1006 * non-word-aligned buffers or lengths. Also, we don't bother
1007 * with all the DMA setup overhead for short transfers.
1009 if (data
->blocks
* data
->blksz
< ATMCI_DMA_THRESHOLD
)
1010 return atmci_prepare_data(host
, data
);
1011 if (data
->blksz
& 3)
1012 return atmci_prepare_data(host
, data
);
1014 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
1015 if (sg
->offset
& 3 || sg
->length
& 3)
1016 return atmci_prepare_data(host
, data
);
1019 /* If we don't have a channel, we can't do DMA */
1020 chan
= host
->dma
.chan
;
1022 host
->data_chan
= chan
;
1027 if (data
->flags
& MMC_DATA_READ
) {
1028 direction
= DMA_FROM_DEVICE
;
1029 host
->dma_conf
.direction
= slave_dirn
= DMA_DEV_TO_MEM
;
1030 maxburst
= atmci_convert_chksize(host
->dma_conf
.src_maxburst
);
1032 direction
= DMA_TO_DEVICE
;
1033 host
->dma_conf
.direction
= slave_dirn
= DMA_MEM_TO_DEV
;
1034 maxburst
= atmci_convert_chksize(host
->dma_conf
.dst_maxburst
);
1037 if (host
->caps
.has_dma_conf_reg
)
1038 atmci_writel(host
, ATMCI_DMA
, ATMCI_DMA_CHKSIZE(maxburst
) |
1041 sglen
= dma_map_sg(chan
->device
->dev
, data
->sg
,
1042 data
->sg_len
, direction
);
1044 dmaengine_slave_config(chan
, &host
->dma_conf
);
1045 desc
= dmaengine_prep_slave_sg(chan
,
1046 data
->sg
, sglen
, slave_dirn
,
1047 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1051 host
->dma
.data_desc
= desc
;
1052 desc
->callback
= atmci_dma_complete
;
1053 desc
->callback_param
= host
;
1057 dma_unmap_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
, direction
);
1062 atmci_submit_data(struct atmel_mci
*host
, struct mmc_data
*data
)
1068 * Start PDC according to transfer direction.
1071 atmci_submit_data_pdc(struct atmel_mci
*host
, struct mmc_data
*data
)
1073 if (data
->flags
& MMC_DATA_READ
)
1074 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTEN
);
1076 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_TXTEN
);
1080 atmci_submit_data_dma(struct atmel_mci
*host
, struct mmc_data
*data
)
1082 struct dma_chan
*chan
= host
->data_chan
;
1083 struct dma_async_tx_descriptor
*desc
= host
->dma
.data_desc
;
1086 dmaengine_submit(desc
);
1087 dma_async_issue_pending(chan
);
1091 static void atmci_stop_transfer(struct atmel_mci
*host
)
1093 dev_dbg(&host
->pdev
->dev
,
1094 "(%s) set pending xfer complete\n", __func__
);
1095 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1096 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1100 * Stop data transfer because error(s) occurred.
1102 static void atmci_stop_transfer_pdc(struct atmel_mci
*host
)
1104 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTDIS
| ATMEL_PDC_TXTDIS
);
1107 static void atmci_stop_transfer_dma(struct atmel_mci
*host
)
1109 struct dma_chan
*chan
= host
->data_chan
;
1112 dmaengine_terminate_all(chan
);
1113 atmci_dma_cleanup(host
);
1115 /* Data transfer was stopped by the interrupt handler */
1116 dev_dbg(&host
->pdev
->dev
,
1117 "(%s) set pending xfer complete\n", __func__
);
1118 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1119 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1124 * Start a request: prepare data if needed, prepare the command and activate
1127 static void atmci_start_request(struct atmel_mci
*host
,
1128 struct atmel_mci_slot
*slot
)
1130 struct mmc_request
*mrq
;
1131 struct mmc_command
*cmd
;
1132 struct mmc_data
*data
;
1137 host
->cur_slot
= slot
;
1140 host
->pending_events
= 0;
1141 host
->completed_events
= 0;
1142 host
->cmd_status
= 0;
1143 host
->data_status
= 0;
1145 dev_dbg(&host
->pdev
->dev
, "start request: cmd %u\n", mrq
->cmd
->opcode
);
1147 if (host
->need_reset
|| host
->caps
.need_reset_after_xfer
) {
1148 iflags
= atmci_readl(host
, ATMCI_IMR
);
1149 iflags
&= (ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
);
1150 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1151 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1152 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1153 if (host
->caps
.has_cfg_reg
)
1154 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1155 atmci_writel(host
, ATMCI_IER
, iflags
);
1156 host
->need_reset
= false;
1158 atmci_writel(host
, ATMCI_SDCR
, slot
->sdc_reg
);
1160 iflags
= atmci_readl(host
, ATMCI_IMR
);
1161 if (iflags
& ~(ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
))
1162 dev_dbg(&slot
->mmc
->class_dev
, "WARNING: IMR=0x%08x\n",
1165 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT
, &slot
->flags
))) {
1166 /* Send init sequence (74 clock cycles) */
1167 atmci_writel(host
, ATMCI_CMDR
, ATMCI_CMDR_SPCMD_INIT
);
1168 while (!(atmci_readl(host
, ATMCI_SR
) & ATMCI_CMDRDY
))
1174 atmci_set_timeout(host
, slot
, data
);
1176 /* Must set block count/size before sending command */
1177 atmci_writel(host
, ATMCI_BLKR
, ATMCI_BCNT(data
->blocks
)
1178 | ATMCI_BLKLEN(data
->blksz
));
1179 dev_vdbg(&slot
->mmc
->class_dev
, "BLKR=0x%08x\n",
1180 ATMCI_BCNT(data
->blocks
) | ATMCI_BLKLEN(data
->blksz
));
1182 iflags
|= host
->prepare_data(host
, data
);
1185 iflags
|= ATMCI_CMDRDY
;
1187 cmdflags
= atmci_prepare_command(slot
->mmc
, cmd
);
1190 * DMA transfer should be started before sending the command to avoid
1191 * unexpected errors especially for read operations in SDIO mode.
1192 * Unfortunately, in PDC mode, command has to be sent before starting
1195 if (host
->submit_data
!= &atmci_submit_data_dma
)
1196 atmci_send_command(host
, cmd
, cmdflags
);
1199 host
->submit_data(host
, data
);
1201 if (host
->submit_data
== &atmci_submit_data_dma
)
1202 atmci_send_command(host
, cmd
, cmdflags
);
1205 host
->stop_cmdr
= atmci_prepare_command(slot
->mmc
, mrq
->stop
);
1206 host
->stop_cmdr
|= ATMCI_CMDR_STOP_XFER
;
1207 if (!(data
->flags
& MMC_DATA_WRITE
))
1208 host
->stop_cmdr
|= ATMCI_CMDR_TRDIR_READ
;
1209 if (data
->flags
& MMC_DATA_STREAM
)
1210 host
->stop_cmdr
|= ATMCI_CMDR_STREAM
;
1212 host
->stop_cmdr
|= ATMCI_CMDR_MULTI_BLOCK
;
1216 * We could have enabled interrupts earlier, but I suspect
1217 * that would open up a nice can of interesting race
1218 * conditions (e.g. command and data complete, but stop not
1221 atmci_writel(host
, ATMCI_IER
, iflags
);
1223 mod_timer(&host
->timer
, jiffies
+ msecs_to_jiffies(2000));
1226 static void atmci_queue_request(struct atmel_mci
*host
,
1227 struct atmel_mci_slot
*slot
, struct mmc_request
*mrq
)
1229 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1232 spin_lock_bh(&host
->lock
);
1234 if (host
->state
== STATE_IDLE
) {
1235 host
->state
= STATE_SENDING_CMD
;
1236 atmci_start_request(host
, slot
);
1238 dev_dbg(&host
->pdev
->dev
, "queue request\n");
1239 list_add_tail(&slot
->queue_node
, &host
->queue
);
1241 spin_unlock_bh(&host
->lock
);
1244 static void atmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1246 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1247 struct atmel_mci
*host
= slot
->host
;
1248 struct mmc_data
*data
;
1251 dev_dbg(&host
->pdev
->dev
, "MRQ: cmd %u\n", mrq
->cmd
->opcode
);
1254 * We may "know" the card is gone even though there's still an
1255 * electrical connection. If so, we really need to communicate
1256 * this to the MMC core since there won't be any more
1257 * interrupts as the card is completely removed. Otherwise,
1258 * the MMC core might believe the card is still there even
1259 * though the card was just removed very slowly.
1261 if (!test_bit(ATMCI_CARD_PRESENT
, &slot
->flags
)) {
1262 mrq
->cmd
->error
= -ENOMEDIUM
;
1263 mmc_request_done(mmc
, mrq
);
1267 /* We don't support multiple blocks of weird lengths. */
1269 if (data
&& data
->blocks
> 1 && data
->blksz
& 3) {
1270 mrq
->cmd
->error
= -EINVAL
;
1271 mmc_request_done(mmc
, mrq
);
1274 atmci_queue_request(host
, slot
, mrq
);
1277 static void atmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1279 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1280 struct atmel_mci
*host
= slot
->host
;
1284 slot
->sdc_reg
&= ~ATMCI_SDCBUS_MASK
;
1285 switch (ios
->bus_width
) {
1286 case MMC_BUS_WIDTH_1
:
1287 slot
->sdc_reg
|= ATMCI_SDCBUS_1BIT
;
1289 case MMC_BUS_WIDTH_4
:
1290 slot
->sdc_reg
|= ATMCI_SDCBUS_4BIT
;
1295 unsigned int clock_min
= ~0U;
1298 clk_prepare(host
->mck
);
1299 unprepare_clk
= true;
1301 spin_lock_bh(&host
->lock
);
1302 if (!host
->mode_reg
) {
1303 clk_enable(host
->mck
);
1304 unprepare_clk
= false;
1305 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1306 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1307 if (host
->caps
.has_cfg_reg
)
1308 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1312 * Use mirror of ios->clock to prevent race with mmc
1313 * core ios update when finding the minimum.
1315 slot
->clock
= ios
->clock
;
1316 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1317 if (host
->slot
[i
] && host
->slot
[i
]->clock
1318 && host
->slot
[i
]->clock
< clock_min
)
1319 clock_min
= host
->slot
[i
]->clock
;
1322 /* Calculate clock divider */
1323 if (host
->caps
.has_odd_clk_div
) {
1324 clkdiv
= DIV_ROUND_UP(host
->bus_hz
, clock_min
) - 2;
1326 dev_warn(&mmc
->class_dev
,
1327 "clock %u too slow; using %lu\n",
1328 clock_min
, host
->bus_hz
/ (511 + 2));
1331 host
->mode_reg
= ATMCI_MR_CLKDIV(clkdiv
>> 1)
1332 | ATMCI_MR_CLKODD(clkdiv
& 1);
1334 clkdiv
= DIV_ROUND_UP(host
->bus_hz
, 2 * clock_min
) - 1;
1336 dev_warn(&mmc
->class_dev
,
1337 "clock %u too slow; using %lu\n",
1338 clock_min
, host
->bus_hz
/ (2 * 256));
1341 host
->mode_reg
= ATMCI_MR_CLKDIV(clkdiv
);
1345 * WRPROOF and RDPROOF prevent overruns/underruns by
1346 * stopping the clock when the FIFO is full/empty.
1347 * This state is not expected to last for long.
1349 if (host
->caps
.has_rwproof
)
1350 host
->mode_reg
|= (ATMCI_MR_WRPROOF
| ATMCI_MR_RDPROOF
);
1352 if (host
->caps
.has_cfg_reg
) {
1353 /* setup High Speed mode in relation with card capacity */
1354 if (ios
->timing
== MMC_TIMING_SD_HS
)
1355 host
->cfg_reg
|= ATMCI_CFG_HSMODE
;
1357 host
->cfg_reg
&= ~ATMCI_CFG_HSMODE
;
1360 if (list_empty(&host
->queue
)) {
1361 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1362 if (host
->caps
.has_cfg_reg
)
1363 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1365 host
->need_clock_update
= true;
1368 spin_unlock_bh(&host
->lock
);
1370 bool any_slot_active
= false;
1372 unprepare_clk
= false;
1374 spin_lock_bh(&host
->lock
);
1376 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1377 if (host
->slot
[i
] && host
->slot
[i
]->clock
) {
1378 any_slot_active
= true;
1382 if (!any_slot_active
) {
1383 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIDIS
);
1384 if (host
->mode_reg
) {
1385 atmci_readl(host
, ATMCI_MR
);
1386 clk_disable(host
->mck
);
1387 unprepare_clk
= true;
1391 spin_unlock_bh(&host
->lock
);
1395 clk_unprepare(host
->mck
);
1397 switch (ios
->power_mode
) {
1399 if (!IS_ERR(mmc
->supply
.vmmc
))
1400 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1403 set_bit(ATMCI_CARD_NEED_INIT
, &slot
->flags
);
1404 if (!IS_ERR(mmc
->supply
.vmmc
))
1405 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, ios
->vdd
);
1409 * TODO: None of the currently available AVR32-based
1410 * boards allow MMC power to be turned off. Implement
1411 * power control when this can be tested properly.
1413 * We also need to hook this into the clock management
1414 * somehow so that newly inserted cards aren't
1415 * subjected to a fast clock before we have a chance
1416 * to figure out what the maximum rate is. Currently,
1417 * there's no way to avoid this, and there never will
1418 * be for boards that don't support power control.
1424 static int atmci_get_ro(struct mmc_host
*mmc
)
1426 int read_only
= -ENOSYS
;
1427 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1429 if (gpio_is_valid(slot
->wp_pin
)) {
1430 read_only
= gpio_get_value(slot
->wp_pin
);
1431 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1432 read_only
? "read-only" : "read-write");
1438 static int atmci_get_cd(struct mmc_host
*mmc
)
1440 int present
= -ENOSYS
;
1441 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1443 if (gpio_is_valid(slot
->detect_pin
)) {
1444 present
= !(gpio_get_value(slot
->detect_pin
) ^
1445 slot
->detect_is_active_high
);
1446 dev_dbg(&mmc
->class_dev
, "card is %spresent\n",
1447 present
? "" : "not ");
1453 static void atmci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1455 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1456 struct atmel_mci
*host
= slot
->host
;
1459 atmci_writel(host
, ATMCI_IER
, slot
->sdio_irq
);
1461 atmci_writel(host
, ATMCI_IDR
, slot
->sdio_irq
);
1464 static const struct mmc_host_ops atmci_ops
= {
1465 .request
= atmci_request
,
1466 .set_ios
= atmci_set_ios
,
1467 .get_ro
= atmci_get_ro
,
1468 .get_cd
= atmci_get_cd
,
1469 .enable_sdio_irq
= atmci_enable_sdio_irq
,
1472 /* Called with host->lock held */
1473 static void atmci_request_end(struct atmel_mci
*host
, struct mmc_request
*mrq
)
1474 __releases(&host
->lock
)
1475 __acquires(&host
->lock
)
1477 struct atmel_mci_slot
*slot
= NULL
;
1478 struct mmc_host
*prev_mmc
= host
->cur_slot
->mmc
;
1480 WARN_ON(host
->cmd
|| host
->data
);
1483 * Update the MMC clock rate if necessary. This may be
1484 * necessary if set_ios() is called when a different slot is
1485 * busy transferring data.
1487 if (host
->need_clock_update
) {
1488 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1489 if (host
->caps
.has_cfg_reg
)
1490 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1493 host
->cur_slot
->mrq
= NULL
;
1495 if (!list_empty(&host
->queue
)) {
1496 slot
= list_entry(host
->queue
.next
,
1497 struct atmel_mci_slot
, queue_node
);
1498 list_del(&slot
->queue_node
);
1499 dev_vdbg(&host
->pdev
->dev
, "list not empty: %s is next\n",
1500 mmc_hostname(slot
->mmc
));
1501 host
->state
= STATE_SENDING_CMD
;
1502 atmci_start_request(host
, slot
);
1504 dev_vdbg(&host
->pdev
->dev
, "list empty\n");
1505 host
->state
= STATE_IDLE
;
1508 del_timer(&host
->timer
);
1510 spin_unlock(&host
->lock
);
1511 mmc_request_done(prev_mmc
, mrq
);
1512 spin_lock(&host
->lock
);
1515 static void atmci_command_complete(struct atmel_mci
*host
,
1516 struct mmc_command
*cmd
)
1518 u32 status
= host
->cmd_status
;
1520 /* Read the response from the card (up to 16 bytes) */
1521 cmd
->resp
[0] = atmci_readl(host
, ATMCI_RSPR
);
1522 cmd
->resp
[1] = atmci_readl(host
, ATMCI_RSPR
);
1523 cmd
->resp
[2] = atmci_readl(host
, ATMCI_RSPR
);
1524 cmd
->resp
[3] = atmci_readl(host
, ATMCI_RSPR
);
1526 if (status
& ATMCI_RTOE
)
1527 cmd
->error
= -ETIMEDOUT
;
1528 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& ATMCI_RCRCE
))
1529 cmd
->error
= -EILSEQ
;
1530 else if (status
& (ATMCI_RINDE
| ATMCI_RDIRE
| ATMCI_RENDE
))
1532 else if (host
->mrq
->data
&& (host
->mrq
->data
->blksz
& 3)) {
1533 if (host
->caps
.need_blksz_mul_4
) {
1534 cmd
->error
= -EINVAL
;
1535 host
->need_reset
= 1;
1541 static void atmci_detect_change(unsigned long data
)
1543 struct atmel_mci_slot
*slot
= (struct atmel_mci_slot
*)data
;
1548 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1549 * freeing the interrupt. We must not re-enable the interrupt
1550 * if it has been freed, and if we're shutting down, it
1551 * doesn't really matter whether the card is present or not.
1554 if (test_bit(ATMCI_SHUTDOWN
, &slot
->flags
))
1557 enable_irq(gpio_to_irq(slot
->detect_pin
));
1558 present
= !(gpio_get_value(slot
->detect_pin
) ^
1559 slot
->detect_is_active_high
);
1560 present_old
= test_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1562 dev_vdbg(&slot
->mmc
->class_dev
, "detect change: %d (was %d)\n",
1563 present
, present_old
);
1565 if (present
!= present_old
) {
1566 struct atmel_mci
*host
= slot
->host
;
1567 struct mmc_request
*mrq
;
1569 dev_dbg(&slot
->mmc
->class_dev
, "card %s\n",
1570 present
? "inserted" : "removed");
1572 spin_lock(&host
->lock
);
1575 clear_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1577 set_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1579 /* Clean up queue if present */
1582 if (mrq
== host
->mrq
) {
1584 * Reset controller to terminate any ongoing
1585 * commands or data transfers.
1587 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1588 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1589 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1590 if (host
->caps
.has_cfg_reg
)
1591 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1596 switch (host
->state
) {
1599 case STATE_SENDING_CMD
:
1600 mrq
->cmd
->error
= -ENOMEDIUM
;
1602 host
->stop_transfer(host
);
1604 case STATE_DATA_XFER
:
1605 mrq
->data
->error
= -ENOMEDIUM
;
1606 host
->stop_transfer(host
);
1608 case STATE_WAITING_NOTBUSY
:
1609 mrq
->data
->error
= -ENOMEDIUM
;
1611 case STATE_SENDING_STOP
:
1612 mrq
->stop
->error
= -ENOMEDIUM
;
1614 case STATE_END_REQUEST
:
1618 atmci_request_end(host
, mrq
);
1620 list_del(&slot
->queue_node
);
1621 mrq
->cmd
->error
= -ENOMEDIUM
;
1623 mrq
->data
->error
= -ENOMEDIUM
;
1625 mrq
->stop
->error
= -ENOMEDIUM
;
1627 spin_unlock(&host
->lock
);
1628 mmc_request_done(slot
->mmc
, mrq
);
1629 spin_lock(&host
->lock
);
1632 spin_unlock(&host
->lock
);
1634 mmc_detect_change(slot
->mmc
, 0);
1638 static void atmci_tasklet_func(unsigned long priv
)
1640 struct atmel_mci
*host
= (struct atmel_mci
*)priv
;
1641 struct mmc_request
*mrq
= host
->mrq
;
1642 struct mmc_data
*data
= host
->data
;
1643 enum atmel_mci_state state
= host
->state
;
1644 enum atmel_mci_state prev_state
;
1647 spin_lock(&host
->lock
);
1649 state
= host
->state
;
1651 dev_vdbg(&host
->pdev
->dev
,
1652 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1653 state
, host
->pending_events
, host
->completed_events
,
1654 atmci_readl(host
, ATMCI_IMR
));
1658 dev_dbg(&host
->pdev
->dev
, "FSM: state=%d\n", state
);
1664 case STATE_SENDING_CMD
:
1666 * Command has been sent, we are waiting for command
1667 * ready. Then we have three next states possible:
1668 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1669 * command needing it or DATA_XFER if there is data.
1671 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready?\n");
1672 if (!atmci_test_and_clear_pending(host
,
1676 dev_dbg(&host
->pdev
->dev
, "set completed cmd ready\n");
1678 atmci_set_completed(host
, EVENT_CMD_RDY
);
1679 atmci_command_complete(host
, mrq
->cmd
);
1681 dev_dbg(&host
->pdev
->dev
,
1682 "command with data transfer");
1684 * If there is a command error don't start
1687 if (mrq
->cmd
->error
) {
1688 host
->stop_transfer(host
);
1690 atmci_writel(host
, ATMCI_IDR
,
1691 ATMCI_TXRDY
| ATMCI_RXRDY
1692 | ATMCI_DATA_ERROR_FLAGS
);
1693 state
= STATE_END_REQUEST
;
1695 state
= STATE_DATA_XFER
;
1696 } else if ((!mrq
->data
) && (mrq
->cmd
->flags
& MMC_RSP_BUSY
)) {
1697 dev_dbg(&host
->pdev
->dev
,
1698 "command response need waiting notbusy");
1699 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1700 state
= STATE_WAITING_NOTBUSY
;
1702 state
= STATE_END_REQUEST
;
1706 case STATE_DATA_XFER
:
1707 if (atmci_test_and_clear_pending(host
,
1708 EVENT_DATA_ERROR
)) {
1709 dev_dbg(&host
->pdev
->dev
, "set completed data error\n");
1710 atmci_set_completed(host
, EVENT_DATA_ERROR
);
1711 state
= STATE_END_REQUEST
;
1716 * A data transfer is in progress. The event expected
1717 * to move to the next state depends of data transfer
1718 * type (PDC or DMA). Once transfer done we can move
1719 * to the next step which is WAITING_NOTBUSY in write
1720 * case and directly SENDING_STOP in read case.
1722 dev_dbg(&host
->pdev
->dev
, "FSM: xfer complete?\n");
1723 if (!atmci_test_and_clear_pending(host
,
1724 EVENT_XFER_COMPLETE
))
1727 dev_dbg(&host
->pdev
->dev
,
1728 "(%s) set completed xfer complete\n",
1730 atmci_set_completed(host
, EVENT_XFER_COMPLETE
);
1732 if (host
->caps
.need_notbusy_for_read_ops
||
1733 (host
->data
->flags
& MMC_DATA_WRITE
)) {
1734 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1735 state
= STATE_WAITING_NOTBUSY
;
1736 } else if (host
->mrq
->stop
) {
1737 atmci_writel(host
, ATMCI_IER
, ATMCI_CMDRDY
);
1738 atmci_send_stop_cmd(host
, data
);
1739 state
= STATE_SENDING_STOP
;
1742 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1744 state
= STATE_END_REQUEST
;
1748 case STATE_WAITING_NOTBUSY
:
1750 * We can be in the state for two reasons: a command
1751 * requiring waiting not busy signal (stop command
1752 * included) or a write operation. In the latest case,
1753 * we need to send a stop command.
1755 dev_dbg(&host
->pdev
->dev
, "FSM: not busy?\n");
1756 if (!atmci_test_and_clear_pending(host
,
1760 dev_dbg(&host
->pdev
->dev
, "set completed not busy\n");
1761 atmci_set_completed(host
, EVENT_NOTBUSY
);
1765 * For some commands such as CMD53, even if
1766 * there is data transfer, there is no stop
1769 if (host
->mrq
->stop
) {
1770 atmci_writel(host
, ATMCI_IER
,
1772 atmci_send_stop_cmd(host
, data
);
1773 state
= STATE_SENDING_STOP
;
1776 data
->bytes_xfered
= data
->blocks
1779 state
= STATE_END_REQUEST
;
1782 state
= STATE_END_REQUEST
;
1785 case STATE_SENDING_STOP
:
1787 * In this state, it is important to set host->data to
1788 * NULL (which is tested in the waiting notbusy state)
1789 * in order to go to the end request state instead of
1790 * sending stop again.
1792 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready?\n");
1793 if (!atmci_test_and_clear_pending(host
,
1797 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready\n");
1799 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1801 atmci_command_complete(host
, mrq
->stop
);
1802 if (mrq
->stop
->error
) {
1803 host
->stop_transfer(host
);
1804 atmci_writel(host
, ATMCI_IDR
,
1805 ATMCI_TXRDY
| ATMCI_RXRDY
1806 | ATMCI_DATA_ERROR_FLAGS
);
1807 state
= STATE_END_REQUEST
;
1809 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1810 state
= STATE_WAITING_NOTBUSY
;
1815 case STATE_END_REQUEST
:
1816 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXRDY
| ATMCI_RXRDY
1817 | ATMCI_DATA_ERROR_FLAGS
);
1818 status
= host
->data_status
;
1819 if (unlikely(status
)) {
1820 host
->stop_transfer(host
);
1823 if (status
& ATMCI_DTOE
) {
1824 data
->error
= -ETIMEDOUT
;
1825 } else if (status
& ATMCI_DCRCE
) {
1826 data
->error
= -EILSEQ
;
1833 atmci_request_end(host
, host
->mrq
);
1837 } while (state
!= prev_state
);
1839 host
->state
= state
;
1841 spin_unlock(&host
->lock
);
1844 static void atmci_read_data_pio(struct atmel_mci
*host
)
1846 struct scatterlist
*sg
= host
->sg
;
1847 void *buf
= sg_virt(sg
);
1848 unsigned int offset
= host
->pio_offset
;
1849 struct mmc_data
*data
= host
->data
;
1852 unsigned int nbytes
= 0;
1855 value
= atmci_readl(host
, ATMCI_RDR
);
1856 if (likely(offset
+ 4 <= sg
->length
)) {
1857 put_unaligned(value
, (u32
*)(buf
+ offset
));
1862 if (offset
== sg
->length
) {
1863 flush_dcache_page(sg_page(sg
));
1864 host
->sg
= sg
= sg_next(sg
);
1866 if (!sg
|| !host
->sg_len
)
1873 unsigned int remaining
= sg
->length
- offset
;
1874 memcpy(buf
+ offset
, &value
, remaining
);
1875 nbytes
+= remaining
;
1877 flush_dcache_page(sg_page(sg
));
1878 host
->sg
= sg
= sg_next(sg
);
1880 if (!sg
|| !host
->sg_len
)
1883 offset
= 4 - remaining
;
1885 memcpy(buf
, (u8
*)&value
+ remaining
, offset
);
1889 status
= atmci_readl(host
, ATMCI_SR
);
1890 if (status
& ATMCI_DATA_ERROR_FLAGS
) {
1891 atmci_writel(host
, ATMCI_IDR
, (ATMCI_NOTBUSY
| ATMCI_RXRDY
1892 | ATMCI_DATA_ERROR_FLAGS
));
1893 host
->data_status
= status
;
1894 data
->bytes_xfered
+= nbytes
;
1897 } while (status
& ATMCI_RXRDY
);
1899 host
->pio_offset
= offset
;
1900 data
->bytes_xfered
+= nbytes
;
1905 atmci_writel(host
, ATMCI_IDR
, ATMCI_RXRDY
);
1906 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1907 data
->bytes_xfered
+= nbytes
;
1909 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1912 static void atmci_write_data_pio(struct atmel_mci
*host
)
1914 struct scatterlist
*sg
= host
->sg
;
1915 void *buf
= sg_virt(sg
);
1916 unsigned int offset
= host
->pio_offset
;
1917 struct mmc_data
*data
= host
->data
;
1920 unsigned int nbytes
= 0;
1923 if (likely(offset
+ 4 <= sg
->length
)) {
1924 value
= get_unaligned((u32
*)(buf
+ offset
));
1925 atmci_writel(host
, ATMCI_TDR
, value
);
1929 if (offset
== sg
->length
) {
1930 host
->sg
= sg
= sg_next(sg
);
1932 if (!sg
|| !host
->sg_len
)
1939 unsigned int remaining
= sg
->length
- offset
;
1942 memcpy(&value
, buf
+ offset
, remaining
);
1943 nbytes
+= remaining
;
1945 host
->sg
= sg
= sg_next(sg
);
1947 if (!sg
|| !host
->sg_len
) {
1948 atmci_writel(host
, ATMCI_TDR
, value
);
1952 offset
= 4 - remaining
;
1954 memcpy((u8
*)&value
+ remaining
, buf
, offset
);
1955 atmci_writel(host
, ATMCI_TDR
, value
);
1959 status
= atmci_readl(host
, ATMCI_SR
);
1960 if (status
& ATMCI_DATA_ERROR_FLAGS
) {
1961 atmci_writel(host
, ATMCI_IDR
, (ATMCI_NOTBUSY
| ATMCI_TXRDY
1962 | ATMCI_DATA_ERROR_FLAGS
));
1963 host
->data_status
= status
;
1964 data
->bytes_xfered
+= nbytes
;
1967 } while (status
& ATMCI_TXRDY
);
1969 host
->pio_offset
= offset
;
1970 data
->bytes_xfered
+= nbytes
;
1975 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXRDY
);
1976 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1977 data
->bytes_xfered
+= nbytes
;
1979 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1982 static void atmci_sdio_interrupt(struct atmel_mci
*host
, u32 status
)
1986 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1987 struct atmel_mci_slot
*slot
= host
->slot
[i
];
1988 if (slot
&& (status
& slot
->sdio_irq
)) {
1989 mmc_signal_sdio_irq(slot
->mmc
);
1995 static irqreturn_t
atmci_interrupt(int irq
, void *dev_id
)
1997 struct atmel_mci
*host
= dev_id
;
1998 u32 status
, mask
, pending
;
1999 unsigned int pass_count
= 0;
2002 status
= atmci_readl(host
, ATMCI_SR
);
2003 mask
= atmci_readl(host
, ATMCI_IMR
);
2004 pending
= status
& mask
;
2008 if (pending
& ATMCI_DATA_ERROR_FLAGS
) {
2009 dev_dbg(&host
->pdev
->dev
, "IRQ: data error\n");
2010 atmci_writel(host
, ATMCI_IDR
, ATMCI_DATA_ERROR_FLAGS
2011 | ATMCI_RXRDY
| ATMCI_TXRDY
2012 | ATMCI_ENDRX
| ATMCI_ENDTX
2013 | ATMCI_RXBUFF
| ATMCI_TXBUFE
);
2015 host
->data_status
= status
;
2016 dev_dbg(&host
->pdev
->dev
, "set pending data error\n");
2018 atmci_set_pending(host
, EVENT_DATA_ERROR
);
2019 tasklet_schedule(&host
->tasklet
);
2022 if (pending
& ATMCI_TXBUFE
) {
2023 dev_dbg(&host
->pdev
->dev
, "IRQ: tx buffer empty\n");
2024 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXBUFE
);
2025 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDTX
);
2027 * We can receive this interruption before having configured
2028 * the second pdc buffer, so we need to reconfigure first and
2029 * second buffers again
2031 if (host
->data_size
) {
2032 atmci_pdc_set_both_buf(host
, XFER_TRANSMIT
);
2033 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDTX
);
2034 atmci_writel(host
, ATMCI_IER
, ATMCI_TXBUFE
);
2036 atmci_pdc_complete(host
);
2038 } else if (pending
& ATMCI_ENDTX
) {
2039 dev_dbg(&host
->pdev
->dev
, "IRQ: end of tx buffer\n");
2040 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDTX
);
2042 if (host
->data_size
) {
2043 atmci_pdc_set_single_buf(host
,
2044 XFER_TRANSMIT
, PDC_SECOND_BUF
);
2045 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDTX
);
2049 if (pending
& ATMCI_RXBUFF
) {
2050 dev_dbg(&host
->pdev
->dev
, "IRQ: rx buffer full\n");
2051 atmci_writel(host
, ATMCI_IDR
, ATMCI_RXBUFF
);
2052 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDRX
);
2054 * We can receive this interruption before having configured
2055 * the second pdc buffer, so we need to reconfigure first and
2056 * second buffers again
2058 if (host
->data_size
) {
2059 atmci_pdc_set_both_buf(host
, XFER_RECEIVE
);
2060 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDRX
);
2061 atmci_writel(host
, ATMCI_IER
, ATMCI_RXBUFF
);
2063 atmci_pdc_complete(host
);
2065 } else if (pending
& ATMCI_ENDRX
) {
2066 dev_dbg(&host
->pdev
->dev
, "IRQ: end of rx buffer\n");
2067 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDRX
);
2069 if (host
->data_size
) {
2070 atmci_pdc_set_single_buf(host
,
2071 XFER_RECEIVE
, PDC_SECOND_BUF
);
2072 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDRX
);
2077 * First mci IPs, so mainly the ones having pdc, have some
2078 * issues with the notbusy signal. You can't get it after
2079 * data transmission if you have not sent a stop command.
2080 * The appropriate workaround is to use the BLKE signal.
2082 if (pending
& ATMCI_BLKE
) {
2083 dev_dbg(&host
->pdev
->dev
, "IRQ: blke\n");
2084 atmci_writel(host
, ATMCI_IDR
, ATMCI_BLKE
);
2086 dev_dbg(&host
->pdev
->dev
, "set pending notbusy\n");
2087 atmci_set_pending(host
, EVENT_NOTBUSY
);
2088 tasklet_schedule(&host
->tasklet
);
2091 if (pending
& ATMCI_NOTBUSY
) {
2092 dev_dbg(&host
->pdev
->dev
, "IRQ: not_busy\n");
2093 atmci_writel(host
, ATMCI_IDR
, ATMCI_NOTBUSY
);
2095 dev_dbg(&host
->pdev
->dev
, "set pending notbusy\n");
2096 atmci_set_pending(host
, EVENT_NOTBUSY
);
2097 tasklet_schedule(&host
->tasklet
);
2100 if (pending
& ATMCI_RXRDY
)
2101 atmci_read_data_pio(host
);
2102 if (pending
& ATMCI_TXRDY
)
2103 atmci_write_data_pio(host
);
2105 if (pending
& ATMCI_CMDRDY
) {
2106 dev_dbg(&host
->pdev
->dev
, "IRQ: cmd ready\n");
2107 atmci_writel(host
, ATMCI_IDR
, ATMCI_CMDRDY
);
2108 host
->cmd_status
= status
;
2110 dev_dbg(&host
->pdev
->dev
, "set pending cmd rdy\n");
2111 atmci_set_pending(host
, EVENT_CMD_RDY
);
2112 tasklet_schedule(&host
->tasklet
);
2115 if (pending
& (ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
))
2116 atmci_sdio_interrupt(host
, status
);
2118 } while (pass_count
++ < 5);
2120 return pass_count
? IRQ_HANDLED
: IRQ_NONE
;
2123 static irqreturn_t
atmci_detect_interrupt(int irq
, void *dev_id
)
2125 struct atmel_mci_slot
*slot
= dev_id
;
2128 * Disable interrupts until the pin has stabilized and check
2129 * the state then. Use mod_timer() since we may be in the
2130 * middle of the timer routine when this interrupt triggers.
2132 disable_irq_nosync(irq
);
2133 mod_timer(&slot
->detect_timer
, jiffies
+ msecs_to_jiffies(20));
2138 static int __init
atmci_init_slot(struct atmel_mci
*host
,
2139 struct mci_slot_pdata
*slot_data
, unsigned int id
,
2140 u32 sdc_reg
, u32 sdio_irq
)
2142 struct mmc_host
*mmc
;
2143 struct atmel_mci_slot
*slot
;
2145 mmc
= mmc_alloc_host(sizeof(struct atmel_mci_slot
), &host
->pdev
->dev
);
2149 slot
= mmc_priv(mmc
);
2152 slot
->detect_pin
= slot_data
->detect_pin
;
2153 slot
->wp_pin
= slot_data
->wp_pin
;
2154 slot
->detect_is_active_high
= slot_data
->detect_is_active_high
;
2155 slot
->sdc_reg
= sdc_reg
;
2156 slot
->sdio_irq
= sdio_irq
;
2158 dev_dbg(&mmc
->class_dev
,
2159 "slot[%u]: bus_width=%u, detect_pin=%d, "
2160 "detect_is_active_high=%s, wp_pin=%d\n",
2161 id
, slot_data
->bus_width
, slot_data
->detect_pin
,
2162 slot_data
->detect_is_active_high
? "true" : "false",
2165 mmc
->ops
= &atmci_ops
;
2166 mmc
->f_min
= DIV_ROUND_UP(host
->bus_hz
, 512);
2167 mmc
->f_max
= host
->bus_hz
/ 2;
2168 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2170 mmc
->caps
|= MMC_CAP_SDIO_IRQ
;
2171 if (host
->caps
.has_highspeed
)
2172 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
2174 * Without the read/write proof capability, it is strongly suggested to
2175 * use only one bit for data to prevent fifo underruns and overruns
2176 * which will corrupt data.
2178 if ((slot_data
->bus_width
>= 4) && host
->caps
.has_rwproof
)
2179 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2181 if (atmci_get_version(host
) < 0x200) {
2182 mmc
->max_segs
= 256;
2183 mmc
->max_blk_size
= 4095;
2184 mmc
->max_blk_count
= 256;
2185 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
2186 mmc
->max_seg_size
= mmc
->max_blk_size
* mmc
->max_segs
;
2189 mmc
->max_req_size
= 32768 * 512;
2190 mmc
->max_blk_size
= 32768;
2191 mmc
->max_blk_count
= 512;
2194 /* Assume card is present initially */
2195 set_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
2196 if (gpio_is_valid(slot
->detect_pin
)) {
2197 if (gpio_request(slot
->detect_pin
, "mmc_detect")) {
2198 dev_dbg(&mmc
->class_dev
, "no detect pin available\n");
2199 slot
->detect_pin
= -EBUSY
;
2200 } else if (gpio_get_value(slot
->detect_pin
) ^
2201 slot
->detect_is_active_high
) {
2202 clear_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
2206 if (!gpio_is_valid(slot
->detect_pin
))
2207 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2209 if (gpio_is_valid(slot
->wp_pin
)) {
2210 if (gpio_request(slot
->wp_pin
, "mmc_wp")) {
2211 dev_dbg(&mmc
->class_dev
, "no WP pin available\n");
2212 slot
->wp_pin
= -EBUSY
;
2216 host
->slot
[id
] = slot
;
2217 mmc_regulator_get_supply(mmc
);
2220 if (gpio_is_valid(slot
->detect_pin
)) {
2223 setup_timer(&slot
->detect_timer
, atmci_detect_change
,
2224 (unsigned long)slot
);
2226 ret
= request_irq(gpio_to_irq(slot
->detect_pin
),
2227 atmci_detect_interrupt
,
2228 IRQF_TRIGGER_FALLING
| IRQF_TRIGGER_RISING
,
2229 "mmc-detect", slot
);
2231 dev_dbg(&mmc
->class_dev
,
2232 "could not request IRQ %d for detect pin\n",
2233 gpio_to_irq(slot
->detect_pin
));
2234 gpio_free(slot
->detect_pin
);
2235 slot
->detect_pin
= -EBUSY
;
2239 atmci_init_debugfs(slot
);
2244 static void __exit
atmci_cleanup_slot(struct atmel_mci_slot
*slot
,
2247 /* Debugfs stuff is cleaned up by mmc core */
2249 set_bit(ATMCI_SHUTDOWN
, &slot
->flags
);
2252 mmc_remove_host(slot
->mmc
);
2254 if (gpio_is_valid(slot
->detect_pin
)) {
2255 int pin
= slot
->detect_pin
;
2257 free_irq(gpio_to_irq(pin
), slot
);
2258 del_timer_sync(&slot
->detect_timer
);
2261 if (gpio_is_valid(slot
->wp_pin
))
2262 gpio_free(slot
->wp_pin
);
2264 slot
->host
->slot
[id
] = NULL
;
2265 mmc_free_host(slot
->mmc
);
2268 static bool atmci_filter(struct dma_chan
*chan
, void *pdata
)
2270 struct mci_platform_data
*sl_pdata
= pdata
;
2271 struct mci_dma_data
*sl
;
2276 sl
= sl_pdata
->dma_slave
;
2277 if (sl
&& find_slave_dev(sl
) == chan
->device
->dev
) {
2278 chan
->private = slave_data_ptr(sl
);
2285 static bool atmci_configure_dma(struct atmel_mci
*host
)
2287 struct mci_platform_data
*pdata
;
2288 dma_cap_mask_t mask
;
2293 pdata
= host
->pdev
->dev
.platform_data
;
2296 dma_cap_set(DMA_SLAVE
, mask
);
2298 host
->dma
.chan
= dma_request_slave_channel_compat(mask
, atmci_filter
, pdata
,
2299 &host
->pdev
->dev
, "rxtx");
2300 if (!host
->dma
.chan
) {
2301 dev_warn(&host
->pdev
->dev
, "no DMA channel available\n");
2304 dev_info(&host
->pdev
->dev
,
2305 "using %s for DMA transfers\n",
2306 dma_chan_name(host
->dma
.chan
));
2308 host
->dma_conf
.src_addr
= host
->mapbase
+ ATMCI_RDR
;
2309 host
->dma_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
2310 host
->dma_conf
.src_maxburst
= 1;
2311 host
->dma_conf
.dst_addr
= host
->mapbase
+ ATMCI_TDR
;
2312 host
->dma_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
2313 host
->dma_conf
.dst_maxburst
= 1;
2314 host
->dma_conf
.device_fc
= false;
2320 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2321 * HSMCI provides DMA support and a new config register but no more supports
2324 static void __init
atmci_get_cap(struct atmel_mci
*host
)
2326 unsigned int version
;
2328 version
= atmci_get_version(host
);
2329 dev_info(&host
->pdev
->dev
,
2330 "version: 0x%x\n", version
);
2332 host
->caps
.has_dma_conf_reg
= 0;
2333 host
->caps
.has_pdc
= ATMCI_PDC_CONNECTED
;
2334 host
->caps
.has_cfg_reg
= 0;
2335 host
->caps
.has_cstor_reg
= 0;
2336 host
->caps
.has_highspeed
= 0;
2337 host
->caps
.has_rwproof
= 0;
2338 host
->caps
.has_odd_clk_div
= 0;
2339 host
->caps
.has_bad_data_ordering
= 1;
2340 host
->caps
.need_reset_after_xfer
= 1;
2341 host
->caps
.need_blksz_mul_4
= 1;
2342 host
->caps
.need_notbusy_for_read_ops
= 0;
2344 /* keep only major version number */
2345 switch (version
& 0xf00) {
2347 host
->caps
.has_odd_clk_div
= 1;
2350 host
->caps
.has_dma_conf_reg
= 1;
2351 host
->caps
.has_pdc
= 0;
2352 host
->caps
.has_cfg_reg
= 1;
2353 host
->caps
.has_cstor_reg
= 1;
2354 host
->caps
.has_highspeed
= 1;
2356 host
->caps
.has_rwproof
= 1;
2357 host
->caps
.need_blksz_mul_4
= 0;
2358 host
->caps
.need_notbusy_for_read_ops
= 1;
2360 host
->caps
.has_bad_data_ordering
= 0;
2361 host
->caps
.need_reset_after_xfer
= 0;
2365 host
->caps
.has_pdc
= 0;
2366 dev_warn(&host
->pdev
->dev
,
2367 "Unmanaged mci version, set minimum capabilities\n");
2372 static int __init
atmci_probe(struct platform_device
*pdev
)
2374 struct mci_platform_data
*pdata
;
2375 struct atmel_mci
*host
;
2376 struct resource
*regs
;
2377 unsigned int nr_slots
;
2381 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2384 pdata
= pdev
->dev
.platform_data
;
2386 pdata
= atmci_of_init(pdev
);
2387 if (IS_ERR(pdata
)) {
2388 dev_err(&pdev
->dev
, "platform data not available\n");
2389 return PTR_ERR(pdata
);
2393 irq
= platform_get_irq(pdev
, 0);
2397 host
= kzalloc(sizeof(struct atmel_mci
), GFP_KERNEL
);
2402 spin_lock_init(&host
->lock
);
2403 INIT_LIST_HEAD(&host
->queue
);
2405 host
->mck
= clk_get(&pdev
->dev
, "mci_clk");
2406 if (IS_ERR(host
->mck
)) {
2407 ret
= PTR_ERR(host
->mck
);
2412 host
->regs
= ioremap(regs
->start
, resource_size(regs
));
2416 ret
= clk_prepare_enable(host
->mck
);
2418 goto err_request_irq
;
2419 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
2420 host
->bus_hz
= clk_get_rate(host
->mck
);
2421 clk_disable_unprepare(host
->mck
);
2423 host
->mapbase
= regs
->start
;
2425 tasklet_init(&host
->tasklet
, atmci_tasklet_func
, (unsigned long)host
);
2427 ret
= request_irq(irq
, atmci_interrupt
, 0, dev_name(&pdev
->dev
), host
);
2429 goto err_request_irq
;
2431 /* Get MCI capabilities and set operations according to it */
2432 atmci_get_cap(host
);
2433 if (atmci_configure_dma(host
)) {
2434 host
->prepare_data
= &atmci_prepare_data_dma
;
2435 host
->submit_data
= &atmci_submit_data_dma
;
2436 host
->stop_transfer
= &atmci_stop_transfer_dma
;
2437 } else if (host
->caps
.has_pdc
) {
2438 dev_info(&pdev
->dev
, "using PDC\n");
2439 host
->prepare_data
= &atmci_prepare_data_pdc
;
2440 host
->submit_data
= &atmci_submit_data_pdc
;
2441 host
->stop_transfer
= &atmci_stop_transfer_pdc
;
2443 dev_info(&pdev
->dev
, "using PIO\n");
2444 host
->prepare_data
= &atmci_prepare_data
;
2445 host
->submit_data
= &atmci_submit_data
;
2446 host
->stop_transfer
= &atmci_stop_transfer
;
2449 platform_set_drvdata(pdev
, host
);
2451 setup_timer(&host
->timer
, atmci_timeout_timer
, (unsigned long)host
);
2453 /* We need at least one slot to succeed */
2456 if (pdata
->slot
[0].bus_width
) {
2457 ret
= atmci_init_slot(host
, &pdata
->slot
[0],
2458 0, ATMCI_SDCSEL_SLOT_A
, ATMCI_SDIOIRQA
);
2461 host
->buf_size
= host
->slot
[0]->mmc
->max_req_size
;
2464 if (pdata
->slot
[1].bus_width
) {
2465 ret
= atmci_init_slot(host
, &pdata
->slot
[1],
2466 1, ATMCI_SDCSEL_SLOT_B
, ATMCI_SDIOIRQB
);
2469 if (host
->slot
[1]->mmc
->max_req_size
> host
->buf_size
)
2471 host
->slot
[1]->mmc
->max_req_size
;
2476 dev_err(&pdev
->dev
, "init failed: no slot defined\n");
2480 if (!host
->caps
.has_rwproof
) {
2481 host
->buffer
= dma_alloc_coherent(&pdev
->dev
, host
->buf_size
,
2482 &host
->buf_phys_addr
,
2484 if (!host
->buffer
) {
2486 dev_err(&pdev
->dev
, "buffer allocation failed\n");
2491 dev_info(&pdev
->dev
,
2492 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2493 host
->mapbase
, irq
, nr_slots
);
2499 dma_release_channel(host
->dma
.chan
);
2500 free_irq(irq
, host
);
2502 iounmap(host
->regs
);
2510 static int __exit
atmci_remove(struct platform_device
*pdev
)
2512 struct atmel_mci
*host
= platform_get_drvdata(pdev
);
2516 dma_free_coherent(&pdev
->dev
, host
->buf_size
,
2517 host
->buffer
, host
->buf_phys_addr
);
2519 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
2521 atmci_cleanup_slot(host
->slot
[i
], i
);
2524 clk_prepare_enable(host
->mck
);
2525 atmci_writel(host
, ATMCI_IDR
, ~0UL);
2526 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIDIS
);
2527 atmci_readl(host
, ATMCI_SR
);
2528 clk_disable_unprepare(host
->mck
);
2531 dma_release_channel(host
->dma
.chan
);
2533 free_irq(platform_get_irq(pdev
, 0), host
);
2534 iounmap(host
->regs
);
2542 static struct platform_driver atmci_driver
= {
2543 .remove
= __exit_p(atmci_remove
),
2545 .name
= "atmel_mci",
2546 .of_match_table
= of_match_ptr(atmci_dt_ids
),
2550 static int __init
atmci_init(void)
2552 return platform_driver_probe(&atmci_driver
, atmci_probe
);
2555 static void __exit
atmci_exit(void)
2557 platform_driver_unregister(&atmci_driver
);
2560 late_initcall(atmci_init
); /* try to load after dma driver when built-in */
2561 module_exit(atmci_exit
);
2563 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2564 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2565 MODULE_LICENSE("GPL v2");