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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/mmc/host/dw_mmc-exynos.h
0280d394a32ab493fa49c9c636fd201e84136dae
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
5 * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
8 #ifndef _DW_MMC_EXYNOS_H_
9 #define _DW_MMC_EXYNOS_H_
11 #define SDMMC_CLKSEL 0x09C
12 #define SDMMC_CLKSEL64 0x0A8
14 /* Extended Register's Offset */
15 #define SDMMC_HS400_DQS_EN 0x180
16 #define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
17 #define SDMMC_HS400_DLINE_CTRL 0x188
19 /* CLKSEL register defines */
20 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
21 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
22 #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
23 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
24 #define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7)
25 #define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
26 SDMMC_CLKSEL_CCLK_SAMPLE(y))
27 #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
28 SDMMC_CLKSEL_CCLK_DRIVE(y) | \
29 SDMMC_CLKSEL_CCLK_DIVIDER(z))
30 #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
31 #define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
33 /* RCLK_EN register defines */
34 #define DATA_STROBE_EN BIT(0)
35 #define AXI_NON_BLOCKING_WR BIT(7)
37 /* DLINE_CTRL register defines */
38 #define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF))
39 #define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF)
41 /* Protector Register */
42 #define SDMMC_EMMCP_BASE 0x1000
43 #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
44 #define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
45 #define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
46 #define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
48 /* SMU control defines */
49 #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
50 #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
51 #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
52 #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
53 #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3)
54 #define SDMMC_MPSCTRL_ECB_MODE BIT(2)
55 #define SDMMC_MPSCTRL_ENCRYPTION BIT(1)
56 #define SDMMC_MPSCTRL_VALID BIT(0)
58 /* Maximum number of Ending sector */
59 #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
61 /* Fixed clock divider */
62 #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
63 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
64 #define HS400_FIXED_CIU_CLK_DIV 1
66 /* Minimal required clock frequency for cclkin, unit: HZ */
67 #define EXYNOS_CCLKIN_MIN 50000000
69 #endif /* _DW_MMC_EXYNOS_H_ */