drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/clk.h>
  13 #include <linux/mmc/host.h>
  14 #include <linux/mmc/dw_mmc.h>
  15 #include <linux/of_address.h>
  16 #include <linux/mmc/slot-gpio.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #include "dw_mmc.h"
  21 #include "dw_mmc-pltfm.h"
  22
  23 #define RK3288_CLKGEN_DIV       2
  24
  25 struct dw_mci_rockchip_priv_data {
  26         struct clk              *drv_clk;
  27         struct clk              *sample_clk;
  28         int                     default_sample_phase;
  29 };
  30
  31 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  32 {
  33         struct dw_mci_rockchip_priv_data *priv = host->priv;
  34         int ret;
  35         unsigned int cclkin;
  36         u32 bus_hz;
  37
  38         if (ios->clock == 0)
  39                 return;
  40
  41         /*
  42          * cclkin: source clock of mmc controller
  43          * bus_hz: card interface clock generated by CLKGEN
  44          * bus_hz = cclkin / RK3288_CLKGEN_DIV
  45          * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
  46          *
  47          * Note: div can only be 0 or 1
  48          *       if DDR50 8bit mode(only emmc work in 8bit mode),
  49          *       div must be set 1
  50          */
  51         if (ios->bus_width == MMC_BUS_WIDTH_8 &&
  52             ios->timing == MMC_TIMING_MMC_DDR52)
  53                 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
  54         else
  55                 cclkin = ios->clock * RK3288_CLKGEN_DIV;
  56
  57         ret = clk_set_rate(host->ciu_clk, cclkin);
  58         if (ret)
  59                 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  60
  61         bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
  62         if (bus_hz != host->bus_hz) {
  63                 host->bus_hz = bus_hz;
  64                 /* force dw_mci_setup_bus() */
  65                 host->current_speed = 0;
  66         }
  67
  68         /* Make sure we use phases which we can enumerate with */
  69         if (!IS_ERR(priv->sample_clk))
  70                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  71
  72         /*
  73          * Set the drive phase offset based on speed mode to achieve hold times.
  74          *
  75          * NOTE: this is _not_ a value that is dynamically tuned and is also
  76          * _not_ a value that will vary from board to board.  It is a value
  77          * that could vary between different SoC models if they had massively
  78          * different output clock delays inside their dw_mmc IP block (delay_o),
  79          * but since it's OK to overshoot a little we don't need to do complex
  80          * calculations and can pick values that will just work for everyone.
  81          *
  82          * When picking values we'll stick with picking 0/90/180/270 since
  83          * those can be made very accurately on all known Rockchip SoCs.
  84          *
  85          * Note that these values match values from the DesignWare Databook
  86          * tables for the most part except for SDR12 and "ID mode".  For those
  87          * two modes the databook calculations assume a clock in of 50MHz.  As
  88          * seen above, we always use a clock in rate that is exactly the
  89          * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
  90          * back out before the controller sees it).
  91          *
  92          * From measurement of a single device, it appears that delay_o is
  93          * about .5 ns.  Since we try to leave a bit of margin, it's expected
  94          * that numbers here will be fine even with much larger delay_o
  95          * (the 1.4 ns assumed by the DesignWare Databook would result in the
  96          * same results, for instance).
  97          */
  98         if (!IS_ERR(priv->drv_clk)) {
  99                 int phase;
 100
 101                 /*
 102                  * In almost all cases a 90 degree phase offset will provide
 103                  * sufficient hold times across all valid input clock rates
 104                  * assuming delay_o is not absurd for a given SoC.  We'll use
 105                  * that as a default.
 106                  */
 107                 phase = 90;
 108
 109                 switch (ios->timing) {
 110                 case MMC_TIMING_MMC_DDR52:
 111                         /*
 112                          * Since clock in rate with MMC_DDR52 is doubled when
 113                          * bus width is 8 we need to double the phase offset
 114                          * to get the same timings.
 115                          */
 116                         if (ios->bus_width == MMC_BUS_WIDTH_8)
 117                                 phase = 180;
 118                         break;
 119                 case MMC_TIMING_UHS_SDR104:
 120                 case MMC_TIMING_MMC_HS200:
 121                         /*
 122                          * In the case of 150 MHz clock (typical max for
 123                          * Rockchip SoCs), 90 degree offset will add a delay
 124                          * of 1.67 ns.  That will meet min hold time of .8 ns
 125                          * as long as clock output delay is < .87 ns.  On
 126                          * SoCs measured this seems to be OK, but it doesn't
 127                          * hurt to give margin here, so we use 180.
 128                          */
 129                         phase = 180;
 130                         break;
 131                 }
 132
 133                 clk_set_phase(priv->drv_clk, phase);
 134         }
 135 }
 136
 137 #define NUM_PHASES                      360
 138 #define TUNING_ITERATION_TO_PHASE(i)    (DIV_ROUND_UP((i) * 360, NUM_PHASES))
 139
 140 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 141 {
 142         struct dw_mci *host = slot->host;
 143         struct dw_mci_rockchip_priv_data *priv = host->priv;
 144         struct mmc_host *mmc = slot->mmc;
 145         int ret = 0;
 146         int i;
 147         bool v, prev_v = 0, first_v;
 148         struct range_t {
 149                 int start;
 150                 int end; /* inclusive */
 151         };
 152         struct range_t *ranges;
 153         unsigned int range_count = 0;
 154         int longest_range_len = -1;
 155         int longest_range = -1;
 156         int middle_phase;
 157
 158         if (IS_ERR(priv->sample_clk)) {
 159                 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
 160                 return -EIO;
 161         }
 162
 163         ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
 164         if (!ranges)
 165                 return -ENOMEM;
 166
 167         /* Try each phase and extract good ranges */
 168         for (i = 0; i < NUM_PHASES; ) {
 169                 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
 170
 171                 v = !mmc_send_tuning(mmc, opcode, NULL);
 172
 173                 if (i == 0)
 174                         first_v = v;
 175
 176                 if ((!prev_v) && v) {
 177                         range_count++;
 178                         ranges[range_count-1].start = i;
 179                 }
 180                 if (v) {
 181                         ranges[range_count-1].end = i;
 182                         i++;
 183                 } else if (i == NUM_PHASES - 1) {
 184                         /* No extra skipping rules if we're at the end */
 185                         i++;
 186                 } else {
 187                         /*
 188                          * No need to check too close to an invalid
 189                          * one since testing bad phases is slow.  Skip
 190                          * 20 degrees.
 191                          */
 192                         i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
 193
 194                         /* Always test the last one */
 195                         if (i >= NUM_PHASES)
 196                                 i = NUM_PHASES - 1;
 197                 }
 198
 199                 prev_v = v;
 200         }
 201
 202         if (range_count == 0) {
 203                 dev_warn(host->dev, "All phases bad!");
 204                 ret = -EIO;
 205                 goto free;
 206         }
 207
 208         /* wrap around case, merge the end points */
 209         if ((range_count > 1) && first_v && v) {
 210                 ranges[0].start = ranges[range_count-1].start;
 211                 range_count--;
 212         }
 213
 214         if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
 215                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
 216                 dev_info(host->dev, "All phases work, using default phase %d.",
 217                          priv->default_sample_phase);
 218                 goto free;
 219         }
 220
 221         /* Find the longest range */
 222         for (i = 0; i < range_count; i++) {
 223                 int len = (ranges[i].end - ranges[i].start + 1);
 224
 225                 if (len < 0)
 226                         len += NUM_PHASES;
 227
 228                 if (longest_range_len < len) {
 229                         longest_range_len = len;
 230                         longest_range = i;
 231                 }
 232
 233                 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
 234                         TUNING_ITERATION_TO_PHASE(ranges[i].start),
 235                         TUNING_ITERATION_TO_PHASE(ranges[i].end),
 236                         len
 237                 );
 238         }
 239
 240         dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
 241                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
 242                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
 243                 longest_range_len
 244         );
 245
 246         middle_phase = ranges[longest_range].start + longest_range_len / 2;
 247         middle_phase %= NUM_PHASES;
 248         dev_info(host->dev, "Successfully tuned phase to %d\n",
 249                  TUNING_ITERATION_TO_PHASE(middle_phase));
 250
 251         clk_set_phase(priv->sample_clk,
 252                       TUNING_ITERATION_TO_PHASE(middle_phase));
 253
 254 free:
 255         kfree(ranges);
 256         return ret;
 257 }
 258
 259 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
 260 {
 261         struct device_node *np = host->dev->of_node;
 262         struct dw_mci_rockchip_priv_data *priv;
 263
 264         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 265         if (!priv)
 266                 return -ENOMEM;
 267
 268         if (of_property_read_u32(np, "rockchip,default-sample-phase",
 269                                         &priv->default_sample_phase))
 270                 priv->default_sample_phase = 0;
 271
 272         priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
 273         if (IS_ERR(priv->drv_clk))
 274                 dev_dbg(host->dev, "ciu_drv not available\n");
 275
 276         priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
 277         if (IS_ERR(priv->sample_clk))
 278                 dev_dbg(host->dev, "ciu_sample not available\n");
 279
 280         host->priv = priv;
 281
 282         return 0;
 283 }
 284
 285 static int dw_mci_rockchip_init(struct dw_mci *host)
 286 {
 287         /* It is slot 8 on Rockchip SoCs */
 288         host->sdio_id0 = 8;
 289
 290         if (of_device_is_compatible(host->dev->of_node,
 291                                     "rockchip,rk3288-dw-mshc"))
 292                 host->bus_hz /= RK3288_CLKGEN_DIV;
 293
 294         return 0;
 295 }
 296
 297 /* Common capabilities of RK3288 SoC */
 298 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
 299         MMC_CAP_CMD23,
 300         MMC_CAP_CMD23,
 301         MMC_CAP_CMD23,
 302         MMC_CAP_CMD23,
 303 };
 304
 305 static const struct dw_mci_drv_data rk2928_drv_data = {
 306         .init                   = dw_mci_rockchip_init,
 307 };
 308
 309 static const struct dw_mci_drv_data rk3288_drv_data = {
 310         .caps                   = dw_mci_rk3288_dwmmc_caps,
 311         .set_ios                = dw_mci_rk3288_set_ios,
 312         .execute_tuning         = dw_mci_rk3288_execute_tuning,
 313         .parse_dt               = dw_mci_rk3288_parse_dt,
 314         .init                   = dw_mci_rockchip_init,
 315 };
 316
 317 static const struct of_device_id dw_mci_rockchip_match[] = {
 318         { .compatible = "rockchip,rk2928-dw-mshc",
 319                 .data = &rk2928_drv_data },
 320         { .compatible = "rockchip,rk3288-dw-mshc",
 321                 .data = &rk3288_drv_data },
 322         {},
 323 };
 324 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 325
 326 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 327 {
 328         const struct dw_mci_drv_data *drv_data;
 329         const struct of_device_id *match;
 330         int ret;
 331
 332         if (!pdev->dev.of_node)
 333                 return -ENODEV;
 334
 335         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 336         drv_data = match->data;
 337
 338         pm_runtime_get_noresume(&pdev->dev);
 339         pm_runtime_set_active(&pdev->dev);
 340         pm_runtime_enable(&pdev->dev);
 341         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 342         pm_runtime_use_autosuspend(&pdev->dev);
 343
 344         ret = dw_mci_pltfm_register(pdev, drv_data);
 345         if (ret) {
 346                 pm_runtime_disable(&pdev->dev);
 347                 pm_runtime_set_suspended(&pdev->dev);
 348                 pm_runtime_put_noidle(&pdev->dev);
 349                 return ret;
 350         }
 351
 352         pm_runtime_put_autosuspend(&pdev->dev);
 353
 354         return 0;
 355 }
 356
 357 static int dw_mci_rockchip_remove(struct platform_device *pdev)
 358 {
 359         pm_runtime_get_sync(&pdev->dev);
 360         pm_runtime_disable(&pdev->dev);
 361         pm_runtime_put_noidle(&pdev->dev);
 362
 363         return dw_mci_pltfm_remove(pdev);
 364 }
 365
 366 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
 367         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 368                                 pm_runtime_force_resume)
 369         SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
 370                            dw_mci_runtime_resume,
 371                            NULL)
 372 };
 373
 374 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 375         .probe          = dw_mci_rockchip_probe,
 376         .remove         = dw_mci_rockchip_remove,
 377         .driver         = {
 378                 .name           = "dwmmc_rockchip",
 379                 .of_match_table = dw_mci_rockchip_match,
 380                 .pm             = &dw_mci_rockchip_dev_pm_ops,
 381         },
 382 };
 383
 384 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 385
 386 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 387 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
 388 MODULE_ALIAS("platform:dwmmc_rockchip");
 389 MODULE_LICENSE("GPL v2");