drivers/mmc/host/dw_mmc-zx.h

   1 #ifndef _DW_MMC_ZX_H_
   2 #define _DW_MMC_ZX_H_
   3
   4 /* ZX296718 SoC specific DLL register offset. */
   5 #define LB_AON_EMMC_CFG_REG0  0x1B0
   6 #define LB_AON_EMMC_CFG_REG1  0x1B4
   7 #define LB_AON_EMMC_CFG_REG2  0x1B8
   8
   9 /* LB_AON_EMMC_CFG_REG0 register defines */
  10 #define PARA_DLL_START(x)       ((x) & 0xFF)
  11 #define PARA_DLL_START_MASK     0xFF
  12 #define DLL_REG_SET             BIT(8)
  13 #define PARA_DLL_LOCK_NUM(x)    (((x) & 7) << 16)
  14 #define PARA_DLL_LOCK_NUM_MASK  (7 << 16)
  15 #define PARA_PHASE_DET_SEL(x)   (((x) & 7) << 20)
  16 #define PARA_PHASE_DET_SEL_MASK (7 << 20)
  17 #define PARA_DLL_BYPASS_MODE    BIT(23)
  18 #define PARA_HALF_CLK_MODE      BIT(24)
  19
  20 /* LB_AON_EMMC_CFG_REG1 register defines */
  21 #define READ_DQS_DELAY(x)       ((x) & 0x7F)
  22 #define READ_DQS_DELAY_MASK     (0x7F)
  23 #define READ_DQS_BYPASS_MODE    BIT(7)
  24 #define CLK_SAMP_DELAY(x)       (((x) & 0x7F) << 8)
  25 #define CLK_SAMP_DELAY_MASK     (0x7F << 8)
  26 #define CLK_SAMP_BYPASS_MODE    BIT(15)
  27
  28 /* LB_AON_EMMC_CFG_REG2 register defines */
  29 #define ZX_DLL_LOCKED           BIT(2)
  30
  31 #endif /* _DW_MMC_ZX_H_ */