2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
65 #define DESC_RING_BUF_SZ PAGE_SIZE
67 struct idmac_desc_64addr
{
68 u32 des0
; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
72 u32 des1
; /* Reserved */
74 u32 des2
; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
79 u32 des3
; /* Reserved */
81 u32 des4
; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5
; /* Upper 32-bits of Buffer Address Pointer 1*/
84 u32 des6
; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7
; /* Upper 32-bits of Next Descriptor Address */
89 __le32 des0
; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
98 __le32 des1
; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
102 __le32 des2
; /* buffer 1 physical address */
104 __le32 des3
; /* buffer 2 physical address */
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file
*s
, void *v
)
113 struct dw_mci_slot
*slot
= s
->private;
114 struct mmc_request
*mrq
;
115 struct mmc_command
*cmd
;
116 struct mmc_command
*stop
;
117 struct mmc_data
*data
;
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot
->host
->lock
);
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
132 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
133 cmd
->resp
[2], cmd
->error
);
135 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
136 data
->bytes_xfered
, data
->blocks
,
137 data
->blksz
, data
->flags
, data
->error
);
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop
->opcode
, stop
->arg
, stop
->flags
,
142 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
143 stop
->resp
[2], stop
->error
);
146 spin_unlock_bh(&slot
->host
->lock
);
151 static int dw_mci_req_open(struct inode
*inode
, struct file
*file
)
153 return single_open(file
, dw_mci_req_show
, inode
->i_private
);
156 static const struct file_operations dw_mci_req_fops
= {
157 .owner
= THIS_MODULE
,
158 .open
= dw_mci_req_open
,
161 .release
= single_release
,
164 static int dw_mci_regs_show(struct seq_file
*s
, void *v
)
166 struct dw_mci
*host
= s
->private;
168 pm_runtime_get_sync(host
->dev
);
170 seq_printf(s
, "STATUS:\t0x%08x\n", mci_readl(host
, STATUS
));
171 seq_printf(s
, "RINTSTS:\t0x%08x\n", mci_readl(host
, RINTSTS
));
172 seq_printf(s
, "CMD:\t0x%08x\n", mci_readl(host
, CMD
));
173 seq_printf(s
, "CTRL:\t0x%08x\n", mci_readl(host
, CTRL
));
174 seq_printf(s
, "INTMASK:\t0x%08x\n", mci_readl(host
, INTMASK
));
175 seq_printf(s
, "CLKENA:\t0x%08x\n", mci_readl(host
, CLKENA
));
177 pm_runtime_put_autosuspend(host
->dev
);
182 static int dw_mci_regs_open(struct inode
*inode
, struct file
*file
)
184 return single_open(file
, dw_mci_regs_show
, inode
->i_private
);
187 static const struct file_operations dw_mci_regs_fops
= {
188 .owner
= THIS_MODULE
,
189 .open
= dw_mci_regs_open
,
192 .release
= single_release
,
195 static void dw_mci_init_debugfs(struct dw_mci_slot
*slot
)
197 struct mmc_host
*mmc
= slot
->mmc
;
198 struct dw_mci
*host
= slot
->host
;
202 root
= mmc
->debugfs_root
;
206 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
211 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
,
216 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
220 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
221 (u32
*)&host
->pending_events
);
225 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
226 (u32
*)&host
->completed_events
);
233 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
235 #endif /* defined(CONFIG_DEBUG_FS) */
237 static bool dw_mci_ctrl_reset(struct dw_mci
*host
, u32 reset
)
241 ctrl
= mci_readl(host
, CTRL
);
243 mci_writel(host
, CTRL
, ctrl
);
245 /* wait till resets clear */
246 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CTRL
, ctrl
,
248 1, 500 * USEC_PER_MSEC
)) {
250 "Timeout resetting block (ctrl reset %#x)\n",
258 static void dw_mci_wait_while_busy(struct dw_mci
*host
, u32 cmd_flags
)
263 * Databook says that before issuing a new data transfer command
264 * we need to check to see if the card is busy. Data transfer commands
265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
270 if ((cmd_flags
& SDMMC_CMD_PRV_DAT_WAIT
) &&
271 !(cmd_flags
& SDMMC_CMD_VOLT_SWITCH
)) {
272 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
274 !(status
& SDMMC_STATUS_BUSY
),
275 10, 500 * USEC_PER_MSEC
))
276 dev_err(host
->dev
, "Busy; trying anyway\n");
280 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
)
282 struct dw_mci
*host
= slot
->host
;
283 unsigned int cmd_status
= 0;
285 mci_writel(host
, CMDARG
, arg
);
286 wmb(); /* drain writebuffer */
287 dw_mci_wait_while_busy(host
, cmd
);
288 mci_writel(host
, CMD
, SDMMC_CMD_START
| cmd
);
290 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CMD
, cmd_status
,
291 !(cmd_status
& SDMMC_CMD_START
),
292 1, 500 * USEC_PER_MSEC
))
293 dev_err(&slot
->mmc
->class_dev
,
294 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
295 cmd
, arg
, cmd_status
);
298 static u32
dw_mci_prepare_command(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
300 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
301 struct dw_mci
*host
= slot
->host
;
304 cmd
->error
= -EINPROGRESS
;
307 if (cmd
->opcode
== MMC_STOP_TRANSMISSION
||
308 cmd
->opcode
== MMC_GO_IDLE_STATE
||
309 cmd
->opcode
== MMC_GO_INACTIVE_STATE
||
310 (cmd
->opcode
== SD_IO_RW_DIRECT
&&
311 ((cmd
->arg
>> 9) & 0x1FFFF) == SDIO_CCCR_ABORT
))
312 cmdr
|= SDMMC_CMD_STOP
;
313 else if (cmd
->opcode
!= MMC_SEND_STATUS
&& cmd
->data
)
314 cmdr
|= SDMMC_CMD_PRV_DAT_WAIT
;
316 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
319 /* Special bit makes CMD11 not die */
320 cmdr
|= SDMMC_CMD_VOLT_SWITCH
;
322 /* Change state to continue to handle CMD11 weirdness */
323 WARN_ON(slot
->host
->state
!= STATE_SENDING_CMD
);
324 slot
->host
->state
= STATE_SENDING_CMD11
;
327 * We need to disable low power mode (automatic clock stop)
328 * while doing voltage switch so we don't confuse the card,
329 * since stopping the clock is a specific part of the UHS
330 * voltage change dance.
332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
333 * unconditionally turned back on in dw_mci_setup_bus() if it's
334 * ever called with a non-zero clock. That shouldn't happen
335 * until the voltage change is all done.
337 clk_en_a
= mci_readl(host
, CLKENA
);
338 clk_en_a
&= ~(SDMMC_CLKEN_LOW_PWR
<< slot
->id
);
339 mci_writel(host
, CLKENA
, clk_en_a
);
340 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
341 SDMMC_CMD_PRV_DAT_WAIT
, 0);
344 if (cmd
->flags
& MMC_RSP_PRESENT
) {
345 /* We expect a response, so set this bit */
346 cmdr
|= SDMMC_CMD_RESP_EXP
;
347 if (cmd
->flags
& MMC_RSP_136
)
348 cmdr
|= SDMMC_CMD_RESP_LONG
;
351 if (cmd
->flags
& MMC_RSP_CRC
)
352 cmdr
|= SDMMC_CMD_RESP_CRC
;
355 cmdr
|= SDMMC_CMD_DAT_EXP
;
356 if (cmd
->data
->flags
& MMC_DATA_WRITE
)
357 cmdr
|= SDMMC_CMD_DAT_WR
;
360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &slot
->flags
))
361 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
366 static u32
dw_mci_prep_stop_abort(struct dw_mci
*host
, struct mmc_command
*cmd
)
368 struct mmc_command
*stop
;
374 stop
= &host
->stop_abort
;
376 memset(stop
, 0, sizeof(struct mmc_command
));
378 if (cmdr
== MMC_READ_SINGLE_BLOCK
||
379 cmdr
== MMC_READ_MULTIPLE_BLOCK
||
380 cmdr
== MMC_WRITE_BLOCK
||
381 cmdr
== MMC_WRITE_MULTIPLE_BLOCK
||
382 cmdr
== MMC_SEND_TUNING_BLOCK
||
383 cmdr
== MMC_SEND_TUNING_BLOCK_HS200
) {
384 stop
->opcode
= MMC_STOP_TRANSMISSION
;
386 stop
->flags
= MMC_RSP_R1B
| MMC_CMD_AC
;
387 } else if (cmdr
== SD_IO_RW_EXTENDED
) {
388 stop
->opcode
= SD_IO_RW_DIRECT
;
389 stop
->arg
|= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT
<< 9) |
390 ((cmd
->arg
>> 28) & 0x7);
391 stop
->flags
= MMC_RSP_SPI_R5
| MMC_RSP_R5
| MMC_CMD_AC
;
396 cmdr
= stop
->opcode
| SDMMC_CMD_STOP
|
397 SDMMC_CMD_RESP_CRC
| SDMMC_CMD_RESP_EXP
;
399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &host
->slot
->flags
))
400 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
405 static inline void dw_mci_set_cto(struct dw_mci
*host
)
407 unsigned int cto_clks
;
408 unsigned int cto_div
;
410 unsigned long irqflags
;
412 cto_clks
= mci_readl(host
, TMOUT
) & 0xff;
413 cto_div
= (mci_readl(host
, CLKDIV
) & 0xff) * 2;
417 cto_ms
= DIV_ROUND_UP_ULL((u64
)MSEC_PER_SEC
* cto_clks
* cto_div
,
420 /* add a bit spare time */
424 * The durations we're working with are fairly short so we have to be
425 * extra careful about synchronization here. Specifically in hardware a
426 * command timeout is _at most_ 5.1 ms, so that means we expect an
427 * interrupt (either command done or timeout) to come rather quickly
428 * after the mci_writel. ...but just in case we have a long interrupt
429 * latency let's add a bit of paranoia.
431 * In general we'll assume that at least an interrupt will be asserted
432 * in hardware by the time the cto_timer runs. ...and if it hasn't
433 * been asserted in hardware by that time then we'll assume it'll never
436 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
437 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
438 mod_timer(&host
->cto_timer
,
439 jiffies
+ msecs_to_jiffies(cto_ms
) + 1);
440 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
443 static void dw_mci_start_command(struct dw_mci
*host
,
444 struct mmc_command
*cmd
, u32 cmd_flags
)
448 "start command: ARGR=0x%08x CMDR=0x%08x\n",
449 cmd
->arg
, cmd_flags
);
451 mci_writel(host
, CMDARG
, cmd
->arg
);
452 wmb(); /* drain writebuffer */
453 dw_mci_wait_while_busy(host
, cmd_flags
);
455 mci_writel(host
, CMD
, cmd_flags
| SDMMC_CMD_START
);
457 /* response expected command only */
458 if (cmd_flags
& SDMMC_CMD_RESP_EXP
)
459 dw_mci_set_cto(host
);
462 static inline void send_stop_abort(struct dw_mci
*host
, struct mmc_data
*data
)
464 struct mmc_command
*stop
= &host
->stop_abort
;
466 dw_mci_start_command(host
, stop
, host
->stop_cmdr
);
469 /* DMA interface functions */
470 static void dw_mci_stop_dma(struct dw_mci
*host
)
472 if (host
->using_dma
) {
473 host
->dma_ops
->stop(host
);
474 host
->dma_ops
->cleanup(host
);
477 /* Data transfer was stopped by the interrupt handler */
478 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
481 static void dw_mci_dma_cleanup(struct dw_mci
*host
)
483 struct mmc_data
*data
= host
->data
;
485 if (data
&& data
->host_cookie
== COOKIE_MAPPED
) {
486 dma_unmap_sg(host
->dev
,
489 mmc_get_dma_dir(data
));
490 data
->host_cookie
= COOKIE_UNMAPPED
;
494 static void dw_mci_idmac_reset(struct dw_mci
*host
)
496 u32 bmod
= mci_readl(host
, BMOD
);
497 /* Software reset of DMA */
498 bmod
|= SDMMC_IDMAC_SWRESET
;
499 mci_writel(host
, BMOD
, bmod
);
502 static void dw_mci_idmac_stop_dma(struct dw_mci
*host
)
506 /* Disable and reset the IDMAC interface */
507 temp
= mci_readl(host
, CTRL
);
508 temp
&= ~SDMMC_CTRL_USE_IDMAC
;
509 temp
|= SDMMC_CTRL_DMA_RESET
;
510 mci_writel(host
, CTRL
, temp
);
512 /* Stop the IDMAC running */
513 temp
= mci_readl(host
, BMOD
);
514 temp
&= ~(SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
);
515 temp
|= SDMMC_IDMAC_SWRESET
;
516 mci_writel(host
, BMOD
, temp
);
519 static void dw_mci_dmac_complete_dma(void *arg
)
521 struct dw_mci
*host
= arg
;
522 struct mmc_data
*data
= host
->data
;
524 dev_vdbg(host
->dev
, "DMA complete\n");
526 if ((host
->use_dma
== TRANS_MODE_EDMAC
) &&
527 data
&& (data
->flags
& MMC_DATA_READ
))
528 /* Invalidate cache after read */
529 dma_sync_sg_for_cpu(mmc_dev(host
->slot
->mmc
),
534 host
->dma_ops
->cleanup(host
);
537 * If the card was removed, data will be NULL. No point in trying to
538 * send the stop command or waiting for NBUSY in this case.
541 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
542 tasklet_schedule(&host
->tasklet
);
546 static int dw_mci_idmac_init(struct dw_mci
*host
)
550 if (host
->dma_64bit_address
== 1) {
551 struct idmac_desc_64addr
*p
;
552 /* Number of descriptors in the ring buffer */
554 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc_64addr
);
556 /* Forward link the descriptor list */
557 for (i
= 0, p
= host
->sg_cpu
; i
< host
->ring_size
- 1;
559 p
->des6
= (host
->sg_dma
+
560 (sizeof(struct idmac_desc_64addr
) *
561 (i
+ 1))) & 0xffffffff;
563 p
->des7
= (u64
)(host
->sg_dma
+
564 (sizeof(struct idmac_desc_64addr
) *
566 /* Initialize reserved and buffer size fields to "0" */
573 /* Set the last descriptor as the end-of-ring descriptor */
574 p
->des6
= host
->sg_dma
& 0xffffffff;
575 p
->des7
= (u64
)host
->sg_dma
>> 32;
576 p
->des0
= IDMAC_DES0_ER
;
579 struct idmac_desc
*p
;
580 /* Number of descriptors in the ring buffer */
582 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc
);
584 /* Forward link the descriptor list */
585 for (i
= 0, p
= host
->sg_cpu
;
586 i
< host
->ring_size
- 1;
588 p
->des3
= cpu_to_le32(host
->sg_dma
+
589 (sizeof(struct idmac_desc
) * (i
+ 1)));
594 /* Set the last descriptor as the end-of-ring descriptor */
595 p
->des3
= cpu_to_le32(host
->sg_dma
);
596 p
->des0
= cpu_to_le32(IDMAC_DES0_ER
);
599 dw_mci_idmac_reset(host
);
601 if (host
->dma_64bit_address
== 1) {
602 /* Mask out interrupts - get Tx & Rx complete only */
603 mci_writel(host
, IDSTS64
, IDMAC_INT_CLR
);
604 mci_writel(host
, IDINTEN64
, SDMMC_IDMAC_INT_NI
|
605 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
607 /* Set the descriptor base address */
608 mci_writel(host
, DBADDRL
, host
->sg_dma
& 0xffffffff);
609 mci_writel(host
, DBADDRU
, (u64
)host
->sg_dma
>> 32);
612 /* Mask out interrupts - get Tx & Rx complete only */
613 mci_writel(host
, IDSTS
, IDMAC_INT_CLR
);
614 mci_writel(host
, IDINTEN
, SDMMC_IDMAC_INT_NI
|
615 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
617 /* Set the descriptor base address */
618 mci_writel(host
, DBADDR
, host
->sg_dma
);
624 static inline int dw_mci_prepare_desc64(struct dw_mci
*host
,
625 struct mmc_data
*data
,
628 unsigned int desc_len
;
629 struct idmac_desc_64addr
*desc_first
, *desc_last
, *desc
;
633 desc_first
= desc_last
= desc
= host
->sg_cpu
;
635 for (i
= 0; i
< sg_len
; i
++) {
636 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
638 u64 mem_addr
= sg_dma_address(&data
->sg
[i
]);
640 for ( ; length
; desc
++) {
641 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
642 length
: DW_MCI_DESC_DATA_LENGTH
;
647 * Wait for the former clear OWN bit operation
648 * of IDMAC to make sure that this descriptor
649 * isn't still owned by IDMAC as IDMAC's write
650 * ops and CPU's read ops are asynchronous.
652 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
653 !(val
& IDMAC_DES0_OWN
),
654 10, 100 * USEC_PER_MSEC
))
658 * Set the OWN bit and disable interrupts
659 * for this descriptor
661 desc
->des0
= IDMAC_DES0_OWN
| IDMAC_DES0_DIC
|
665 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc
, desc_len
);
667 /* Physical address to DMA to/from */
668 desc
->des4
= mem_addr
& 0xffffffff;
669 desc
->des5
= mem_addr
>> 32;
671 /* Update physical address for the next desc */
672 mem_addr
+= desc_len
;
674 /* Save pointer to the last descriptor */
679 /* Set first descriptor */
680 desc_first
->des0
|= IDMAC_DES0_FD
;
682 /* Set last descriptor */
683 desc_last
->des0
&= ~(IDMAC_DES0_CH
| IDMAC_DES0_DIC
);
684 desc_last
->des0
|= IDMAC_DES0_LD
;
688 /* restore the descriptor chain as it's polluted */
689 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
690 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
691 dw_mci_idmac_init(host
);
696 static inline int dw_mci_prepare_desc32(struct dw_mci
*host
,
697 struct mmc_data
*data
,
700 unsigned int desc_len
;
701 struct idmac_desc
*desc_first
, *desc_last
, *desc
;
705 desc_first
= desc_last
= desc
= host
->sg_cpu
;
707 for (i
= 0; i
< sg_len
; i
++) {
708 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
710 u32 mem_addr
= sg_dma_address(&data
->sg
[i
]);
712 for ( ; length
; desc
++) {
713 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
714 length
: DW_MCI_DESC_DATA_LENGTH
;
719 * Wait for the former clear OWN bit operation
720 * of IDMAC to make sure that this descriptor
721 * isn't still owned by IDMAC as IDMAC's write
722 * ops and CPU's read ops are asynchronous.
724 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
725 IDMAC_OWN_CLR64(val
),
727 100 * USEC_PER_MSEC
))
731 * Set the OWN bit and disable interrupts
732 * for this descriptor
734 desc
->des0
= cpu_to_le32(IDMAC_DES0_OWN
|
739 IDMAC_SET_BUFFER1_SIZE(desc
, desc_len
);
741 /* Physical address to DMA to/from */
742 desc
->des2
= cpu_to_le32(mem_addr
);
744 /* Update physical address for the next desc */
745 mem_addr
+= desc_len
;
747 /* Save pointer to the last descriptor */
752 /* Set first descriptor */
753 desc_first
->des0
|= cpu_to_le32(IDMAC_DES0_FD
);
755 /* Set last descriptor */
756 desc_last
->des0
&= cpu_to_le32(~(IDMAC_DES0_CH
|
758 desc_last
->des0
|= cpu_to_le32(IDMAC_DES0_LD
);
762 /* restore the descriptor chain as it's polluted */
763 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
764 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
765 dw_mci_idmac_init(host
);
769 static int dw_mci_idmac_start_dma(struct dw_mci
*host
, unsigned int sg_len
)
774 if (host
->dma_64bit_address
== 1)
775 ret
= dw_mci_prepare_desc64(host
, host
->data
, sg_len
);
777 ret
= dw_mci_prepare_desc32(host
, host
->data
, sg_len
);
782 /* drain writebuffer */
785 /* Make sure to reset DMA in case we did PIO before this */
786 dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
);
787 dw_mci_idmac_reset(host
);
789 /* Select IDMAC interface */
790 temp
= mci_readl(host
, CTRL
);
791 temp
|= SDMMC_CTRL_USE_IDMAC
;
792 mci_writel(host
, CTRL
, temp
);
794 /* drain writebuffer */
797 /* Enable the IDMAC */
798 temp
= mci_readl(host
, BMOD
);
799 temp
|= SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
;
800 mci_writel(host
, BMOD
, temp
);
802 /* Start it running */
803 mci_writel(host
, PLDMND
, 1);
809 static const struct dw_mci_dma_ops dw_mci_idmac_ops
= {
810 .init
= dw_mci_idmac_init
,
811 .start
= dw_mci_idmac_start_dma
,
812 .stop
= dw_mci_idmac_stop_dma
,
813 .complete
= dw_mci_dmac_complete_dma
,
814 .cleanup
= dw_mci_dma_cleanup
,
817 static void dw_mci_edmac_stop_dma(struct dw_mci
*host
)
819 dmaengine_terminate_async(host
->dms
->ch
);
822 static int dw_mci_edmac_start_dma(struct dw_mci
*host
,
825 struct dma_slave_config cfg
;
826 struct dma_async_tx_descriptor
*desc
= NULL
;
827 struct scatterlist
*sgl
= host
->data
->sg
;
828 static const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
829 u32 sg_elems
= host
->data
->sg_len
;
831 u32 fifo_offset
= host
->fifo_reg
- host
->regs
;
834 /* Set external dma config: burst size, burst width */
835 cfg
.dst_addr
= host
->phy_regs
+ fifo_offset
;
836 cfg
.src_addr
= cfg
.dst_addr
;
837 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
838 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
840 /* Match burst msize with external dma config */
841 fifoth_val
= mci_readl(host
, FIFOTH
);
842 cfg
.dst_maxburst
= mszs
[(fifoth_val
>> 28) & 0x7];
843 cfg
.src_maxburst
= cfg
.dst_maxburst
;
845 if (host
->data
->flags
& MMC_DATA_WRITE
)
846 cfg
.direction
= DMA_MEM_TO_DEV
;
848 cfg
.direction
= DMA_DEV_TO_MEM
;
850 ret
= dmaengine_slave_config(host
->dms
->ch
, &cfg
);
852 dev_err(host
->dev
, "Failed to config edmac.\n");
856 desc
= dmaengine_prep_slave_sg(host
->dms
->ch
, sgl
,
857 sg_len
, cfg
.direction
,
858 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
860 dev_err(host
->dev
, "Can't prepare slave sg.\n");
864 /* Set dw_mci_dmac_complete_dma as callback */
865 desc
->callback
= dw_mci_dmac_complete_dma
;
866 desc
->callback_param
= (void *)host
;
867 dmaengine_submit(desc
);
869 /* Flush cache before write */
870 if (host
->data
->flags
& MMC_DATA_WRITE
)
871 dma_sync_sg_for_device(mmc_dev(host
->slot
->mmc
), sgl
,
872 sg_elems
, DMA_TO_DEVICE
);
874 dma_async_issue_pending(host
->dms
->ch
);
879 static int dw_mci_edmac_init(struct dw_mci
*host
)
881 /* Request external dma channel */
882 host
->dms
= kzalloc(sizeof(struct dw_mci_dma_slave
), GFP_KERNEL
);
886 host
->dms
->ch
= dma_request_slave_channel(host
->dev
, "rx-tx");
887 if (!host
->dms
->ch
) {
888 dev_err(host
->dev
, "Failed to get external DMA channel.\n");
897 static void dw_mci_edmac_exit(struct dw_mci
*host
)
901 dma_release_channel(host
->dms
->ch
);
902 host
->dms
->ch
= NULL
;
909 static const struct dw_mci_dma_ops dw_mci_edmac_ops
= {
910 .init
= dw_mci_edmac_init
,
911 .exit
= dw_mci_edmac_exit
,
912 .start
= dw_mci_edmac_start_dma
,
913 .stop
= dw_mci_edmac_stop_dma
,
914 .complete
= dw_mci_dmac_complete_dma
,
915 .cleanup
= dw_mci_dma_cleanup
,
918 static int dw_mci_pre_dma_transfer(struct dw_mci
*host
,
919 struct mmc_data
*data
,
922 struct scatterlist
*sg
;
923 unsigned int i
, sg_len
;
925 if (data
->host_cookie
== COOKIE_PRE_MAPPED
)
929 * We don't do DMA on "complex" transfers, i.e. with
930 * non-word-aligned buffers or lengths. Also, we don't bother
931 * with all the DMA setup overhead for short transfers.
933 if (data
->blocks
* data
->blksz
< DW_MCI_DMA_THRESHOLD
)
939 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
940 if (sg
->offset
& 3 || sg
->length
& 3)
944 sg_len
= dma_map_sg(host
->dev
,
947 mmc_get_dma_dir(data
));
951 data
->host_cookie
= cookie
;
956 static void dw_mci_pre_req(struct mmc_host
*mmc
,
957 struct mmc_request
*mrq
)
959 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
960 struct mmc_data
*data
= mrq
->data
;
962 if (!slot
->host
->use_dma
|| !data
)
965 /* This data might be unmapped at this time */
966 data
->host_cookie
= COOKIE_UNMAPPED
;
968 if (dw_mci_pre_dma_transfer(slot
->host
, mrq
->data
,
969 COOKIE_PRE_MAPPED
) < 0)
970 data
->host_cookie
= COOKIE_UNMAPPED
;
973 static void dw_mci_post_req(struct mmc_host
*mmc
,
974 struct mmc_request
*mrq
,
977 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
978 struct mmc_data
*data
= mrq
->data
;
980 if (!slot
->host
->use_dma
|| !data
)
983 if (data
->host_cookie
!= COOKIE_UNMAPPED
)
984 dma_unmap_sg(slot
->host
->dev
,
987 mmc_get_dma_dir(data
));
988 data
->host_cookie
= COOKIE_UNMAPPED
;
991 static int dw_mci_get_cd(struct mmc_host
*mmc
)
994 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
995 struct dw_mci
*host
= slot
->host
;
996 int gpio_cd
= mmc_gpio_get_cd(mmc
);
998 /* Use platform get_cd function, else try onboard card detect */
999 if (((mmc
->caps
& MMC_CAP_NEEDS_POLL
)
1000 || !mmc_card_is_removable(mmc
))) {
1003 if (!test_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
)) {
1004 if (mmc
->caps
& MMC_CAP_NEEDS_POLL
) {
1005 dev_info(&mmc
->class_dev
,
1006 "card is polling.\n");
1008 dev_info(&mmc
->class_dev
,
1009 "card is non-removable.\n");
1011 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1015 } else if (gpio_cd
>= 0)
1018 present
= (mci_readl(slot
->host
, CDETECT
) & (1 << slot
->id
))
1021 spin_lock_bh(&host
->lock
);
1022 if (present
&& !test_and_set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
1023 dev_dbg(&mmc
->class_dev
, "card is present\n");
1024 else if (!present
&&
1025 !test_and_clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
1026 dev_dbg(&mmc
->class_dev
, "card is not present\n");
1027 spin_unlock_bh(&host
->lock
);
1032 static void dw_mci_adjust_fifoth(struct dw_mci
*host
, struct mmc_data
*data
)
1034 unsigned int blksz
= data
->blksz
;
1035 static const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
1036 u32 fifo_width
= 1 << host
->data_shift
;
1037 u32 blksz_depth
= blksz
/ fifo_width
, fifoth_val
;
1038 u32 msize
= 0, rx_wmark
= 1, tx_wmark
, tx_wmark_invers
;
1039 int idx
= ARRAY_SIZE(mszs
) - 1;
1041 /* pio should ship this scenario */
1045 tx_wmark
= (host
->fifo_depth
) / 2;
1046 tx_wmark_invers
= host
->fifo_depth
- tx_wmark
;
1050 * if blksz is not a multiple of the FIFO width
1052 if (blksz
% fifo_width
)
1056 if (!((blksz_depth
% mszs
[idx
]) ||
1057 (tx_wmark_invers
% mszs
[idx
]))) {
1059 rx_wmark
= mszs
[idx
] - 1;
1062 } while (--idx
> 0);
1064 * If idx is '0', it won't be tried
1065 * Thus, initial values are uesed
1068 fifoth_val
= SDMMC_SET_FIFOTH(msize
, rx_wmark
, tx_wmark
);
1069 mci_writel(host
, FIFOTH
, fifoth_val
);
1072 static void dw_mci_ctrl_thld(struct dw_mci
*host
, struct mmc_data
*data
)
1074 unsigned int blksz
= data
->blksz
;
1075 u32 blksz_depth
, fifo_depth
;
1080 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1081 * in the FIFO region, so we really shouldn't access it).
1083 if (host
->verid
< DW_MMC_240A
||
1084 (host
->verid
< DW_MMC_280A
&& data
->flags
& MMC_DATA_WRITE
))
1088 * Card write Threshold is introduced since 2.80a
1089 * It's used when HS400 mode is enabled.
1091 if (data
->flags
& MMC_DATA_WRITE
&&
1092 host
->timing
!= MMC_TIMING_MMC_HS400
)
1095 if (data
->flags
& MMC_DATA_WRITE
)
1096 enable
= SDMMC_CARD_WR_THR_EN
;
1098 enable
= SDMMC_CARD_RD_THR_EN
;
1100 if (host
->timing
!= MMC_TIMING_MMC_HS200
&&
1101 host
->timing
!= MMC_TIMING_UHS_SDR104
&&
1102 host
->timing
!= MMC_TIMING_MMC_HS400
)
1105 blksz_depth
= blksz
/ (1 << host
->data_shift
);
1106 fifo_depth
= host
->fifo_depth
;
1108 if (blksz_depth
> fifo_depth
)
1112 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1113 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1114 * Currently just choose blksz.
1117 mci_writel(host
, CDTHRCTL
, SDMMC_SET_THLD(thld_size
, enable
));
1121 mci_writel(host
, CDTHRCTL
, 0);
1124 static int dw_mci_submit_data_dma(struct dw_mci
*host
, struct mmc_data
*data
)
1126 unsigned long irqflags
;
1130 host
->using_dma
= 0;
1132 /* If we don't have a channel, we can't do DMA */
1136 sg_len
= dw_mci_pre_dma_transfer(host
, data
, COOKIE_MAPPED
);
1138 host
->dma_ops
->stop(host
);
1142 host
->using_dma
= 1;
1144 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1146 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1147 (unsigned long)host
->sg_cpu
,
1148 (unsigned long)host
->sg_dma
,
1152 * Decide the MSIZE and RX/TX Watermark.
1153 * If current block size is same with previous size,
1154 * no need to update fifoth.
1156 if (host
->prev_blksz
!= data
->blksz
)
1157 dw_mci_adjust_fifoth(host
, data
);
1159 /* Enable the DMA interface */
1160 temp
= mci_readl(host
, CTRL
);
1161 temp
|= SDMMC_CTRL_DMA_ENABLE
;
1162 mci_writel(host
, CTRL
, temp
);
1164 /* Disable RX/TX IRQs, let DMA handle it */
1165 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1166 temp
= mci_readl(host
, INTMASK
);
1167 temp
&= ~(SDMMC_INT_RXDR
| SDMMC_INT_TXDR
);
1168 mci_writel(host
, INTMASK
, temp
);
1169 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1171 if (host
->dma_ops
->start(host
, sg_len
)) {
1172 host
->dma_ops
->stop(host
);
1173 /* We can't do DMA, try PIO for this one */
1175 "%s: fall back to PIO mode for current transfer\n",
1183 static void dw_mci_submit_data(struct dw_mci
*host
, struct mmc_data
*data
)
1185 unsigned long irqflags
;
1186 int flags
= SG_MITER_ATOMIC
;
1189 data
->error
= -EINPROGRESS
;
1191 WARN_ON(host
->data
);
1195 if (data
->flags
& MMC_DATA_READ
)
1196 host
->dir_status
= DW_MCI_RECV_STATUS
;
1198 host
->dir_status
= DW_MCI_SEND_STATUS
;
1200 dw_mci_ctrl_thld(host
, data
);
1202 if (dw_mci_submit_data_dma(host
, data
)) {
1203 if (host
->data
->flags
& MMC_DATA_READ
)
1204 flags
|= SG_MITER_TO_SG
;
1206 flags
|= SG_MITER_FROM_SG
;
1208 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
1209 host
->sg
= data
->sg
;
1210 host
->part_buf_start
= 0;
1211 host
->part_buf_count
= 0;
1213 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
| SDMMC_INT_RXDR
);
1215 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1216 temp
= mci_readl(host
, INTMASK
);
1217 temp
|= SDMMC_INT_TXDR
| SDMMC_INT_RXDR
;
1218 mci_writel(host
, INTMASK
, temp
);
1219 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1221 temp
= mci_readl(host
, CTRL
);
1222 temp
&= ~SDMMC_CTRL_DMA_ENABLE
;
1223 mci_writel(host
, CTRL
, temp
);
1226 * Use the initial fifoth_val for PIO mode. If wm_algined
1227 * is set, we set watermark same as data size.
1228 * If next issued data may be transfered by DMA mode,
1229 * prev_blksz should be invalidated.
1231 if (host
->wm_aligned
)
1232 dw_mci_adjust_fifoth(host
, data
);
1234 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
1235 host
->prev_blksz
= 0;
1238 * Keep the current block size.
1239 * It will be used to decide whether to update
1240 * fifoth register next time.
1242 host
->prev_blksz
= data
->blksz
;
1246 static void dw_mci_setup_bus(struct dw_mci_slot
*slot
, bool force_clkinit
)
1248 struct dw_mci
*host
= slot
->host
;
1249 unsigned int clock
= slot
->clock
;
1252 u32 sdmmc_cmd_bits
= SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
;
1254 /* We must continue to set bit 28 in CMD until the change is complete */
1255 if (host
->state
== STATE_WAITING_CMD11_DONE
)
1256 sdmmc_cmd_bits
|= SDMMC_CMD_VOLT_SWITCH
;
1258 slot
->mmc
->actual_clock
= 0;
1261 mci_writel(host
, CLKENA
, 0);
1262 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1263 } else if (clock
!= host
->current_speed
|| force_clkinit
) {
1264 div
= host
->bus_hz
/ clock
;
1265 if (host
->bus_hz
% clock
&& host
->bus_hz
> clock
)
1267 * move the + 1 after the divide to prevent
1268 * over-clocking the card.
1272 div
= (host
->bus_hz
!= clock
) ? DIV_ROUND_UP(div
, 2) : 0;
1274 if ((clock
!= slot
->__clk_old
&&
1275 !test_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
)) ||
1277 /* Silent the verbose log if calling from PM context */
1279 dev_info(&slot
->mmc
->class_dev
,
1280 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1281 slot
->id
, host
->bus_hz
, clock
,
1282 div
? ((host
->bus_hz
/ div
) >> 1) :
1286 * If card is polling, display the message only
1287 * one time at boot time.
1289 if (slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
&&
1290 slot
->mmc
->f_min
== clock
)
1291 set_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
);
1295 mci_writel(host
, CLKENA
, 0);
1296 mci_writel(host
, CLKSRC
, 0);
1299 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1301 /* set clock to desired speed */
1302 mci_writel(host
, CLKDIV
, div
);
1305 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1307 /* enable clock; only low power if no SDIO */
1308 clk_en_a
= SDMMC_CLKEN_ENABLE
<< slot
->id
;
1309 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
))
1310 clk_en_a
|= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1311 mci_writel(host
, CLKENA
, clk_en_a
);
1314 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1316 /* keep the last clock value that was requested from core */
1317 slot
->__clk_old
= clock
;
1318 slot
->mmc
->actual_clock
= div
? ((host
->bus_hz
/ div
) >> 1) :
1322 host
->current_speed
= clock
;
1324 /* Set the current slot bus width */
1325 mci_writel(host
, CTYPE
, (slot
->ctype
<< slot
->id
));
1328 static void __dw_mci_start_request(struct dw_mci
*host
,
1329 struct dw_mci_slot
*slot
,
1330 struct mmc_command
*cmd
)
1332 struct mmc_request
*mrq
;
1333 struct mmc_data
*data
;
1340 host
->pending_events
= 0;
1341 host
->completed_events
= 0;
1342 host
->cmd_status
= 0;
1343 host
->data_status
= 0;
1344 host
->dir_status
= 0;
1348 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
1349 mci_writel(host
, BYTCNT
, data
->blksz
*data
->blocks
);
1350 mci_writel(host
, BLKSIZ
, data
->blksz
);
1353 cmdflags
= dw_mci_prepare_command(slot
->mmc
, cmd
);
1355 /* this is the first command, send the initialization clock */
1356 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
))
1357 cmdflags
|= SDMMC_CMD_INIT
;
1360 dw_mci_submit_data(host
, data
);
1361 wmb(); /* drain writebuffer */
1364 dw_mci_start_command(host
, cmd
, cmdflags
);
1366 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
1367 unsigned long irqflags
;
1370 * Databook says to fail after 2ms w/ no response, but evidence
1371 * shows that sometimes the cmd11 interrupt takes over 130ms.
1372 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1373 * is just about to roll over.
1375 * We do this whole thing under spinlock and only if the
1376 * command hasn't already completed (indicating the the irq
1377 * already ran so we don't want the timeout).
1379 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1380 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1381 mod_timer(&host
->cmd11_timer
,
1382 jiffies
+ msecs_to_jiffies(500) + 1);
1383 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1386 host
->stop_cmdr
= dw_mci_prep_stop_abort(host
, cmd
);
1389 static void dw_mci_start_request(struct dw_mci
*host
,
1390 struct dw_mci_slot
*slot
)
1392 struct mmc_request
*mrq
= slot
->mrq
;
1393 struct mmc_command
*cmd
;
1395 cmd
= mrq
->sbc
? mrq
->sbc
: mrq
->cmd
;
1396 __dw_mci_start_request(host
, slot
, cmd
);
1399 /* must be called with host->lock held */
1400 static void dw_mci_queue_request(struct dw_mci
*host
, struct dw_mci_slot
*slot
,
1401 struct mmc_request
*mrq
)
1403 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1408 if (host
->state
== STATE_WAITING_CMD11_DONE
) {
1409 dev_warn(&slot
->mmc
->class_dev
,
1410 "Voltage change didn't complete\n");
1412 * this case isn't expected to happen, so we can
1413 * either crash here or just try to continue on
1414 * in the closest possible state
1416 host
->state
= STATE_IDLE
;
1419 if (host
->state
== STATE_IDLE
) {
1420 host
->state
= STATE_SENDING_CMD
;
1421 dw_mci_start_request(host
, slot
);
1423 list_add_tail(&slot
->queue_node
, &host
->queue
);
1427 static void dw_mci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1429 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1430 struct dw_mci
*host
= slot
->host
;
1435 * The check for card presence and queueing of the request must be
1436 * atomic, otherwise the card could be removed in between and the
1437 * request wouldn't fail until another card was inserted.
1440 if (!dw_mci_get_cd(mmc
)) {
1441 mrq
->cmd
->error
= -ENOMEDIUM
;
1442 mmc_request_done(mmc
, mrq
);
1446 spin_lock_bh(&host
->lock
);
1448 dw_mci_queue_request(host
, slot
, mrq
);
1450 spin_unlock_bh(&host
->lock
);
1453 static void dw_mci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1455 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1456 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
1460 switch (ios
->bus_width
) {
1461 case MMC_BUS_WIDTH_4
:
1462 slot
->ctype
= SDMMC_CTYPE_4BIT
;
1464 case MMC_BUS_WIDTH_8
:
1465 slot
->ctype
= SDMMC_CTYPE_8BIT
;
1468 /* set default 1 bit mode */
1469 slot
->ctype
= SDMMC_CTYPE_1BIT
;
1472 regs
= mci_readl(slot
->host
, UHS_REG
);
1475 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
1476 ios
->timing
== MMC_TIMING_UHS_DDR50
||
1477 ios
->timing
== MMC_TIMING_MMC_HS400
)
1478 regs
|= ((0x1 << slot
->id
) << 16);
1480 regs
&= ~((0x1 << slot
->id
) << 16);
1482 mci_writel(slot
->host
, UHS_REG
, regs
);
1483 slot
->host
->timing
= ios
->timing
;
1486 * Use mirror of ios->clock to prevent race with mmc
1487 * core ios update when finding the minimum.
1489 slot
->clock
= ios
->clock
;
1491 if (drv_data
&& drv_data
->set_ios
)
1492 drv_data
->set_ios(slot
->host
, ios
);
1494 switch (ios
->power_mode
) {
1496 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1497 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
1500 dev_err(slot
->host
->dev
,
1501 "failed to enable vmmc regulator\n");
1502 /*return, if failed turn on vmmc*/
1506 set_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
);
1507 regs
= mci_readl(slot
->host
, PWREN
);
1508 regs
|= (1 << slot
->id
);
1509 mci_writel(slot
->host
, PWREN
, regs
);
1512 if (!slot
->host
->vqmmc_enabled
) {
1513 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1514 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1516 dev_err(slot
->host
->dev
,
1517 "failed to enable vqmmc\n");
1519 slot
->host
->vqmmc_enabled
= true;
1522 /* Keep track so we don't reset again */
1523 slot
->host
->vqmmc_enabled
= true;
1526 /* Reset our state machine after powering on */
1527 dw_mci_ctrl_reset(slot
->host
,
1528 SDMMC_CTRL_ALL_RESET_FLAGS
);
1531 /* Adjust clock / bus width after power is up */
1532 dw_mci_setup_bus(slot
, false);
1536 /* Turn clock off before power goes down */
1537 dw_mci_setup_bus(slot
, false);
1539 if (!IS_ERR(mmc
->supply
.vmmc
))
1540 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1542 if (!IS_ERR(mmc
->supply
.vqmmc
) && slot
->host
->vqmmc_enabled
)
1543 regulator_disable(mmc
->supply
.vqmmc
);
1544 slot
->host
->vqmmc_enabled
= false;
1546 regs
= mci_readl(slot
->host
, PWREN
);
1547 regs
&= ~(1 << slot
->id
);
1548 mci_writel(slot
->host
, PWREN
, regs
);
1554 if (slot
->host
->state
== STATE_WAITING_CMD11_DONE
&& ios
->clock
!= 0)
1555 slot
->host
->state
= STATE_IDLE
;
1558 static int dw_mci_card_busy(struct mmc_host
*mmc
)
1560 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1564 * Check the busy bit which is low when DAT[3:0]
1565 * (the data lines) are 0000
1567 status
= mci_readl(slot
->host
, STATUS
);
1569 return !!(status
& SDMMC_STATUS_BUSY
);
1572 static int dw_mci_switch_voltage(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1574 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1575 struct dw_mci
*host
= slot
->host
;
1576 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1578 u32 v18
= SDMMC_UHS_18V
<< slot
->id
;
1581 if (drv_data
&& drv_data
->switch_voltage
)
1582 return drv_data
->switch_voltage(mmc
, ios
);
1585 * Program the voltage. Note that some instances of dw_mmc may use
1586 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1587 * does no harm but you need to set the regulator directly. Try both.
1589 uhs
= mci_readl(host
, UHS_REG
);
1590 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1595 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1596 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1599 dev_dbg(&mmc
->class_dev
,
1600 "Regulator set error %d - %s V\n",
1601 ret
, uhs
& v18
? "1.8" : "3.3");
1605 mci_writel(host
, UHS_REG
, uhs
);
1610 static int dw_mci_get_ro(struct mmc_host
*mmc
)
1613 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1614 int gpio_ro
= mmc_gpio_get_ro(mmc
);
1616 /* Use platform get_ro function, else try on board write protect */
1618 read_only
= gpio_ro
;
1621 mci_readl(slot
->host
, WRTPRT
) & (1 << slot
->id
) ? 1 : 0;
1623 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1624 read_only
? "read-only" : "read-write");
1629 static void dw_mci_hw_reset(struct mmc_host
*mmc
)
1631 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1632 struct dw_mci
*host
= slot
->host
;
1635 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1636 dw_mci_idmac_reset(host
);
1638 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
|
1639 SDMMC_CTRL_FIFO_RESET
))
1643 * According to eMMC spec, card reset procedure:
1644 * tRstW >= 1us: RST_n pulse width
1645 * tRSCA >= 200us: RST_n to Command time
1646 * tRSTH >= 1us: RST_n high period
1648 reset
= mci_readl(host
, RST_N
);
1649 reset
&= ~(SDMMC_RST_HWACTIVE
<< slot
->id
);
1650 mci_writel(host
, RST_N
, reset
);
1652 reset
|= SDMMC_RST_HWACTIVE
<< slot
->id
;
1653 mci_writel(host
, RST_N
, reset
);
1654 usleep_range(200, 300);
1657 static void dw_mci_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1659 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1660 struct dw_mci
*host
= slot
->host
;
1663 * Low power mode will stop the card clock when idle. According to the
1664 * description of the CLKENA register we should disable low power mode
1665 * for SDIO cards if we need SDIO interrupts to work.
1667 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
) {
1668 const u32 clken_low_pwr
= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1672 clk_en_a_old
= mci_readl(host
, CLKENA
);
1674 if (card
->type
== MMC_TYPE_SDIO
||
1675 card
->type
== MMC_TYPE_SD_COMBO
) {
1676 set_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1677 clk_en_a
= clk_en_a_old
& ~clken_low_pwr
;
1679 clear_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1680 clk_en_a
= clk_en_a_old
| clken_low_pwr
;
1683 if (clk_en_a
!= clk_en_a_old
) {
1684 mci_writel(host
, CLKENA
, clk_en_a
);
1685 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
1686 SDMMC_CMD_PRV_DAT_WAIT
, 0);
1691 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot
*slot
, int enb
)
1693 struct dw_mci
*host
= slot
->host
;
1694 unsigned long irqflags
;
1697 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1699 /* Enable/disable Slot Specific SDIO interrupt */
1700 int_mask
= mci_readl(host
, INTMASK
);
1702 int_mask
|= SDMMC_INT_SDIO(slot
->sdio_id
);
1704 int_mask
&= ~SDMMC_INT_SDIO(slot
->sdio_id
);
1705 mci_writel(host
, INTMASK
, int_mask
);
1707 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1710 static void dw_mci_enable_sdio_irq(struct mmc_host
*mmc
, int enb
)
1712 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1713 struct dw_mci
*host
= slot
->host
;
1715 __dw_mci_enable_sdio_irq(slot
, enb
);
1717 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1719 pm_runtime_get_noresume(host
->dev
);
1721 pm_runtime_put_noidle(host
->dev
);
1724 static void dw_mci_ack_sdio_irq(struct mmc_host
*mmc
)
1726 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1728 __dw_mci_enable_sdio_irq(slot
, 1);
1731 static int dw_mci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1733 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1734 struct dw_mci
*host
= slot
->host
;
1735 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1738 if (drv_data
&& drv_data
->execute_tuning
)
1739 err
= drv_data
->execute_tuning(slot
, opcode
);
1743 static int dw_mci_prepare_hs400_tuning(struct mmc_host
*mmc
,
1744 struct mmc_ios
*ios
)
1746 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1747 struct dw_mci
*host
= slot
->host
;
1748 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1750 if (drv_data
&& drv_data
->prepare_hs400_tuning
)
1751 return drv_data
->prepare_hs400_tuning(host
, ios
);
1756 static bool dw_mci_reset(struct dw_mci
*host
)
1758 u32 flags
= SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
;
1763 * Resetting generates a block interrupt, hence setting
1764 * the scatter-gather pointer to NULL.
1767 sg_miter_stop(&host
->sg_miter
);
1772 flags
|= SDMMC_CTRL_DMA_RESET
;
1774 if (dw_mci_ctrl_reset(host
, flags
)) {
1776 * In all cases we clear the RAWINTS
1777 * register to clear any interrupts.
1779 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
1781 if (!host
->use_dma
) {
1786 /* Wait for dma_req to be cleared */
1787 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
1789 !(status
& SDMMC_STATUS_DMA_REQ
),
1790 1, 500 * USEC_PER_MSEC
)) {
1792 "%s: Timeout waiting for dma_req to be cleared\n",
1797 /* when using DMA next we reset the fifo again */
1798 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_FIFO_RESET
))
1801 /* if the controller reset bit did clear, then set clock regs */
1802 if (!(mci_readl(host
, CTRL
) & SDMMC_CTRL_RESET
)) {
1804 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1810 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1811 /* It is also required that we reinit idmac */
1812 dw_mci_idmac_init(host
);
1817 /* After a CTRL reset we need to have CIU set clock registers */
1818 mci_send_cmd(host
->slot
, SDMMC_CMD_UPD_CLK
, 0);
1823 static const struct mmc_host_ops dw_mci_ops
= {
1824 .request
= dw_mci_request
,
1825 .pre_req
= dw_mci_pre_req
,
1826 .post_req
= dw_mci_post_req
,
1827 .set_ios
= dw_mci_set_ios
,
1828 .get_ro
= dw_mci_get_ro
,
1829 .get_cd
= dw_mci_get_cd
,
1830 .hw_reset
= dw_mci_hw_reset
,
1831 .enable_sdio_irq
= dw_mci_enable_sdio_irq
,
1832 .ack_sdio_irq
= dw_mci_ack_sdio_irq
,
1833 .execute_tuning
= dw_mci_execute_tuning
,
1834 .card_busy
= dw_mci_card_busy
,
1835 .start_signal_voltage_switch
= dw_mci_switch_voltage
,
1836 .init_card
= dw_mci_init_card
,
1837 .prepare_hs400_tuning
= dw_mci_prepare_hs400_tuning
,
1840 static void dw_mci_request_end(struct dw_mci
*host
, struct mmc_request
*mrq
)
1841 __releases(&host
->lock
)
1842 __acquires(&host
->lock
)
1844 struct dw_mci_slot
*slot
;
1845 struct mmc_host
*prev_mmc
= host
->slot
->mmc
;
1847 WARN_ON(host
->cmd
|| host
->data
);
1849 host
->slot
->mrq
= NULL
;
1851 if (!list_empty(&host
->queue
)) {
1852 slot
= list_entry(host
->queue
.next
,
1853 struct dw_mci_slot
, queue_node
);
1854 list_del(&slot
->queue_node
);
1855 dev_vdbg(host
->dev
, "list not empty: %s is next\n",
1856 mmc_hostname(slot
->mmc
));
1857 host
->state
= STATE_SENDING_CMD
;
1858 dw_mci_start_request(host
, slot
);
1860 dev_vdbg(host
->dev
, "list empty\n");
1862 if (host
->state
== STATE_SENDING_CMD11
)
1863 host
->state
= STATE_WAITING_CMD11_DONE
;
1865 host
->state
= STATE_IDLE
;
1868 spin_unlock(&host
->lock
);
1869 mmc_request_done(prev_mmc
, mrq
);
1870 spin_lock(&host
->lock
);
1873 static int dw_mci_command_complete(struct dw_mci
*host
, struct mmc_command
*cmd
)
1875 u32 status
= host
->cmd_status
;
1877 host
->cmd_status
= 0;
1879 /* Read the response from the card (up to 16 bytes) */
1880 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1881 if (cmd
->flags
& MMC_RSP_136
) {
1882 cmd
->resp
[3] = mci_readl(host
, RESP0
);
1883 cmd
->resp
[2] = mci_readl(host
, RESP1
);
1884 cmd
->resp
[1] = mci_readl(host
, RESP2
);
1885 cmd
->resp
[0] = mci_readl(host
, RESP3
);
1887 cmd
->resp
[0] = mci_readl(host
, RESP0
);
1894 if (status
& SDMMC_INT_RTO
)
1895 cmd
->error
= -ETIMEDOUT
;
1896 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& SDMMC_INT_RCRC
))
1897 cmd
->error
= -EILSEQ
;
1898 else if (status
& SDMMC_INT_RESP_ERR
)
1906 static int dw_mci_data_complete(struct dw_mci
*host
, struct mmc_data
*data
)
1908 u32 status
= host
->data_status
;
1910 if (status
& DW_MCI_DATA_ERROR_FLAGS
) {
1911 if (status
& SDMMC_INT_DRTO
) {
1912 data
->error
= -ETIMEDOUT
;
1913 } else if (status
& SDMMC_INT_DCRC
) {
1914 data
->error
= -EILSEQ
;
1915 } else if (status
& SDMMC_INT_EBE
) {
1916 if (host
->dir_status
==
1917 DW_MCI_SEND_STATUS
) {
1919 * No data CRC status was returned.
1920 * The number of bytes transferred
1921 * will be exaggerated in PIO mode.
1923 data
->bytes_xfered
= 0;
1924 data
->error
= -ETIMEDOUT
;
1925 } else if (host
->dir_status
==
1926 DW_MCI_RECV_STATUS
) {
1927 data
->error
= -EILSEQ
;
1930 /* SDMMC_INT_SBE is included */
1931 data
->error
= -EILSEQ
;
1934 dev_dbg(host
->dev
, "data error, status 0x%08x\n", status
);
1937 * After an error, there may be data lingering
1942 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1949 static void dw_mci_set_drto(struct dw_mci
*host
)
1951 unsigned int drto_clks
;
1952 unsigned int drto_div
;
1953 unsigned int drto_ms
;
1954 unsigned long irqflags
;
1956 drto_clks
= mci_readl(host
, TMOUT
) >> 8;
1957 drto_div
= (mci_readl(host
, CLKDIV
) & 0xff) * 2;
1961 drto_ms
= DIV_ROUND_UP_ULL((u64
)MSEC_PER_SEC
* drto_clks
* drto_div
,
1964 /* add a bit spare time */
1967 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1968 if (!test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
))
1969 mod_timer(&host
->dto_timer
,
1970 jiffies
+ msecs_to_jiffies(drto_ms
));
1971 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1974 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci
*host
)
1976 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1980 * Really be certain that the timer has stopped. This is a bit of
1981 * paranoia and could only really happen if we had really bad
1982 * interrupt latency and the interrupt routine and timeout were
1983 * running concurrently so that the del_timer() in the interrupt
1984 * handler couldn't run.
1986 WARN_ON(del_timer_sync(&host
->cto_timer
));
1987 clear_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
1992 static bool dw_mci_clear_pending_data_complete(struct dw_mci
*host
)
1994 if (!test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
))
1997 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1998 WARN_ON(del_timer_sync(&host
->dto_timer
));
1999 clear_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2004 static void dw_mci_tasklet_func(unsigned long priv
)
2006 struct dw_mci
*host
= (struct dw_mci
*)priv
;
2007 struct mmc_data
*data
;
2008 struct mmc_command
*cmd
;
2009 struct mmc_request
*mrq
;
2010 enum dw_mci_state state
;
2011 enum dw_mci_state prev_state
;
2014 spin_lock(&host
->lock
);
2016 state
= host
->state
;
2025 case STATE_WAITING_CMD11_DONE
:
2028 case STATE_SENDING_CMD11
:
2029 case STATE_SENDING_CMD
:
2030 if (!dw_mci_clear_pending_cmd_complete(host
))
2035 set_bit(EVENT_CMD_COMPLETE
, &host
->completed_events
);
2036 err
= dw_mci_command_complete(host
, cmd
);
2037 if (cmd
== mrq
->sbc
&& !err
) {
2038 prev_state
= state
= STATE_SENDING_CMD
;
2039 __dw_mci_start_request(host
, host
->slot
,
2044 if (cmd
->data
&& err
) {
2046 * During UHS tuning sequence, sending the stop
2047 * command after the response CRC error would
2048 * throw the system into a confused state
2049 * causing all future tuning phases to report
2052 * In such case controller will move into a data
2053 * transfer state after a response error or
2054 * response CRC error. Let's let that finish
2055 * before trying to send a stop, so we'll go to
2056 * STATE_SENDING_DATA.
2058 * Although letting the data transfer take place
2059 * will waste a bit of time (we already know
2060 * the command was bad), it can't cause any
2061 * errors since it's possible it would have
2062 * taken place anyway if this tasklet got
2063 * delayed. Allowing the transfer to take place
2064 * avoids races and keeps things simple.
2066 if (err
!= -ETIMEDOUT
) {
2067 state
= STATE_SENDING_DATA
;
2071 dw_mci_stop_dma(host
);
2072 send_stop_abort(host
, data
);
2073 state
= STATE_SENDING_STOP
;
2077 if (!cmd
->data
|| err
) {
2078 dw_mci_request_end(host
, mrq
);
2082 prev_state
= state
= STATE_SENDING_DATA
;
2085 case STATE_SENDING_DATA
:
2087 * We could get a data error and never a transfer
2088 * complete so we'd better check for it here.
2090 * Note that we don't really care if we also got a
2091 * transfer complete; stopping the DMA and sending an
2094 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2095 &host
->pending_events
)) {
2096 dw_mci_stop_dma(host
);
2097 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2099 send_stop_abort(host
, data
);
2100 state
= STATE_DATA_ERROR
;
2104 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2105 &host
->pending_events
)) {
2107 * If all data-related interrupts don't come
2108 * within the given time in reading data state.
2110 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2111 dw_mci_set_drto(host
);
2115 set_bit(EVENT_XFER_COMPLETE
, &host
->completed_events
);
2118 * Handle an EVENT_DATA_ERROR that might have shown up
2119 * before the transfer completed. This might not have
2120 * been caught by the check above because the interrupt
2121 * could have gone off between the previous check and
2122 * the check for transfer complete.
2124 * Technically this ought not be needed assuming we
2125 * get a DATA_COMPLETE eventually (we'll notice the
2126 * error and end the request), but it shouldn't hurt.
2128 * This has the advantage of sending the stop command.
2130 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2131 &host
->pending_events
)) {
2132 dw_mci_stop_dma(host
);
2133 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2135 send_stop_abort(host
, data
);
2136 state
= STATE_DATA_ERROR
;
2139 prev_state
= state
= STATE_DATA_BUSY
;
2143 case STATE_DATA_BUSY
:
2144 if (!dw_mci_clear_pending_data_complete(host
)) {
2146 * If data error interrupt comes but data over
2147 * interrupt doesn't come within the given time.
2148 * in reading data state.
2150 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2151 dw_mci_set_drto(host
);
2156 set_bit(EVENT_DATA_COMPLETE
, &host
->completed_events
);
2157 err
= dw_mci_data_complete(host
, data
);
2160 if (!data
->stop
|| mrq
->sbc
) {
2161 if (mrq
->sbc
&& data
->stop
)
2162 data
->stop
->error
= 0;
2163 dw_mci_request_end(host
, mrq
);
2167 /* stop command for open-ended transfer*/
2169 send_stop_abort(host
, data
);
2172 * If we don't have a command complete now we'll
2173 * never get one since we just reset everything;
2174 * better end the request.
2176 * If we do have a command complete we'll fall
2177 * through to the SENDING_STOP command and
2178 * everything will be peachy keen.
2180 if (!test_bit(EVENT_CMD_COMPLETE
,
2181 &host
->pending_events
)) {
2183 dw_mci_request_end(host
, mrq
);
2189 * If err has non-zero,
2190 * stop-abort command has been already issued.
2192 prev_state
= state
= STATE_SENDING_STOP
;
2196 case STATE_SENDING_STOP
:
2197 if (!dw_mci_clear_pending_cmd_complete(host
))
2200 /* CMD error in data command */
2201 if (mrq
->cmd
->error
&& mrq
->data
)
2207 if (!mrq
->sbc
&& mrq
->stop
)
2208 dw_mci_command_complete(host
, mrq
->stop
);
2210 host
->cmd_status
= 0;
2212 dw_mci_request_end(host
, mrq
);
2215 case STATE_DATA_ERROR
:
2216 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2217 &host
->pending_events
))
2220 state
= STATE_DATA_BUSY
;
2223 } while (state
!= prev_state
);
2225 host
->state
= state
;
2227 spin_unlock(&host
->lock
);
2231 /* push final bytes to part_buf, only use during push */
2232 static void dw_mci_set_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2234 memcpy((void *)&host
->part_buf
, buf
, cnt
);
2235 host
->part_buf_count
= cnt
;
2238 /* append bytes to part_buf, only use during push */
2239 static int dw_mci_push_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2241 cnt
= min(cnt
, (1 << host
->data_shift
) - host
->part_buf_count
);
2242 memcpy((void *)&host
->part_buf
+ host
->part_buf_count
, buf
, cnt
);
2243 host
->part_buf_count
+= cnt
;
2247 /* pull first bytes from part_buf, only use during pull */
2248 static int dw_mci_pull_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2250 cnt
= min_t(int, cnt
, host
->part_buf_count
);
2252 memcpy(buf
, (void *)&host
->part_buf
+ host
->part_buf_start
,
2254 host
->part_buf_count
-= cnt
;
2255 host
->part_buf_start
+= cnt
;
2260 /* pull final bytes from the part_buf, assuming it's just been filled */
2261 static void dw_mci_pull_final_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2263 memcpy(buf
, &host
->part_buf
, cnt
);
2264 host
->part_buf_start
= cnt
;
2265 host
->part_buf_count
= (1 << host
->data_shift
) - cnt
;
2268 static void dw_mci_push_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2270 struct mmc_data
*data
= host
->data
;
2273 /* try and push anything in the part_buf */
2274 if (unlikely(host
->part_buf_count
)) {
2275 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2279 if (host
->part_buf_count
== 2) {
2280 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2281 host
->part_buf_count
= 0;
2284 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2285 if (unlikely((unsigned long)buf
& 0x1)) {
2287 u16 aligned_buf
[64];
2288 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2289 int items
= len
>> 1;
2291 /* memcpy from input buffer into aligned buffer */
2292 memcpy(aligned_buf
, buf
, len
);
2295 /* push data from aligned buffer into fifo */
2296 for (i
= 0; i
< items
; ++i
)
2297 mci_fifo_writew(host
->fifo_reg
, aligned_buf
[i
]);
2304 for (; cnt
>= 2; cnt
-= 2)
2305 mci_fifo_writew(host
->fifo_reg
, *pdata
++);
2308 /* put anything remaining in the part_buf */
2310 dw_mci_set_part_bytes(host
, buf
, cnt
);
2311 /* Push data if we have reached the expected data length */
2312 if ((data
->bytes_xfered
+ init_cnt
) ==
2313 (data
->blksz
* data
->blocks
))
2314 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2318 static void dw_mci_pull_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2320 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2321 if (unlikely((unsigned long)buf
& 0x1)) {
2323 /* pull data from fifo into aligned buffer */
2324 u16 aligned_buf
[64];
2325 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2326 int items
= len
>> 1;
2329 for (i
= 0; i
< items
; ++i
)
2330 aligned_buf
[i
] = mci_fifo_readw(host
->fifo_reg
);
2331 /* memcpy from aligned buffer into output buffer */
2332 memcpy(buf
, aligned_buf
, len
);
2341 for (; cnt
>= 2; cnt
-= 2)
2342 *pdata
++ = mci_fifo_readw(host
->fifo_reg
);
2346 host
->part_buf16
= mci_fifo_readw(host
->fifo_reg
);
2347 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2351 static void dw_mci_push_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2353 struct mmc_data
*data
= host
->data
;
2356 /* try and push anything in the part_buf */
2357 if (unlikely(host
->part_buf_count
)) {
2358 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2362 if (host
->part_buf_count
== 4) {
2363 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2364 host
->part_buf_count
= 0;
2367 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2368 if (unlikely((unsigned long)buf
& 0x3)) {
2370 u32 aligned_buf
[32];
2371 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2372 int items
= len
>> 2;
2374 /* memcpy from input buffer into aligned buffer */
2375 memcpy(aligned_buf
, buf
, len
);
2378 /* push data from aligned buffer into fifo */
2379 for (i
= 0; i
< items
; ++i
)
2380 mci_fifo_writel(host
->fifo_reg
, aligned_buf
[i
]);
2387 for (; cnt
>= 4; cnt
-= 4)
2388 mci_fifo_writel(host
->fifo_reg
, *pdata
++);
2391 /* put anything remaining in the part_buf */
2393 dw_mci_set_part_bytes(host
, buf
, cnt
);
2394 /* Push data if we have reached the expected data length */
2395 if ((data
->bytes_xfered
+ init_cnt
) ==
2396 (data
->blksz
* data
->blocks
))
2397 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2401 static void dw_mci_pull_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2403 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2404 if (unlikely((unsigned long)buf
& 0x3)) {
2406 /* pull data from fifo into aligned buffer */
2407 u32 aligned_buf
[32];
2408 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2409 int items
= len
>> 2;
2412 for (i
= 0; i
< items
; ++i
)
2413 aligned_buf
[i
] = mci_fifo_readl(host
->fifo_reg
);
2414 /* memcpy from aligned buffer into output buffer */
2415 memcpy(buf
, aligned_buf
, len
);
2424 for (; cnt
>= 4; cnt
-= 4)
2425 *pdata
++ = mci_fifo_readl(host
->fifo_reg
);
2429 host
->part_buf32
= mci_fifo_readl(host
->fifo_reg
);
2430 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2434 static void dw_mci_push_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2436 struct mmc_data
*data
= host
->data
;
2439 /* try and push anything in the part_buf */
2440 if (unlikely(host
->part_buf_count
)) {
2441 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2446 if (host
->part_buf_count
== 8) {
2447 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2448 host
->part_buf_count
= 0;
2451 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2452 if (unlikely((unsigned long)buf
& 0x7)) {
2454 u64 aligned_buf
[16];
2455 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2456 int items
= len
>> 3;
2458 /* memcpy from input buffer into aligned buffer */
2459 memcpy(aligned_buf
, buf
, len
);
2462 /* push data from aligned buffer into fifo */
2463 for (i
= 0; i
< items
; ++i
)
2464 mci_fifo_writeq(host
->fifo_reg
, aligned_buf
[i
]);
2471 for (; cnt
>= 8; cnt
-= 8)
2472 mci_fifo_writeq(host
->fifo_reg
, *pdata
++);
2475 /* put anything remaining in the part_buf */
2477 dw_mci_set_part_bytes(host
, buf
, cnt
);
2478 /* Push data if we have reached the expected data length */
2479 if ((data
->bytes_xfered
+ init_cnt
) ==
2480 (data
->blksz
* data
->blocks
))
2481 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2485 static void dw_mci_pull_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2487 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2488 if (unlikely((unsigned long)buf
& 0x7)) {
2490 /* pull data from fifo into aligned buffer */
2491 u64 aligned_buf
[16];
2492 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2493 int items
= len
>> 3;
2496 for (i
= 0; i
< items
; ++i
)
2497 aligned_buf
[i
] = mci_fifo_readq(host
->fifo_reg
);
2499 /* memcpy from aligned buffer into output buffer */
2500 memcpy(buf
, aligned_buf
, len
);
2509 for (; cnt
>= 8; cnt
-= 8)
2510 *pdata
++ = mci_fifo_readq(host
->fifo_reg
);
2514 host
->part_buf
= mci_fifo_readq(host
->fifo_reg
);
2515 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2519 static void dw_mci_pull_data(struct dw_mci
*host
, void *buf
, int cnt
)
2523 /* get remaining partial bytes */
2524 len
= dw_mci_pull_part_bytes(host
, buf
, cnt
);
2525 if (unlikely(len
== cnt
))
2530 /* get the rest of the data */
2531 host
->pull_data(host
, buf
, cnt
);
2534 static void dw_mci_read_data_pio(struct dw_mci
*host
, bool dto
)
2536 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2538 unsigned int offset
;
2539 struct mmc_data
*data
= host
->data
;
2540 int shift
= host
->data_shift
;
2543 unsigned int remain
, fcnt
;
2546 if (!sg_miter_next(sg_miter
))
2549 host
->sg
= sg_miter
->piter
.sg
;
2550 buf
= sg_miter
->addr
;
2551 remain
= sg_miter
->length
;
2555 fcnt
= (SDMMC_GET_FCNT(mci_readl(host
, STATUS
))
2556 << shift
) + host
->part_buf_count
;
2557 len
= min(remain
, fcnt
);
2560 dw_mci_pull_data(host
, (void *)(buf
+ offset
), len
);
2561 data
->bytes_xfered
+= len
;
2566 sg_miter
->consumed
= offset
;
2567 status
= mci_readl(host
, MINTSTS
);
2568 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2569 /* if the RXDR is ready read again */
2570 } while ((status
& SDMMC_INT_RXDR
) ||
2571 (dto
&& SDMMC_GET_FCNT(mci_readl(host
, STATUS
))));
2574 if (!sg_miter_next(sg_miter
))
2576 sg_miter
->consumed
= 0;
2578 sg_miter_stop(sg_miter
);
2582 sg_miter_stop(sg_miter
);
2584 smp_wmb(); /* drain writebuffer */
2585 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2588 static void dw_mci_write_data_pio(struct dw_mci
*host
)
2590 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2592 unsigned int offset
;
2593 struct mmc_data
*data
= host
->data
;
2594 int shift
= host
->data_shift
;
2597 unsigned int fifo_depth
= host
->fifo_depth
;
2598 unsigned int remain
, fcnt
;
2601 if (!sg_miter_next(sg_miter
))
2604 host
->sg
= sg_miter
->piter
.sg
;
2605 buf
= sg_miter
->addr
;
2606 remain
= sg_miter
->length
;
2610 fcnt
= ((fifo_depth
-
2611 SDMMC_GET_FCNT(mci_readl(host
, STATUS
)))
2612 << shift
) - host
->part_buf_count
;
2613 len
= min(remain
, fcnt
);
2616 host
->push_data(host
, (void *)(buf
+ offset
), len
);
2617 data
->bytes_xfered
+= len
;
2622 sg_miter
->consumed
= offset
;
2623 status
= mci_readl(host
, MINTSTS
);
2624 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2625 } while (status
& SDMMC_INT_TXDR
); /* if TXDR write again */
2628 if (!sg_miter_next(sg_miter
))
2630 sg_miter
->consumed
= 0;
2632 sg_miter_stop(sg_miter
);
2636 sg_miter_stop(sg_miter
);
2638 smp_wmb(); /* drain writebuffer */
2639 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2642 static void dw_mci_cmd_interrupt(struct dw_mci
*host
, u32 status
)
2644 del_timer(&host
->cto_timer
);
2646 if (!host
->cmd_status
)
2647 host
->cmd_status
= status
;
2649 smp_wmb(); /* drain writebuffer */
2651 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2652 tasklet_schedule(&host
->tasklet
);
2655 static void dw_mci_handle_cd(struct dw_mci
*host
)
2657 struct dw_mci_slot
*slot
= host
->slot
;
2659 if (slot
->mmc
->ops
->card_event
)
2660 slot
->mmc
->ops
->card_event(slot
->mmc
);
2661 mmc_detect_change(slot
->mmc
,
2662 msecs_to_jiffies(host
->pdata
->detect_delay_ms
));
2665 static irqreturn_t
dw_mci_interrupt(int irq
, void *dev_id
)
2667 struct dw_mci
*host
= dev_id
;
2669 struct dw_mci_slot
*slot
= host
->slot
;
2670 unsigned long irqflags
;
2672 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
2675 /* Check volt switch first, since it can look like an error */
2676 if ((host
->state
== STATE_SENDING_CMD11
) &&
2677 (pending
& SDMMC_INT_VOLT_SWITCH
)) {
2678 mci_writel(host
, RINTSTS
, SDMMC_INT_VOLT_SWITCH
);
2679 pending
&= ~SDMMC_INT_VOLT_SWITCH
;
2682 * Hold the lock; we know cmd11_timer can't be kicked
2683 * off after the lock is released, so safe to delete.
2685 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2686 dw_mci_cmd_interrupt(host
, pending
);
2687 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2689 del_timer(&host
->cmd11_timer
);
2692 if (pending
& DW_MCI_CMD_ERROR_FLAGS
) {
2693 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2695 del_timer(&host
->cto_timer
);
2696 mci_writel(host
, RINTSTS
, DW_MCI_CMD_ERROR_FLAGS
);
2697 host
->cmd_status
= pending
;
2698 smp_wmb(); /* drain writebuffer */
2699 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2701 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2704 if (pending
& DW_MCI_DATA_ERROR_FLAGS
) {
2705 /* if there is an error report DATA_ERROR */
2706 mci_writel(host
, RINTSTS
, DW_MCI_DATA_ERROR_FLAGS
);
2707 host
->data_status
= pending
;
2708 smp_wmb(); /* drain writebuffer */
2709 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2710 tasklet_schedule(&host
->tasklet
);
2713 if (pending
& SDMMC_INT_DATA_OVER
) {
2714 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2716 del_timer(&host
->dto_timer
);
2718 mci_writel(host
, RINTSTS
, SDMMC_INT_DATA_OVER
);
2719 if (!host
->data_status
)
2720 host
->data_status
= pending
;
2721 smp_wmb(); /* drain writebuffer */
2722 if (host
->dir_status
== DW_MCI_RECV_STATUS
) {
2723 if (host
->sg
!= NULL
)
2724 dw_mci_read_data_pio(host
, true);
2726 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2727 tasklet_schedule(&host
->tasklet
);
2729 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2732 if (pending
& SDMMC_INT_RXDR
) {
2733 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2734 if (host
->dir_status
== DW_MCI_RECV_STATUS
&& host
->sg
)
2735 dw_mci_read_data_pio(host
, false);
2738 if (pending
& SDMMC_INT_TXDR
) {
2739 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2740 if (host
->dir_status
== DW_MCI_SEND_STATUS
&& host
->sg
)
2741 dw_mci_write_data_pio(host
);
2744 if (pending
& SDMMC_INT_CMD_DONE
) {
2745 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2747 mci_writel(host
, RINTSTS
, SDMMC_INT_CMD_DONE
);
2748 dw_mci_cmd_interrupt(host
, pending
);
2750 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2753 if (pending
& SDMMC_INT_CD
) {
2754 mci_writel(host
, RINTSTS
, SDMMC_INT_CD
);
2755 dw_mci_handle_cd(host
);
2758 if (pending
& SDMMC_INT_SDIO(slot
->sdio_id
)) {
2759 mci_writel(host
, RINTSTS
,
2760 SDMMC_INT_SDIO(slot
->sdio_id
));
2761 __dw_mci_enable_sdio_irq(slot
, 0);
2762 sdio_signal_irq(slot
->mmc
);
2767 if (host
->use_dma
!= TRANS_MODE_IDMAC
)
2770 /* Handle IDMA interrupts */
2771 if (host
->dma_64bit_address
== 1) {
2772 pending
= mci_readl(host
, IDSTS64
);
2773 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2774 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_TI
|
2775 SDMMC_IDMAC_INT_RI
);
2776 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_NI
);
2777 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2778 host
->dma_ops
->complete((void *)host
);
2781 pending
= mci_readl(host
, IDSTS
);
2782 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2783 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_TI
|
2784 SDMMC_IDMAC_INT_RI
);
2785 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_NI
);
2786 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2787 host
->dma_ops
->complete((void *)host
);
2794 static int dw_mci_init_slot_caps(struct dw_mci_slot
*slot
)
2796 struct dw_mci
*host
= slot
->host
;
2797 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2798 struct mmc_host
*mmc
= slot
->mmc
;
2801 if (host
->pdata
->caps
)
2802 mmc
->caps
= host
->pdata
->caps
;
2805 * Support MMC_CAP_ERASE by default.
2806 * It needs to use trim/discard/erase commands.
2808 mmc
->caps
|= MMC_CAP_ERASE
;
2810 if (host
->pdata
->pm_caps
)
2811 mmc
->pm_caps
= host
->pdata
->pm_caps
;
2813 if (host
->dev
->of_node
) {
2814 ctrl_id
= of_alias_get_id(host
->dev
->of_node
, "mshc");
2818 ctrl_id
= to_platform_device(host
->dev
)->id
;
2821 if (drv_data
&& drv_data
->caps
) {
2822 if (ctrl_id
>= drv_data
->num_caps
) {
2823 dev_err(host
->dev
, "invalid controller id %d\n",
2827 mmc
->caps
|= drv_data
->caps
[ctrl_id
];
2830 if (host
->pdata
->caps2
)
2831 mmc
->caps2
= host
->pdata
->caps2
;
2833 /* Process SDIO IRQs through the sdio_irq_work. */
2834 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
)
2835 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
2840 static int dw_mci_init_slot(struct dw_mci
*host
)
2842 struct mmc_host
*mmc
;
2843 struct dw_mci_slot
*slot
;
2847 mmc
= mmc_alloc_host(sizeof(struct dw_mci_slot
), host
->dev
);
2851 slot
= mmc_priv(mmc
);
2853 slot
->sdio_id
= host
->sdio_id0
+ slot
->id
;
2858 mmc
->ops
= &dw_mci_ops
;
2859 if (device_property_read_u32_array(host
->dev
, "clock-freq-min-max",
2861 mmc
->f_min
= DW_MCI_FREQ_MIN
;
2862 mmc
->f_max
= DW_MCI_FREQ_MAX
;
2865 "'clock-freq-min-max' property was deprecated.\n");
2866 mmc
->f_min
= freq
[0];
2867 mmc
->f_max
= freq
[1];
2870 /*if there are external regulators, get them*/
2871 ret
= mmc_regulator_get_supply(mmc
);
2873 goto err_host_allocated
;
2875 if (!mmc
->ocr_avail
)
2876 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2878 ret
= mmc_of_parse(mmc
);
2880 goto err_host_allocated
;
2882 ret
= dw_mci_init_slot_caps(slot
);
2884 goto err_host_allocated
;
2886 /* Useful defaults if platform data is unset. */
2887 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2888 mmc
->max_segs
= host
->ring_size
;
2889 mmc
->max_blk_size
= 65535;
2890 mmc
->max_seg_size
= 0x1000;
2891 mmc
->max_req_size
= mmc
->max_seg_size
* host
->ring_size
;
2892 mmc
->max_blk_count
= mmc
->max_req_size
/ 512;
2893 } else if (host
->use_dma
== TRANS_MODE_EDMAC
) {
2895 mmc
->max_blk_size
= 65535;
2896 mmc
->max_blk_count
= 65535;
2898 mmc
->max_blk_size
* mmc
->max_blk_count
;
2899 mmc
->max_seg_size
= mmc
->max_req_size
;
2901 /* TRANS_MODE_PIO */
2903 mmc
->max_blk_size
= 65535; /* BLKSIZ is 16 bits */
2904 mmc
->max_blk_count
= 512;
2905 mmc
->max_req_size
= mmc
->max_blk_size
*
2907 mmc
->max_seg_size
= mmc
->max_req_size
;
2912 ret
= mmc_add_host(mmc
);
2914 goto err_host_allocated
;
2916 #if defined(CONFIG_DEBUG_FS)
2917 dw_mci_init_debugfs(slot
);
2927 static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot
)
2929 /* Debugfs stuff is cleaned up by mmc core */
2930 mmc_remove_host(slot
->mmc
);
2931 slot
->host
->slot
= NULL
;
2932 mmc_free_host(slot
->mmc
);
2935 static void dw_mci_init_dma(struct dw_mci
*host
)
2938 struct device
*dev
= host
->dev
;
2941 * Check tansfer mode from HCON[17:16]
2942 * Clear the ambiguous description of dw_mmc databook:
2943 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2944 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2945 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2946 * 2b'11: Non DW DMA Interface -> pio only
2947 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2948 * simpler request/acknowledge handshake mechanism and both of them
2949 * are regarded as external dma master for dw_mmc.
2951 host
->use_dma
= SDMMC_GET_TRANS_MODE(mci_readl(host
, HCON
));
2952 if (host
->use_dma
== DMA_INTERFACE_IDMA
) {
2953 host
->use_dma
= TRANS_MODE_IDMAC
;
2954 } else if (host
->use_dma
== DMA_INTERFACE_DWDMA
||
2955 host
->use_dma
== DMA_INTERFACE_GDMA
) {
2956 host
->use_dma
= TRANS_MODE_EDMAC
;
2961 /* Determine which DMA interface to use */
2962 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2964 * Check ADDR_CONFIG bit in HCON to find
2965 * IDMAC address bus width
2967 addr_config
= SDMMC_GET_ADDR_CONFIG(mci_readl(host
, HCON
));
2969 if (addr_config
== 1) {
2970 /* host supports IDMAC in 64-bit address mode */
2971 host
->dma_64bit_address
= 1;
2973 "IDMAC supports 64-bit address mode.\n");
2974 if (!dma_set_mask(host
->dev
, DMA_BIT_MASK(64)))
2975 dma_set_coherent_mask(host
->dev
,
2978 /* host supports IDMAC in 32-bit address mode */
2979 host
->dma_64bit_address
= 0;
2981 "IDMAC supports 32-bit address mode.\n");
2984 /* Alloc memory for sg translation */
2985 host
->sg_cpu
= dmam_alloc_coherent(host
->dev
,
2987 &host
->sg_dma
, GFP_KERNEL
);
2988 if (!host
->sg_cpu
) {
2990 "%s: could not alloc DMA memory\n",
2995 host
->dma_ops
= &dw_mci_idmac_ops
;
2996 dev_info(host
->dev
, "Using internal DMA controller.\n");
2998 /* TRANS_MODE_EDMAC: check dma bindings again */
2999 if ((device_property_read_string_array(dev
, "dma-names",
3001 !device_property_present(dev
, "dmas")) {
3004 host
->dma_ops
= &dw_mci_edmac_ops
;
3005 dev_info(host
->dev
, "Using external DMA controller.\n");
3008 if (host
->dma_ops
->init
&& host
->dma_ops
->start
&&
3009 host
->dma_ops
->stop
&& host
->dma_ops
->cleanup
) {
3010 if (host
->dma_ops
->init(host
)) {
3011 dev_err(host
->dev
, "%s: Unable to initialize DMA Controller.\n",
3016 dev_err(host
->dev
, "DMA initialization not found.\n");
3023 dev_info(host
->dev
, "Using PIO mode.\n");
3024 host
->use_dma
= TRANS_MODE_PIO
;
3027 static void dw_mci_cmd11_timer(struct timer_list
*t
)
3029 struct dw_mci
*host
= from_timer(host
, t
, cmd11_timer
);
3031 if (host
->state
!= STATE_SENDING_CMD11
) {
3032 dev_warn(host
->dev
, "Unexpected CMD11 timeout\n");
3036 host
->cmd_status
= SDMMC_INT_RTO
;
3037 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
3038 tasklet_schedule(&host
->tasklet
);
3041 static void dw_mci_cto_timer(struct timer_list
*t
)
3043 struct dw_mci
*host
= from_timer(host
, t
, cto_timer
);
3044 unsigned long irqflags
;
3047 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3050 * If somehow we have very bad interrupt latency it's remotely possible
3051 * that the timer could fire while the interrupt is still pending or
3052 * while the interrupt is midway through running. Let's be paranoid
3053 * and detect those two cases. Note that this is paranoia is somewhat
3054 * justified because in this function we don't actually cancel the
3055 * pending command in the controller--we just assume it will never come.
3057 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
3058 if (pending
& (DW_MCI_CMD_ERROR_FLAGS
| SDMMC_INT_CMD_DONE
)) {
3059 /* The interrupt should fire; no need to act but we can warn */
3060 dev_warn(host
->dev
, "Unexpected interrupt latency\n");
3063 if (test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
)) {
3064 /* Presumably interrupt handler couldn't delete the timer */
3065 dev_warn(host
->dev
, "CTO timeout when already completed\n");
3070 * Continued paranoia to make sure we're in the state we expect.
3071 * This paranoia isn't really justified but it seems good to be safe.
3073 switch (host
->state
) {
3074 case STATE_SENDING_CMD11
:
3075 case STATE_SENDING_CMD
:
3076 case STATE_SENDING_STOP
:
3078 * If CMD_DONE interrupt does NOT come in sending command
3079 * state, we should notify the driver to terminate current
3080 * transfer and report a command timeout to the core.
3082 host
->cmd_status
= SDMMC_INT_RTO
;
3083 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
3084 tasklet_schedule(&host
->tasklet
);
3087 dev_warn(host
->dev
, "Unexpected command timeout, state %d\n",
3093 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3096 static void dw_mci_dto_timer(struct timer_list
*t
)
3098 struct dw_mci
*host
= from_timer(host
, t
, dto_timer
);
3099 unsigned long irqflags
;
3102 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3105 * The DTO timer is much longer than the CTO timer, so it's even less
3106 * likely that we'll these cases, but it pays to be paranoid.
3108 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
3109 if (pending
& SDMMC_INT_DATA_OVER
) {
3110 /* The interrupt should fire; no need to act but we can warn */
3111 dev_warn(host
->dev
, "Unexpected data interrupt latency\n");
3114 if (test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
)) {
3115 /* Presumably interrupt handler couldn't delete the timer */
3116 dev_warn(host
->dev
, "DTO timeout when already completed\n");
3121 * Continued paranoia to make sure we're in the state we expect.
3122 * This paranoia isn't really justified but it seems good to be safe.
3124 switch (host
->state
) {
3125 case STATE_SENDING_DATA
:
3126 case STATE_DATA_BUSY
:
3128 * If DTO interrupt does NOT come in sending data state,
3129 * we should notify the driver to terminate current transfer
3130 * and report a data timeout to the core.
3132 host
->data_status
= SDMMC_INT_DRTO
;
3133 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
3134 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
3135 tasklet_schedule(&host
->tasklet
);
3138 dev_warn(host
->dev
, "Unexpected data timeout, state %d\n",
3144 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3148 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
3150 struct dw_mci_board
*pdata
;
3151 struct device
*dev
= host
->dev
;
3152 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
3154 u32 clock_frequency
;
3156 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
3158 return ERR_PTR(-ENOMEM
);
3160 /* find reset controller when exist */
3161 pdata
->rstc
= devm_reset_control_get_optional_exclusive(dev
, "reset");
3162 if (IS_ERR(pdata
->rstc
)) {
3163 if (PTR_ERR(pdata
->rstc
) == -EPROBE_DEFER
)
3164 return ERR_PTR(-EPROBE_DEFER
);
3167 /* find out number of slots supported */
3168 if (!device_property_read_u32(dev
, "num-slots", &pdata
->num_slots
))
3169 dev_info(dev
, "'num-slots' was deprecated.\n");
3171 if (device_property_read_u32(dev
, "fifo-depth", &pdata
->fifo_depth
))
3173 "fifo-depth property not found, using value of FIFOTH register as default\n");
3175 device_property_read_u32(dev
, "card-detect-delay",
3176 &pdata
->detect_delay_ms
);
3178 device_property_read_u32(dev
, "data-addr", &host
->data_addr_override
);
3180 if (device_property_present(dev
, "fifo-watermark-aligned"))
3181 host
->wm_aligned
= true;
3183 if (!device_property_read_u32(dev
, "clock-frequency", &clock_frequency
))
3184 pdata
->bus_hz
= clock_frequency
;
3186 if (drv_data
&& drv_data
->parse_dt
) {
3187 ret
= drv_data
->parse_dt(host
);
3189 return ERR_PTR(ret
);
3195 #else /* CONFIG_OF */
3196 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
3198 return ERR_PTR(-EINVAL
);
3200 #endif /* CONFIG_OF */
3202 static void dw_mci_enable_cd(struct dw_mci
*host
)
3204 unsigned long irqflags
;
3208 * No need for CD if all slots have a non-error GPIO
3209 * as well as broken card detection is found.
3211 if (host
->slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
)
3214 if (mmc_gpio_get_cd(host
->slot
->mmc
) < 0) {
3215 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3216 temp
= mci_readl(host
, INTMASK
);
3217 temp
|= SDMMC_INT_CD
;
3218 mci_writel(host
, INTMASK
, temp
);
3219 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3223 int dw_mci_probe(struct dw_mci
*host
)
3225 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
3226 int width
, i
, ret
= 0;
3230 host
->pdata
= dw_mci_parse_dt(host
);
3231 if (PTR_ERR(host
->pdata
) == -EPROBE_DEFER
) {
3232 return -EPROBE_DEFER
;
3233 } else if (IS_ERR(host
->pdata
)) {
3234 dev_err(host
->dev
, "platform data not available\n");
3239 host
->biu_clk
= devm_clk_get(host
->dev
, "biu");
3240 if (IS_ERR(host
->biu_clk
)) {
3241 dev_dbg(host
->dev
, "biu clock not available\n");
3243 ret
= clk_prepare_enable(host
->biu_clk
);
3245 dev_err(host
->dev
, "failed to enable biu clock\n");
3250 host
->ciu_clk
= devm_clk_get(host
->dev
, "ciu");
3251 if (IS_ERR(host
->ciu_clk
)) {
3252 dev_dbg(host
->dev
, "ciu clock not available\n");
3253 host
->bus_hz
= host
->pdata
->bus_hz
;
3255 ret
= clk_prepare_enable(host
->ciu_clk
);
3257 dev_err(host
->dev
, "failed to enable ciu clock\n");
3261 if (host
->pdata
->bus_hz
) {
3262 ret
= clk_set_rate(host
->ciu_clk
, host
->pdata
->bus_hz
);
3265 "Unable to set bus rate to %uHz\n",
3266 host
->pdata
->bus_hz
);
3268 host
->bus_hz
= clk_get_rate(host
->ciu_clk
);
3271 if (!host
->bus_hz
) {
3273 "Platform data must supply bus speed\n");
3278 if (!IS_ERR(host
->pdata
->rstc
)) {
3279 reset_control_assert(host
->pdata
->rstc
);
3280 usleep_range(10, 50);
3281 reset_control_deassert(host
->pdata
->rstc
);
3284 if (drv_data
&& drv_data
->init
) {
3285 ret
= drv_data
->init(host
);
3288 "implementation specific init failed\n");
3293 timer_setup(&host
->cmd11_timer
, dw_mci_cmd11_timer
, 0);
3294 timer_setup(&host
->cto_timer
, dw_mci_cto_timer
, 0);
3295 timer_setup(&host
->dto_timer
, dw_mci_dto_timer
, 0);
3297 spin_lock_init(&host
->lock
);
3298 spin_lock_init(&host
->irq_lock
);
3299 INIT_LIST_HEAD(&host
->queue
);
3302 * Get the host data width - this assumes that HCON has been set with
3303 * the correct values.
3305 i
= SDMMC_GET_HDATA_WIDTH(mci_readl(host
, HCON
));
3307 host
->push_data
= dw_mci_push_data16
;
3308 host
->pull_data
= dw_mci_pull_data16
;
3310 host
->data_shift
= 1;
3311 } else if (i
== 2) {
3312 host
->push_data
= dw_mci_push_data64
;
3313 host
->pull_data
= dw_mci_pull_data64
;
3315 host
->data_shift
= 3;
3317 /* Check for a reserved value, and warn if it is */
3319 "HCON reports a reserved host data width!\n"
3320 "Defaulting to 32-bit access.\n");
3321 host
->push_data
= dw_mci_push_data32
;
3322 host
->pull_data
= dw_mci_pull_data32
;
3324 host
->data_shift
= 2;
3327 /* Reset all blocks */
3328 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3333 host
->dma_ops
= host
->pdata
->dma_ops
;
3334 dw_mci_init_dma(host
);
3336 /* Clear the interrupts for the host controller */
3337 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3338 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3340 /* Put in max timeout */
3341 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3344 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3345 * Tx Mark = fifo_size / 2 DMA Size = 8
3347 if (!host
->pdata
->fifo_depth
) {
3349 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3350 * have been overwritten by the bootloader, just like we're
3351 * about to do, so if you know the value for your hardware, you
3352 * should put it in the platform data.
3354 fifo_size
= mci_readl(host
, FIFOTH
);
3355 fifo_size
= 1 + ((fifo_size
>> 16) & 0xfff);
3357 fifo_size
= host
->pdata
->fifo_depth
;
3359 host
->fifo_depth
= fifo_size
;
3361 SDMMC_SET_FIFOTH(0x2, fifo_size
/ 2 - 1, fifo_size
/ 2);
3362 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3364 /* disable clock to CIU */
3365 mci_writel(host
, CLKENA
, 0);
3366 mci_writel(host
, CLKSRC
, 0);
3369 * In 2.40a spec, Data offset is changed.
3370 * Need to check the version-id and set data-offset for DATA register.
3372 host
->verid
= SDMMC_GET_VERID(mci_readl(host
, VERID
));
3373 dev_info(host
->dev
, "Version ID is %04x\n", host
->verid
);
3375 if (host
->data_addr_override
)
3376 host
->fifo_reg
= host
->regs
+ host
->data_addr_override
;
3377 else if (host
->verid
< DW_MMC_240A
)
3378 host
->fifo_reg
= host
->regs
+ DATA_OFFSET
;
3380 host
->fifo_reg
= host
->regs
+ DATA_240A_OFFSET
;
3382 tasklet_init(&host
->tasklet
, dw_mci_tasklet_func
, (unsigned long)host
);
3383 ret
= devm_request_irq(host
->dev
, host
->irq
, dw_mci_interrupt
,
3384 host
->irq_flags
, "dw-mci", host
);
3389 * Enable interrupts for command done, data over, data empty,
3390 * receive ready and error such as transmit, receive timeout, crc error
3392 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3393 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3394 DW_MCI_ERROR_FLAGS
);
3395 /* Enable mci interrupt */
3396 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3399 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3400 host
->irq
, width
, fifo_size
);
3402 /* We need at least one slot to succeed */
3403 ret
= dw_mci_init_slot(host
);
3405 dev_dbg(host
->dev
, "slot %d init failed\n", i
);
3409 /* Now that slots are all setup, we can enable card detect */
3410 dw_mci_enable_cd(host
);
3415 if (host
->use_dma
&& host
->dma_ops
->exit
)
3416 host
->dma_ops
->exit(host
);
3418 if (!IS_ERR(host
->pdata
->rstc
))
3419 reset_control_assert(host
->pdata
->rstc
);
3422 clk_disable_unprepare(host
->ciu_clk
);
3425 clk_disable_unprepare(host
->biu_clk
);
3429 EXPORT_SYMBOL(dw_mci_probe
);
3431 void dw_mci_remove(struct dw_mci
*host
)
3433 dev_dbg(host
->dev
, "remove slot\n");
3435 dw_mci_cleanup_slot(host
->slot
);
3437 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3438 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3440 /* disable clock to CIU */
3441 mci_writel(host
, CLKENA
, 0);
3442 mci_writel(host
, CLKSRC
, 0);
3444 if (host
->use_dma
&& host
->dma_ops
->exit
)
3445 host
->dma_ops
->exit(host
);
3447 if (!IS_ERR(host
->pdata
->rstc
))
3448 reset_control_assert(host
->pdata
->rstc
);
3450 clk_disable_unprepare(host
->ciu_clk
);
3451 clk_disable_unprepare(host
->biu_clk
);
3453 EXPORT_SYMBOL(dw_mci_remove
);
3458 int dw_mci_runtime_suspend(struct device
*dev
)
3460 struct dw_mci
*host
= dev_get_drvdata(dev
);
3462 if (host
->use_dma
&& host
->dma_ops
->exit
)
3463 host
->dma_ops
->exit(host
);
3465 clk_disable_unprepare(host
->ciu_clk
);
3468 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3469 !mmc_card_is_removable(host
->slot
->mmc
)))
3470 clk_disable_unprepare(host
->biu_clk
);
3474 EXPORT_SYMBOL(dw_mci_runtime_suspend
);
3476 int dw_mci_runtime_resume(struct device
*dev
)
3479 struct dw_mci
*host
= dev_get_drvdata(dev
);
3482 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3483 !mmc_card_is_removable(host
->slot
->mmc
))) {
3484 ret
= clk_prepare_enable(host
->biu_clk
);
3489 ret
= clk_prepare_enable(host
->ciu_clk
);
3493 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3494 clk_disable_unprepare(host
->ciu_clk
);
3499 if (host
->use_dma
&& host
->dma_ops
->init
)
3500 host
->dma_ops
->init(host
);
3503 * Restore the initial value at FIFOTH register
3504 * And Invalidate the prev_blksz with zero
3506 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3507 host
->prev_blksz
= 0;
3509 /* Put in max timeout */
3510 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3512 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3513 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3514 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3515 DW_MCI_ERROR_FLAGS
);
3516 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3519 if (host
->slot
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)
3520 dw_mci_set_ios(host
->slot
->mmc
, &host
->slot
->mmc
->ios
);
3522 /* Force setup bus to guarantee available clock output */
3523 dw_mci_setup_bus(host
->slot
, true);
3525 /* Now that slots are all setup, we can enable card detect */
3526 dw_mci_enable_cd(host
);
3532 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3533 !mmc_card_is_removable(host
->slot
->mmc
)))
3534 clk_disable_unprepare(host
->biu_clk
);
3538 EXPORT_SYMBOL(dw_mci_runtime_resume
);
3539 #endif /* CONFIG_PM */
3541 static int __init
dw_mci_init(void)
3543 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3547 static void __exit
dw_mci_exit(void)
3551 module_init(dw_mci_init
);
3552 module_exit(dw_mci_exit
);
3554 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3555 MODULE_AUTHOR("NXP Semiconductor VietNam");
3556 MODULE_AUTHOR("Imagination Technologies Ltd");
3557 MODULE_LICENSE("GPL v2");