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Merge tag 'for-4.2' of git://git.infradead.org/battery-2.6
[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/of.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #include "dw_mmc.h"
43
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
55
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74
75 u32 des3; /* Reserved */
76
77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79
80 u32 des6; /* Lower 32-bits of Next Descriptor Address */
81 u32 des7; /* Upper 32-bits of Next Descriptor Address */
82 };
83
84 struct idmac_desc {
85 __le32 des0; /* Control Descriptor */
86 #define IDMAC_DES0_DIC BIT(1)
87 #define IDMAC_DES0_LD BIT(2)
88 #define IDMAC_DES0_FD BIT(3)
89 #define IDMAC_DES0_CH BIT(4)
90 #define IDMAC_DES0_ER BIT(5)
91 #define IDMAC_DES0_CES BIT(30)
92 #define IDMAC_DES0_OWN BIT(31)
93
94 __le32 des1; /* Buffer sizes */
95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
96 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
97
98 __le32 des2; /* buffer 1 physical address */
99
100 __le32 des3; /* buffer 2 physical address */
101 };
102 #endif /* CONFIG_MMC_DW_IDMAC */
103
104 static bool dw_mci_reset(struct dw_mci *host);
105 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
106 static int dw_mci_card_busy(struct mmc_host *mmc);
107
108 #if defined(CONFIG_DEBUG_FS)
109 static int dw_mci_req_show(struct seq_file *s, void *v)
110 {
111 struct dw_mci_slot *slot = s->private;
112 struct mmc_request *mrq;
113 struct mmc_command *cmd;
114 struct mmc_command *stop;
115 struct mmc_data *data;
116
117 /* Make sure we get a consistent snapshot */
118 spin_lock_bh(&slot->host->lock);
119 mrq = slot->mrq;
120
121 if (mrq) {
122 cmd = mrq->cmd;
123 data = mrq->data;
124 stop = mrq->stop;
125
126 if (cmd)
127 seq_printf(s,
128 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
129 cmd->opcode, cmd->arg, cmd->flags,
130 cmd->resp[0], cmd->resp[1], cmd->resp[2],
131 cmd->resp[2], cmd->error);
132 if (data)
133 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
134 data->bytes_xfered, data->blocks,
135 data->blksz, data->flags, data->error);
136 if (stop)
137 seq_printf(s,
138 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
139 stop->opcode, stop->arg, stop->flags,
140 stop->resp[0], stop->resp[1], stop->resp[2],
141 stop->resp[2], stop->error);
142 }
143
144 spin_unlock_bh(&slot->host->lock);
145
146 return 0;
147 }
148
149 static int dw_mci_req_open(struct inode *inode, struct file *file)
150 {
151 return single_open(file, dw_mci_req_show, inode->i_private);
152 }
153
154 static const struct file_operations dw_mci_req_fops = {
155 .owner = THIS_MODULE,
156 .open = dw_mci_req_open,
157 .read = seq_read,
158 .llseek = seq_lseek,
159 .release = single_release,
160 };
161
162 static int dw_mci_regs_show(struct seq_file *s, void *v)
163 {
164 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
165 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
166 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
167 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
168 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
169 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
170
171 return 0;
172 }
173
174 static int dw_mci_regs_open(struct inode *inode, struct file *file)
175 {
176 return single_open(file, dw_mci_regs_show, inode->i_private);
177 }
178
179 static const struct file_operations dw_mci_regs_fops = {
180 .owner = THIS_MODULE,
181 .open = dw_mci_regs_open,
182 .read = seq_read,
183 .llseek = seq_lseek,
184 .release = single_release,
185 };
186
187 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
188 {
189 struct mmc_host *mmc = slot->mmc;
190 struct dw_mci *host = slot->host;
191 struct dentry *root;
192 struct dentry *node;
193
194 root = mmc->debugfs_root;
195 if (!root)
196 return;
197
198 node = debugfs_create_file("regs", S_IRUSR, root, host,
199 &dw_mci_regs_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_file("req", S_IRUSR, root, slot,
204 &dw_mci_req_fops);
205 if (!node)
206 goto err;
207
208 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("pending_events", S_IRUSR, root,
213 (u32 *)&host->pending_events);
214 if (!node)
215 goto err;
216
217 node = debugfs_create_x32("completed_events", S_IRUSR, root,
218 (u32 *)&host->completed_events);
219 if (!node)
220 goto err;
221
222 return;
223
224 err:
225 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
226 }
227 #endif /* defined(CONFIG_DEBUG_FS) */
228
229 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
230
231 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
232 {
233 struct mmc_data *data;
234 struct dw_mci_slot *slot = mmc_priv(mmc);
235 struct dw_mci *host = slot->host;
236 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
237 u32 cmdr;
238 cmd->error = -EINPROGRESS;
239
240 cmdr = cmd->opcode;
241
242 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
243 cmd->opcode == MMC_GO_IDLE_STATE ||
244 cmd->opcode == MMC_GO_INACTIVE_STATE ||
245 (cmd->opcode == SD_IO_RW_DIRECT &&
246 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
247 cmdr |= SDMMC_CMD_STOP;
248 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
249 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
250
251 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
252 u32 clk_en_a;
253
254 /* Special bit makes CMD11 not die */
255 cmdr |= SDMMC_CMD_VOLT_SWITCH;
256
257 /* Change state to continue to handle CMD11 weirdness */
258 WARN_ON(slot->host->state != STATE_SENDING_CMD);
259 slot->host->state = STATE_SENDING_CMD11;
260
261 /*
262 * We need to disable low power mode (automatic clock stop)
263 * while doing voltage switch so we don't confuse the card,
264 * since stopping the clock is a specific part of the UHS
265 * voltage change dance.
266 *
267 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
268 * unconditionally turned back on in dw_mci_setup_bus() if it's
269 * ever called with a non-zero clock. That shouldn't happen
270 * until the voltage change is all done.
271 */
272 clk_en_a = mci_readl(host, CLKENA);
273 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
274 mci_writel(host, CLKENA, clk_en_a);
275 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
276 SDMMC_CMD_PRV_DAT_WAIT, 0);
277 }
278
279 if (cmd->flags & MMC_RSP_PRESENT) {
280 /* We expect a response, so set this bit */
281 cmdr |= SDMMC_CMD_RESP_EXP;
282 if (cmd->flags & MMC_RSP_136)
283 cmdr |= SDMMC_CMD_RESP_LONG;
284 }
285
286 if (cmd->flags & MMC_RSP_CRC)
287 cmdr |= SDMMC_CMD_RESP_CRC;
288
289 data = cmd->data;
290 if (data) {
291 cmdr |= SDMMC_CMD_DAT_EXP;
292 if (data->flags & MMC_DATA_STREAM)
293 cmdr |= SDMMC_CMD_STRM_MODE;
294 if (data->flags & MMC_DATA_WRITE)
295 cmdr |= SDMMC_CMD_DAT_WR;
296 }
297
298 if (drv_data && drv_data->prepare_command)
299 drv_data->prepare_command(slot->host, &cmdr);
300
301 return cmdr;
302 }
303
304 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
305 {
306 struct mmc_command *stop;
307 u32 cmdr;
308
309 if (!cmd->data)
310 return 0;
311
312 stop = &host->stop_abort;
313 cmdr = cmd->opcode;
314 memset(stop, 0, sizeof(struct mmc_command));
315
316 if (cmdr == MMC_READ_SINGLE_BLOCK ||
317 cmdr == MMC_READ_MULTIPLE_BLOCK ||
318 cmdr == MMC_WRITE_BLOCK ||
319 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
322 stop->opcode = MMC_STOP_TRANSMISSION;
323 stop->arg = 0;
324 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
325 } else if (cmdr == SD_IO_RW_EXTENDED) {
326 stop->opcode = SD_IO_RW_DIRECT;
327 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
328 ((cmd->arg >> 28) & 0x7);
329 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
330 } else {
331 return 0;
332 }
333
334 cmdr = stop->opcode | SDMMC_CMD_STOP |
335 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
336
337 return cmdr;
338 }
339
340 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
341 {
342 unsigned long timeout = jiffies + msecs_to_jiffies(500);
343
344 /*
345 * Databook says that before issuing a new data transfer command
346 * we need to check to see if the card is busy. Data transfer commands
347 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
348 *
349 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
350 * expected.
351 */
352 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
353 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
354 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
355 if (time_after(jiffies, timeout)) {
356 /* Command will fail; we'll pass error then */
357 dev_err(host->dev, "Busy; trying anyway\n");
358 break;
359 }
360 udelay(10);
361 }
362 }
363 }
364
365 static void dw_mci_start_command(struct dw_mci *host,
366 struct mmc_command *cmd, u32 cmd_flags)
367 {
368 host->cmd = cmd;
369 dev_vdbg(host->dev,
370 "start command: ARGR=0x%08x CMDR=0x%08x\n",
371 cmd->arg, cmd_flags);
372
373 mci_writel(host, CMDARG, cmd->arg);
374 wmb();
375 dw_mci_wait_while_busy(host, cmd_flags);
376
377 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
378 }
379
380 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
381 {
382 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
383 dw_mci_start_command(host, stop, host->stop_cmdr);
384 }
385
386 /* DMA interface functions */
387 static void dw_mci_stop_dma(struct dw_mci *host)
388 {
389 if (host->using_dma) {
390 host->dma_ops->stop(host);
391 host->dma_ops->cleanup(host);
392 }
393
394 /* Data transfer was stopped by the interrupt handler */
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
396 }
397
398 static int dw_mci_get_dma_dir(struct mmc_data *data)
399 {
400 if (data->flags & MMC_DATA_WRITE)
401 return DMA_TO_DEVICE;
402 else
403 return DMA_FROM_DEVICE;
404 }
405
406 #ifdef CONFIG_MMC_DW_IDMAC
407 static void dw_mci_dma_cleanup(struct dw_mci *host)
408 {
409 struct mmc_data *data = host->data;
410
411 if (data)
412 if (!data->host_cookie)
413 dma_unmap_sg(host->dev,
414 data->sg,
415 data->sg_len,
416 dw_mci_get_dma_dir(data));
417 }
418
419 static void dw_mci_idmac_reset(struct dw_mci *host)
420 {
421 u32 bmod = mci_readl(host, BMOD);
422 /* Software reset of DMA */
423 bmod |= SDMMC_IDMAC_SWRESET;
424 mci_writel(host, BMOD, bmod);
425 }
426
427 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
428 {
429 u32 temp;
430
431 /* Disable and reset the IDMAC interface */
432 temp = mci_readl(host, CTRL);
433 temp &= ~SDMMC_CTRL_USE_IDMAC;
434 temp |= SDMMC_CTRL_DMA_RESET;
435 mci_writel(host, CTRL, temp);
436
437 /* Stop the IDMAC running */
438 temp = mci_readl(host, BMOD);
439 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
440 temp |= SDMMC_IDMAC_SWRESET;
441 mci_writel(host, BMOD, temp);
442 }
443
444 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
445 {
446 struct mmc_data *data = host->data;
447
448 dev_vdbg(host->dev, "DMA complete\n");
449
450 host->dma_ops->cleanup(host);
451
452 /*
453 * If the card was removed, data will be NULL. No point in trying to
454 * send the stop command or waiting for NBUSY in this case.
455 */
456 if (data) {
457 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
458 tasklet_schedule(&host->tasklet);
459 }
460 }
461
462 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
463 unsigned int sg_len)
464 {
465 int i;
466 if (host->dma_64bit_address == 1) {
467 struct idmac_desc_64addr *desc = host->sg_cpu;
468
469 for (i = 0; i < sg_len; i++, desc++) {
470 unsigned int length = sg_dma_len(&data->sg[i]);
471 u64 mem_addr = sg_dma_address(&data->sg[i]);
472
473 /*
474 * Set the OWN bit and disable interrupts for this
475 * descriptor
476 */
477 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
478 IDMAC_DES0_CH;
479 /* Buffer length */
480 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
481
482 /* Physical address to DMA to/from */
483 desc->des4 = mem_addr & 0xffffffff;
484 desc->des5 = mem_addr >> 32;
485 }
486
487 /* Set first descriptor */
488 desc = host->sg_cpu;
489 desc->des0 |= IDMAC_DES0_FD;
490
491 /* Set last descriptor */
492 desc = host->sg_cpu + (i - 1) *
493 sizeof(struct idmac_desc_64addr);
494 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
495 desc->des0 |= IDMAC_DES0_LD;
496
497 } else {
498 struct idmac_desc *desc = host->sg_cpu;
499
500 for (i = 0; i < sg_len; i++, desc++) {
501 unsigned int length = sg_dma_len(&data->sg[i]);
502 u32 mem_addr = sg_dma_address(&data->sg[i]);
503
504 /*
505 * Set the OWN bit and disable interrupts for this
506 * descriptor
507 */
508 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
509 IDMAC_DES0_DIC | IDMAC_DES0_CH);
510 /* Buffer length */
511 IDMAC_SET_BUFFER1_SIZE(desc, length);
512
513 /* Physical address to DMA to/from */
514 desc->des2 = cpu_to_le32(mem_addr);
515 }
516
517 /* Set first descriptor */
518 desc = host->sg_cpu;
519 desc->des0 |= cpu_to_le32(IDMAC_DES0_FD);
520
521 /* Set last descriptor */
522 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
523 desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC));
524 desc->des0 |= cpu_to_le32(IDMAC_DES0_LD);
525 }
526
527 wmb();
528 }
529
530 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
531 {
532 u32 temp;
533
534 dw_mci_translate_sglist(host, host->data, sg_len);
535
536 /* Make sure to reset DMA in case we did PIO before this */
537 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
538 dw_mci_idmac_reset(host);
539
540 /* Select IDMAC interface */
541 temp = mci_readl(host, CTRL);
542 temp |= SDMMC_CTRL_USE_IDMAC;
543 mci_writel(host, CTRL, temp);
544
545 wmb();
546
547 /* Enable the IDMAC */
548 temp = mci_readl(host, BMOD);
549 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
550 mci_writel(host, BMOD, temp);
551
552 /* Start it running */
553 mci_writel(host, PLDMND, 1);
554 }
555
556 static int dw_mci_idmac_init(struct dw_mci *host)
557 {
558 int i;
559
560 if (host->dma_64bit_address == 1) {
561 struct idmac_desc_64addr *p;
562 /* Number of descriptors in the ring buffer */
563 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
564
565 /* Forward link the descriptor list */
566 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
567 i++, p++) {
568 p->des6 = (host->sg_dma +
569 (sizeof(struct idmac_desc_64addr) *
570 (i + 1))) & 0xffffffff;
571
572 p->des7 = (u64)(host->sg_dma +
573 (sizeof(struct idmac_desc_64addr) *
574 (i + 1))) >> 32;
575 /* Initialize reserved and buffer size fields to "0" */
576 p->des1 = 0;
577 p->des2 = 0;
578 p->des3 = 0;
579 }
580
581 /* Set the last descriptor as the end-of-ring descriptor */
582 p->des6 = host->sg_dma & 0xffffffff;
583 p->des7 = (u64)host->sg_dma >> 32;
584 p->des0 = IDMAC_DES0_ER;
585
586 } else {
587 struct idmac_desc *p;
588 /* Number of descriptors in the ring buffer */
589 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
590
591 /* Forward link the descriptor list */
592 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
593 p->des3 = cpu_to_le32(host->sg_dma +
594 (sizeof(struct idmac_desc) * (i + 1)));
595 p->des1 = 0;
596 }
597
598 /* Set the last descriptor as the end-of-ring descriptor */
599 p->des3 = cpu_to_le32(host->sg_dma);
600 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
601 }
602
603 dw_mci_idmac_reset(host);
604
605 if (host->dma_64bit_address == 1) {
606 /* Mask out interrupts - get Tx & Rx complete only */
607 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
608 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
609 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
610
611 /* Set the descriptor base address */
612 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
613 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
614
615 } else {
616 /* Mask out interrupts - get Tx & Rx complete only */
617 mci_writel(host, IDSTS, IDMAC_INT_CLR);
618 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
619 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
620
621 /* Set the descriptor base address */
622 mci_writel(host, DBADDR, host->sg_dma);
623 }
624
625 return 0;
626 }
627
628 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
629 .init = dw_mci_idmac_init,
630 .start = dw_mci_idmac_start_dma,
631 .stop = dw_mci_idmac_stop_dma,
632 .complete = dw_mci_idmac_complete_dma,
633 .cleanup = dw_mci_dma_cleanup,
634 };
635 #endif /* CONFIG_MMC_DW_IDMAC */
636
637 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
638 struct mmc_data *data,
639 bool next)
640 {
641 struct scatterlist *sg;
642 unsigned int i, sg_len;
643
644 if (!next && data->host_cookie)
645 return data->host_cookie;
646
647 /*
648 * We don't do DMA on "complex" transfers, i.e. with
649 * non-word-aligned buffers or lengths. Also, we don't bother
650 * with all the DMA setup overhead for short transfers.
651 */
652 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
653 return -EINVAL;
654
655 if (data->blksz & 3)
656 return -EINVAL;
657
658 for_each_sg(data->sg, sg, data->sg_len, i) {
659 if (sg->offset & 3 || sg->length & 3)
660 return -EINVAL;
661 }
662
663 sg_len = dma_map_sg(host->dev,
664 data->sg,
665 data->sg_len,
666 dw_mci_get_dma_dir(data));
667 if (sg_len == 0)
668 return -EINVAL;
669
670 if (next)
671 data->host_cookie = sg_len;
672
673 return sg_len;
674 }
675
676 static void dw_mci_pre_req(struct mmc_host *mmc,
677 struct mmc_request *mrq,
678 bool is_first_req)
679 {
680 struct dw_mci_slot *slot = mmc_priv(mmc);
681 struct mmc_data *data = mrq->data;
682
683 if (!slot->host->use_dma || !data)
684 return;
685
686 if (data->host_cookie) {
687 data->host_cookie = 0;
688 return;
689 }
690
691 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
692 data->host_cookie = 0;
693 }
694
695 static void dw_mci_post_req(struct mmc_host *mmc,
696 struct mmc_request *mrq,
697 int err)
698 {
699 struct dw_mci_slot *slot = mmc_priv(mmc);
700 struct mmc_data *data = mrq->data;
701
702 if (!slot->host->use_dma || !data)
703 return;
704
705 if (data->host_cookie)
706 dma_unmap_sg(slot->host->dev,
707 data->sg,
708 data->sg_len,
709 dw_mci_get_dma_dir(data));
710 data->host_cookie = 0;
711 }
712
713 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
714 {
715 #ifdef CONFIG_MMC_DW_IDMAC
716 unsigned int blksz = data->blksz;
717 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
718 u32 fifo_width = 1 << host->data_shift;
719 u32 blksz_depth = blksz / fifo_width, fifoth_val;
720 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
721 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
722
723 tx_wmark = (host->fifo_depth) / 2;
724 tx_wmark_invers = host->fifo_depth - tx_wmark;
725
726 /*
727 * MSIZE is '1',
728 * if blksz is not a multiple of the FIFO width
729 */
730 if (blksz % fifo_width) {
731 msize = 0;
732 rx_wmark = 1;
733 goto done;
734 }
735
736 do {
737 if (!((blksz_depth % mszs[idx]) ||
738 (tx_wmark_invers % mszs[idx]))) {
739 msize = idx;
740 rx_wmark = mszs[idx] - 1;
741 break;
742 }
743 } while (--idx > 0);
744 /*
745 * If idx is '0', it won't be tried
746 * Thus, initial values are uesed
747 */
748 done:
749 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
750 mci_writel(host, FIFOTH, fifoth_val);
751 #endif
752 }
753
754 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
755 {
756 unsigned int blksz = data->blksz;
757 u32 blksz_depth, fifo_depth;
758 u16 thld_size;
759
760 WARN_ON(!(data->flags & MMC_DATA_READ));
761
762 /*
763 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
764 * in the FIFO region, so we really shouldn't access it).
765 */
766 if (host->verid < DW_MMC_240A)
767 return;
768
769 if (host->timing != MMC_TIMING_MMC_HS200 &&
770 host->timing != MMC_TIMING_MMC_HS400 &&
771 host->timing != MMC_TIMING_UHS_SDR104)
772 goto disable;
773
774 blksz_depth = blksz / (1 << host->data_shift);
775 fifo_depth = host->fifo_depth;
776
777 if (blksz_depth > fifo_depth)
778 goto disable;
779
780 /*
781 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
782 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
783 * Currently just choose blksz.
784 */
785 thld_size = blksz;
786 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
787 return;
788
789 disable:
790 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
791 }
792
793 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
794 {
795 unsigned long irqflags;
796 int sg_len;
797 u32 temp;
798
799 host->using_dma = 0;
800
801 /* If we don't have a channel, we can't do DMA */
802 if (!host->use_dma)
803 return -ENODEV;
804
805 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
806 if (sg_len < 0) {
807 host->dma_ops->stop(host);
808 return sg_len;
809 }
810
811 host->using_dma = 1;
812
813 dev_vdbg(host->dev,
814 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
815 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
816 sg_len);
817
818 /*
819 * Decide the MSIZE and RX/TX Watermark.
820 * If current block size is same with previous size,
821 * no need to update fifoth.
822 */
823 if (host->prev_blksz != data->blksz)
824 dw_mci_adjust_fifoth(host, data);
825
826 /* Enable the DMA interface */
827 temp = mci_readl(host, CTRL);
828 temp |= SDMMC_CTRL_DMA_ENABLE;
829 mci_writel(host, CTRL, temp);
830
831 /* Disable RX/TX IRQs, let DMA handle it */
832 spin_lock_irqsave(&host->irq_lock, irqflags);
833 temp = mci_readl(host, INTMASK);
834 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
835 mci_writel(host, INTMASK, temp);
836 spin_unlock_irqrestore(&host->irq_lock, irqflags);
837
838 host->dma_ops->start(host, sg_len);
839
840 return 0;
841 }
842
843 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
844 {
845 unsigned long irqflags;
846 u32 temp;
847
848 data->error = -EINPROGRESS;
849
850 WARN_ON(host->data);
851 host->sg = NULL;
852 host->data = data;
853
854 if (data->flags & MMC_DATA_READ) {
855 host->dir_status = DW_MCI_RECV_STATUS;
856 dw_mci_ctrl_rd_thld(host, data);
857 } else {
858 host->dir_status = DW_MCI_SEND_STATUS;
859 }
860
861 if (dw_mci_submit_data_dma(host, data)) {
862 int flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867
868 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
869 host->sg = data->sg;
870 host->part_buf_start = 0;
871 host->part_buf_count = 0;
872
873 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
874
875 spin_lock_irqsave(&host->irq_lock, irqflags);
876 temp = mci_readl(host, INTMASK);
877 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
878 mci_writel(host, INTMASK, temp);
879 spin_unlock_irqrestore(&host->irq_lock, irqflags);
880
881 temp = mci_readl(host, CTRL);
882 temp &= ~SDMMC_CTRL_DMA_ENABLE;
883 mci_writel(host, CTRL, temp);
884
885 /*
886 * Use the initial fifoth_val for PIO mode.
887 * If next issued data may be transfered by DMA mode,
888 * prev_blksz should be invalidated.
889 */
890 mci_writel(host, FIFOTH, host->fifoth_val);
891 host->prev_blksz = 0;
892 } else {
893 /*
894 * Keep the current block size.
895 * It will be used to decide whether to update
896 * fifoth register next time.
897 */
898 host->prev_blksz = data->blksz;
899 }
900 }
901
902 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
903 {
904 struct dw_mci *host = slot->host;
905 unsigned long timeout = jiffies + msecs_to_jiffies(500);
906 unsigned int cmd_status = 0;
907
908 mci_writel(host, CMDARG, arg);
909 wmb();
910 dw_mci_wait_while_busy(host, cmd);
911 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
912
913 while (time_before(jiffies, timeout)) {
914 cmd_status = mci_readl(host, CMD);
915 if (!(cmd_status & SDMMC_CMD_START))
916 return;
917 }
918 dev_err(&slot->mmc->class_dev,
919 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
920 cmd, arg, cmd_status);
921 }
922
923 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
924 {
925 struct dw_mci *host = slot->host;
926 unsigned int clock = slot->clock;
927 u32 div;
928 u32 clk_en_a;
929 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
930
931 /* We must continue to set bit 28 in CMD until the change is complete */
932 if (host->state == STATE_WAITING_CMD11_DONE)
933 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
934
935 if (!clock) {
936 mci_writel(host, CLKENA, 0);
937 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
938 } else if (clock != host->current_speed || force_clkinit) {
939 div = host->bus_hz / clock;
940 if (host->bus_hz % clock && host->bus_hz > clock)
941 /*
942 * move the + 1 after the divide to prevent
943 * over-clocking the card.
944 */
945 div += 1;
946
947 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
948
949 if ((clock << div) != slot->__clk_old || force_clkinit)
950 dev_info(&slot->mmc->class_dev,
951 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
952 slot->id, host->bus_hz, clock,
953 div ? ((host->bus_hz / div) >> 1) :
954 host->bus_hz, div);
955
956 /* disable clock */
957 mci_writel(host, CLKENA, 0);
958 mci_writel(host, CLKSRC, 0);
959
960 /* inform CIU */
961 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
962
963 /* set clock to desired speed */
964 mci_writel(host, CLKDIV, div);
965
966 /* inform CIU */
967 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
968
969 /* enable clock; only low power if no SDIO */
970 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
971 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
972 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
973 mci_writel(host, CLKENA, clk_en_a);
974
975 /* inform CIU */
976 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
977
978 /* keep the clock with reflecting clock dividor */
979 slot->__clk_old = clock << div;
980 }
981
982 host->current_speed = clock;
983
984 /* Set the current slot bus width */
985 mci_writel(host, CTYPE, (slot->ctype << slot->id));
986 }
987
988 static void __dw_mci_start_request(struct dw_mci *host,
989 struct dw_mci_slot *slot,
990 struct mmc_command *cmd)
991 {
992 struct mmc_request *mrq;
993 struct mmc_data *data;
994 u32 cmdflags;
995
996 mrq = slot->mrq;
997
998 host->cur_slot = slot;
999 host->mrq = mrq;
1000
1001 host->pending_events = 0;
1002 host->completed_events = 0;
1003 host->cmd_status = 0;
1004 host->data_status = 0;
1005 host->dir_status = 0;
1006
1007 data = cmd->data;
1008 if (data) {
1009 mci_writel(host, TMOUT, 0xFFFFFFFF);
1010 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1011 mci_writel(host, BLKSIZ, data->blksz);
1012 }
1013
1014 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1015
1016 /* this is the first command, send the initialization clock */
1017 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1018 cmdflags |= SDMMC_CMD_INIT;
1019
1020 if (data) {
1021 dw_mci_submit_data(host, data);
1022 wmb();
1023 }
1024
1025 dw_mci_start_command(host, cmd, cmdflags);
1026
1027 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1028 unsigned long irqflags;
1029
1030 /*
1031 * Databook says to fail after 2ms w/ no response, but evidence
1032 * shows that sometimes the cmd11 interrupt takes over 130ms.
1033 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1034 * is just about to roll over.
1035 *
1036 * We do this whole thing under spinlock and only if the
1037 * command hasn't already completed (indicating the the irq
1038 * already ran so we don't want the timeout).
1039 */
1040 spin_lock_irqsave(&host->irq_lock, irqflags);
1041 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1042 mod_timer(&host->cmd11_timer,
1043 jiffies + msecs_to_jiffies(500) + 1);
1044 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1045 }
1046
1047 if (mrq->stop)
1048 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1049 else
1050 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1051 }
1052
1053 static void dw_mci_start_request(struct dw_mci *host,
1054 struct dw_mci_slot *slot)
1055 {
1056 struct mmc_request *mrq = slot->mrq;
1057 struct mmc_command *cmd;
1058
1059 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1060 __dw_mci_start_request(host, slot, cmd);
1061 }
1062
1063 /* must be called with host->lock held */
1064 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1065 struct mmc_request *mrq)
1066 {
1067 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1068 host->state);
1069
1070 slot->mrq = mrq;
1071
1072 if (host->state == STATE_WAITING_CMD11_DONE) {
1073 dev_warn(&slot->mmc->class_dev,
1074 "Voltage change didn't complete\n");
1075 /*
1076 * this case isn't expected to happen, so we can
1077 * either crash here or just try to continue on
1078 * in the closest possible state
1079 */
1080 host->state = STATE_IDLE;
1081 }
1082
1083 if (host->state == STATE_IDLE) {
1084 host->state = STATE_SENDING_CMD;
1085 dw_mci_start_request(host, slot);
1086 } else {
1087 list_add_tail(&slot->queue_node, &host->queue);
1088 }
1089 }
1090
1091 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1092 {
1093 struct dw_mci_slot *slot = mmc_priv(mmc);
1094 struct dw_mci *host = slot->host;
1095
1096 WARN_ON(slot->mrq);
1097
1098 /*
1099 * The check for card presence and queueing of the request must be
1100 * atomic, otherwise the card could be removed in between and the
1101 * request wouldn't fail until another card was inserted.
1102 */
1103 spin_lock_bh(&host->lock);
1104
1105 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1106 spin_unlock_bh(&host->lock);
1107 mrq->cmd->error = -ENOMEDIUM;
1108 mmc_request_done(mmc, mrq);
1109 return;
1110 }
1111
1112 dw_mci_queue_request(host, slot, mrq);
1113
1114 spin_unlock_bh(&host->lock);
1115 }
1116
1117 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1118 {
1119 struct dw_mci_slot *slot = mmc_priv(mmc);
1120 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1121 u32 regs;
1122 int ret;
1123
1124 switch (ios->bus_width) {
1125 case MMC_BUS_WIDTH_4:
1126 slot->ctype = SDMMC_CTYPE_4BIT;
1127 break;
1128 case MMC_BUS_WIDTH_8:
1129 slot->ctype = SDMMC_CTYPE_8BIT;
1130 break;
1131 default:
1132 /* set default 1 bit mode */
1133 slot->ctype = SDMMC_CTYPE_1BIT;
1134 }
1135
1136 regs = mci_readl(slot->host, UHS_REG);
1137
1138 /* DDR mode set */
1139 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1140 ios->timing == MMC_TIMING_MMC_HS400)
1141 regs |= ((0x1 << slot->id) << 16);
1142 else
1143 regs &= ~((0x1 << slot->id) << 16);
1144
1145 mci_writel(slot->host, UHS_REG, regs);
1146 slot->host->timing = ios->timing;
1147
1148 /*
1149 * Use mirror of ios->clock to prevent race with mmc
1150 * core ios update when finding the minimum.
1151 */
1152 slot->clock = ios->clock;
1153
1154 if (drv_data && drv_data->set_ios)
1155 drv_data->set_ios(slot->host, ios);
1156
1157 switch (ios->power_mode) {
1158 case MMC_POWER_UP:
1159 if (!IS_ERR(mmc->supply.vmmc)) {
1160 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1161 ios->vdd);
1162 if (ret) {
1163 dev_err(slot->host->dev,
1164 "failed to enable vmmc regulator\n");
1165 /*return, if failed turn on vmmc*/
1166 return;
1167 }
1168 }
1169 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1170 regs = mci_readl(slot->host, PWREN);
1171 regs |= (1 << slot->id);
1172 mci_writel(slot->host, PWREN, regs);
1173 break;
1174 case MMC_POWER_ON:
1175 if (!slot->host->vqmmc_enabled) {
1176 if (!IS_ERR(mmc->supply.vqmmc)) {
1177 ret = regulator_enable(mmc->supply.vqmmc);
1178 if (ret < 0)
1179 dev_err(slot->host->dev,
1180 "failed to enable vqmmc\n");
1181 else
1182 slot->host->vqmmc_enabled = true;
1183
1184 } else {
1185 /* Keep track so we don't reset again */
1186 slot->host->vqmmc_enabled = true;
1187 }
1188
1189 /* Reset our state machine after powering on */
1190 dw_mci_ctrl_reset(slot->host,
1191 SDMMC_CTRL_ALL_RESET_FLAGS);
1192 }
1193
1194 /* Adjust clock / bus width after power is up */
1195 dw_mci_setup_bus(slot, false);
1196
1197 break;
1198 case MMC_POWER_OFF:
1199 /* Turn clock off before power goes down */
1200 dw_mci_setup_bus(slot, false);
1201
1202 if (!IS_ERR(mmc->supply.vmmc))
1203 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1204
1205 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1206 regulator_disable(mmc->supply.vqmmc);
1207 slot->host->vqmmc_enabled = false;
1208
1209 regs = mci_readl(slot->host, PWREN);
1210 regs &= ~(1 << slot->id);
1211 mci_writel(slot->host, PWREN, regs);
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1218 slot->host->state = STATE_IDLE;
1219 }
1220
1221 static int dw_mci_card_busy(struct mmc_host *mmc)
1222 {
1223 struct dw_mci_slot *slot = mmc_priv(mmc);
1224 u32 status;
1225
1226 /*
1227 * Check the busy bit which is low when DAT[3:0]
1228 * (the data lines) are 0000
1229 */
1230 status = mci_readl(slot->host, STATUS);
1231
1232 return !!(status & SDMMC_STATUS_BUSY);
1233 }
1234
1235 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1236 {
1237 struct dw_mci_slot *slot = mmc_priv(mmc);
1238 struct dw_mci *host = slot->host;
1239 const struct dw_mci_drv_data *drv_data = host->drv_data;
1240 u32 uhs;
1241 u32 v18 = SDMMC_UHS_18V << slot->id;
1242 int min_uv, max_uv;
1243 int ret;
1244
1245 if (drv_data && drv_data->switch_voltage)
1246 return drv_data->switch_voltage(mmc, ios);
1247
1248 /*
1249 * Program the voltage. Note that some instances of dw_mmc may use
1250 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1251 * does no harm but you need to set the regulator directly. Try both.
1252 */
1253 uhs = mci_readl(host, UHS_REG);
1254 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1255 min_uv = 2700000;
1256 max_uv = 3600000;
1257 uhs &= ~v18;
1258 } else {
1259 min_uv = 1700000;
1260 max_uv = 1950000;
1261 uhs |= v18;
1262 }
1263 if (!IS_ERR(mmc->supply.vqmmc)) {
1264 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1265
1266 if (ret) {
1267 dev_dbg(&mmc->class_dev,
1268 "Regulator set error %d: %d - %d\n",
1269 ret, min_uv, max_uv);
1270 return ret;
1271 }
1272 }
1273 mci_writel(host, UHS_REG, uhs);
1274
1275 return 0;
1276 }
1277
1278 static int dw_mci_get_ro(struct mmc_host *mmc)
1279 {
1280 int read_only;
1281 struct dw_mci_slot *slot = mmc_priv(mmc);
1282 int gpio_ro = mmc_gpio_get_ro(mmc);
1283
1284 /* Use platform get_ro function, else try on board write protect */
1285 if (!IS_ERR_VALUE(gpio_ro))
1286 read_only = gpio_ro;
1287 else
1288 read_only =
1289 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1290
1291 dev_dbg(&mmc->class_dev, "card is %s\n",
1292 read_only ? "read-only" : "read-write");
1293
1294 return read_only;
1295 }
1296
1297 static int dw_mci_get_cd(struct mmc_host *mmc)
1298 {
1299 int present;
1300 struct dw_mci_slot *slot = mmc_priv(mmc);
1301 struct dw_mci_board *brd = slot->host->pdata;
1302 struct dw_mci *host = slot->host;
1303 int gpio_cd = mmc_gpio_get_cd(mmc);
1304
1305 /* Use platform get_cd function, else try onboard card detect */
1306 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1307 (mmc->caps & MMC_CAP_NONREMOVABLE))
1308 present = 1;
1309 else if (!IS_ERR_VALUE(gpio_cd))
1310 present = gpio_cd;
1311 else
1312 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1313 == 0 ? 1 : 0;
1314
1315 spin_lock_bh(&host->lock);
1316 if (present) {
1317 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1318 dev_dbg(&mmc->class_dev, "card is present\n");
1319 } else {
1320 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1321 dev_dbg(&mmc->class_dev, "card is not present\n");
1322 }
1323 spin_unlock_bh(&host->lock);
1324
1325 return present;
1326 }
1327
1328 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1329 {
1330 struct dw_mci_slot *slot = mmc_priv(mmc);
1331 struct dw_mci *host = slot->host;
1332
1333 /*
1334 * Low power mode will stop the card clock when idle. According to the
1335 * description of the CLKENA register we should disable low power mode
1336 * for SDIO cards if we need SDIO interrupts to work.
1337 */
1338 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1339 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1340 u32 clk_en_a_old;
1341 u32 clk_en_a;
1342
1343 clk_en_a_old = mci_readl(host, CLKENA);
1344
1345 if (card->type == MMC_TYPE_SDIO ||
1346 card->type == MMC_TYPE_SD_COMBO) {
1347 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1348 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1349 } else {
1350 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1351 clk_en_a = clk_en_a_old | clken_low_pwr;
1352 }
1353
1354 if (clk_en_a != clk_en_a_old) {
1355 mci_writel(host, CLKENA, clk_en_a);
1356 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1357 SDMMC_CMD_PRV_DAT_WAIT, 0);
1358 }
1359 }
1360 }
1361
1362 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1363 {
1364 struct dw_mci_slot *slot = mmc_priv(mmc);
1365 struct dw_mci *host = slot->host;
1366 unsigned long irqflags;
1367 u32 int_mask;
1368
1369 spin_lock_irqsave(&host->irq_lock, irqflags);
1370
1371 /* Enable/disable Slot Specific SDIO interrupt */
1372 int_mask = mci_readl(host, INTMASK);
1373 if (enb)
1374 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1375 else
1376 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1377 mci_writel(host, INTMASK, int_mask);
1378
1379 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1380 }
1381
1382 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1383 {
1384 struct dw_mci_slot *slot = mmc_priv(mmc);
1385 struct dw_mci *host = slot->host;
1386 const struct dw_mci_drv_data *drv_data = host->drv_data;
1387 int err = -ENOSYS;
1388
1389 if (drv_data && drv_data->execute_tuning)
1390 err = drv_data->execute_tuning(slot);
1391 return err;
1392 }
1393
1394 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1395 {
1396 struct dw_mci_slot *slot = mmc_priv(mmc);
1397 struct dw_mci *host = slot->host;
1398 const struct dw_mci_drv_data *drv_data = host->drv_data;
1399
1400 if (drv_data && drv_data->prepare_hs400_tuning)
1401 return drv_data->prepare_hs400_tuning(host, ios);
1402
1403 return 0;
1404 }
1405
1406 static const struct mmc_host_ops dw_mci_ops = {
1407 .request = dw_mci_request,
1408 .pre_req = dw_mci_pre_req,
1409 .post_req = dw_mci_post_req,
1410 .set_ios = dw_mci_set_ios,
1411 .get_ro = dw_mci_get_ro,
1412 .get_cd = dw_mci_get_cd,
1413 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1414 .execute_tuning = dw_mci_execute_tuning,
1415 .card_busy = dw_mci_card_busy,
1416 .start_signal_voltage_switch = dw_mci_switch_voltage,
1417 .init_card = dw_mci_init_card,
1418 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1419 };
1420
1421 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1422 __releases(&host->lock)
1423 __acquires(&host->lock)
1424 {
1425 struct dw_mci_slot *slot;
1426 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1427
1428 WARN_ON(host->cmd || host->data);
1429
1430 host->cur_slot->mrq = NULL;
1431 host->mrq = NULL;
1432 if (!list_empty(&host->queue)) {
1433 slot = list_entry(host->queue.next,
1434 struct dw_mci_slot, queue_node);
1435 list_del(&slot->queue_node);
1436 dev_vdbg(host->dev, "list not empty: %s is next\n",
1437 mmc_hostname(slot->mmc));
1438 host->state = STATE_SENDING_CMD;
1439 dw_mci_start_request(host, slot);
1440 } else {
1441 dev_vdbg(host->dev, "list empty\n");
1442
1443 if (host->state == STATE_SENDING_CMD11)
1444 host->state = STATE_WAITING_CMD11_DONE;
1445 else
1446 host->state = STATE_IDLE;
1447 }
1448
1449 spin_unlock(&host->lock);
1450 mmc_request_done(prev_mmc, mrq);
1451 spin_lock(&host->lock);
1452 }
1453
1454 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1455 {
1456 u32 status = host->cmd_status;
1457
1458 host->cmd_status = 0;
1459
1460 /* Read the response from the card (up to 16 bytes) */
1461 if (cmd->flags & MMC_RSP_PRESENT) {
1462 if (cmd->flags & MMC_RSP_136) {
1463 cmd->resp[3] = mci_readl(host, RESP0);
1464 cmd->resp[2] = mci_readl(host, RESP1);
1465 cmd->resp[1] = mci_readl(host, RESP2);
1466 cmd->resp[0] = mci_readl(host, RESP3);
1467 } else {
1468 cmd->resp[0] = mci_readl(host, RESP0);
1469 cmd->resp[1] = 0;
1470 cmd->resp[2] = 0;
1471 cmd->resp[3] = 0;
1472 }
1473 }
1474
1475 if (status & SDMMC_INT_RTO)
1476 cmd->error = -ETIMEDOUT;
1477 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1478 cmd->error = -EILSEQ;
1479 else if (status & SDMMC_INT_RESP_ERR)
1480 cmd->error = -EIO;
1481 else
1482 cmd->error = 0;
1483
1484 if (cmd->error) {
1485 /* newer ip versions need a delay between retries */
1486 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1487 mdelay(20);
1488 }
1489
1490 return cmd->error;
1491 }
1492
1493 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1494 {
1495 u32 status = host->data_status;
1496
1497 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1498 if (status & SDMMC_INT_DRTO) {
1499 data->error = -ETIMEDOUT;
1500 } else if (status & SDMMC_INT_DCRC) {
1501 data->error = -EILSEQ;
1502 } else if (status & SDMMC_INT_EBE) {
1503 if (host->dir_status ==
1504 DW_MCI_SEND_STATUS) {
1505 /*
1506 * No data CRC status was returned.
1507 * The number of bytes transferred
1508 * will be exaggerated in PIO mode.
1509 */
1510 data->bytes_xfered = 0;
1511 data->error = -ETIMEDOUT;
1512 } else if (host->dir_status ==
1513 DW_MCI_RECV_STATUS) {
1514 data->error = -EIO;
1515 }
1516 } else {
1517 /* SDMMC_INT_SBE is included */
1518 data->error = -EIO;
1519 }
1520
1521 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1522
1523 /*
1524 * After an error, there may be data lingering
1525 * in the FIFO
1526 */
1527 dw_mci_reset(host);
1528 } else {
1529 data->bytes_xfered = data->blocks * data->blksz;
1530 data->error = 0;
1531 }
1532
1533 return data->error;
1534 }
1535
1536 static void dw_mci_tasklet_func(unsigned long priv)
1537 {
1538 struct dw_mci *host = (struct dw_mci *)priv;
1539 struct mmc_data *data;
1540 struct mmc_command *cmd;
1541 struct mmc_request *mrq;
1542 enum dw_mci_state state;
1543 enum dw_mci_state prev_state;
1544 unsigned int err;
1545
1546 spin_lock(&host->lock);
1547
1548 state = host->state;
1549 data = host->data;
1550 mrq = host->mrq;
1551
1552 do {
1553 prev_state = state;
1554
1555 switch (state) {
1556 case STATE_IDLE:
1557 case STATE_WAITING_CMD11_DONE:
1558 break;
1559
1560 case STATE_SENDING_CMD11:
1561 case STATE_SENDING_CMD:
1562 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1563 &host->pending_events))
1564 break;
1565
1566 cmd = host->cmd;
1567 host->cmd = NULL;
1568 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1569 err = dw_mci_command_complete(host, cmd);
1570 if (cmd == mrq->sbc && !err) {
1571 prev_state = state = STATE_SENDING_CMD;
1572 __dw_mci_start_request(host, host->cur_slot,
1573 mrq->cmd);
1574 goto unlock;
1575 }
1576
1577 if (cmd->data && err) {
1578 dw_mci_stop_dma(host);
1579 send_stop_abort(host, data);
1580 state = STATE_SENDING_STOP;
1581 break;
1582 }
1583
1584 if (!cmd->data || err) {
1585 dw_mci_request_end(host, mrq);
1586 goto unlock;
1587 }
1588
1589 prev_state = state = STATE_SENDING_DATA;
1590 /* fall through */
1591
1592 case STATE_SENDING_DATA:
1593 /*
1594 * We could get a data error and never a transfer
1595 * complete so we'd better check for it here.
1596 *
1597 * Note that we don't really care if we also got a
1598 * transfer complete; stopping the DMA and sending an
1599 * abort won't hurt.
1600 */
1601 if (test_and_clear_bit(EVENT_DATA_ERROR,
1602 &host->pending_events)) {
1603 dw_mci_stop_dma(host);
1604 if (data->stop ||
1605 !(host->data_status & (SDMMC_INT_DRTO |
1606 SDMMC_INT_EBE)))
1607 send_stop_abort(host, data);
1608 state = STATE_DATA_ERROR;
1609 break;
1610 }
1611
1612 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1613 &host->pending_events))
1614 break;
1615
1616 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1617
1618 /*
1619 * Handle an EVENT_DATA_ERROR that might have shown up
1620 * before the transfer completed. This might not have
1621 * been caught by the check above because the interrupt
1622 * could have gone off between the previous check and
1623 * the check for transfer complete.
1624 *
1625 * Technically this ought not be needed assuming we
1626 * get a DATA_COMPLETE eventually (we'll notice the
1627 * error and end the request), but it shouldn't hurt.
1628 *
1629 * This has the advantage of sending the stop command.
1630 */
1631 if (test_and_clear_bit(EVENT_DATA_ERROR,
1632 &host->pending_events)) {
1633 dw_mci_stop_dma(host);
1634 if (data->stop ||
1635 !(host->data_status & (SDMMC_INT_DRTO |
1636 SDMMC_INT_EBE)))
1637 send_stop_abort(host, data);
1638 state = STATE_DATA_ERROR;
1639 break;
1640 }
1641 prev_state = state = STATE_DATA_BUSY;
1642
1643 /* fall through */
1644
1645 case STATE_DATA_BUSY:
1646 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1647 &host->pending_events))
1648 break;
1649
1650 host->data = NULL;
1651 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1652 err = dw_mci_data_complete(host, data);
1653
1654 if (!err) {
1655 if (!data->stop || mrq->sbc) {
1656 if (mrq->sbc && data->stop)
1657 data->stop->error = 0;
1658 dw_mci_request_end(host, mrq);
1659 goto unlock;
1660 }
1661
1662 /* stop command for open-ended transfer*/
1663 if (data->stop)
1664 send_stop_abort(host, data);
1665 } else {
1666 /*
1667 * If we don't have a command complete now we'll
1668 * never get one since we just reset everything;
1669 * better end the request.
1670 *
1671 * If we do have a command complete we'll fall
1672 * through to the SENDING_STOP command and
1673 * everything will be peachy keen.
1674 */
1675 if (!test_bit(EVENT_CMD_COMPLETE,
1676 &host->pending_events)) {
1677 host->cmd = NULL;
1678 dw_mci_request_end(host, mrq);
1679 goto unlock;
1680 }
1681 }
1682
1683 /*
1684 * If err has non-zero,
1685 * stop-abort command has been already issued.
1686 */
1687 prev_state = state = STATE_SENDING_STOP;
1688
1689 /* fall through */
1690
1691 case STATE_SENDING_STOP:
1692 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1693 &host->pending_events))
1694 break;
1695
1696 /* CMD error in data command */
1697 if (mrq->cmd->error && mrq->data)
1698 dw_mci_reset(host);
1699
1700 host->cmd = NULL;
1701 host->data = NULL;
1702
1703 if (mrq->stop)
1704 dw_mci_command_complete(host, mrq->stop);
1705 else
1706 host->cmd_status = 0;
1707
1708 dw_mci_request_end(host, mrq);
1709 goto unlock;
1710
1711 case STATE_DATA_ERROR:
1712 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1713 &host->pending_events))
1714 break;
1715
1716 state = STATE_DATA_BUSY;
1717 break;
1718 }
1719 } while (state != prev_state);
1720
1721 host->state = state;
1722 unlock:
1723 spin_unlock(&host->lock);
1724
1725 }
1726
1727 /* push final bytes to part_buf, only use during push */
1728 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1729 {
1730 memcpy((void *)&host->part_buf, buf, cnt);
1731 host->part_buf_count = cnt;
1732 }
1733
1734 /* append bytes to part_buf, only use during push */
1735 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1736 {
1737 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1738 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1739 host->part_buf_count += cnt;
1740 return cnt;
1741 }
1742
1743 /* pull first bytes from part_buf, only use during pull */
1744 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1745 {
1746 cnt = min(cnt, (int)host->part_buf_count);
1747 if (cnt) {
1748 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1749 cnt);
1750 host->part_buf_count -= cnt;
1751 host->part_buf_start += cnt;
1752 }
1753 return cnt;
1754 }
1755
1756 /* pull final bytes from the part_buf, assuming it's just been filled */
1757 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1758 {
1759 memcpy(buf, &host->part_buf, cnt);
1760 host->part_buf_start = cnt;
1761 host->part_buf_count = (1 << host->data_shift) - cnt;
1762 }
1763
1764 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1765 {
1766 struct mmc_data *data = host->data;
1767 int init_cnt = cnt;
1768
1769 /* try and push anything in the part_buf */
1770 if (unlikely(host->part_buf_count)) {
1771 int len = dw_mci_push_part_bytes(host, buf, cnt);
1772 buf += len;
1773 cnt -= len;
1774 if (host->part_buf_count == 2) {
1775 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1776 host->part_buf_count = 0;
1777 }
1778 }
1779 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1780 if (unlikely((unsigned long)buf & 0x1)) {
1781 while (cnt >= 2) {
1782 u16 aligned_buf[64];
1783 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1784 int items = len >> 1;
1785 int i;
1786 /* memcpy from input buffer into aligned buffer */
1787 memcpy(aligned_buf, buf, len);
1788 buf += len;
1789 cnt -= len;
1790 /* push data from aligned buffer into fifo */
1791 for (i = 0; i < items; ++i)
1792 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
1793 }
1794 } else
1795 #endif
1796 {
1797 u16 *pdata = buf;
1798 for (; cnt >= 2; cnt -= 2)
1799 mci_fifo_writew(host->fifo_reg, *pdata++);
1800 buf = pdata;
1801 }
1802 /* put anything remaining in the part_buf */
1803 if (cnt) {
1804 dw_mci_set_part_bytes(host, buf, cnt);
1805 /* Push data if we have reached the expected data length */
1806 if ((data->bytes_xfered + init_cnt) ==
1807 (data->blksz * data->blocks))
1808 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1809 }
1810 }
1811
1812 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1813 {
1814 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1815 if (unlikely((unsigned long)buf & 0x1)) {
1816 while (cnt >= 2) {
1817 /* pull data from fifo into aligned buffer */
1818 u16 aligned_buf[64];
1819 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1820 int items = len >> 1;
1821 int i;
1822 for (i = 0; i < items; ++i)
1823 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
1824 /* memcpy from aligned buffer into output buffer */
1825 memcpy(buf, aligned_buf, len);
1826 buf += len;
1827 cnt -= len;
1828 }
1829 } else
1830 #endif
1831 {
1832 u16 *pdata = buf;
1833 for (; cnt >= 2; cnt -= 2)
1834 *pdata++ = mci_fifo_readw(host->fifo_reg);
1835 buf = pdata;
1836 }
1837 if (cnt) {
1838 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
1839 dw_mci_pull_final_bytes(host, buf, cnt);
1840 }
1841 }
1842
1843 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1844 {
1845 struct mmc_data *data = host->data;
1846 int init_cnt = cnt;
1847
1848 /* try and push anything in the part_buf */
1849 if (unlikely(host->part_buf_count)) {
1850 int len = dw_mci_push_part_bytes(host, buf, cnt);
1851 buf += len;
1852 cnt -= len;
1853 if (host->part_buf_count == 4) {
1854 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1855 host->part_buf_count = 0;
1856 }
1857 }
1858 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1859 if (unlikely((unsigned long)buf & 0x3)) {
1860 while (cnt >= 4) {
1861 u32 aligned_buf[32];
1862 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1863 int items = len >> 2;
1864 int i;
1865 /* memcpy from input buffer into aligned buffer */
1866 memcpy(aligned_buf, buf, len);
1867 buf += len;
1868 cnt -= len;
1869 /* push data from aligned buffer into fifo */
1870 for (i = 0; i < items; ++i)
1871 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
1872 }
1873 } else
1874 #endif
1875 {
1876 u32 *pdata = buf;
1877 for (; cnt >= 4; cnt -= 4)
1878 mci_fifo_writel(host->fifo_reg, *pdata++);
1879 buf = pdata;
1880 }
1881 /* put anything remaining in the part_buf */
1882 if (cnt) {
1883 dw_mci_set_part_bytes(host, buf, cnt);
1884 /* Push data if we have reached the expected data length */
1885 if ((data->bytes_xfered + init_cnt) ==
1886 (data->blksz * data->blocks))
1887 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1888 }
1889 }
1890
1891 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1892 {
1893 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1894 if (unlikely((unsigned long)buf & 0x3)) {
1895 while (cnt >= 4) {
1896 /* pull data from fifo into aligned buffer */
1897 u32 aligned_buf[32];
1898 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1899 int items = len >> 2;
1900 int i;
1901 for (i = 0; i < items; ++i)
1902 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
1903 /* memcpy from aligned buffer into output buffer */
1904 memcpy(buf, aligned_buf, len);
1905 buf += len;
1906 cnt -= len;
1907 }
1908 } else
1909 #endif
1910 {
1911 u32 *pdata = buf;
1912 for (; cnt >= 4; cnt -= 4)
1913 *pdata++ = mci_fifo_readl(host->fifo_reg);
1914 buf = pdata;
1915 }
1916 if (cnt) {
1917 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
1918 dw_mci_pull_final_bytes(host, buf, cnt);
1919 }
1920 }
1921
1922 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1923 {
1924 struct mmc_data *data = host->data;
1925 int init_cnt = cnt;
1926
1927 /* try and push anything in the part_buf */
1928 if (unlikely(host->part_buf_count)) {
1929 int len = dw_mci_push_part_bytes(host, buf, cnt);
1930 buf += len;
1931 cnt -= len;
1932
1933 if (host->part_buf_count == 8) {
1934 mci_fifo_writeq(host->fifo_reg, host->part_buf);
1935 host->part_buf_count = 0;
1936 }
1937 }
1938 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1939 if (unlikely((unsigned long)buf & 0x7)) {
1940 while (cnt >= 8) {
1941 u64 aligned_buf[16];
1942 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1943 int items = len >> 3;
1944 int i;
1945 /* memcpy from input buffer into aligned buffer */
1946 memcpy(aligned_buf, buf, len);
1947 buf += len;
1948 cnt -= len;
1949 /* push data from aligned buffer into fifo */
1950 for (i = 0; i < items; ++i)
1951 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
1952 }
1953 } else
1954 #endif
1955 {
1956 u64 *pdata = buf;
1957 for (; cnt >= 8; cnt -= 8)
1958 mci_fifo_writeq(host->fifo_reg, *pdata++);
1959 buf = pdata;
1960 }
1961 /* put anything remaining in the part_buf */
1962 if (cnt) {
1963 dw_mci_set_part_bytes(host, buf, cnt);
1964 /* Push data if we have reached the expected data length */
1965 if ((data->bytes_xfered + init_cnt) ==
1966 (data->blksz * data->blocks))
1967 mci_fifo_writeq(host->fifo_reg, host->part_buf);
1968 }
1969 }
1970
1971 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1972 {
1973 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1974 if (unlikely((unsigned long)buf & 0x7)) {
1975 while (cnt >= 8) {
1976 /* pull data from fifo into aligned buffer */
1977 u64 aligned_buf[16];
1978 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1979 int items = len >> 3;
1980 int i;
1981 for (i = 0; i < items; ++i)
1982 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
1983
1984 /* memcpy from aligned buffer into output buffer */
1985 memcpy(buf, aligned_buf, len);
1986 buf += len;
1987 cnt -= len;
1988 }
1989 } else
1990 #endif
1991 {
1992 u64 *pdata = buf;
1993 for (; cnt >= 8; cnt -= 8)
1994 *pdata++ = mci_fifo_readq(host->fifo_reg);
1995 buf = pdata;
1996 }
1997 if (cnt) {
1998 host->part_buf = mci_fifo_readq(host->fifo_reg);
1999 dw_mci_pull_final_bytes(host, buf, cnt);
2000 }
2001 }
2002
2003 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2004 {
2005 int len;
2006
2007 /* get remaining partial bytes */
2008 len = dw_mci_pull_part_bytes(host, buf, cnt);
2009 if (unlikely(len == cnt))
2010 return;
2011 buf += len;
2012 cnt -= len;
2013
2014 /* get the rest of the data */
2015 host->pull_data(host, buf, cnt);
2016 }
2017
2018 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2019 {
2020 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2021 void *buf;
2022 unsigned int offset;
2023 struct mmc_data *data = host->data;
2024 int shift = host->data_shift;
2025 u32 status;
2026 unsigned int len;
2027 unsigned int remain, fcnt;
2028
2029 do {
2030 if (!sg_miter_next(sg_miter))
2031 goto done;
2032
2033 host->sg = sg_miter->piter.sg;
2034 buf = sg_miter->addr;
2035 remain = sg_miter->length;
2036 offset = 0;
2037
2038 do {
2039 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2040 << shift) + host->part_buf_count;
2041 len = min(remain, fcnt);
2042 if (!len)
2043 break;
2044 dw_mci_pull_data(host, (void *)(buf + offset), len);
2045 data->bytes_xfered += len;
2046 offset += len;
2047 remain -= len;
2048 } while (remain);
2049
2050 sg_miter->consumed = offset;
2051 status = mci_readl(host, MINTSTS);
2052 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2053 /* if the RXDR is ready read again */
2054 } while ((status & SDMMC_INT_RXDR) ||
2055 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2056
2057 if (!remain) {
2058 if (!sg_miter_next(sg_miter))
2059 goto done;
2060 sg_miter->consumed = 0;
2061 }
2062 sg_miter_stop(sg_miter);
2063 return;
2064
2065 done:
2066 sg_miter_stop(sg_miter);
2067 host->sg = NULL;
2068 smp_wmb();
2069 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2070 }
2071
2072 static void dw_mci_write_data_pio(struct dw_mci *host)
2073 {
2074 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2075 void *buf;
2076 unsigned int offset;
2077 struct mmc_data *data = host->data;
2078 int shift = host->data_shift;
2079 u32 status;
2080 unsigned int len;
2081 unsigned int fifo_depth = host->fifo_depth;
2082 unsigned int remain, fcnt;
2083
2084 do {
2085 if (!sg_miter_next(sg_miter))
2086 goto done;
2087
2088 host->sg = sg_miter->piter.sg;
2089 buf = sg_miter->addr;
2090 remain = sg_miter->length;
2091 offset = 0;
2092
2093 do {
2094 fcnt = ((fifo_depth -
2095 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2096 << shift) - host->part_buf_count;
2097 len = min(remain, fcnt);
2098 if (!len)
2099 break;
2100 host->push_data(host, (void *)(buf + offset), len);
2101 data->bytes_xfered += len;
2102 offset += len;
2103 remain -= len;
2104 } while (remain);
2105
2106 sg_miter->consumed = offset;
2107 status = mci_readl(host, MINTSTS);
2108 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2109 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2110
2111 if (!remain) {
2112 if (!sg_miter_next(sg_miter))
2113 goto done;
2114 sg_miter->consumed = 0;
2115 }
2116 sg_miter_stop(sg_miter);
2117 return;
2118
2119 done:
2120 sg_miter_stop(sg_miter);
2121 host->sg = NULL;
2122 smp_wmb();
2123 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2124 }
2125
2126 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2127 {
2128 if (!host->cmd_status)
2129 host->cmd_status = status;
2130
2131 smp_wmb();
2132
2133 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2134 tasklet_schedule(&host->tasklet);
2135 }
2136
2137 static void dw_mci_handle_cd(struct dw_mci *host)
2138 {
2139 int i;
2140
2141 for (i = 0; i < host->num_slots; i++) {
2142 struct dw_mci_slot *slot = host->slot[i];
2143
2144 if (!slot)
2145 continue;
2146
2147 if (slot->mmc->ops->card_event)
2148 slot->mmc->ops->card_event(slot->mmc);
2149 mmc_detect_change(slot->mmc,
2150 msecs_to_jiffies(host->pdata->detect_delay_ms));
2151 }
2152 }
2153
2154 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2155 {
2156 struct dw_mci *host = dev_id;
2157 u32 pending;
2158 int i;
2159
2160 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2161
2162 /*
2163 * DTO fix - version 2.10a and below, and only if internal DMA
2164 * is configured.
2165 */
2166 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2167 if (!pending &&
2168 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2169 pending |= SDMMC_INT_DATA_OVER;
2170 }
2171
2172 if (pending) {
2173 /* Check volt switch first, since it can look like an error */
2174 if ((host->state == STATE_SENDING_CMD11) &&
2175 (pending & SDMMC_INT_VOLT_SWITCH)) {
2176 unsigned long irqflags;
2177
2178 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2179 pending &= ~SDMMC_INT_VOLT_SWITCH;
2180
2181 /*
2182 * Hold the lock; we know cmd11_timer can't be kicked
2183 * off after the lock is released, so safe to delete.
2184 */
2185 spin_lock_irqsave(&host->irq_lock, irqflags);
2186 dw_mci_cmd_interrupt(host, pending);
2187 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2188
2189 del_timer(&host->cmd11_timer);
2190 }
2191
2192 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2193 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2194 host->cmd_status = pending;
2195 smp_wmb();
2196 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2197 }
2198
2199 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2200 /* if there is an error report DATA_ERROR */
2201 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2202 host->data_status = pending;
2203 smp_wmb();
2204 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2205 tasklet_schedule(&host->tasklet);
2206 }
2207
2208 if (pending & SDMMC_INT_DATA_OVER) {
2209 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2210 if (!host->data_status)
2211 host->data_status = pending;
2212 smp_wmb();
2213 if (host->dir_status == DW_MCI_RECV_STATUS) {
2214 if (host->sg != NULL)
2215 dw_mci_read_data_pio(host, true);
2216 }
2217 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2218 tasklet_schedule(&host->tasklet);
2219 }
2220
2221 if (pending & SDMMC_INT_RXDR) {
2222 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2223 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2224 dw_mci_read_data_pio(host, false);
2225 }
2226
2227 if (pending & SDMMC_INT_TXDR) {
2228 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2229 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2230 dw_mci_write_data_pio(host);
2231 }
2232
2233 if (pending & SDMMC_INT_CMD_DONE) {
2234 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2235 dw_mci_cmd_interrupt(host, pending);
2236 }
2237
2238 if (pending & SDMMC_INT_CD) {
2239 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2240 dw_mci_handle_cd(host);
2241 }
2242
2243 /* Handle SDIO Interrupts */
2244 for (i = 0; i < host->num_slots; i++) {
2245 struct dw_mci_slot *slot = host->slot[i];
2246
2247 if (!slot)
2248 continue;
2249
2250 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2251 mci_writel(host, RINTSTS,
2252 SDMMC_INT_SDIO(slot->sdio_id));
2253 mmc_signal_sdio_irq(slot->mmc);
2254 }
2255 }
2256
2257 }
2258
2259 #ifdef CONFIG_MMC_DW_IDMAC
2260 /* Handle DMA interrupts */
2261 if (host->dma_64bit_address == 1) {
2262 pending = mci_readl(host, IDSTS64);
2263 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2264 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2265 SDMMC_IDMAC_INT_RI);
2266 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2267 host->dma_ops->complete(host);
2268 }
2269 } else {
2270 pending = mci_readl(host, IDSTS);
2271 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2272 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2273 SDMMC_IDMAC_INT_RI);
2274 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2275 host->dma_ops->complete(host);
2276 }
2277 }
2278 #endif
2279
2280 return IRQ_HANDLED;
2281 }
2282
2283 #ifdef CONFIG_OF
2284 /* given a slot, find out the device node representing that slot */
2285 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2286 {
2287 struct device *dev = slot->mmc->parent;
2288 struct device_node *np;
2289 const __be32 *addr;
2290 int len;
2291
2292 if (!dev || !dev->of_node)
2293 return NULL;
2294
2295 for_each_child_of_node(dev->of_node, np) {
2296 addr = of_get_property(np, "reg", &len);
2297 if (!addr || (len < sizeof(int)))
2298 continue;
2299 if (be32_to_cpup(addr) == slot->id)
2300 return np;
2301 }
2302 return NULL;
2303 }
2304
2305 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2306 {
2307 struct device_node *np = dw_mci_of_find_slot_node(slot);
2308
2309 if (!np)
2310 return;
2311
2312 if (of_property_read_bool(np, "disable-wp")) {
2313 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2314 dev_warn(slot->mmc->parent,
2315 "Slot quirk 'disable-wp' is deprecated\n");
2316 }
2317 }
2318 #else /* CONFIG_OF */
2319 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2320 {
2321 }
2322 #endif /* CONFIG_OF */
2323
2324 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2325 {
2326 struct mmc_host *mmc;
2327 struct dw_mci_slot *slot;
2328 const struct dw_mci_drv_data *drv_data = host->drv_data;
2329 int ctrl_id, ret;
2330 u32 freq[2];
2331
2332 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2333 if (!mmc)
2334 return -ENOMEM;
2335
2336 slot = mmc_priv(mmc);
2337 slot->id = id;
2338 slot->sdio_id = host->sdio_id0 + id;
2339 slot->mmc = mmc;
2340 slot->host = host;
2341 host->slot[id] = slot;
2342
2343 mmc->ops = &dw_mci_ops;
2344 if (of_property_read_u32_array(host->dev->of_node,
2345 "clock-freq-min-max", freq, 2)) {
2346 mmc->f_min = DW_MCI_FREQ_MIN;
2347 mmc->f_max = DW_MCI_FREQ_MAX;
2348 } else {
2349 mmc->f_min = freq[0];
2350 mmc->f_max = freq[1];
2351 }
2352
2353 /*if there are external regulators, get them*/
2354 ret = mmc_regulator_get_supply(mmc);
2355 if (ret == -EPROBE_DEFER)
2356 goto err_host_allocated;
2357
2358 if (!mmc->ocr_avail)
2359 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2360
2361 if (host->pdata->caps)
2362 mmc->caps = host->pdata->caps;
2363
2364 if (host->pdata->pm_caps)
2365 mmc->pm_caps = host->pdata->pm_caps;
2366
2367 if (host->dev->of_node) {
2368 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2369 if (ctrl_id < 0)
2370 ctrl_id = 0;
2371 } else {
2372 ctrl_id = to_platform_device(host->dev)->id;
2373 }
2374 if (drv_data && drv_data->caps)
2375 mmc->caps |= drv_data->caps[ctrl_id];
2376
2377 if (host->pdata->caps2)
2378 mmc->caps2 = host->pdata->caps2;
2379
2380 dw_mci_slot_of_parse(slot);
2381
2382 ret = mmc_of_parse(mmc);
2383 if (ret)
2384 goto err_host_allocated;
2385
2386 if (host->pdata->blk_settings) {
2387 mmc->max_segs = host->pdata->blk_settings->max_segs;
2388 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2389 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2390 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2391 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2392 } else {
2393 /* Useful defaults if platform data is unset. */
2394 #ifdef CONFIG_MMC_DW_IDMAC
2395 mmc->max_segs = host->ring_size;
2396 mmc->max_blk_size = 65536;
2397 mmc->max_seg_size = 0x1000;
2398 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2399 mmc->max_blk_count = mmc->max_req_size / 512;
2400 #else
2401 mmc->max_segs = 64;
2402 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2403 mmc->max_blk_count = 512;
2404 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2405 mmc->max_seg_size = mmc->max_req_size;
2406 #endif /* CONFIG_MMC_DW_IDMAC */
2407 }
2408
2409 if (dw_mci_get_cd(mmc))
2410 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2411 else
2412 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2413
2414 ret = mmc_add_host(mmc);
2415 if (ret)
2416 goto err_host_allocated;
2417
2418 #if defined(CONFIG_DEBUG_FS)
2419 dw_mci_init_debugfs(slot);
2420 #endif
2421
2422 return 0;
2423
2424 err_host_allocated:
2425 mmc_free_host(mmc);
2426 return ret;
2427 }
2428
2429 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2430 {
2431 /* Debugfs stuff is cleaned up by mmc core */
2432 mmc_remove_host(slot->mmc);
2433 slot->host->slot[id] = NULL;
2434 mmc_free_host(slot->mmc);
2435 }
2436
2437 static void dw_mci_init_dma(struct dw_mci *host)
2438 {
2439 int addr_config;
2440 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2441 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2442
2443 if (addr_config == 1) {
2444 /* host supports IDMAC in 64-bit address mode */
2445 host->dma_64bit_address = 1;
2446 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2447 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2448 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2449 } else {
2450 /* host supports IDMAC in 32-bit address mode */
2451 host->dma_64bit_address = 0;
2452 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2453 }
2454
2455 /* Alloc memory for sg translation */
2456 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2457 &host->sg_dma, GFP_KERNEL);
2458 if (!host->sg_cpu) {
2459 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2460 __func__);
2461 goto no_dma;
2462 }
2463
2464 /* Determine which DMA interface to use */
2465 #ifdef CONFIG_MMC_DW_IDMAC
2466 host->dma_ops = &dw_mci_idmac_ops;
2467 dev_info(host->dev, "Using internal DMA controller.\n");
2468 #endif
2469
2470 if (!host->dma_ops)
2471 goto no_dma;
2472
2473 if (host->dma_ops->init && host->dma_ops->start &&
2474 host->dma_ops->stop && host->dma_ops->cleanup) {
2475 if (host->dma_ops->init(host)) {
2476 dev_err(host->dev, "%s: Unable to initialize "
2477 "DMA Controller.\n", __func__);
2478 goto no_dma;
2479 }
2480 } else {
2481 dev_err(host->dev, "DMA initialization not found.\n");
2482 goto no_dma;
2483 }
2484
2485 host->use_dma = 1;
2486 return;
2487
2488 no_dma:
2489 dev_info(host->dev, "Using PIO mode.\n");
2490 host->use_dma = 0;
2491 return;
2492 }
2493
2494 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2495 {
2496 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2497 u32 ctrl;
2498
2499 ctrl = mci_readl(host, CTRL);
2500 ctrl |= reset;
2501 mci_writel(host, CTRL, ctrl);
2502
2503 /* wait till resets clear */
2504 do {
2505 ctrl = mci_readl(host, CTRL);
2506 if (!(ctrl & reset))
2507 return true;
2508 } while (time_before(jiffies, timeout));
2509
2510 dev_err(host->dev,
2511 "Timeout resetting block (ctrl reset %#x)\n",
2512 ctrl & reset);
2513
2514 return false;
2515 }
2516
2517 static bool dw_mci_reset(struct dw_mci *host)
2518 {
2519 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2520 bool ret = false;
2521
2522 /*
2523 * Reseting generates a block interrupt, hence setting
2524 * the scatter-gather pointer to NULL.
2525 */
2526 if (host->sg) {
2527 sg_miter_stop(&host->sg_miter);
2528 host->sg = NULL;
2529 }
2530
2531 if (host->use_dma)
2532 flags |= SDMMC_CTRL_DMA_RESET;
2533
2534 if (dw_mci_ctrl_reset(host, flags)) {
2535 /*
2536 * In all cases we clear the RAWINTS register to clear any
2537 * interrupts.
2538 */
2539 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2540
2541 /* if using dma we wait for dma_req to clear */
2542 if (host->use_dma) {
2543 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2544 u32 status;
2545 do {
2546 status = mci_readl(host, STATUS);
2547 if (!(status & SDMMC_STATUS_DMA_REQ))
2548 break;
2549 cpu_relax();
2550 } while (time_before(jiffies, timeout));
2551
2552 if (status & SDMMC_STATUS_DMA_REQ) {
2553 dev_err(host->dev,
2554 "%s: Timeout waiting for dma_req to "
2555 "clear during reset\n", __func__);
2556 goto ciu_out;
2557 }
2558
2559 /* when using DMA next we reset the fifo again */
2560 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2561 goto ciu_out;
2562 }
2563 } else {
2564 /* if the controller reset bit did clear, then set clock regs */
2565 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2566 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2567 "clear but ciu was reset, doing clock update\n",
2568 __func__);
2569 goto ciu_out;
2570 }
2571 }
2572
2573 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2574 /* It is also recommended that we reset and reprogram idmac */
2575 dw_mci_idmac_reset(host);
2576 #endif
2577
2578 ret = true;
2579
2580 ciu_out:
2581 /* After a CTRL reset we need to have CIU set clock registers */
2582 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2583
2584 return ret;
2585 }
2586
2587 static void dw_mci_cmd11_timer(unsigned long arg)
2588 {
2589 struct dw_mci *host = (struct dw_mci *)arg;
2590
2591 if (host->state != STATE_SENDING_CMD11) {
2592 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2593 return;
2594 }
2595
2596 host->cmd_status = SDMMC_INT_RTO;
2597 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2598 tasklet_schedule(&host->tasklet);
2599 }
2600
2601 #ifdef CONFIG_OF
2602 static struct dw_mci_of_quirks {
2603 char *quirk;
2604 int id;
2605 } of_quirks[] = {
2606 {
2607 .quirk = "broken-cd",
2608 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2609 },
2610 };
2611
2612 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2613 {
2614 struct dw_mci_board *pdata;
2615 struct device *dev = host->dev;
2616 struct device_node *np = dev->of_node;
2617 const struct dw_mci_drv_data *drv_data = host->drv_data;
2618 int idx, ret;
2619 u32 clock_frequency;
2620
2621 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2622 if (!pdata)
2623 return ERR_PTR(-ENOMEM);
2624
2625 /* find out number of slots supported */
2626 if (of_property_read_u32(dev->of_node, "num-slots",
2627 &pdata->num_slots)) {
2628 dev_info(dev, "num-slots property not found, "
2629 "assuming 1 slot is available\n");
2630 pdata->num_slots = 1;
2631 }
2632
2633 /* get quirks */
2634 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2635 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2636 pdata->quirks |= of_quirks[idx].id;
2637
2638 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2639 dev_info(dev, "fifo-depth property not found, using "
2640 "value of FIFOTH register as default\n");
2641
2642 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2643
2644 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2645 pdata->bus_hz = clock_frequency;
2646
2647 if (drv_data && drv_data->parse_dt) {
2648 ret = drv_data->parse_dt(host);
2649 if (ret)
2650 return ERR_PTR(ret);
2651 }
2652
2653 if (of_find_property(np, "supports-highspeed", NULL))
2654 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2655
2656 return pdata;
2657 }
2658
2659 #else /* CONFIG_OF */
2660 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2661 {
2662 return ERR_PTR(-EINVAL);
2663 }
2664 #endif /* CONFIG_OF */
2665
2666 static void dw_mci_enable_cd(struct dw_mci *host)
2667 {
2668 struct dw_mci_board *brd = host->pdata;
2669 unsigned long irqflags;
2670 u32 temp;
2671 int i;
2672
2673 /* No need for CD if broken card detection */
2674 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2675 return;
2676
2677 /* No need for CD if all slots have a non-error GPIO */
2678 for (i = 0; i < host->num_slots; i++) {
2679 struct dw_mci_slot *slot = host->slot[i];
2680
2681 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2682 break;
2683 }
2684 if (i == host->num_slots)
2685 return;
2686
2687 spin_lock_irqsave(&host->irq_lock, irqflags);
2688 temp = mci_readl(host, INTMASK);
2689 temp |= SDMMC_INT_CD;
2690 mci_writel(host, INTMASK, temp);
2691 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2692 }
2693
2694 int dw_mci_probe(struct dw_mci *host)
2695 {
2696 const struct dw_mci_drv_data *drv_data = host->drv_data;
2697 int width, i, ret = 0;
2698 u32 fifo_size;
2699 int init_slots = 0;
2700
2701 if (!host->pdata) {
2702 host->pdata = dw_mci_parse_dt(host);
2703 if (IS_ERR(host->pdata)) {
2704 dev_err(host->dev, "platform data not available\n");
2705 return -EINVAL;
2706 }
2707 }
2708
2709 if (host->pdata->num_slots > 1) {
2710 dev_err(host->dev,
2711 "Platform data must supply num_slots.\n");
2712 return -ENODEV;
2713 }
2714
2715 host->biu_clk = devm_clk_get(host->dev, "biu");
2716 if (IS_ERR(host->biu_clk)) {
2717 dev_dbg(host->dev, "biu clock not available\n");
2718 } else {
2719 ret = clk_prepare_enable(host->biu_clk);
2720 if (ret) {
2721 dev_err(host->dev, "failed to enable biu clock\n");
2722 return ret;
2723 }
2724 }
2725
2726 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2727 if (IS_ERR(host->ciu_clk)) {
2728 dev_dbg(host->dev, "ciu clock not available\n");
2729 host->bus_hz = host->pdata->bus_hz;
2730 } else {
2731 ret = clk_prepare_enable(host->ciu_clk);
2732 if (ret) {
2733 dev_err(host->dev, "failed to enable ciu clock\n");
2734 goto err_clk_biu;
2735 }
2736
2737 if (host->pdata->bus_hz) {
2738 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2739 if (ret)
2740 dev_warn(host->dev,
2741 "Unable to set bus rate to %uHz\n",
2742 host->pdata->bus_hz);
2743 }
2744 host->bus_hz = clk_get_rate(host->ciu_clk);
2745 }
2746
2747 if (!host->bus_hz) {
2748 dev_err(host->dev,
2749 "Platform data must supply bus speed\n");
2750 ret = -ENODEV;
2751 goto err_clk_ciu;
2752 }
2753
2754 if (drv_data && drv_data->init) {
2755 ret = drv_data->init(host);
2756 if (ret) {
2757 dev_err(host->dev,
2758 "implementation specific init failed\n");
2759 goto err_clk_ciu;
2760 }
2761 }
2762
2763 if (drv_data && drv_data->setup_clock) {
2764 ret = drv_data->setup_clock(host);
2765 if (ret) {
2766 dev_err(host->dev,
2767 "implementation specific clock setup failed\n");
2768 goto err_clk_ciu;
2769 }
2770 }
2771
2772 setup_timer(&host->cmd11_timer,
2773 dw_mci_cmd11_timer, (unsigned long)host);
2774
2775 host->quirks = host->pdata->quirks;
2776
2777 spin_lock_init(&host->lock);
2778 spin_lock_init(&host->irq_lock);
2779 INIT_LIST_HEAD(&host->queue);
2780
2781 /*
2782 * Get the host data width - this assumes that HCON has been set with
2783 * the correct values.
2784 */
2785 i = (mci_readl(host, HCON) >> 7) & 0x7;
2786 if (!i) {
2787 host->push_data = dw_mci_push_data16;
2788 host->pull_data = dw_mci_pull_data16;
2789 width = 16;
2790 host->data_shift = 1;
2791 } else if (i == 2) {
2792 host->push_data = dw_mci_push_data64;
2793 host->pull_data = dw_mci_pull_data64;
2794 width = 64;
2795 host->data_shift = 3;
2796 } else {
2797 /* Check for a reserved value, and warn if it is */
2798 WARN((i != 1),
2799 "HCON reports a reserved host data width!\n"
2800 "Defaulting to 32-bit access.\n");
2801 host->push_data = dw_mci_push_data32;
2802 host->pull_data = dw_mci_pull_data32;
2803 width = 32;
2804 host->data_shift = 2;
2805 }
2806
2807 /* Reset all blocks */
2808 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2809 return -ENODEV;
2810
2811 host->dma_ops = host->pdata->dma_ops;
2812 dw_mci_init_dma(host);
2813
2814 /* Clear the interrupts for the host controller */
2815 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2816 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2817
2818 /* Put in max timeout */
2819 mci_writel(host, TMOUT, 0xFFFFFFFF);
2820
2821 /*
2822 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2823 * Tx Mark = fifo_size / 2 DMA Size = 8
2824 */
2825 if (!host->pdata->fifo_depth) {
2826 /*
2827 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2828 * have been overwritten by the bootloader, just like we're
2829 * about to do, so if you know the value for your hardware, you
2830 * should put it in the platform data.
2831 */
2832 fifo_size = mci_readl(host, FIFOTH);
2833 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2834 } else {
2835 fifo_size = host->pdata->fifo_depth;
2836 }
2837 host->fifo_depth = fifo_size;
2838 host->fifoth_val =
2839 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2840 mci_writel(host, FIFOTH, host->fifoth_val);
2841
2842 /* disable clock to CIU */
2843 mci_writel(host, CLKENA, 0);
2844 mci_writel(host, CLKSRC, 0);
2845
2846 /*
2847 * In 2.40a spec, Data offset is changed.
2848 * Need to check the version-id and set data-offset for DATA register.
2849 */
2850 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2851 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2852
2853 if (host->verid < DW_MMC_240A)
2854 host->fifo_reg = host->regs + DATA_OFFSET;
2855 else
2856 host->fifo_reg = host->regs + DATA_240A_OFFSET;
2857
2858 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2859 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2860 host->irq_flags, "dw-mci", host);
2861 if (ret)
2862 goto err_dmaunmap;
2863
2864 if (host->pdata->num_slots)
2865 host->num_slots = host->pdata->num_slots;
2866 else
2867 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2868
2869 /*
2870 * Enable interrupts for command done, data over, data empty,
2871 * receive ready and error such as transmit, receive timeout, crc error
2872 */
2873 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2874 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2875 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2876 DW_MCI_ERROR_FLAGS);
2877 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2878
2879 dev_info(host->dev, "DW MMC controller at irq %d, "
2880 "%d bit host data width, "
2881 "%u deep fifo\n",
2882 host->irq, width, fifo_size);
2883
2884 /* We need at least one slot to succeed */
2885 for (i = 0; i < host->num_slots; i++) {
2886 ret = dw_mci_init_slot(host, i);
2887 if (ret)
2888 dev_dbg(host->dev, "slot %d init failed\n", i);
2889 else
2890 init_slots++;
2891 }
2892
2893 if (init_slots) {
2894 dev_info(host->dev, "%d slots initialized\n", init_slots);
2895 } else {
2896 dev_dbg(host->dev, "attempted to initialize %d slots, "
2897 "but failed on all\n", host->num_slots);
2898 goto err_dmaunmap;
2899 }
2900
2901 /* Now that slots are all setup, we can enable card detect */
2902 dw_mci_enable_cd(host);
2903
2904 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2905 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2906
2907 return 0;
2908
2909 err_dmaunmap:
2910 if (host->use_dma && host->dma_ops->exit)
2911 host->dma_ops->exit(host);
2912
2913 err_clk_ciu:
2914 if (!IS_ERR(host->ciu_clk))
2915 clk_disable_unprepare(host->ciu_clk);
2916
2917 err_clk_biu:
2918 if (!IS_ERR(host->biu_clk))
2919 clk_disable_unprepare(host->biu_clk);
2920
2921 return ret;
2922 }
2923 EXPORT_SYMBOL(dw_mci_probe);
2924
2925 void dw_mci_remove(struct dw_mci *host)
2926 {
2927 int i;
2928
2929 for (i = 0; i < host->num_slots; i++) {
2930 dev_dbg(host->dev, "remove slot %d\n", i);
2931 if (host->slot[i])
2932 dw_mci_cleanup_slot(host->slot[i], i);
2933 }
2934
2935 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2936 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2937
2938 /* disable clock to CIU */
2939 mci_writel(host, CLKENA, 0);
2940 mci_writel(host, CLKSRC, 0);
2941
2942 if (host->use_dma && host->dma_ops->exit)
2943 host->dma_ops->exit(host);
2944
2945 if (!IS_ERR(host->ciu_clk))
2946 clk_disable_unprepare(host->ciu_clk);
2947
2948 if (!IS_ERR(host->biu_clk))
2949 clk_disable_unprepare(host->biu_clk);
2950 }
2951 EXPORT_SYMBOL(dw_mci_remove);
2952
2953
2954
2955 #ifdef CONFIG_PM_SLEEP
2956 /*
2957 * TODO: we should probably disable the clock to the card in the suspend path.
2958 */
2959 int dw_mci_suspend(struct dw_mci *host)
2960 {
2961 return 0;
2962 }
2963 EXPORT_SYMBOL(dw_mci_suspend);
2964
2965 int dw_mci_resume(struct dw_mci *host)
2966 {
2967 int i, ret;
2968
2969 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2970 ret = -ENODEV;
2971 return ret;
2972 }
2973
2974 if (host->use_dma && host->dma_ops->init)
2975 host->dma_ops->init(host);
2976
2977 /*
2978 * Restore the initial value at FIFOTH register
2979 * And Invalidate the prev_blksz with zero
2980 */
2981 mci_writel(host, FIFOTH, host->fifoth_val);
2982 host->prev_blksz = 0;
2983
2984 /* Put in max timeout */
2985 mci_writel(host, TMOUT, 0xFFFFFFFF);
2986
2987 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2988 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2989 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2990 DW_MCI_ERROR_FLAGS);
2991 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2992
2993 for (i = 0; i < host->num_slots; i++) {
2994 struct dw_mci_slot *slot = host->slot[i];
2995 if (!slot)
2996 continue;
2997 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2998 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2999 dw_mci_setup_bus(slot, true);
3000 }
3001 }
3002
3003 /* Now that slots are all setup, we can enable card detect */
3004 dw_mci_enable_cd(host);
3005
3006 return 0;
3007 }
3008 EXPORT_SYMBOL(dw_mci_resume);
3009 #endif /* CONFIG_PM_SLEEP */
3010
3011 static int __init dw_mci_init(void)
3012 {
3013 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3014 return 0;
3015 }
3016
3017 static void __exit dw_mci_exit(void)
3018 {
3019 }
3020
3021 module_init(dw_mci_init);
3022 module_exit(dw_mci_exit);
3023
3024 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3025 MODULE_AUTHOR("NXP Semiconductor VietNam");
3026 MODULE_AUTHOR("Imagination Technologies Ltd");
3027 MODULE_LICENSE("GPL v2");
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