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[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
28 #include <linux/stat.h>
29 #include <linux/delay.h>
30 #include <linux/irq.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/dw_mmc.h>
34 #include <linux/bitops.h>
35 #include <linux/regulator/consumer.h>
36
37 #include "dw_mmc.h"
38
39 /* Common flag combinations */
40 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47 #define DW_MCI_SEND_STATUS 1
48 #define DW_MCI_RECV_STATUS 2
49 #define DW_MCI_DMA_THRESHOLD 16
50
51 #ifdef CONFIG_MMC_DW_IDMAC
52 struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54 #define IDMAC_DES0_DIC BIT(1)
55 #define IDMAC_DES0_LD BIT(2)
56 #define IDMAC_DES0_FD BIT(3)
57 #define IDMAC_DES0_CH BIT(4)
58 #define IDMAC_DES0_ER BIT(5)
59 #define IDMAC_DES0_CES BIT(30)
60 #define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
64 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69 };
70 #endif /* CONFIG_MMC_DW_IDMAC */
71
72 /**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86 struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97 #define DW_MMC_CARD_PRESENT 0
98 #define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101 };
102
103 #if defined(CONFIG_DEBUG_FS)
104 static int dw_mci_req_show(struct seq_file *s, void *v)
105 {
106 struct dw_mci_slot *slot = s->private;
107 struct mmc_request *mrq;
108 struct mmc_command *cmd;
109 struct mmc_command *stop;
110 struct mmc_data *data;
111
112 /* Make sure we get a consistent snapshot */
113 spin_lock_bh(&slot->host->lock);
114 mrq = slot->mrq;
115
116 if (mrq) {
117 cmd = mrq->cmd;
118 data = mrq->data;
119 stop = mrq->stop;
120
121 if (cmd)
122 seq_printf(s,
123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
124 cmd->opcode, cmd->arg, cmd->flags,
125 cmd->resp[0], cmd->resp[1], cmd->resp[2],
126 cmd->resp[2], cmd->error);
127 if (data)
128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
129 data->bytes_xfered, data->blocks,
130 data->blksz, data->flags, data->error);
131 if (stop)
132 seq_printf(s,
133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
134 stop->opcode, stop->arg, stop->flags,
135 stop->resp[0], stop->resp[1], stop->resp[2],
136 stop->resp[2], stop->error);
137 }
138
139 spin_unlock_bh(&slot->host->lock);
140
141 return 0;
142 }
143
144 static int dw_mci_req_open(struct inode *inode, struct file *file)
145 {
146 return single_open(file, dw_mci_req_show, inode->i_private);
147 }
148
149 static const struct file_operations dw_mci_req_fops = {
150 .owner = THIS_MODULE,
151 .open = dw_mci_req_open,
152 .read = seq_read,
153 .llseek = seq_lseek,
154 .release = single_release,
155 };
156
157 static int dw_mci_regs_show(struct seq_file *s, void *v)
158 {
159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
165
166 return 0;
167 }
168
169 static int dw_mci_regs_open(struct inode *inode, struct file *file)
170 {
171 return single_open(file, dw_mci_regs_show, inode->i_private);
172 }
173
174 static const struct file_operations dw_mci_regs_fops = {
175 .owner = THIS_MODULE,
176 .open = dw_mci_regs_open,
177 .read = seq_read,
178 .llseek = seq_lseek,
179 .release = single_release,
180 };
181
182 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
183 {
184 struct mmc_host *mmc = slot->mmc;
185 struct dw_mci *host = slot->host;
186 struct dentry *root;
187 struct dentry *node;
188
189 root = mmc->debugfs_root;
190 if (!root)
191 return;
192
193 node = debugfs_create_file("regs", S_IRUSR, root, host,
194 &dw_mci_regs_fops);
195 if (!node)
196 goto err;
197
198 node = debugfs_create_file("req", S_IRUSR, root, slot,
199 &dw_mci_req_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_x32("pending_events", S_IRUSR, root,
208 (u32 *)&host->pending_events);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("completed_events", S_IRUSR, root,
213 (u32 *)&host->completed_events);
214 if (!node)
215 goto err;
216
217 return;
218
219 err:
220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
221 }
222 #endif /* defined(CONFIG_DEBUG_FS) */
223
224 static void dw_mci_set_timeout(struct dw_mci *host)
225 {
226 /* timeout (maximum) */
227 mci_writel(host, TMOUT, 0xffffffff);
228 }
229
230 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231 {
232 struct mmc_data *data;
233 u32 cmdr;
234 cmd->error = -EINPROGRESS;
235
236 cmdr = cmd->opcode;
237
238 if (cmdr == MMC_STOP_TRANSMISSION)
239 cmdr |= SDMMC_CMD_STOP;
240 else
241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
242
243 if (cmd->flags & MMC_RSP_PRESENT) {
244 /* We expect a response, so set this bit */
245 cmdr |= SDMMC_CMD_RESP_EXP;
246 if (cmd->flags & MMC_RSP_136)
247 cmdr |= SDMMC_CMD_RESP_LONG;
248 }
249
250 if (cmd->flags & MMC_RSP_CRC)
251 cmdr |= SDMMC_CMD_RESP_CRC;
252
253 data = cmd->data;
254 if (data) {
255 cmdr |= SDMMC_CMD_DAT_EXP;
256 if (data->flags & MMC_DATA_STREAM)
257 cmdr |= SDMMC_CMD_STRM_MODE;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdr |= SDMMC_CMD_DAT_WR;
260 }
261
262 return cmdr;
263 }
264
265 static void dw_mci_start_command(struct dw_mci *host,
266 struct mmc_command *cmd, u32 cmd_flags)
267 {
268 host->cmd = cmd;
269 dev_vdbg(&host->pdev->dev,
270 "start command: ARGR=0x%08x CMDR=0x%08x\n",
271 cmd->arg, cmd_flags);
272
273 mci_writel(host, CMDARG, cmd->arg);
274 wmb();
275
276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
277 }
278
279 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
280 {
281 dw_mci_start_command(host, data->stop, host->stop_cmdr);
282 }
283
284 /* DMA interface functions */
285 static void dw_mci_stop_dma(struct dw_mci *host)
286 {
287 if (host->use_dma) {
288 host->dma_ops->stop(host);
289 host->dma_ops->cleanup(host);
290 } else {
291 /* Data transfer was stopped by the interrupt handler */
292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
293 }
294 }
295
296 #ifdef CONFIG_MMC_DW_IDMAC
297 static void dw_mci_dma_cleanup(struct dw_mci *host)
298 {
299 struct mmc_data *data = host->data;
300
301 if (data)
302 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
303 ((data->flags & MMC_DATA_WRITE)
304 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
305 }
306
307 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
308 {
309 u32 temp;
310
311 /* Disable and reset the IDMAC interface */
312 temp = mci_readl(host, CTRL);
313 temp &= ~SDMMC_CTRL_USE_IDMAC;
314 temp |= SDMMC_CTRL_DMA_RESET;
315 mci_writel(host, CTRL, temp);
316
317 /* Stop the IDMAC running */
318 temp = mci_readl(host, BMOD);
319 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
320 mci_writel(host, BMOD, temp);
321 }
322
323 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
324 {
325 struct mmc_data *data = host->data;
326
327 dev_vdbg(&host->pdev->dev, "DMA complete\n");
328
329 host->dma_ops->cleanup(host);
330
331 /*
332 * If the card was removed, data will be NULL. No point in trying to
333 * send the stop command or waiting for NBUSY in this case.
334 */
335 if (data) {
336 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
337 tasklet_schedule(&host->tasklet);
338 }
339 }
340
341 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
342 unsigned int sg_len)
343 {
344 int i;
345 struct idmac_desc *desc = host->sg_cpu;
346
347 for (i = 0; i < sg_len; i++, desc++) {
348 unsigned int length = sg_dma_len(&data->sg[i]);
349 u32 mem_addr = sg_dma_address(&data->sg[i]);
350
351 /* Set the OWN bit and disable interrupts for this descriptor */
352 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
353
354 /* Buffer length */
355 IDMAC_SET_BUFFER1_SIZE(desc, length);
356
357 /* Physical address to DMA to/from */
358 desc->des2 = mem_addr;
359 }
360
361 /* Set first descriptor */
362 desc = host->sg_cpu;
363 desc->des0 |= IDMAC_DES0_FD;
364
365 /* Set last descriptor */
366 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
367 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
368 desc->des0 |= IDMAC_DES0_LD;
369
370 wmb();
371 }
372
373 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
374 {
375 u32 temp;
376
377 dw_mci_translate_sglist(host, host->data, sg_len);
378
379 /* Select IDMAC interface */
380 temp = mci_readl(host, CTRL);
381 temp |= SDMMC_CTRL_USE_IDMAC;
382 mci_writel(host, CTRL, temp);
383
384 wmb();
385
386 /* Enable the IDMAC */
387 temp = mci_readl(host, BMOD);
388 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
389 mci_writel(host, BMOD, temp);
390
391 /* Start it running */
392 mci_writel(host, PLDMND, 1);
393 }
394
395 static int dw_mci_idmac_init(struct dw_mci *host)
396 {
397 struct idmac_desc *p;
398 int i;
399
400 /* Number of descriptors in the ring buffer */
401 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
402
403 /* Forward link the descriptor list */
404 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
405 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
406
407 /* Set the last descriptor as the end-of-ring descriptor */
408 p->des3 = host->sg_dma;
409 p->des0 = IDMAC_DES0_ER;
410
411 /* Mask out interrupts - get Tx & Rx complete only */
412 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
413 SDMMC_IDMAC_INT_TI);
414
415 /* Set the descriptor base address */
416 mci_writel(host, DBADDR, host->sg_dma);
417 return 0;
418 }
419
420 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
421 .init = dw_mci_idmac_init,
422 .start = dw_mci_idmac_start_dma,
423 .stop = dw_mci_idmac_stop_dma,
424 .complete = dw_mci_idmac_complete_dma,
425 .cleanup = dw_mci_dma_cleanup,
426 };
427 #endif /* CONFIG_MMC_DW_IDMAC */
428
429 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
430 {
431 struct scatterlist *sg;
432 unsigned int i, direction, sg_len;
433 u32 temp;
434
435 /* If we don't have a channel, we can't do DMA */
436 if (!host->use_dma)
437 return -ENODEV;
438
439 /*
440 * We don't do DMA on "complex" transfers, i.e. with
441 * non-word-aligned buffers or lengths. Also, we don't bother
442 * with all the DMA setup overhead for short transfers.
443 */
444 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
445 return -EINVAL;
446 if (data->blksz & 3)
447 return -EINVAL;
448
449 for_each_sg(data->sg, sg, data->sg_len, i) {
450 if (sg->offset & 3 || sg->length & 3)
451 return -EINVAL;
452 }
453
454 if (data->flags & MMC_DATA_READ)
455 direction = DMA_FROM_DEVICE;
456 else
457 direction = DMA_TO_DEVICE;
458
459 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
460 direction);
461
462 dev_vdbg(&host->pdev->dev,
463 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
464 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
465 sg_len);
466
467 /* Enable the DMA interface */
468 temp = mci_readl(host, CTRL);
469 temp |= SDMMC_CTRL_DMA_ENABLE;
470 mci_writel(host, CTRL, temp);
471
472 /* Disable RX/TX IRQs, let DMA handle it */
473 temp = mci_readl(host, INTMASK);
474 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
475 mci_writel(host, INTMASK, temp);
476
477 host->dma_ops->start(host, sg_len);
478
479 return 0;
480 }
481
482 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
483 {
484 u32 temp;
485
486 data->error = -EINPROGRESS;
487
488 WARN_ON(host->data);
489 host->sg = NULL;
490 host->data = data;
491
492 if (dw_mci_submit_data_dma(host, data)) {
493 host->sg = data->sg;
494 host->pio_offset = 0;
495 if (data->flags & MMC_DATA_READ)
496 host->dir_status = DW_MCI_RECV_STATUS;
497 else
498 host->dir_status = DW_MCI_SEND_STATUS;
499
500 temp = mci_readl(host, INTMASK);
501 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
502 mci_writel(host, INTMASK, temp);
503
504 temp = mci_readl(host, CTRL);
505 temp &= ~SDMMC_CTRL_DMA_ENABLE;
506 mci_writel(host, CTRL, temp);
507 }
508 }
509
510 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
511 {
512 struct dw_mci *host = slot->host;
513 unsigned long timeout = jiffies + msecs_to_jiffies(500);
514 unsigned int cmd_status = 0;
515
516 mci_writel(host, CMDARG, arg);
517 wmb();
518 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
519
520 while (time_before(jiffies, timeout)) {
521 cmd_status = mci_readl(host, CMD);
522 if (!(cmd_status & SDMMC_CMD_START))
523 return;
524 }
525 dev_err(&slot->mmc->class_dev,
526 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
527 cmd, arg, cmd_status);
528 }
529
530 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
531 {
532 struct dw_mci *host = slot->host;
533 u32 div;
534
535 if (slot->clock != host->current_speed) {
536 if (host->bus_hz % slot->clock)
537 /*
538 * move the + 1 after the divide to prevent
539 * over-clocking the card.
540 */
541 div = ((host->bus_hz / slot->clock) >> 1) + 1;
542 else
543 div = (host->bus_hz / slot->clock) >> 1;
544
545 dev_info(&slot->mmc->class_dev,
546 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
547 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
548 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
549
550 /* disable clock */
551 mci_writel(host, CLKENA, 0);
552 mci_writel(host, CLKSRC, 0);
553
554 /* inform CIU */
555 mci_send_cmd(slot,
556 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
557
558 /* set clock to desired speed */
559 mci_writel(host, CLKDIV, div);
560
561 /* inform CIU */
562 mci_send_cmd(slot,
563 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
564
565 /* enable clock */
566 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
567 SDMMC_CLKEN_LOW_PWR);
568
569 /* inform CIU */
570 mci_send_cmd(slot,
571 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
572
573 host->current_speed = slot->clock;
574 }
575
576 /* Set the current slot bus width */
577 mci_writel(host, CTYPE, slot->ctype);
578 }
579
580 static void dw_mci_start_request(struct dw_mci *host,
581 struct dw_mci_slot *slot)
582 {
583 struct mmc_request *mrq;
584 struct mmc_command *cmd;
585 struct mmc_data *data;
586 u32 cmdflags;
587
588 mrq = slot->mrq;
589 if (host->pdata->select_slot)
590 host->pdata->select_slot(slot->id);
591
592 /* Slot specific timing and width adjustment */
593 dw_mci_setup_bus(slot);
594
595 host->cur_slot = slot;
596 host->mrq = mrq;
597
598 host->pending_events = 0;
599 host->completed_events = 0;
600 host->data_status = 0;
601
602 data = mrq->data;
603 if (data) {
604 dw_mci_set_timeout(host);
605 mci_writel(host, BYTCNT, data->blksz*data->blocks);
606 mci_writel(host, BLKSIZ, data->blksz);
607 }
608
609 cmd = mrq->cmd;
610 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
611
612 /* this is the first command, send the initialization clock */
613 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
614 cmdflags |= SDMMC_CMD_INIT;
615
616 if (data) {
617 dw_mci_submit_data(host, data);
618 wmb();
619 }
620
621 dw_mci_start_command(host, cmd, cmdflags);
622
623 if (mrq->stop)
624 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
625 }
626
627 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
628 struct mmc_request *mrq)
629 {
630 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
631 host->state);
632
633 spin_lock_bh(&host->lock);
634 slot->mrq = mrq;
635
636 if (host->state == STATE_IDLE) {
637 host->state = STATE_SENDING_CMD;
638 dw_mci_start_request(host, slot);
639 } else {
640 list_add_tail(&slot->queue_node, &host->queue);
641 }
642
643 spin_unlock_bh(&host->lock);
644 }
645
646 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
647 {
648 struct dw_mci_slot *slot = mmc_priv(mmc);
649 struct dw_mci *host = slot->host;
650
651 WARN_ON(slot->mrq);
652
653 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
654 mrq->cmd->error = -ENOMEDIUM;
655 mmc_request_done(mmc, mrq);
656 return;
657 }
658
659 /* We don't support multiple blocks of weird lengths. */
660 dw_mci_queue_request(host, slot, mrq);
661 }
662
663 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
664 {
665 struct dw_mci_slot *slot = mmc_priv(mmc);
666 u32 regs;
667
668 /* set default 1 bit mode */
669 slot->ctype = SDMMC_CTYPE_1BIT;
670
671 switch (ios->bus_width) {
672 case MMC_BUS_WIDTH_1:
673 slot->ctype = SDMMC_CTYPE_1BIT;
674 break;
675 case MMC_BUS_WIDTH_4:
676 slot->ctype = SDMMC_CTYPE_4BIT;
677 break;
678 case MMC_BUS_WIDTH_8:
679 slot->ctype = SDMMC_CTYPE_8BIT;
680 break;
681 }
682
683 /* DDR mode set */
684 if (ios->ddr) {
685 regs = mci_readl(slot->host, UHS_REG);
686 regs |= (0x1 << slot->id) << 16;
687 mci_writel(slot->host, UHS_REG, regs);
688 }
689
690 if (ios->clock) {
691 /*
692 * Use mirror of ios->clock to prevent race with mmc
693 * core ios update when finding the minimum.
694 */
695 slot->clock = ios->clock;
696 }
697
698 switch (ios->power_mode) {
699 case MMC_POWER_UP:
700 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
701 break;
702 default:
703 break;
704 }
705 }
706
707 static int dw_mci_get_ro(struct mmc_host *mmc)
708 {
709 int read_only;
710 struct dw_mci_slot *slot = mmc_priv(mmc);
711 struct dw_mci_board *brd = slot->host->pdata;
712
713 /* Use platform get_ro function, else try on board write protect */
714 if (brd->get_ro)
715 read_only = brd->get_ro(slot->id);
716 else
717 read_only =
718 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
719
720 dev_dbg(&mmc->class_dev, "card is %s\n",
721 read_only ? "read-only" : "read-write");
722
723 return read_only;
724 }
725
726 static int dw_mci_get_cd(struct mmc_host *mmc)
727 {
728 int present;
729 struct dw_mci_slot *slot = mmc_priv(mmc);
730 struct dw_mci_board *brd = slot->host->pdata;
731
732 /* Use platform get_cd function, else try onboard card detect */
733 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
734 present = 1;
735 else if (brd->get_cd)
736 present = !brd->get_cd(slot->id);
737 else
738 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
739 == 0 ? 1 : 0;
740
741 if (present)
742 dev_dbg(&mmc->class_dev, "card is present\n");
743 else
744 dev_dbg(&mmc->class_dev, "card is not present\n");
745
746 return present;
747 }
748
749 static const struct mmc_host_ops dw_mci_ops = {
750 .request = dw_mci_request,
751 .set_ios = dw_mci_set_ios,
752 .get_ro = dw_mci_get_ro,
753 .get_cd = dw_mci_get_cd,
754 };
755
756 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
757 __releases(&host->lock)
758 __acquires(&host->lock)
759 {
760 struct dw_mci_slot *slot;
761 struct mmc_host *prev_mmc = host->cur_slot->mmc;
762
763 WARN_ON(host->cmd || host->data);
764
765 host->cur_slot->mrq = NULL;
766 host->mrq = NULL;
767 if (!list_empty(&host->queue)) {
768 slot = list_entry(host->queue.next,
769 struct dw_mci_slot, queue_node);
770 list_del(&slot->queue_node);
771 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
772 mmc_hostname(slot->mmc));
773 host->state = STATE_SENDING_CMD;
774 dw_mci_start_request(host, slot);
775 } else {
776 dev_vdbg(&host->pdev->dev, "list empty\n");
777 host->state = STATE_IDLE;
778 }
779
780 spin_unlock(&host->lock);
781 mmc_request_done(prev_mmc, mrq);
782 spin_lock(&host->lock);
783 }
784
785 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
786 {
787 u32 status = host->cmd_status;
788
789 host->cmd_status = 0;
790
791 /* Read the response from the card (up to 16 bytes) */
792 if (cmd->flags & MMC_RSP_PRESENT) {
793 if (cmd->flags & MMC_RSP_136) {
794 cmd->resp[3] = mci_readl(host, RESP0);
795 cmd->resp[2] = mci_readl(host, RESP1);
796 cmd->resp[1] = mci_readl(host, RESP2);
797 cmd->resp[0] = mci_readl(host, RESP3);
798 } else {
799 cmd->resp[0] = mci_readl(host, RESP0);
800 cmd->resp[1] = 0;
801 cmd->resp[2] = 0;
802 cmd->resp[3] = 0;
803 }
804 }
805
806 if (status & SDMMC_INT_RTO)
807 cmd->error = -ETIMEDOUT;
808 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
809 cmd->error = -EILSEQ;
810 else if (status & SDMMC_INT_RESP_ERR)
811 cmd->error = -EIO;
812 else
813 cmd->error = 0;
814
815 if (cmd->error) {
816 /* newer ip versions need a delay between retries */
817 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
818 mdelay(20);
819
820 if (cmd->data) {
821 host->data = NULL;
822 dw_mci_stop_dma(host);
823 }
824 }
825 }
826
827 static void dw_mci_tasklet_func(unsigned long priv)
828 {
829 struct dw_mci *host = (struct dw_mci *)priv;
830 struct mmc_data *data;
831 struct mmc_command *cmd;
832 enum dw_mci_state state;
833 enum dw_mci_state prev_state;
834 u32 status;
835
836 spin_lock(&host->lock);
837
838 state = host->state;
839 data = host->data;
840
841 do {
842 prev_state = state;
843
844 switch (state) {
845 case STATE_IDLE:
846 break;
847
848 case STATE_SENDING_CMD:
849 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
850 &host->pending_events))
851 break;
852
853 cmd = host->cmd;
854 host->cmd = NULL;
855 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
856 dw_mci_command_complete(host, host->mrq->cmd);
857 if (!host->mrq->data || cmd->error) {
858 dw_mci_request_end(host, host->mrq);
859 goto unlock;
860 }
861
862 prev_state = state = STATE_SENDING_DATA;
863 /* fall through */
864
865 case STATE_SENDING_DATA:
866 if (test_and_clear_bit(EVENT_DATA_ERROR,
867 &host->pending_events)) {
868 dw_mci_stop_dma(host);
869 if (data->stop)
870 send_stop_cmd(host, data);
871 state = STATE_DATA_ERROR;
872 break;
873 }
874
875 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
876 &host->pending_events))
877 break;
878
879 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
880 prev_state = state = STATE_DATA_BUSY;
881 /* fall through */
882
883 case STATE_DATA_BUSY:
884 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
885 &host->pending_events))
886 break;
887
888 host->data = NULL;
889 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
890 status = host->data_status;
891
892 if (status & DW_MCI_DATA_ERROR_FLAGS) {
893 if (status & SDMMC_INT_DTO) {
894 dev_err(&host->pdev->dev,
895 "data timeout error\n");
896 data->error = -ETIMEDOUT;
897 } else if (status & SDMMC_INT_DCRC) {
898 dev_err(&host->pdev->dev,
899 "data CRC error\n");
900 data->error = -EILSEQ;
901 } else {
902 dev_err(&host->pdev->dev,
903 "data FIFO error "
904 "(status=%08x)\n",
905 status);
906 data->error = -EIO;
907 }
908 } else {
909 data->bytes_xfered = data->blocks * data->blksz;
910 data->error = 0;
911 }
912
913 if (!data->stop) {
914 dw_mci_request_end(host, host->mrq);
915 goto unlock;
916 }
917
918 prev_state = state = STATE_SENDING_STOP;
919 if (!data->error)
920 send_stop_cmd(host, data);
921 /* fall through */
922
923 case STATE_SENDING_STOP:
924 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
925 &host->pending_events))
926 break;
927
928 host->cmd = NULL;
929 dw_mci_command_complete(host, host->mrq->stop);
930 dw_mci_request_end(host, host->mrq);
931 goto unlock;
932
933 case STATE_DATA_ERROR:
934 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
935 &host->pending_events))
936 break;
937
938 state = STATE_DATA_BUSY;
939 break;
940 }
941 } while (state != prev_state);
942
943 host->state = state;
944 unlock:
945 spin_unlock(&host->lock);
946
947 }
948
949 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
950 {
951 u16 *pdata = (u16 *)buf;
952
953 WARN_ON(cnt % 2 != 0);
954
955 cnt = cnt >> 1;
956 while (cnt > 0) {
957 mci_writew(host, DATA, *pdata++);
958 cnt--;
959 }
960 }
961
962 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
963 {
964 u16 *pdata = (u16 *)buf;
965
966 WARN_ON(cnt % 2 != 0);
967
968 cnt = cnt >> 1;
969 while (cnt > 0) {
970 *pdata++ = mci_readw(host, DATA);
971 cnt--;
972 }
973 }
974
975 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
976 {
977 u32 *pdata = (u32 *)buf;
978
979 WARN_ON(cnt % 4 != 0);
980 WARN_ON((unsigned long)pdata & 0x3);
981
982 cnt = cnt >> 2;
983 while (cnt > 0) {
984 mci_writel(host, DATA, *pdata++);
985 cnt--;
986 }
987 }
988
989 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
990 {
991 u32 *pdata = (u32 *)buf;
992
993 WARN_ON(cnt % 4 != 0);
994 WARN_ON((unsigned long)pdata & 0x3);
995
996 cnt = cnt >> 2;
997 while (cnt > 0) {
998 *pdata++ = mci_readl(host, DATA);
999 cnt--;
1000 }
1001 }
1002
1003 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1004 {
1005 u64 *pdata = (u64 *)buf;
1006
1007 WARN_ON(cnt % 8 != 0);
1008
1009 cnt = cnt >> 3;
1010 while (cnt > 0) {
1011 mci_writeq(host, DATA, *pdata++);
1012 cnt--;
1013 }
1014 }
1015
1016 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1017 {
1018 u64 *pdata = (u64 *)buf;
1019
1020 WARN_ON(cnt % 8 != 0);
1021
1022 cnt = cnt >> 3;
1023 while (cnt > 0) {
1024 *pdata++ = mci_readq(host, DATA);
1025 cnt--;
1026 }
1027 }
1028
1029 static void dw_mci_read_data_pio(struct dw_mci *host)
1030 {
1031 struct scatterlist *sg = host->sg;
1032 void *buf = sg_virt(sg);
1033 unsigned int offset = host->pio_offset;
1034 struct mmc_data *data = host->data;
1035 int shift = host->data_shift;
1036 u32 status;
1037 unsigned int nbytes = 0, len;
1038
1039 do {
1040 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
1041 if (offset + len <= sg->length) {
1042 host->pull_data(host, (void *)(buf + offset), len);
1043
1044 offset += len;
1045 nbytes += len;
1046
1047 if (offset == sg->length) {
1048 flush_dcache_page(sg_page(sg));
1049 host->sg = sg = sg_next(sg);
1050 if (!sg)
1051 goto done;
1052
1053 offset = 0;
1054 buf = sg_virt(sg);
1055 }
1056 } else {
1057 unsigned int remaining = sg->length - offset;
1058 host->pull_data(host, (void *)(buf + offset),
1059 remaining);
1060 nbytes += remaining;
1061
1062 flush_dcache_page(sg_page(sg));
1063 host->sg = sg = sg_next(sg);
1064 if (!sg)
1065 goto done;
1066
1067 offset = len - remaining;
1068 buf = sg_virt(sg);
1069 host->pull_data(host, buf, offset);
1070 nbytes += offset;
1071 }
1072
1073 status = mci_readl(host, MINTSTS);
1074 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1075 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1076 host->data_status = status;
1077 data->bytes_xfered += nbytes;
1078 smp_wmb();
1079
1080 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1081
1082 tasklet_schedule(&host->tasklet);
1083 return;
1084 }
1085 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1086 len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1087 host->pio_offset = offset;
1088 data->bytes_xfered += nbytes;
1089 return;
1090
1091 done:
1092 data->bytes_xfered += nbytes;
1093 smp_wmb();
1094 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1095 }
1096
1097 static void dw_mci_write_data_pio(struct dw_mci *host)
1098 {
1099 struct scatterlist *sg = host->sg;
1100 void *buf = sg_virt(sg);
1101 unsigned int offset = host->pio_offset;
1102 struct mmc_data *data = host->data;
1103 int shift = host->data_shift;
1104 u32 status;
1105 unsigned int nbytes = 0, len;
1106
1107 do {
1108 len = SDMMC_FIFO_SZ -
1109 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1110 if (offset + len <= sg->length) {
1111 host->push_data(host, (void *)(buf + offset), len);
1112
1113 offset += len;
1114 nbytes += len;
1115 if (offset == sg->length) {
1116 host->sg = sg = sg_next(sg);
1117 if (!sg)
1118 goto done;
1119
1120 offset = 0;
1121 buf = sg_virt(sg);
1122 }
1123 } else {
1124 unsigned int remaining = sg->length - offset;
1125
1126 host->push_data(host, (void *)(buf + offset),
1127 remaining);
1128 nbytes += remaining;
1129
1130 host->sg = sg = sg_next(sg);
1131 if (!sg)
1132 goto done;
1133
1134 offset = len - remaining;
1135 buf = sg_virt(sg);
1136 host->push_data(host, (void *)buf, offset);
1137 nbytes += offset;
1138 }
1139
1140 status = mci_readl(host, MINTSTS);
1141 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1142 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1143 host->data_status = status;
1144 data->bytes_xfered += nbytes;
1145
1146 smp_wmb();
1147
1148 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1149
1150 tasklet_schedule(&host->tasklet);
1151 return;
1152 }
1153 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1154
1155 host->pio_offset = offset;
1156 data->bytes_xfered += nbytes;
1157
1158 return;
1159
1160 done:
1161 data->bytes_xfered += nbytes;
1162 smp_wmb();
1163 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1164 }
1165
1166 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1167 {
1168 if (!host->cmd_status)
1169 host->cmd_status = status;
1170
1171 smp_wmb();
1172
1173 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1174 tasklet_schedule(&host->tasklet);
1175 }
1176
1177 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1178 {
1179 struct dw_mci *host = dev_id;
1180 u32 status, pending;
1181 unsigned int pass_count = 0;
1182
1183 do {
1184 status = mci_readl(host, RINTSTS);
1185 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1186
1187 /*
1188 * DTO fix - version 2.10a and below, and only if internal DMA
1189 * is configured.
1190 */
1191 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1192 if (!pending &&
1193 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1194 pending |= SDMMC_INT_DATA_OVER;
1195 }
1196
1197 if (!pending)
1198 break;
1199
1200 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1201 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1202 host->cmd_status = status;
1203 smp_wmb();
1204 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1205 tasklet_schedule(&host->tasklet);
1206 }
1207
1208 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1209 /* if there is an error report DATA_ERROR */
1210 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1211 host->data_status = status;
1212 smp_wmb();
1213 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1214 tasklet_schedule(&host->tasklet);
1215 }
1216
1217 if (pending & SDMMC_INT_DATA_OVER) {
1218 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1219 if (!host->data_status)
1220 host->data_status = status;
1221 smp_wmb();
1222 if (host->dir_status == DW_MCI_RECV_STATUS) {
1223 if (host->sg != NULL)
1224 dw_mci_read_data_pio(host);
1225 }
1226 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1227 tasklet_schedule(&host->tasklet);
1228 }
1229
1230 if (pending & SDMMC_INT_RXDR) {
1231 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1232 if (host->sg)
1233 dw_mci_read_data_pio(host);
1234 }
1235
1236 if (pending & SDMMC_INT_TXDR) {
1237 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1238 if (host->sg)
1239 dw_mci_write_data_pio(host);
1240 }
1241
1242 if (pending & SDMMC_INT_CMD_DONE) {
1243 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1244 dw_mci_cmd_interrupt(host, status);
1245 }
1246
1247 if (pending & SDMMC_INT_CD) {
1248 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1249 tasklet_schedule(&host->card_tasklet);
1250 }
1251
1252 } while (pass_count++ < 5);
1253
1254 #ifdef CONFIG_MMC_DW_IDMAC
1255 /* Handle DMA interrupts */
1256 pending = mci_readl(host, IDSTS);
1257 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1258 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1259 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1260 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1261 host->dma_ops->complete(host);
1262 }
1263 #endif
1264
1265 return IRQ_HANDLED;
1266 }
1267
1268 static void dw_mci_tasklet_card(unsigned long data)
1269 {
1270 struct dw_mci *host = (struct dw_mci *)data;
1271 int i;
1272
1273 for (i = 0; i < host->num_slots; i++) {
1274 struct dw_mci_slot *slot = host->slot[i];
1275 struct mmc_host *mmc = slot->mmc;
1276 struct mmc_request *mrq;
1277 int present;
1278 u32 ctrl;
1279
1280 present = dw_mci_get_cd(mmc);
1281 while (present != slot->last_detect_state) {
1282 spin_lock(&host->lock);
1283
1284 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1285 present ? "inserted" : "removed");
1286
1287 /* Card change detected */
1288 slot->last_detect_state = present;
1289
1290 /* Power up slot */
1291 if (present != 0) {
1292 if (host->pdata->setpower)
1293 host->pdata->setpower(slot->id,
1294 mmc->ocr_avail);
1295
1296 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1297 }
1298
1299 /* Clean up queue if present */
1300 mrq = slot->mrq;
1301 if (mrq) {
1302 if (mrq == host->mrq) {
1303 host->data = NULL;
1304 host->cmd = NULL;
1305
1306 switch (host->state) {
1307 case STATE_IDLE:
1308 break;
1309 case STATE_SENDING_CMD:
1310 mrq->cmd->error = -ENOMEDIUM;
1311 if (!mrq->data)
1312 break;
1313 /* fall through */
1314 case STATE_SENDING_DATA:
1315 mrq->data->error = -ENOMEDIUM;
1316 dw_mci_stop_dma(host);
1317 break;
1318 case STATE_DATA_BUSY:
1319 case STATE_DATA_ERROR:
1320 if (mrq->data->error == -EINPROGRESS)
1321 mrq->data->error = -ENOMEDIUM;
1322 if (!mrq->stop)
1323 break;
1324 /* fall through */
1325 case STATE_SENDING_STOP:
1326 mrq->stop->error = -ENOMEDIUM;
1327 break;
1328 }
1329
1330 dw_mci_request_end(host, mrq);
1331 } else {
1332 list_del(&slot->queue_node);
1333 mrq->cmd->error = -ENOMEDIUM;
1334 if (mrq->data)
1335 mrq->data->error = -ENOMEDIUM;
1336 if (mrq->stop)
1337 mrq->stop->error = -ENOMEDIUM;
1338
1339 spin_unlock(&host->lock);
1340 mmc_request_done(slot->mmc, mrq);
1341 spin_lock(&host->lock);
1342 }
1343 }
1344
1345 /* Power down slot */
1346 if (present == 0) {
1347 if (host->pdata->setpower)
1348 host->pdata->setpower(slot->id, 0);
1349 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1350
1351 /*
1352 * Clear down the FIFO - doing so generates a
1353 * block interrupt, hence setting the
1354 * scatter-gather pointer to NULL.
1355 */
1356 host->sg = NULL;
1357
1358 ctrl = mci_readl(host, CTRL);
1359 ctrl |= SDMMC_CTRL_FIFO_RESET;
1360 mci_writel(host, CTRL, ctrl);
1361
1362 #ifdef CONFIG_MMC_DW_IDMAC
1363 ctrl = mci_readl(host, BMOD);
1364 ctrl |= 0x01; /* Software reset of DMA */
1365 mci_writel(host, BMOD, ctrl);
1366 #endif
1367
1368 }
1369
1370 spin_unlock(&host->lock);
1371 present = dw_mci_get_cd(mmc);
1372 }
1373
1374 mmc_detect_change(slot->mmc,
1375 msecs_to_jiffies(host->pdata->detect_delay_ms));
1376 }
1377 }
1378
1379 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1380 {
1381 struct mmc_host *mmc;
1382 struct dw_mci_slot *slot;
1383
1384 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1385 if (!mmc)
1386 return -ENOMEM;
1387
1388 slot = mmc_priv(mmc);
1389 slot->id = id;
1390 slot->mmc = mmc;
1391 slot->host = host;
1392
1393 mmc->ops = &dw_mci_ops;
1394 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1395 mmc->f_max = host->bus_hz;
1396
1397 if (host->pdata->get_ocr)
1398 mmc->ocr_avail = host->pdata->get_ocr(id);
1399 else
1400 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1401
1402 /*
1403 * Start with slot power disabled, it will be enabled when a card
1404 * is detected.
1405 */
1406 if (host->pdata->setpower)
1407 host->pdata->setpower(id, 0);
1408
1409 if (host->pdata->caps)
1410 mmc->caps = host->pdata->caps;
1411 else
1412 mmc->caps = 0;
1413
1414 if (host->pdata->get_bus_wd)
1415 if (host->pdata->get_bus_wd(slot->id) >= 4)
1416 mmc->caps |= MMC_CAP_4_BIT_DATA;
1417
1418 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1419 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1420
1421 #ifdef CONFIG_MMC_DW_IDMAC
1422 mmc->max_segs = host->ring_size;
1423 mmc->max_blk_size = 65536;
1424 mmc->max_blk_count = host->ring_size;
1425 mmc->max_seg_size = 0x1000;
1426 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1427 #else
1428 if (host->pdata->blk_settings) {
1429 mmc->max_segs = host->pdata->blk_settings->max_segs;
1430 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1431 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1432 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1433 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1434 } else {
1435 /* Useful defaults if platform data is unset. */
1436 mmc->max_segs = 64;
1437 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1438 mmc->max_blk_count = 512;
1439 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1440 mmc->max_seg_size = mmc->max_req_size;
1441 }
1442 #endif /* CONFIG_MMC_DW_IDMAC */
1443
1444 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1445 if (IS_ERR(host->vmmc)) {
1446 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1447 host->vmmc = NULL;
1448 } else
1449 regulator_enable(host->vmmc);
1450
1451 if (dw_mci_get_cd(mmc))
1452 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1453 else
1454 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1455
1456 host->slot[id] = slot;
1457 mmc_add_host(mmc);
1458
1459 #if defined(CONFIG_DEBUG_FS)
1460 dw_mci_init_debugfs(slot);
1461 #endif
1462
1463 /* Card initially undetected */
1464 slot->last_detect_state = 0;
1465
1466 /*
1467 * Card may have been plugged in prior to boot so we
1468 * need to run the detect tasklet
1469 */
1470 tasklet_schedule(&host->card_tasklet);
1471
1472 return 0;
1473 }
1474
1475 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1476 {
1477 /* Shutdown detect IRQ */
1478 if (slot->host->pdata->exit)
1479 slot->host->pdata->exit(id);
1480
1481 /* Debugfs stuff is cleaned up by mmc core */
1482 mmc_remove_host(slot->mmc);
1483 slot->host->slot[id] = NULL;
1484 mmc_free_host(slot->mmc);
1485 }
1486
1487 static void dw_mci_init_dma(struct dw_mci *host)
1488 {
1489 /* Alloc memory for sg translation */
1490 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1491 &host->sg_dma, GFP_KERNEL);
1492 if (!host->sg_cpu) {
1493 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1494 __func__);
1495 goto no_dma;
1496 }
1497
1498 /* Determine which DMA interface to use */
1499 #ifdef CONFIG_MMC_DW_IDMAC
1500 host->dma_ops = &dw_mci_idmac_ops;
1501 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1502 #endif
1503
1504 if (!host->dma_ops)
1505 goto no_dma;
1506
1507 if (host->dma_ops->init) {
1508 if (host->dma_ops->init(host)) {
1509 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1510 "DMA Controller.\n", __func__);
1511 goto no_dma;
1512 }
1513 } else {
1514 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1515 goto no_dma;
1516 }
1517
1518 host->use_dma = 1;
1519 return;
1520
1521 no_dma:
1522 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1523 host->use_dma = 0;
1524 return;
1525 }
1526
1527 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1528 {
1529 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1530 unsigned int ctrl;
1531
1532 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1533 SDMMC_CTRL_DMA_RESET));
1534
1535 /* wait till resets clear */
1536 do {
1537 ctrl = mci_readl(host, CTRL);
1538 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1539 SDMMC_CTRL_DMA_RESET)))
1540 return true;
1541 } while (time_before(jiffies, timeout));
1542
1543 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1544
1545 return false;
1546 }
1547
1548 static int dw_mci_probe(struct platform_device *pdev)
1549 {
1550 struct dw_mci *host;
1551 struct resource *regs;
1552 struct dw_mci_board *pdata;
1553 int irq, ret, i, width;
1554 u32 fifo_size;
1555
1556 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1557 if (!regs)
1558 return -ENXIO;
1559
1560 irq = platform_get_irq(pdev, 0);
1561 if (irq < 0)
1562 return irq;
1563
1564 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1565 if (!host)
1566 return -ENOMEM;
1567
1568 host->pdev = pdev;
1569 host->pdata = pdata = pdev->dev.platform_data;
1570 if (!pdata || !pdata->init) {
1571 dev_err(&pdev->dev,
1572 "Platform data must supply init function\n");
1573 ret = -ENODEV;
1574 goto err_freehost;
1575 }
1576
1577 if (!pdata->select_slot && pdata->num_slots > 1) {
1578 dev_err(&pdev->dev,
1579 "Platform data must supply select_slot function\n");
1580 ret = -ENODEV;
1581 goto err_freehost;
1582 }
1583
1584 if (!pdata->bus_hz) {
1585 dev_err(&pdev->dev,
1586 "Platform data must supply bus speed\n");
1587 ret = -ENODEV;
1588 goto err_freehost;
1589 }
1590
1591 host->bus_hz = pdata->bus_hz;
1592 host->quirks = pdata->quirks;
1593
1594 spin_lock_init(&host->lock);
1595 INIT_LIST_HEAD(&host->queue);
1596
1597 ret = -ENOMEM;
1598 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1599 if (!host->regs)
1600 goto err_freehost;
1601
1602 host->dma_ops = pdata->dma_ops;
1603 dw_mci_init_dma(host);
1604
1605 /*
1606 * Get the host data width - this assumes that HCON has been set with
1607 * the correct values.
1608 */
1609 i = (mci_readl(host, HCON) >> 7) & 0x7;
1610 if (!i) {
1611 host->push_data = dw_mci_push_data16;
1612 host->pull_data = dw_mci_pull_data16;
1613 width = 16;
1614 host->data_shift = 1;
1615 } else if (i == 2) {
1616 host->push_data = dw_mci_push_data64;
1617 host->pull_data = dw_mci_pull_data64;
1618 width = 64;
1619 host->data_shift = 3;
1620 } else {
1621 /* Check for a reserved value, and warn if it is */
1622 WARN((i != 1),
1623 "HCON reports a reserved host data width!\n"
1624 "Defaulting to 32-bit access.\n");
1625 host->push_data = dw_mci_push_data32;
1626 host->pull_data = dw_mci_pull_data32;
1627 width = 32;
1628 host->data_shift = 2;
1629 }
1630
1631 /* Reset all blocks */
1632 if (!mci_wait_reset(&pdev->dev, host)) {
1633 ret = -ENODEV;
1634 goto err_dmaunmap;
1635 }
1636
1637 /* Clear the interrupts for the host controller */
1638 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1639 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1640
1641 /* Put in max timeout */
1642 mci_writel(host, TMOUT, 0xFFFFFFFF);
1643
1644 /*
1645 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1646 * Tx Mark = fifo_size / 2 DMA Size = 8
1647 */
1648 fifo_size = mci_readl(host, FIFOTH);
1649 fifo_size = (fifo_size >> 16) & 0x7ff;
1650 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1651 ((fifo_size/2) << 0));
1652 mci_writel(host, FIFOTH, host->fifoth_val);
1653
1654 /* disable clock to CIU */
1655 mci_writel(host, CLKENA, 0);
1656 mci_writel(host, CLKSRC, 0);
1657
1658 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1659 tasklet_init(&host->card_tasklet,
1660 dw_mci_tasklet_card, (unsigned long)host);
1661
1662 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1663 if (ret)
1664 goto err_dmaunmap;
1665
1666 platform_set_drvdata(pdev, host);
1667
1668 if (host->pdata->num_slots)
1669 host->num_slots = host->pdata->num_slots;
1670 else
1671 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1672
1673 /* We need at least one slot to succeed */
1674 for (i = 0; i < host->num_slots; i++) {
1675 ret = dw_mci_init_slot(host, i);
1676 if (ret) {
1677 ret = -ENODEV;
1678 goto err_init_slot;
1679 }
1680 }
1681
1682 /*
1683 * Enable interrupts for command done, data over, data empty, card det,
1684 * receive ready and error such as transmit, receive timeout, crc error
1685 */
1686 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1687 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1688 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1689 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1690 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1691
1692 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1693 "%d bit host data width\n", irq, width);
1694 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1695 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1696
1697 return 0;
1698
1699 err_init_slot:
1700 /* De-init any initialized slots */
1701 while (i > 0) {
1702 if (host->slot[i])
1703 dw_mci_cleanup_slot(host->slot[i], i);
1704 i--;
1705 }
1706 free_irq(irq, host);
1707
1708 err_dmaunmap:
1709 if (host->use_dma && host->dma_ops->exit)
1710 host->dma_ops->exit(host);
1711 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1712 host->sg_cpu, host->sg_dma);
1713 iounmap(host->regs);
1714
1715 if (host->vmmc) {
1716 regulator_disable(host->vmmc);
1717 regulator_put(host->vmmc);
1718 }
1719
1720
1721 err_freehost:
1722 kfree(host);
1723 return ret;
1724 }
1725
1726 static int __exit dw_mci_remove(struct platform_device *pdev)
1727 {
1728 struct dw_mci *host = platform_get_drvdata(pdev);
1729 int i;
1730
1731 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1732 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1733
1734 platform_set_drvdata(pdev, NULL);
1735
1736 for (i = 0; i < host->num_slots; i++) {
1737 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1738 if (host->slot[i])
1739 dw_mci_cleanup_slot(host->slot[i], i);
1740 }
1741
1742 /* disable clock to CIU */
1743 mci_writel(host, CLKENA, 0);
1744 mci_writel(host, CLKSRC, 0);
1745
1746 free_irq(platform_get_irq(pdev, 0), host);
1747 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1748
1749 if (host->use_dma && host->dma_ops->exit)
1750 host->dma_ops->exit(host);
1751
1752 if (host->vmmc) {
1753 regulator_disable(host->vmmc);
1754 regulator_put(host->vmmc);
1755 }
1756
1757 iounmap(host->regs);
1758
1759 kfree(host);
1760 return 0;
1761 }
1762
1763 #ifdef CONFIG_PM
1764 /*
1765 * TODO: we should probably disable the clock to the card in the suspend path.
1766 */
1767 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1768 {
1769 int i, ret;
1770 struct dw_mci *host = platform_get_drvdata(pdev);
1771
1772 for (i = 0; i < host->num_slots; i++) {
1773 struct dw_mci_slot *slot = host->slot[i];
1774 if (!slot)
1775 continue;
1776 ret = mmc_suspend_host(slot->mmc);
1777 if (ret < 0) {
1778 while (--i >= 0) {
1779 slot = host->slot[i];
1780 if (slot)
1781 mmc_resume_host(host->slot[i]->mmc);
1782 }
1783 return ret;
1784 }
1785 }
1786
1787 if (host->vmmc)
1788 regulator_disable(host->vmmc);
1789
1790 return 0;
1791 }
1792
1793 static int dw_mci_resume(struct platform_device *pdev)
1794 {
1795 int i, ret;
1796 struct dw_mci *host = platform_get_drvdata(pdev);
1797
1798 if (host->vmmc)
1799 regulator_enable(host->vmmc);
1800
1801 if (host->dma_ops->init)
1802 host->dma_ops->init(host);
1803
1804 if (!mci_wait_reset(&pdev->dev, host)) {
1805 ret = -ENODEV;
1806 return ret;
1807 }
1808
1809 /* Restore the old value at FIFOTH register */
1810 mci_writel(host, FIFOTH, host->fifoth_val);
1811
1812 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1813 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1814 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1815 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1816 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
1817
1818 for (i = 0; i < host->num_slots; i++) {
1819 struct dw_mci_slot *slot = host->slot[i];
1820 if (!slot)
1821 continue;
1822 ret = mmc_resume_host(host->slot[i]->mmc);
1823 if (ret < 0)
1824 return ret;
1825 }
1826
1827 return 0;
1828 }
1829 #else
1830 #define dw_mci_suspend NULL
1831 #define dw_mci_resume NULL
1832 #endif /* CONFIG_PM */
1833
1834 static struct platform_driver dw_mci_driver = {
1835 .remove = __exit_p(dw_mci_remove),
1836 .suspend = dw_mci_suspend,
1837 .resume = dw_mci_resume,
1838 .driver = {
1839 .name = "dw_mmc",
1840 },
1841 };
1842
1843 static int __init dw_mci_init(void)
1844 {
1845 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1846 }
1847
1848 static void __exit dw_mci_exit(void)
1849 {
1850 platform_driver_unregister(&dw_mci_driver);
1851 }
1852
1853 module_init(dw_mci_init);
1854 module_exit(dw_mci_exit);
1855
1856 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1857 MODULE_AUTHOR("NXP Semiconductor VietNam");
1858 MODULE_AUTHOR("Imagination Technologies Ltd");
1859 MODULE_LICENSE("GPL v2");
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