2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
65 #define DESC_RING_BUF_SZ PAGE_SIZE
67 struct idmac_desc_64addr
{
68 u32 des0
; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
72 u32 des1
; /* Reserved */
74 u32 des2
; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
79 u32 des3
; /* Reserved */
81 u32 des4
; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5
; /* Upper 32-bits of Buffer Address Pointer 1*/
84 u32 des6
; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7
; /* Upper 32-bits of Next Descriptor Address */
89 __le32 des0
; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
98 __le32 des1
; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
102 __le32 des2
; /* buffer 1 physical address */
104 __le32 des3
; /* buffer 2 physical address */
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file
*s
, void *v
)
113 struct dw_mci_slot
*slot
= s
->private;
114 struct mmc_request
*mrq
;
115 struct mmc_command
*cmd
;
116 struct mmc_command
*stop
;
117 struct mmc_data
*data
;
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot
->host
->lock
);
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
132 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
133 cmd
->resp
[2], cmd
->error
);
135 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
136 data
->bytes_xfered
, data
->blocks
,
137 data
->blksz
, data
->flags
, data
->error
);
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop
->opcode
, stop
->arg
, stop
->flags
,
142 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
143 stop
->resp
[2], stop
->error
);
146 spin_unlock_bh(&slot
->host
->lock
);
151 static int dw_mci_req_open(struct inode
*inode
, struct file
*file
)
153 return single_open(file
, dw_mci_req_show
, inode
->i_private
);
156 static const struct file_operations dw_mci_req_fops
= {
157 .owner
= THIS_MODULE
,
158 .open
= dw_mci_req_open
,
161 .release
= single_release
,
164 static int dw_mci_regs_show(struct seq_file
*s
, void *v
)
166 struct dw_mci
*host
= s
->private;
168 pm_runtime_get_sync(host
->dev
);
170 seq_printf(s
, "STATUS:\t0x%08x\n", mci_readl(host
, STATUS
));
171 seq_printf(s
, "RINTSTS:\t0x%08x\n", mci_readl(host
, RINTSTS
));
172 seq_printf(s
, "CMD:\t0x%08x\n", mci_readl(host
, CMD
));
173 seq_printf(s
, "CTRL:\t0x%08x\n", mci_readl(host
, CTRL
));
174 seq_printf(s
, "INTMASK:\t0x%08x\n", mci_readl(host
, INTMASK
));
175 seq_printf(s
, "CLKENA:\t0x%08x\n", mci_readl(host
, CLKENA
));
177 pm_runtime_put_autosuspend(host
->dev
);
182 static int dw_mci_regs_open(struct inode
*inode
, struct file
*file
)
184 return single_open(file
, dw_mci_regs_show
, inode
->i_private
);
187 static const struct file_operations dw_mci_regs_fops
= {
188 .owner
= THIS_MODULE
,
189 .open
= dw_mci_regs_open
,
192 .release
= single_release
,
195 static void dw_mci_init_debugfs(struct dw_mci_slot
*slot
)
197 struct mmc_host
*mmc
= slot
->mmc
;
198 struct dw_mci
*host
= slot
->host
;
202 root
= mmc
->debugfs_root
;
206 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
211 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
,
216 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
220 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
221 (u32
*)&host
->pending_events
);
225 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
226 (u32
*)&host
->completed_events
);
233 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
235 #endif /* defined(CONFIG_DEBUG_FS) */
237 static bool dw_mci_ctrl_reset(struct dw_mci
*host
, u32 reset
)
241 ctrl
= mci_readl(host
, CTRL
);
243 mci_writel(host
, CTRL
, ctrl
);
245 /* wait till resets clear */
246 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CTRL
, ctrl
,
248 1, 500 * USEC_PER_MSEC
)) {
250 "Timeout resetting block (ctrl reset %#x)\n",
258 static void dw_mci_wait_while_busy(struct dw_mci
*host
, u32 cmd_flags
)
263 * Databook says that before issuing a new data transfer command
264 * we need to check to see if the card is busy. Data transfer commands
265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
270 if ((cmd_flags
& SDMMC_CMD_PRV_DAT_WAIT
) &&
271 !(cmd_flags
& SDMMC_CMD_VOLT_SWITCH
)) {
272 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
274 !(status
& SDMMC_STATUS_BUSY
),
275 10, 500 * USEC_PER_MSEC
))
276 dev_err(host
->dev
, "Busy; trying anyway\n");
280 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
)
282 struct dw_mci
*host
= slot
->host
;
283 unsigned int cmd_status
= 0;
285 mci_writel(host
, CMDARG
, arg
);
286 wmb(); /* drain writebuffer */
287 dw_mci_wait_while_busy(host
, cmd
);
288 mci_writel(host
, CMD
, SDMMC_CMD_START
| cmd
);
290 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CMD
, cmd_status
,
291 !(cmd_status
& SDMMC_CMD_START
),
292 1, 500 * USEC_PER_MSEC
))
293 dev_err(&slot
->mmc
->class_dev
,
294 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
295 cmd
, arg
, cmd_status
);
298 static u32
dw_mci_prepare_command(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
300 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
301 struct dw_mci
*host
= slot
->host
;
304 cmd
->error
= -EINPROGRESS
;
307 if (cmd
->opcode
== MMC_STOP_TRANSMISSION
||
308 cmd
->opcode
== MMC_GO_IDLE_STATE
||
309 cmd
->opcode
== MMC_GO_INACTIVE_STATE
||
310 (cmd
->opcode
== SD_IO_RW_DIRECT
&&
311 ((cmd
->arg
>> 9) & 0x1FFFF) == SDIO_CCCR_ABORT
))
312 cmdr
|= SDMMC_CMD_STOP
;
313 else if (cmd
->opcode
!= MMC_SEND_STATUS
&& cmd
->data
)
314 cmdr
|= SDMMC_CMD_PRV_DAT_WAIT
;
316 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
319 /* Special bit makes CMD11 not die */
320 cmdr
|= SDMMC_CMD_VOLT_SWITCH
;
322 /* Change state to continue to handle CMD11 weirdness */
323 WARN_ON(slot
->host
->state
!= STATE_SENDING_CMD
);
324 slot
->host
->state
= STATE_SENDING_CMD11
;
327 * We need to disable low power mode (automatic clock stop)
328 * while doing voltage switch so we don't confuse the card,
329 * since stopping the clock is a specific part of the UHS
330 * voltage change dance.
332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
333 * unconditionally turned back on in dw_mci_setup_bus() if it's
334 * ever called with a non-zero clock. That shouldn't happen
335 * until the voltage change is all done.
337 clk_en_a
= mci_readl(host
, CLKENA
);
338 clk_en_a
&= ~(SDMMC_CLKEN_LOW_PWR
<< slot
->id
);
339 mci_writel(host
, CLKENA
, clk_en_a
);
340 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
341 SDMMC_CMD_PRV_DAT_WAIT
, 0);
344 if (cmd
->flags
& MMC_RSP_PRESENT
) {
345 /* We expect a response, so set this bit */
346 cmdr
|= SDMMC_CMD_RESP_EXP
;
347 if (cmd
->flags
& MMC_RSP_136
)
348 cmdr
|= SDMMC_CMD_RESP_LONG
;
351 if (cmd
->flags
& MMC_RSP_CRC
)
352 cmdr
|= SDMMC_CMD_RESP_CRC
;
355 cmdr
|= SDMMC_CMD_DAT_EXP
;
356 if (cmd
->data
->flags
& MMC_DATA_WRITE
)
357 cmdr
|= SDMMC_CMD_DAT_WR
;
360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &slot
->flags
))
361 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
366 static u32
dw_mci_prep_stop_abort(struct dw_mci
*host
, struct mmc_command
*cmd
)
368 struct mmc_command
*stop
;
374 stop
= &host
->stop_abort
;
376 memset(stop
, 0, sizeof(struct mmc_command
));
378 if (cmdr
== MMC_READ_SINGLE_BLOCK
||
379 cmdr
== MMC_READ_MULTIPLE_BLOCK
||
380 cmdr
== MMC_WRITE_BLOCK
||
381 cmdr
== MMC_WRITE_MULTIPLE_BLOCK
||
382 cmdr
== MMC_SEND_TUNING_BLOCK
||
383 cmdr
== MMC_SEND_TUNING_BLOCK_HS200
) {
384 stop
->opcode
= MMC_STOP_TRANSMISSION
;
386 stop
->flags
= MMC_RSP_R1B
| MMC_CMD_AC
;
387 } else if (cmdr
== SD_IO_RW_EXTENDED
) {
388 stop
->opcode
= SD_IO_RW_DIRECT
;
389 stop
->arg
|= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT
<< 9) |
390 ((cmd
->arg
>> 28) & 0x7);
391 stop
->flags
= MMC_RSP_SPI_R5
| MMC_RSP_R5
| MMC_CMD_AC
;
396 cmdr
= stop
->opcode
| SDMMC_CMD_STOP
|
397 SDMMC_CMD_RESP_CRC
| SDMMC_CMD_RESP_EXP
;
399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &host
->slot
->flags
))
400 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
405 static inline void dw_mci_set_cto(struct dw_mci
*host
)
407 unsigned int cto_clks
;
408 unsigned int cto_div
;
410 unsigned long irqflags
;
412 cto_clks
= mci_readl(host
, TMOUT
) & 0xff;
413 cto_div
= (mci_readl(host
, CLKDIV
) & 0xff) * 2;
416 cto_ms
= DIV_ROUND_UP(MSEC_PER_SEC
* cto_clks
* cto_div
, host
->bus_hz
);
418 /* add a bit spare time */
422 * The durations we're working with are fairly short so we have to be
423 * extra careful about synchronization here. Specifically in hardware a
424 * command timeout is _at most_ 5.1 ms, so that means we expect an
425 * interrupt (either command done or timeout) to come rather quickly
426 * after the mci_writel. ...but just in case we have a long interrupt
427 * latency let's add a bit of paranoia.
429 * In general we'll assume that at least an interrupt will be asserted
430 * in hardware by the time the cto_timer runs. ...and if it hasn't
431 * been asserted in hardware by that time then we'll assume it'll never
434 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
435 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
436 mod_timer(&host
->cto_timer
,
437 jiffies
+ msecs_to_jiffies(cto_ms
) + 1);
438 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
441 static void dw_mci_start_command(struct dw_mci
*host
,
442 struct mmc_command
*cmd
, u32 cmd_flags
)
446 "start command: ARGR=0x%08x CMDR=0x%08x\n",
447 cmd
->arg
, cmd_flags
);
449 mci_writel(host
, CMDARG
, cmd
->arg
);
450 wmb(); /* drain writebuffer */
451 dw_mci_wait_while_busy(host
, cmd_flags
);
453 mci_writel(host
, CMD
, cmd_flags
| SDMMC_CMD_START
);
455 /* response expected command only */
456 if (cmd_flags
& SDMMC_CMD_RESP_EXP
)
457 dw_mci_set_cto(host
);
460 static inline void send_stop_abort(struct dw_mci
*host
, struct mmc_data
*data
)
462 struct mmc_command
*stop
= &host
->stop_abort
;
464 dw_mci_start_command(host
, stop
, host
->stop_cmdr
);
467 /* DMA interface functions */
468 static void dw_mci_stop_dma(struct dw_mci
*host
)
470 if (host
->using_dma
) {
471 host
->dma_ops
->stop(host
);
472 host
->dma_ops
->cleanup(host
);
475 /* Data transfer was stopped by the interrupt handler */
476 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
479 static void dw_mci_dma_cleanup(struct dw_mci
*host
)
481 struct mmc_data
*data
= host
->data
;
483 if (data
&& data
->host_cookie
== COOKIE_MAPPED
) {
484 dma_unmap_sg(host
->dev
,
487 mmc_get_dma_dir(data
));
488 data
->host_cookie
= COOKIE_UNMAPPED
;
492 static void dw_mci_idmac_reset(struct dw_mci
*host
)
494 u32 bmod
= mci_readl(host
, BMOD
);
495 /* Software reset of DMA */
496 bmod
|= SDMMC_IDMAC_SWRESET
;
497 mci_writel(host
, BMOD
, bmod
);
500 static void dw_mci_idmac_stop_dma(struct dw_mci
*host
)
504 /* Disable and reset the IDMAC interface */
505 temp
= mci_readl(host
, CTRL
);
506 temp
&= ~SDMMC_CTRL_USE_IDMAC
;
507 temp
|= SDMMC_CTRL_DMA_RESET
;
508 mci_writel(host
, CTRL
, temp
);
510 /* Stop the IDMAC running */
511 temp
= mci_readl(host
, BMOD
);
512 temp
&= ~(SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
);
513 temp
|= SDMMC_IDMAC_SWRESET
;
514 mci_writel(host
, BMOD
, temp
);
517 static void dw_mci_dmac_complete_dma(void *arg
)
519 struct dw_mci
*host
= arg
;
520 struct mmc_data
*data
= host
->data
;
522 dev_vdbg(host
->dev
, "DMA complete\n");
524 if ((host
->use_dma
== TRANS_MODE_EDMAC
) &&
525 data
&& (data
->flags
& MMC_DATA_READ
))
526 /* Invalidate cache after read */
527 dma_sync_sg_for_cpu(mmc_dev(host
->slot
->mmc
),
532 host
->dma_ops
->cleanup(host
);
535 * If the card was removed, data will be NULL. No point in trying to
536 * send the stop command or waiting for NBUSY in this case.
539 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
540 tasklet_schedule(&host
->tasklet
);
544 static int dw_mci_idmac_init(struct dw_mci
*host
)
548 if (host
->dma_64bit_address
== 1) {
549 struct idmac_desc_64addr
*p
;
550 /* Number of descriptors in the ring buffer */
552 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc_64addr
);
554 /* Forward link the descriptor list */
555 for (i
= 0, p
= host
->sg_cpu
; i
< host
->ring_size
- 1;
557 p
->des6
= (host
->sg_dma
+
558 (sizeof(struct idmac_desc_64addr
) *
559 (i
+ 1))) & 0xffffffff;
561 p
->des7
= (u64
)(host
->sg_dma
+
562 (sizeof(struct idmac_desc_64addr
) *
564 /* Initialize reserved and buffer size fields to "0" */
570 /* Set the last descriptor as the end-of-ring descriptor */
571 p
->des6
= host
->sg_dma
& 0xffffffff;
572 p
->des7
= (u64
)host
->sg_dma
>> 32;
573 p
->des0
= IDMAC_DES0_ER
;
576 struct idmac_desc
*p
;
577 /* Number of descriptors in the ring buffer */
579 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc
);
581 /* Forward link the descriptor list */
582 for (i
= 0, p
= host
->sg_cpu
;
583 i
< host
->ring_size
- 1;
585 p
->des3
= cpu_to_le32(host
->sg_dma
+
586 (sizeof(struct idmac_desc
) * (i
+ 1)));
590 /* Set the last descriptor as the end-of-ring descriptor */
591 p
->des3
= cpu_to_le32(host
->sg_dma
);
592 p
->des0
= cpu_to_le32(IDMAC_DES0_ER
);
595 dw_mci_idmac_reset(host
);
597 if (host
->dma_64bit_address
== 1) {
598 /* Mask out interrupts - get Tx & Rx complete only */
599 mci_writel(host
, IDSTS64
, IDMAC_INT_CLR
);
600 mci_writel(host
, IDINTEN64
, SDMMC_IDMAC_INT_NI
|
601 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
603 /* Set the descriptor base address */
604 mci_writel(host
, DBADDRL
, host
->sg_dma
& 0xffffffff);
605 mci_writel(host
, DBADDRU
, (u64
)host
->sg_dma
>> 32);
608 /* Mask out interrupts - get Tx & Rx complete only */
609 mci_writel(host
, IDSTS
, IDMAC_INT_CLR
);
610 mci_writel(host
, IDINTEN
, SDMMC_IDMAC_INT_NI
|
611 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
613 /* Set the descriptor base address */
614 mci_writel(host
, DBADDR
, host
->sg_dma
);
620 static inline int dw_mci_prepare_desc64(struct dw_mci
*host
,
621 struct mmc_data
*data
,
624 unsigned int desc_len
;
625 struct idmac_desc_64addr
*desc_first
, *desc_last
, *desc
;
629 desc_first
= desc_last
= desc
= host
->sg_cpu
;
631 for (i
= 0; i
< sg_len
; i
++) {
632 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
634 u64 mem_addr
= sg_dma_address(&data
->sg
[i
]);
636 for ( ; length
; desc
++) {
637 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
638 length
: DW_MCI_DESC_DATA_LENGTH
;
643 * Wait for the former clear OWN bit operation
644 * of IDMAC to make sure that this descriptor
645 * isn't still owned by IDMAC as IDMAC's write
646 * ops and CPU's read ops are asynchronous.
648 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
649 !(val
& IDMAC_DES0_OWN
),
650 10, 100 * USEC_PER_MSEC
))
654 * Set the OWN bit and disable interrupts
655 * for this descriptor
657 desc
->des0
= IDMAC_DES0_OWN
| IDMAC_DES0_DIC
|
661 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc
, desc_len
);
663 /* Physical address to DMA to/from */
664 desc
->des4
= mem_addr
& 0xffffffff;
665 desc
->des5
= mem_addr
>> 32;
667 /* Update physical address for the next desc */
668 mem_addr
+= desc_len
;
670 /* Save pointer to the last descriptor */
675 /* Set first descriptor */
676 desc_first
->des0
|= IDMAC_DES0_FD
;
678 /* Set last descriptor */
679 desc_last
->des0
&= ~(IDMAC_DES0_CH
| IDMAC_DES0_DIC
);
680 desc_last
->des0
|= IDMAC_DES0_LD
;
684 /* restore the descriptor chain as it's polluted */
685 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
686 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
687 dw_mci_idmac_init(host
);
692 static inline int dw_mci_prepare_desc32(struct dw_mci
*host
,
693 struct mmc_data
*data
,
696 unsigned int desc_len
;
697 struct idmac_desc
*desc_first
, *desc_last
, *desc
;
701 desc_first
= desc_last
= desc
= host
->sg_cpu
;
703 for (i
= 0; i
< sg_len
; i
++) {
704 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
706 u32 mem_addr
= sg_dma_address(&data
->sg
[i
]);
708 for ( ; length
; desc
++) {
709 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
710 length
: DW_MCI_DESC_DATA_LENGTH
;
715 * Wait for the former clear OWN bit operation
716 * of IDMAC to make sure that this descriptor
717 * isn't still owned by IDMAC as IDMAC's write
718 * ops and CPU's read ops are asynchronous.
720 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
721 IDMAC_OWN_CLR64(val
),
723 100 * USEC_PER_MSEC
))
727 * Set the OWN bit and disable interrupts
728 * for this descriptor
730 desc
->des0
= cpu_to_le32(IDMAC_DES0_OWN
|
735 IDMAC_SET_BUFFER1_SIZE(desc
, desc_len
);
737 /* Physical address to DMA to/from */
738 desc
->des2
= cpu_to_le32(mem_addr
);
740 /* Update physical address for the next desc */
741 mem_addr
+= desc_len
;
743 /* Save pointer to the last descriptor */
748 /* Set first descriptor */
749 desc_first
->des0
|= cpu_to_le32(IDMAC_DES0_FD
);
751 /* Set last descriptor */
752 desc_last
->des0
&= cpu_to_le32(~(IDMAC_DES0_CH
|
754 desc_last
->des0
|= cpu_to_le32(IDMAC_DES0_LD
);
758 /* restore the descriptor chain as it's polluted */
759 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
760 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
761 dw_mci_idmac_init(host
);
765 static int dw_mci_idmac_start_dma(struct dw_mci
*host
, unsigned int sg_len
)
770 if (host
->dma_64bit_address
== 1)
771 ret
= dw_mci_prepare_desc64(host
, host
->data
, sg_len
);
773 ret
= dw_mci_prepare_desc32(host
, host
->data
, sg_len
);
778 /* drain writebuffer */
781 /* Make sure to reset DMA in case we did PIO before this */
782 dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
);
783 dw_mci_idmac_reset(host
);
785 /* Select IDMAC interface */
786 temp
= mci_readl(host
, CTRL
);
787 temp
|= SDMMC_CTRL_USE_IDMAC
;
788 mci_writel(host
, CTRL
, temp
);
790 /* drain writebuffer */
793 /* Enable the IDMAC */
794 temp
= mci_readl(host
, BMOD
);
795 temp
|= SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
;
796 mci_writel(host
, BMOD
, temp
);
798 /* Start it running */
799 mci_writel(host
, PLDMND
, 1);
805 static const struct dw_mci_dma_ops dw_mci_idmac_ops
= {
806 .init
= dw_mci_idmac_init
,
807 .start
= dw_mci_idmac_start_dma
,
808 .stop
= dw_mci_idmac_stop_dma
,
809 .complete
= dw_mci_dmac_complete_dma
,
810 .cleanup
= dw_mci_dma_cleanup
,
813 static void dw_mci_edmac_stop_dma(struct dw_mci
*host
)
815 dmaengine_terminate_async(host
->dms
->ch
);
818 static int dw_mci_edmac_start_dma(struct dw_mci
*host
,
821 struct dma_slave_config cfg
;
822 struct dma_async_tx_descriptor
*desc
= NULL
;
823 struct scatterlist
*sgl
= host
->data
->sg
;
824 static const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
825 u32 sg_elems
= host
->data
->sg_len
;
827 u32 fifo_offset
= host
->fifo_reg
- host
->regs
;
830 /* Set external dma config: burst size, burst width */
831 cfg
.dst_addr
= host
->phy_regs
+ fifo_offset
;
832 cfg
.src_addr
= cfg
.dst_addr
;
833 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
834 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
836 /* Match burst msize with external dma config */
837 fifoth_val
= mci_readl(host
, FIFOTH
);
838 cfg
.dst_maxburst
= mszs
[(fifoth_val
>> 28) & 0x7];
839 cfg
.src_maxburst
= cfg
.dst_maxburst
;
841 if (host
->data
->flags
& MMC_DATA_WRITE
)
842 cfg
.direction
= DMA_MEM_TO_DEV
;
844 cfg
.direction
= DMA_DEV_TO_MEM
;
846 ret
= dmaengine_slave_config(host
->dms
->ch
, &cfg
);
848 dev_err(host
->dev
, "Failed to config edmac.\n");
852 desc
= dmaengine_prep_slave_sg(host
->dms
->ch
, sgl
,
853 sg_len
, cfg
.direction
,
854 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
856 dev_err(host
->dev
, "Can't prepare slave sg.\n");
860 /* Set dw_mci_dmac_complete_dma as callback */
861 desc
->callback
= dw_mci_dmac_complete_dma
;
862 desc
->callback_param
= (void *)host
;
863 dmaengine_submit(desc
);
865 /* Flush cache before write */
866 if (host
->data
->flags
& MMC_DATA_WRITE
)
867 dma_sync_sg_for_device(mmc_dev(host
->slot
->mmc
), sgl
,
868 sg_elems
, DMA_TO_DEVICE
);
870 dma_async_issue_pending(host
->dms
->ch
);
875 static int dw_mci_edmac_init(struct dw_mci
*host
)
877 /* Request external dma channel */
878 host
->dms
= kzalloc(sizeof(struct dw_mci_dma_slave
), GFP_KERNEL
);
882 host
->dms
->ch
= dma_request_slave_channel(host
->dev
, "rx-tx");
883 if (!host
->dms
->ch
) {
884 dev_err(host
->dev
, "Failed to get external DMA channel.\n");
893 static void dw_mci_edmac_exit(struct dw_mci
*host
)
897 dma_release_channel(host
->dms
->ch
);
898 host
->dms
->ch
= NULL
;
905 static const struct dw_mci_dma_ops dw_mci_edmac_ops
= {
906 .init
= dw_mci_edmac_init
,
907 .exit
= dw_mci_edmac_exit
,
908 .start
= dw_mci_edmac_start_dma
,
909 .stop
= dw_mci_edmac_stop_dma
,
910 .complete
= dw_mci_dmac_complete_dma
,
911 .cleanup
= dw_mci_dma_cleanup
,
914 static int dw_mci_pre_dma_transfer(struct dw_mci
*host
,
915 struct mmc_data
*data
,
918 struct scatterlist
*sg
;
919 unsigned int i
, sg_len
;
921 if (data
->host_cookie
== COOKIE_PRE_MAPPED
)
925 * We don't do DMA on "complex" transfers, i.e. with
926 * non-word-aligned buffers or lengths. Also, we don't bother
927 * with all the DMA setup overhead for short transfers.
929 if (data
->blocks
* data
->blksz
< DW_MCI_DMA_THRESHOLD
)
935 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
936 if (sg
->offset
& 3 || sg
->length
& 3)
940 sg_len
= dma_map_sg(host
->dev
,
943 mmc_get_dma_dir(data
));
947 data
->host_cookie
= cookie
;
952 static void dw_mci_pre_req(struct mmc_host
*mmc
,
953 struct mmc_request
*mrq
)
955 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
956 struct mmc_data
*data
= mrq
->data
;
958 if (!slot
->host
->use_dma
|| !data
)
961 /* This data might be unmapped at this time */
962 data
->host_cookie
= COOKIE_UNMAPPED
;
964 if (dw_mci_pre_dma_transfer(slot
->host
, mrq
->data
,
965 COOKIE_PRE_MAPPED
) < 0)
966 data
->host_cookie
= COOKIE_UNMAPPED
;
969 static void dw_mci_post_req(struct mmc_host
*mmc
,
970 struct mmc_request
*mrq
,
973 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
974 struct mmc_data
*data
= mrq
->data
;
976 if (!slot
->host
->use_dma
|| !data
)
979 if (data
->host_cookie
!= COOKIE_UNMAPPED
)
980 dma_unmap_sg(slot
->host
->dev
,
983 mmc_get_dma_dir(data
));
984 data
->host_cookie
= COOKIE_UNMAPPED
;
987 static int dw_mci_get_cd(struct mmc_host
*mmc
)
990 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
991 struct dw_mci
*host
= slot
->host
;
992 int gpio_cd
= mmc_gpio_get_cd(mmc
);
994 /* Use platform get_cd function, else try onboard card detect */
995 if (((mmc
->caps
& MMC_CAP_NEEDS_POLL
)
996 || !mmc_card_is_removable(mmc
))) {
999 if (!test_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
)) {
1000 if (mmc
->caps
& MMC_CAP_NEEDS_POLL
) {
1001 dev_info(&mmc
->class_dev
,
1002 "card is polling.\n");
1004 dev_info(&mmc
->class_dev
,
1005 "card is non-removable.\n");
1007 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1011 } else if (gpio_cd
>= 0)
1014 present
= (mci_readl(slot
->host
, CDETECT
) & (1 << slot
->id
))
1017 spin_lock_bh(&host
->lock
);
1018 if (present
&& !test_and_set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
1019 dev_dbg(&mmc
->class_dev
, "card is present\n");
1020 else if (!present
&&
1021 !test_and_clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
1022 dev_dbg(&mmc
->class_dev
, "card is not present\n");
1023 spin_unlock_bh(&host
->lock
);
1028 static void dw_mci_adjust_fifoth(struct dw_mci
*host
, struct mmc_data
*data
)
1030 unsigned int blksz
= data
->blksz
;
1031 static const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
1032 u32 fifo_width
= 1 << host
->data_shift
;
1033 u32 blksz_depth
= blksz
/ fifo_width
, fifoth_val
;
1034 u32 msize
= 0, rx_wmark
= 1, tx_wmark
, tx_wmark_invers
;
1035 int idx
= ARRAY_SIZE(mszs
) - 1;
1037 /* pio should ship this scenario */
1041 tx_wmark
= (host
->fifo_depth
) / 2;
1042 tx_wmark_invers
= host
->fifo_depth
- tx_wmark
;
1046 * if blksz is not a multiple of the FIFO width
1048 if (blksz
% fifo_width
)
1052 if (!((blksz_depth
% mszs
[idx
]) ||
1053 (tx_wmark_invers
% mszs
[idx
]))) {
1055 rx_wmark
= mszs
[idx
] - 1;
1058 } while (--idx
> 0);
1060 * If idx is '0', it won't be tried
1061 * Thus, initial values are uesed
1064 fifoth_val
= SDMMC_SET_FIFOTH(msize
, rx_wmark
, tx_wmark
);
1065 mci_writel(host
, FIFOTH
, fifoth_val
);
1068 static void dw_mci_ctrl_thld(struct dw_mci
*host
, struct mmc_data
*data
)
1070 unsigned int blksz
= data
->blksz
;
1071 u32 blksz_depth
, fifo_depth
;
1076 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1077 * in the FIFO region, so we really shouldn't access it).
1079 if (host
->verid
< DW_MMC_240A
||
1080 (host
->verid
< DW_MMC_280A
&& data
->flags
& MMC_DATA_WRITE
))
1084 * Card write Threshold is introduced since 2.80a
1085 * It's used when HS400 mode is enabled.
1087 if (data
->flags
& MMC_DATA_WRITE
&&
1088 !(host
->timing
!= MMC_TIMING_MMC_HS400
))
1091 if (data
->flags
& MMC_DATA_WRITE
)
1092 enable
= SDMMC_CARD_WR_THR_EN
;
1094 enable
= SDMMC_CARD_RD_THR_EN
;
1096 if (host
->timing
!= MMC_TIMING_MMC_HS200
&&
1097 host
->timing
!= MMC_TIMING_UHS_SDR104
)
1100 blksz_depth
= blksz
/ (1 << host
->data_shift
);
1101 fifo_depth
= host
->fifo_depth
;
1103 if (blksz_depth
> fifo_depth
)
1107 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1108 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1109 * Currently just choose blksz.
1112 mci_writel(host
, CDTHRCTL
, SDMMC_SET_THLD(thld_size
, enable
));
1116 mci_writel(host
, CDTHRCTL
, 0);
1119 static int dw_mci_submit_data_dma(struct dw_mci
*host
, struct mmc_data
*data
)
1121 unsigned long irqflags
;
1125 host
->using_dma
= 0;
1127 /* If we don't have a channel, we can't do DMA */
1131 sg_len
= dw_mci_pre_dma_transfer(host
, data
, COOKIE_MAPPED
);
1133 host
->dma_ops
->stop(host
);
1137 host
->using_dma
= 1;
1139 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1141 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1142 (unsigned long)host
->sg_cpu
,
1143 (unsigned long)host
->sg_dma
,
1147 * Decide the MSIZE and RX/TX Watermark.
1148 * If current block size is same with previous size,
1149 * no need to update fifoth.
1151 if (host
->prev_blksz
!= data
->blksz
)
1152 dw_mci_adjust_fifoth(host
, data
);
1154 /* Enable the DMA interface */
1155 temp
= mci_readl(host
, CTRL
);
1156 temp
|= SDMMC_CTRL_DMA_ENABLE
;
1157 mci_writel(host
, CTRL
, temp
);
1159 /* Disable RX/TX IRQs, let DMA handle it */
1160 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1161 temp
= mci_readl(host
, INTMASK
);
1162 temp
&= ~(SDMMC_INT_RXDR
| SDMMC_INT_TXDR
);
1163 mci_writel(host
, INTMASK
, temp
);
1164 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1166 if (host
->dma_ops
->start(host
, sg_len
)) {
1167 host
->dma_ops
->stop(host
);
1168 /* We can't do DMA, try PIO for this one */
1170 "%s: fall back to PIO mode for current transfer\n",
1178 static void dw_mci_submit_data(struct dw_mci
*host
, struct mmc_data
*data
)
1180 unsigned long irqflags
;
1181 int flags
= SG_MITER_ATOMIC
;
1184 data
->error
= -EINPROGRESS
;
1186 WARN_ON(host
->data
);
1190 if (data
->flags
& MMC_DATA_READ
)
1191 host
->dir_status
= DW_MCI_RECV_STATUS
;
1193 host
->dir_status
= DW_MCI_SEND_STATUS
;
1195 dw_mci_ctrl_thld(host
, data
);
1197 if (dw_mci_submit_data_dma(host
, data
)) {
1198 if (host
->data
->flags
& MMC_DATA_READ
)
1199 flags
|= SG_MITER_TO_SG
;
1201 flags
|= SG_MITER_FROM_SG
;
1203 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
1204 host
->sg
= data
->sg
;
1205 host
->part_buf_start
= 0;
1206 host
->part_buf_count
= 0;
1208 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
| SDMMC_INT_RXDR
);
1210 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1211 temp
= mci_readl(host
, INTMASK
);
1212 temp
|= SDMMC_INT_TXDR
| SDMMC_INT_RXDR
;
1213 mci_writel(host
, INTMASK
, temp
);
1214 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1216 temp
= mci_readl(host
, CTRL
);
1217 temp
&= ~SDMMC_CTRL_DMA_ENABLE
;
1218 mci_writel(host
, CTRL
, temp
);
1221 * Use the initial fifoth_val for PIO mode. If wm_algined
1222 * is set, we set watermark same as data size.
1223 * If next issued data may be transfered by DMA mode,
1224 * prev_blksz should be invalidated.
1226 if (host
->wm_aligned
)
1227 dw_mci_adjust_fifoth(host
, data
);
1229 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
1230 host
->prev_blksz
= 0;
1233 * Keep the current block size.
1234 * It will be used to decide whether to update
1235 * fifoth register next time.
1237 host
->prev_blksz
= data
->blksz
;
1241 static void dw_mci_setup_bus(struct dw_mci_slot
*slot
, bool force_clkinit
)
1243 struct dw_mci
*host
= slot
->host
;
1244 unsigned int clock
= slot
->clock
;
1247 u32 sdmmc_cmd_bits
= SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
;
1249 /* We must continue to set bit 28 in CMD until the change is complete */
1250 if (host
->state
== STATE_WAITING_CMD11_DONE
)
1251 sdmmc_cmd_bits
|= SDMMC_CMD_VOLT_SWITCH
;
1254 mci_writel(host
, CLKENA
, 0);
1255 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1256 } else if (clock
!= host
->current_speed
|| force_clkinit
) {
1257 div
= host
->bus_hz
/ clock
;
1258 if (host
->bus_hz
% clock
&& host
->bus_hz
> clock
)
1260 * move the + 1 after the divide to prevent
1261 * over-clocking the card.
1265 div
= (host
->bus_hz
!= clock
) ? DIV_ROUND_UP(div
, 2) : 0;
1267 if ((clock
!= slot
->__clk_old
&&
1268 !test_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
)) ||
1270 /* Silent the verbose log if calling from PM context */
1272 dev_info(&slot
->mmc
->class_dev
,
1273 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1274 slot
->id
, host
->bus_hz
, clock
,
1275 div
? ((host
->bus_hz
/ div
) >> 1) :
1279 * If card is polling, display the message only
1280 * one time at boot time.
1282 if (slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
&&
1283 slot
->mmc
->f_min
== clock
)
1284 set_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
);
1288 mci_writel(host
, CLKENA
, 0);
1289 mci_writel(host
, CLKSRC
, 0);
1292 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1294 /* set clock to desired speed */
1295 mci_writel(host
, CLKDIV
, div
);
1298 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1300 /* enable clock; only low power if no SDIO */
1301 clk_en_a
= SDMMC_CLKEN_ENABLE
<< slot
->id
;
1302 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
))
1303 clk_en_a
|= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1304 mci_writel(host
, CLKENA
, clk_en_a
);
1307 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1309 /* keep the last clock value that was requested from core */
1310 slot
->__clk_old
= clock
;
1313 host
->current_speed
= clock
;
1315 /* Set the current slot bus width */
1316 mci_writel(host
, CTYPE
, (slot
->ctype
<< slot
->id
));
1319 static void __dw_mci_start_request(struct dw_mci
*host
,
1320 struct dw_mci_slot
*slot
,
1321 struct mmc_command
*cmd
)
1323 struct mmc_request
*mrq
;
1324 struct mmc_data
*data
;
1331 host
->pending_events
= 0;
1332 host
->completed_events
= 0;
1333 host
->cmd_status
= 0;
1334 host
->data_status
= 0;
1335 host
->dir_status
= 0;
1339 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
1340 mci_writel(host
, BYTCNT
, data
->blksz
*data
->blocks
);
1341 mci_writel(host
, BLKSIZ
, data
->blksz
);
1344 cmdflags
= dw_mci_prepare_command(slot
->mmc
, cmd
);
1346 /* this is the first command, send the initialization clock */
1347 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
))
1348 cmdflags
|= SDMMC_CMD_INIT
;
1351 dw_mci_submit_data(host
, data
);
1352 wmb(); /* drain writebuffer */
1355 dw_mci_start_command(host
, cmd
, cmdflags
);
1357 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
1358 unsigned long irqflags
;
1361 * Databook says to fail after 2ms w/ no response, but evidence
1362 * shows that sometimes the cmd11 interrupt takes over 130ms.
1363 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1364 * is just about to roll over.
1366 * We do this whole thing under spinlock and only if the
1367 * command hasn't already completed (indicating the the irq
1368 * already ran so we don't want the timeout).
1370 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1371 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1372 mod_timer(&host
->cmd11_timer
,
1373 jiffies
+ msecs_to_jiffies(500) + 1);
1374 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1377 host
->stop_cmdr
= dw_mci_prep_stop_abort(host
, cmd
);
1380 static void dw_mci_start_request(struct dw_mci
*host
,
1381 struct dw_mci_slot
*slot
)
1383 struct mmc_request
*mrq
= slot
->mrq
;
1384 struct mmc_command
*cmd
;
1386 cmd
= mrq
->sbc
? mrq
->sbc
: mrq
->cmd
;
1387 __dw_mci_start_request(host
, slot
, cmd
);
1390 /* must be called with host->lock held */
1391 static void dw_mci_queue_request(struct dw_mci
*host
, struct dw_mci_slot
*slot
,
1392 struct mmc_request
*mrq
)
1394 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1399 if (host
->state
== STATE_WAITING_CMD11_DONE
) {
1400 dev_warn(&slot
->mmc
->class_dev
,
1401 "Voltage change didn't complete\n");
1403 * this case isn't expected to happen, so we can
1404 * either crash here or just try to continue on
1405 * in the closest possible state
1407 host
->state
= STATE_IDLE
;
1410 if (host
->state
== STATE_IDLE
) {
1411 host
->state
= STATE_SENDING_CMD
;
1412 dw_mci_start_request(host
, slot
);
1414 list_add_tail(&slot
->queue_node
, &host
->queue
);
1418 static void dw_mci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1420 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1421 struct dw_mci
*host
= slot
->host
;
1426 * The check for card presence and queueing of the request must be
1427 * atomic, otherwise the card could be removed in between and the
1428 * request wouldn't fail until another card was inserted.
1431 if (!dw_mci_get_cd(mmc
)) {
1432 mrq
->cmd
->error
= -ENOMEDIUM
;
1433 mmc_request_done(mmc
, mrq
);
1437 spin_lock_bh(&host
->lock
);
1439 dw_mci_queue_request(host
, slot
, mrq
);
1441 spin_unlock_bh(&host
->lock
);
1444 static void dw_mci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1446 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1447 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
1451 switch (ios
->bus_width
) {
1452 case MMC_BUS_WIDTH_4
:
1453 slot
->ctype
= SDMMC_CTYPE_4BIT
;
1455 case MMC_BUS_WIDTH_8
:
1456 slot
->ctype
= SDMMC_CTYPE_8BIT
;
1459 /* set default 1 bit mode */
1460 slot
->ctype
= SDMMC_CTYPE_1BIT
;
1463 regs
= mci_readl(slot
->host
, UHS_REG
);
1466 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
1467 ios
->timing
== MMC_TIMING_UHS_DDR50
||
1468 ios
->timing
== MMC_TIMING_MMC_HS400
)
1469 regs
|= ((0x1 << slot
->id
) << 16);
1471 regs
&= ~((0x1 << slot
->id
) << 16);
1473 mci_writel(slot
->host
, UHS_REG
, regs
);
1474 slot
->host
->timing
= ios
->timing
;
1477 * Use mirror of ios->clock to prevent race with mmc
1478 * core ios update when finding the minimum.
1480 slot
->clock
= ios
->clock
;
1482 if (drv_data
&& drv_data
->set_ios
)
1483 drv_data
->set_ios(slot
->host
, ios
);
1485 switch (ios
->power_mode
) {
1487 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1488 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
1491 dev_err(slot
->host
->dev
,
1492 "failed to enable vmmc regulator\n");
1493 /*return, if failed turn on vmmc*/
1497 set_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
);
1498 regs
= mci_readl(slot
->host
, PWREN
);
1499 regs
|= (1 << slot
->id
);
1500 mci_writel(slot
->host
, PWREN
, regs
);
1503 if (!slot
->host
->vqmmc_enabled
) {
1504 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1505 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1507 dev_err(slot
->host
->dev
,
1508 "failed to enable vqmmc\n");
1510 slot
->host
->vqmmc_enabled
= true;
1513 /* Keep track so we don't reset again */
1514 slot
->host
->vqmmc_enabled
= true;
1517 /* Reset our state machine after powering on */
1518 dw_mci_ctrl_reset(slot
->host
,
1519 SDMMC_CTRL_ALL_RESET_FLAGS
);
1522 /* Adjust clock / bus width after power is up */
1523 dw_mci_setup_bus(slot
, false);
1527 /* Turn clock off before power goes down */
1528 dw_mci_setup_bus(slot
, false);
1530 if (!IS_ERR(mmc
->supply
.vmmc
))
1531 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1533 if (!IS_ERR(mmc
->supply
.vqmmc
) && slot
->host
->vqmmc_enabled
)
1534 regulator_disable(mmc
->supply
.vqmmc
);
1535 slot
->host
->vqmmc_enabled
= false;
1537 regs
= mci_readl(slot
->host
, PWREN
);
1538 regs
&= ~(1 << slot
->id
);
1539 mci_writel(slot
->host
, PWREN
, regs
);
1545 if (slot
->host
->state
== STATE_WAITING_CMD11_DONE
&& ios
->clock
!= 0)
1546 slot
->host
->state
= STATE_IDLE
;
1549 static int dw_mci_card_busy(struct mmc_host
*mmc
)
1551 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1555 * Check the busy bit which is low when DAT[3:0]
1556 * (the data lines) are 0000
1558 status
= mci_readl(slot
->host
, STATUS
);
1560 return !!(status
& SDMMC_STATUS_BUSY
);
1563 static int dw_mci_switch_voltage(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1565 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1566 struct dw_mci
*host
= slot
->host
;
1567 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1569 u32 v18
= SDMMC_UHS_18V
<< slot
->id
;
1572 if (drv_data
&& drv_data
->switch_voltage
)
1573 return drv_data
->switch_voltage(mmc
, ios
);
1576 * Program the voltage. Note that some instances of dw_mmc may use
1577 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1578 * does no harm but you need to set the regulator directly. Try both.
1580 uhs
= mci_readl(host
, UHS_REG
);
1581 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1586 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1587 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1590 dev_dbg(&mmc
->class_dev
,
1591 "Regulator set error %d - %s V\n",
1592 ret
, uhs
& v18
? "1.8" : "3.3");
1596 mci_writel(host
, UHS_REG
, uhs
);
1601 static int dw_mci_get_ro(struct mmc_host
*mmc
)
1604 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1605 int gpio_ro
= mmc_gpio_get_ro(mmc
);
1607 /* Use platform get_ro function, else try on board write protect */
1609 read_only
= gpio_ro
;
1612 mci_readl(slot
->host
, WRTPRT
) & (1 << slot
->id
) ? 1 : 0;
1614 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1615 read_only
? "read-only" : "read-write");
1620 static void dw_mci_hw_reset(struct mmc_host
*mmc
)
1622 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1623 struct dw_mci
*host
= slot
->host
;
1626 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1627 dw_mci_idmac_reset(host
);
1629 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
|
1630 SDMMC_CTRL_FIFO_RESET
))
1634 * According to eMMC spec, card reset procedure:
1635 * tRstW >= 1us: RST_n pulse width
1636 * tRSCA >= 200us: RST_n to Command time
1637 * tRSTH >= 1us: RST_n high period
1639 reset
= mci_readl(host
, RST_N
);
1640 reset
&= ~(SDMMC_RST_HWACTIVE
<< slot
->id
);
1641 mci_writel(host
, RST_N
, reset
);
1643 reset
|= SDMMC_RST_HWACTIVE
<< slot
->id
;
1644 mci_writel(host
, RST_N
, reset
);
1645 usleep_range(200, 300);
1648 static void dw_mci_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1650 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1651 struct dw_mci
*host
= slot
->host
;
1654 * Low power mode will stop the card clock when idle. According to the
1655 * description of the CLKENA register we should disable low power mode
1656 * for SDIO cards if we need SDIO interrupts to work.
1658 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
) {
1659 const u32 clken_low_pwr
= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1663 clk_en_a_old
= mci_readl(host
, CLKENA
);
1665 if (card
->type
== MMC_TYPE_SDIO
||
1666 card
->type
== MMC_TYPE_SD_COMBO
) {
1667 set_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1668 clk_en_a
= clk_en_a_old
& ~clken_low_pwr
;
1670 clear_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1671 clk_en_a
= clk_en_a_old
| clken_low_pwr
;
1674 if (clk_en_a
!= clk_en_a_old
) {
1675 mci_writel(host
, CLKENA
, clk_en_a
);
1676 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
1677 SDMMC_CMD_PRV_DAT_WAIT
, 0);
1682 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot
*slot
, int enb
)
1684 struct dw_mci
*host
= slot
->host
;
1685 unsigned long irqflags
;
1688 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1690 /* Enable/disable Slot Specific SDIO interrupt */
1691 int_mask
= mci_readl(host
, INTMASK
);
1693 int_mask
|= SDMMC_INT_SDIO(slot
->sdio_id
);
1695 int_mask
&= ~SDMMC_INT_SDIO(slot
->sdio_id
);
1696 mci_writel(host
, INTMASK
, int_mask
);
1698 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1701 static void dw_mci_enable_sdio_irq(struct mmc_host
*mmc
, int enb
)
1703 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1704 struct dw_mci
*host
= slot
->host
;
1706 __dw_mci_enable_sdio_irq(slot
, enb
);
1708 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1710 pm_runtime_get_noresume(host
->dev
);
1712 pm_runtime_put_noidle(host
->dev
);
1715 static void dw_mci_ack_sdio_irq(struct mmc_host
*mmc
)
1717 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1719 __dw_mci_enable_sdio_irq(slot
, 1);
1722 static int dw_mci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1724 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1725 struct dw_mci
*host
= slot
->host
;
1726 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1729 if (drv_data
&& drv_data
->execute_tuning
)
1730 err
= drv_data
->execute_tuning(slot
, opcode
);
1734 static int dw_mci_prepare_hs400_tuning(struct mmc_host
*mmc
,
1735 struct mmc_ios
*ios
)
1737 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1738 struct dw_mci
*host
= slot
->host
;
1739 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1741 if (drv_data
&& drv_data
->prepare_hs400_tuning
)
1742 return drv_data
->prepare_hs400_tuning(host
, ios
);
1747 static bool dw_mci_reset(struct dw_mci
*host
)
1749 u32 flags
= SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
;
1754 * Resetting generates a block interrupt, hence setting
1755 * the scatter-gather pointer to NULL.
1758 sg_miter_stop(&host
->sg_miter
);
1763 flags
|= SDMMC_CTRL_DMA_RESET
;
1765 if (dw_mci_ctrl_reset(host
, flags
)) {
1767 * In all cases we clear the RAWINTS
1768 * register to clear any interrupts.
1770 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
1772 if (!host
->use_dma
) {
1777 /* Wait for dma_req to be cleared */
1778 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
1780 !(status
& SDMMC_STATUS_DMA_REQ
),
1781 1, 500 * USEC_PER_MSEC
)) {
1783 "%s: Timeout waiting for dma_req to be cleared\n",
1788 /* when using DMA next we reset the fifo again */
1789 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_FIFO_RESET
))
1792 /* if the controller reset bit did clear, then set clock regs */
1793 if (!(mci_readl(host
, CTRL
) & SDMMC_CTRL_RESET
)) {
1795 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1801 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1802 /* It is also recommended that we reset and reprogram idmac */
1803 dw_mci_idmac_reset(host
);
1808 /* After a CTRL reset we need to have CIU set clock registers */
1809 mci_send_cmd(host
->slot
, SDMMC_CMD_UPD_CLK
, 0);
1814 static const struct mmc_host_ops dw_mci_ops
= {
1815 .request
= dw_mci_request
,
1816 .pre_req
= dw_mci_pre_req
,
1817 .post_req
= dw_mci_post_req
,
1818 .set_ios
= dw_mci_set_ios
,
1819 .get_ro
= dw_mci_get_ro
,
1820 .get_cd
= dw_mci_get_cd
,
1821 .hw_reset
= dw_mci_hw_reset
,
1822 .enable_sdio_irq
= dw_mci_enable_sdio_irq
,
1823 .ack_sdio_irq
= dw_mci_ack_sdio_irq
,
1824 .execute_tuning
= dw_mci_execute_tuning
,
1825 .card_busy
= dw_mci_card_busy
,
1826 .start_signal_voltage_switch
= dw_mci_switch_voltage
,
1827 .init_card
= dw_mci_init_card
,
1828 .prepare_hs400_tuning
= dw_mci_prepare_hs400_tuning
,
1831 static void dw_mci_request_end(struct dw_mci
*host
, struct mmc_request
*mrq
)
1832 __releases(&host
->lock
)
1833 __acquires(&host
->lock
)
1835 struct dw_mci_slot
*slot
;
1836 struct mmc_host
*prev_mmc
= host
->slot
->mmc
;
1838 WARN_ON(host
->cmd
|| host
->data
);
1840 host
->slot
->mrq
= NULL
;
1842 if (!list_empty(&host
->queue
)) {
1843 slot
= list_entry(host
->queue
.next
,
1844 struct dw_mci_slot
, queue_node
);
1845 list_del(&slot
->queue_node
);
1846 dev_vdbg(host
->dev
, "list not empty: %s is next\n",
1847 mmc_hostname(slot
->mmc
));
1848 host
->state
= STATE_SENDING_CMD
;
1849 dw_mci_start_request(host
, slot
);
1851 dev_vdbg(host
->dev
, "list empty\n");
1853 if (host
->state
== STATE_SENDING_CMD11
)
1854 host
->state
= STATE_WAITING_CMD11_DONE
;
1856 host
->state
= STATE_IDLE
;
1859 spin_unlock(&host
->lock
);
1860 mmc_request_done(prev_mmc
, mrq
);
1861 spin_lock(&host
->lock
);
1864 static int dw_mci_command_complete(struct dw_mci
*host
, struct mmc_command
*cmd
)
1866 u32 status
= host
->cmd_status
;
1868 host
->cmd_status
= 0;
1870 /* Read the response from the card (up to 16 bytes) */
1871 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1872 if (cmd
->flags
& MMC_RSP_136
) {
1873 cmd
->resp
[3] = mci_readl(host
, RESP0
);
1874 cmd
->resp
[2] = mci_readl(host
, RESP1
);
1875 cmd
->resp
[1] = mci_readl(host
, RESP2
);
1876 cmd
->resp
[0] = mci_readl(host
, RESP3
);
1878 cmd
->resp
[0] = mci_readl(host
, RESP0
);
1885 if (status
& SDMMC_INT_RTO
)
1886 cmd
->error
= -ETIMEDOUT
;
1887 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& SDMMC_INT_RCRC
))
1888 cmd
->error
= -EILSEQ
;
1889 else if (status
& SDMMC_INT_RESP_ERR
)
1897 static int dw_mci_data_complete(struct dw_mci
*host
, struct mmc_data
*data
)
1899 u32 status
= host
->data_status
;
1901 if (status
& DW_MCI_DATA_ERROR_FLAGS
) {
1902 if (status
& SDMMC_INT_DRTO
) {
1903 data
->error
= -ETIMEDOUT
;
1904 } else if (status
& SDMMC_INT_DCRC
) {
1905 data
->error
= -EILSEQ
;
1906 } else if (status
& SDMMC_INT_EBE
) {
1907 if (host
->dir_status
==
1908 DW_MCI_SEND_STATUS
) {
1910 * No data CRC status was returned.
1911 * The number of bytes transferred
1912 * will be exaggerated in PIO mode.
1914 data
->bytes_xfered
= 0;
1915 data
->error
= -ETIMEDOUT
;
1916 } else if (host
->dir_status
==
1917 DW_MCI_RECV_STATUS
) {
1918 data
->error
= -EILSEQ
;
1921 /* SDMMC_INT_SBE is included */
1922 data
->error
= -EILSEQ
;
1925 dev_dbg(host
->dev
, "data error, status 0x%08x\n", status
);
1928 * After an error, there may be data lingering
1933 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1940 static void dw_mci_set_drto(struct dw_mci
*host
)
1942 unsigned int drto_clks
;
1943 unsigned int drto_div
;
1944 unsigned int drto_ms
;
1945 unsigned long irqflags
;
1947 drto_clks
= mci_readl(host
, TMOUT
) >> 8;
1948 drto_div
= (mci_readl(host
, CLKDIV
) & 0xff) * 2;
1951 drto_ms
= DIV_ROUND_UP(MSEC_PER_SEC
* drto_clks
* drto_div
,
1954 /* add a bit spare time */
1957 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1958 if (!test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
))
1959 mod_timer(&host
->dto_timer
,
1960 jiffies
+ msecs_to_jiffies(drto_ms
));
1961 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1964 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci
*host
)
1966 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1970 * Really be certain that the timer has stopped. This is a bit of
1971 * paranoia and could only really happen if we had really bad
1972 * interrupt latency and the interrupt routine and timeout were
1973 * running concurrently so that the del_timer() in the interrupt
1974 * handler couldn't run.
1976 WARN_ON(del_timer_sync(&host
->cto_timer
));
1977 clear_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
1982 static bool dw_mci_clear_pending_data_complete(struct dw_mci
*host
)
1984 if (!test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
))
1987 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1988 WARN_ON(del_timer_sync(&host
->dto_timer
));
1989 clear_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
1994 static void dw_mci_tasklet_func(unsigned long priv
)
1996 struct dw_mci
*host
= (struct dw_mci
*)priv
;
1997 struct mmc_data
*data
;
1998 struct mmc_command
*cmd
;
1999 struct mmc_request
*mrq
;
2000 enum dw_mci_state state
;
2001 enum dw_mci_state prev_state
;
2004 spin_lock(&host
->lock
);
2006 state
= host
->state
;
2015 case STATE_WAITING_CMD11_DONE
:
2018 case STATE_SENDING_CMD11
:
2019 case STATE_SENDING_CMD
:
2020 if (!dw_mci_clear_pending_cmd_complete(host
))
2025 set_bit(EVENT_CMD_COMPLETE
, &host
->completed_events
);
2026 err
= dw_mci_command_complete(host
, cmd
);
2027 if (cmd
== mrq
->sbc
&& !err
) {
2028 prev_state
= state
= STATE_SENDING_CMD
;
2029 __dw_mci_start_request(host
, host
->slot
,
2034 if (cmd
->data
&& err
) {
2036 * During UHS tuning sequence, sending the stop
2037 * command after the response CRC error would
2038 * throw the system into a confused state
2039 * causing all future tuning phases to report
2042 * In such case controller will move into a data
2043 * transfer state after a response error or
2044 * response CRC error. Let's let that finish
2045 * before trying to send a stop, so we'll go to
2046 * STATE_SENDING_DATA.
2048 * Although letting the data transfer take place
2049 * will waste a bit of time (we already know
2050 * the command was bad), it can't cause any
2051 * errors since it's possible it would have
2052 * taken place anyway if this tasklet got
2053 * delayed. Allowing the transfer to take place
2054 * avoids races and keeps things simple.
2056 if ((err
!= -ETIMEDOUT
) &&
2057 (cmd
->opcode
== MMC_SEND_TUNING_BLOCK
)) {
2058 state
= STATE_SENDING_DATA
;
2062 dw_mci_stop_dma(host
);
2063 send_stop_abort(host
, data
);
2064 state
= STATE_SENDING_STOP
;
2068 if (!cmd
->data
|| err
) {
2069 dw_mci_request_end(host
, mrq
);
2073 prev_state
= state
= STATE_SENDING_DATA
;
2076 case STATE_SENDING_DATA
:
2078 * We could get a data error and never a transfer
2079 * complete so we'd better check for it here.
2081 * Note that we don't really care if we also got a
2082 * transfer complete; stopping the DMA and sending an
2085 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2086 &host
->pending_events
)) {
2087 dw_mci_stop_dma(host
);
2088 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2090 send_stop_abort(host
, data
);
2091 state
= STATE_DATA_ERROR
;
2095 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2096 &host
->pending_events
)) {
2098 * If all data-related interrupts don't come
2099 * within the given time in reading data state.
2101 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2102 dw_mci_set_drto(host
);
2106 set_bit(EVENT_XFER_COMPLETE
, &host
->completed_events
);
2109 * Handle an EVENT_DATA_ERROR that might have shown up
2110 * before the transfer completed. This might not have
2111 * been caught by the check above because the interrupt
2112 * could have gone off between the previous check and
2113 * the check for transfer complete.
2115 * Technically this ought not be needed assuming we
2116 * get a DATA_COMPLETE eventually (we'll notice the
2117 * error and end the request), but it shouldn't hurt.
2119 * This has the advantage of sending the stop command.
2121 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2122 &host
->pending_events
)) {
2123 dw_mci_stop_dma(host
);
2124 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2126 send_stop_abort(host
, data
);
2127 state
= STATE_DATA_ERROR
;
2130 prev_state
= state
= STATE_DATA_BUSY
;
2134 case STATE_DATA_BUSY
:
2135 if (!dw_mci_clear_pending_data_complete(host
)) {
2137 * If data error interrupt comes but data over
2138 * interrupt doesn't come within the given time.
2139 * in reading data state.
2141 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2142 dw_mci_set_drto(host
);
2147 set_bit(EVENT_DATA_COMPLETE
, &host
->completed_events
);
2148 err
= dw_mci_data_complete(host
, data
);
2151 if (!data
->stop
|| mrq
->sbc
) {
2152 if (mrq
->sbc
&& data
->stop
)
2153 data
->stop
->error
= 0;
2154 dw_mci_request_end(host
, mrq
);
2158 /* stop command for open-ended transfer*/
2160 send_stop_abort(host
, data
);
2163 * If we don't have a command complete now we'll
2164 * never get one since we just reset everything;
2165 * better end the request.
2167 * If we do have a command complete we'll fall
2168 * through to the SENDING_STOP command and
2169 * everything will be peachy keen.
2171 if (!test_bit(EVENT_CMD_COMPLETE
,
2172 &host
->pending_events
)) {
2174 dw_mci_request_end(host
, mrq
);
2180 * If err has non-zero,
2181 * stop-abort command has been already issued.
2183 prev_state
= state
= STATE_SENDING_STOP
;
2187 case STATE_SENDING_STOP
:
2188 if (!dw_mci_clear_pending_cmd_complete(host
))
2191 /* CMD error in data command */
2192 if (mrq
->cmd
->error
&& mrq
->data
)
2198 if (!mrq
->sbc
&& mrq
->stop
)
2199 dw_mci_command_complete(host
, mrq
->stop
);
2201 host
->cmd_status
= 0;
2203 dw_mci_request_end(host
, mrq
);
2206 case STATE_DATA_ERROR
:
2207 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2208 &host
->pending_events
))
2211 state
= STATE_DATA_BUSY
;
2214 } while (state
!= prev_state
);
2216 host
->state
= state
;
2218 spin_unlock(&host
->lock
);
2222 /* push final bytes to part_buf, only use during push */
2223 static void dw_mci_set_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2225 memcpy((void *)&host
->part_buf
, buf
, cnt
);
2226 host
->part_buf_count
= cnt
;
2229 /* append bytes to part_buf, only use during push */
2230 static int dw_mci_push_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2232 cnt
= min(cnt
, (1 << host
->data_shift
) - host
->part_buf_count
);
2233 memcpy((void *)&host
->part_buf
+ host
->part_buf_count
, buf
, cnt
);
2234 host
->part_buf_count
+= cnt
;
2238 /* pull first bytes from part_buf, only use during pull */
2239 static int dw_mci_pull_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2241 cnt
= min_t(int, cnt
, host
->part_buf_count
);
2243 memcpy(buf
, (void *)&host
->part_buf
+ host
->part_buf_start
,
2245 host
->part_buf_count
-= cnt
;
2246 host
->part_buf_start
+= cnt
;
2251 /* pull final bytes from the part_buf, assuming it's just been filled */
2252 static void dw_mci_pull_final_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2254 memcpy(buf
, &host
->part_buf
, cnt
);
2255 host
->part_buf_start
= cnt
;
2256 host
->part_buf_count
= (1 << host
->data_shift
) - cnt
;
2259 static void dw_mci_push_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2261 struct mmc_data
*data
= host
->data
;
2264 /* try and push anything in the part_buf */
2265 if (unlikely(host
->part_buf_count
)) {
2266 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2270 if (host
->part_buf_count
== 2) {
2271 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2272 host
->part_buf_count
= 0;
2275 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2276 if (unlikely((unsigned long)buf
& 0x1)) {
2278 u16 aligned_buf
[64];
2279 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2280 int items
= len
>> 1;
2282 /* memcpy from input buffer into aligned buffer */
2283 memcpy(aligned_buf
, buf
, len
);
2286 /* push data from aligned buffer into fifo */
2287 for (i
= 0; i
< items
; ++i
)
2288 mci_fifo_writew(host
->fifo_reg
, aligned_buf
[i
]);
2295 for (; cnt
>= 2; cnt
-= 2)
2296 mci_fifo_writew(host
->fifo_reg
, *pdata
++);
2299 /* put anything remaining in the part_buf */
2301 dw_mci_set_part_bytes(host
, buf
, cnt
);
2302 /* Push data if we have reached the expected data length */
2303 if ((data
->bytes_xfered
+ init_cnt
) ==
2304 (data
->blksz
* data
->blocks
))
2305 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2309 static void dw_mci_pull_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2311 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2312 if (unlikely((unsigned long)buf
& 0x1)) {
2314 /* pull data from fifo into aligned buffer */
2315 u16 aligned_buf
[64];
2316 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2317 int items
= len
>> 1;
2320 for (i
= 0; i
< items
; ++i
)
2321 aligned_buf
[i
] = mci_fifo_readw(host
->fifo_reg
);
2322 /* memcpy from aligned buffer into output buffer */
2323 memcpy(buf
, aligned_buf
, len
);
2332 for (; cnt
>= 2; cnt
-= 2)
2333 *pdata
++ = mci_fifo_readw(host
->fifo_reg
);
2337 host
->part_buf16
= mci_fifo_readw(host
->fifo_reg
);
2338 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2342 static void dw_mci_push_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2344 struct mmc_data
*data
= host
->data
;
2347 /* try and push anything in the part_buf */
2348 if (unlikely(host
->part_buf_count
)) {
2349 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2353 if (host
->part_buf_count
== 4) {
2354 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2355 host
->part_buf_count
= 0;
2358 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2359 if (unlikely((unsigned long)buf
& 0x3)) {
2361 u32 aligned_buf
[32];
2362 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2363 int items
= len
>> 2;
2365 /* memcpy from input buffer into aligned buffer */
2366 memcpy(aligned_buf
, buf
, len
);
2369 /* push data from aligned buffer into fifo */
2370 for (i
= 0; i
< items
; ++i
)
2371 mci_fifo_writel(host
->fifo_reg
, aligned_buf
[i
]);
2378 for (; cnt
>= 4; cnt
-= 4)
2379 mci_fifo_writel(host
->fifo_reg
, *pdata
++);
2382 /* put anything remaining in the part_buf */
2384 dw_mci_set_part_bytes(host
, buf
, cnt
);
2385 /* Push data if we have reached the expected data length */
2386 if ((data
->bytes_xfered
+ init_cnt
) ==
2387 (data
->blksz
* data
->blocks
))
2388 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2392 static void dw_mci_pull_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2394 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2395 if (unlikely((unsigned long)buf
& 0x3)) {
2397 /* pull data from fifo into aligned buffer */
2398 u32 aligned_buf
[32];
2399 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2400 int items
= len
>> 2;
2403 for (i
= 0; i
< items
; ++i
)
2404 aligned_buf
[i
] = mci_fifo_readl(host
->fifo_reg
);
2405 /* memcpy from aligned buffer into output buffer */
2406 memcpy(buf
, aligned_buf
, len
);
2415 for (; cnt
>= 4; cnt
-= 4)
2416 *pdata
++ = mci_fifo_readl(host
->fifo_reg
);
2420 host
->part_buf32
= mci_fifo_readl(host
->fifo_reg
);
2421 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2425 static void dw_mci_push_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2427 struct mmc_data
*data
= host
->data
;
2430 /* try and push anything in the part_buf */
2431 if (unlikely(host
->part_buf_count
)) {
2432 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2437 if (host
->part_buf_count
== 8) {
2438 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2439 host
->part_buf_count
= 0;
2442 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2443 if (unlikely((unsigned long)buf
& 0x7)) {
2445 u64 aligned_buf
[16];
2446 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2447 int items
= len
>> 3;
2449 /* memcpy from input buffer into aligned buffer */
2450 memcpy(aligned_buf
, buf
, len
);
2453 /* push data from aligned buffer into fifo */
2454 for (i
= 0; i
< items
; ++i
)
2455 mci_fifo_writeq(host
->fifo_reg
, aligned_buf
[i
]);
2462 for (; cnt
>= 8; cnt
-= 8)
2463 mci_fifo_writeq(host
->fifo_reg
, *pdata
++);
2466 /* put anything remaining in the part_buf */
2468 dw_mci_set_part_bytes(host
, buf
, cnt
);
2469 /* Push data if we have reached the expected data length */
2470 if ((data
->bytes_xfered
+ init_cnt
) ==
2471 (data
->blksz
* data
->blocks
))
2472 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2476 static void dw_mci_pull_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2478 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2479 if (unlikely((unsigned long)buf
& 0x7)) {
2481 /* pull data from fifo into aligned buffer */
2482 u64 aligned_buf
[16];
2483 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2484 int items
= len
>> 3;
2487 for (i
= 0; i
< items
; ++i
)
2488 aligned_buf
[i
] = mci_fifo_readq(host
->fifo_reg
);
2490 /* memcpy from aligned buffer into output buffer */
2491 memcpy(buf
, aligned_buf
, len
);
2500 for (; cnt
>= 8; cnt
-= 8)
2501 *pdata
++ = mci_fifo_readq(host
->fifo_reg
);
2505 host
->part_buf
= mci_fifo_readq(host
->fifo_reg
);
2506 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2510 static void dw_mci_pull_data(struct dw_mci
*host
, void *buf
, int cnt
)
2514 /* get remaining partial bytes */
2515 len
= dw_mci_pull_part_bytes(host
, buf
, cnt
);
2516 if (unlikely(len
== cnt
))
2521 /* get the rest of the data */
2522 host
->pull_data(host
, buf
, cnt
);
2525 static void dw_mci_read_data_pio(struct dw_mci
*host
, bool dto
)
2527 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2529 unsigned int offset
;
2530 struct mmc_data
*data
= host
->data
;
2531 int shift
= host
->data_shift
;
2534 unsigned int remain
, fcnt
;
2537 if (!sg_miter_next(sg_miter
))
2540 host
->sg
= sg_miter
->piter
.sg
;
2541 buf
= sg_miter
->addr
;
2542 remain
= sg_miter
->length
;
2546 fcnt
= (SDMMC_GET_FCNT(mci_readl(host
, STATUS
))
2547 << shift
) + host
->part_buf_count
;
2548 len
= min(remain
, fcnt
);
2551 dw_mci_pull_data(host
, (void *)(buf
+ offset
), len
);
2552 data
->bytes_xfered
+= len
;
2557 sg_miter
->consumed
= offset
;
2558 status
= mci_readl(host
, MINTSTS
);
2559 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2560 /* if the RXDR is ready read again */
2561 } while ((status
& SDMMC_INT_RXDR
) ||
2562 (dto
&& SDMMC_GET_FCNT(mci_readl(host
, STATUS
))));
2565 if (!sg_miter_next(sg_miter
))
2567 sg_miter
->consumed
= 0;
2569 sg_miter_stop(sg_miter
);
2573 sg_miter_stop(sg_miter
);
2575 smp_wmb(); /* drain writebuffer */
2576 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2579 static void dw_mci_write_data_pio(struct dw_mci
*host
)
2581 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2583 unsigned int offset
;
2584 struct mmc_data
*data
= host
->data
;
2585 int shift
= host
->data_shift
;
2588 unsigned int fifo_depth
= host
->fifo_depth
;
2589 unsigned int remain
, fcnt
;
2592 if (!sg_miter_next(sg_miter
))
2595 host
->sg
= sg_miter
->piter
.sg
;
2596 buf
= sg_miter
->addr
;
2597 remain
= sg_miter
->length
;
2601 fcnt
= ((fifo_depth
-
2602 SDMMC_GET_FCNT(mci_readl(host
, STATUS
)))
2603 << shift
) - host
->part_buf_count
;
2604 len
= min(remain
, fcnt
);
2607 host
->push_data(host
, (void *)(buf
+ offset
), len
);
2608 data
->bytes_xfered
+= len
;
2613 sg_miter
->consumed
= offset
;
2614 status
= mci_readl(host
, MINTSTS
);
2615 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2616 } while (status
& SDMMC_INT_TXDR
); /* if TXDR write again */
2619 if (!sg_miter_next(sg_miter
))
2621 sg_miter
->consumed
= 0;
2623 sg_miter_stop(sg_miter
);
2627 sg_miter_stop(sg_miter
);
2629 smp_wmb(); /* drain writebuffer */
2630 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2633 static void dw_mci_cmd_interrupt(struct dw_mci
*host
, u32 status
)
2635 del_timer(&host
->cto_timer
);
2637 if (!host
->cmd_status
)
2638 host
->cmd_status
= status
;
2640 smp_wmb(); /* drain writebuffer */
2642 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2643 tasklet_schedule(&host
->tasklet
);
2646 static void dw_mci_handle_cd(struct dw_mci
*host
)
2648 struct dw_mci_slot
*slot
= host
->slot
;
2650 if (slot
->mmc
->ops
->card_event
)
2651 slot
->mmc
->ops
->card_event(slot
->mmc
);
2652 mmc_detect_change(slot
->mmc
,
2653 msecs_to_jiffies(host
->pdata
->detect_delay_ms
));
2656 static irqreturn_t
dw_mci_interrupt(int irq
, void *dev_id
)
2658 struct dw_mci
*host
= dev_id
;
2660 struct dw_mci_slot
*slot
= host
->slot
;
2661 unsigned long irqflags
;
2663 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
2666 /* Check volt switch first, since it can look like an error */
2667 if ((host
->state
== STATE_SENDING_CMD11
) &&
2668 (pending
& SDMMC_INT_VOLT_SWITCH
)) {
2669 mci_writel(host
, RINTSTS
, SDMMC_INT_VOLT_SWITCH
);
2670 pending
&= ~SDMMC_INT_VOLT_SWITCH
;
2673 * Hold the lock; we know cmd11_timer can't be kicked
2674 * off after the lock is released, so safe to delete.
2676 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2677 dw_mci_cmd_interrupt(host
, pending
);
2678 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2680 del_timer(&host
->cmd11_timer
);
2683 if (pending
& DW_MCI_CMD_ERROR_FLAGS
) {
2684 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2686 del_timer(&host
->cto_timer
);
2687 mci_writel(host
, RINTSTS
, DW_MCI_CMD_ERROR_FLAGS
);
2688 host
->cmd_status
= pending
;
2689 smp_wmb(); /* drain writebuffer */
2690 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2692 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2695 if (pending
& DW_MCI_DATA_ERROR_FLAGS
) {
2696 /* if there is an error report DATA_ERROR */
2697 mci_writel(host
, RINTSTS
, DW_MCI_DATA_ERROR_FLAGS
);
2698 host
->data_status
= pending
;
2699 smp_wmb(); /* drain writebuffer */
2700 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2701 tasklet_schedule(&host
->tasklet
);
2704 if (pending
& SDMMC_INT_DATA_OVER
) {
2705 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2707 del_timer(&host
->dto_timer
);
2709 mci_writel(host
, RINTSTS
, SDMMC_INT_DATA_OVER
);
2710 if (!host
->data_status
)
2711 host
->data_status
= pending
;
2712 smp_wmb(); /* drain writebuffer */
2713 if (host
->dir_status
== DW_MCI_RECV_STATUS
) {
2714 if (host
->sg
!= NULL
)
2715 dw_mci_read_data_pio(host
, true);
2717 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2718 tasklet_schedule(&host
->tasklet
);
2720 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2723 if (pending
& SDMMC_INT_RXDR
) {
2724 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2725 if (host
->dir_status
== DW_MCI_RECV_STATUS
&& host
->sg
)
2726 dw_mci_read_data_pio(host
, false);
2729 if (pending
& SDMMC_INT_TXDR
) {
2730 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2731 if (host
->dir_status
== DW_MCI_SEND_STATUS
&& host
->sg
)
2732 dw_mci_write_data_pio(host
);
2735 if (pending
& SDMMC_INT_CMD_DONE
) {
2736 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2738 mci_writel(host
, RINTSTS
, SDMMC_INT_CMD_DONE
);
2739 dw_mci_cmd_interrupt(host
, pending
);
2741 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2744 if (pending
& SDMMC_INT_CD
) {
2745 mci_writel(host
, RINTSTS
, SDMMC_INT_CD
);
2746 dw_mci_handle_cd(host
);
2749 if (pending
& SDMMC_INT_SDIO(slot
->sdio_id
)) {
2750 mci_writel(host
, RINTSTS
,
2751 SDMMC_INT_SDIO(slot
->sdio_id
));
2752 __dw_mci_enable_sdio_irq(slot
, 0);
2753 sdio_signal_irq(slot
->mmc
);
2758 if (host
->use_dma
!= TRANS_MODE_IDMAC
)
2761 /* Handle IDMA interrupts */
2762 if (host
->dma_64bit_address
== 1) {
2763 pending
= mci_readl(host
, IDSTS64
);
2764 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2765 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_TI
|
2766 SDMMC_IDMAC_INT_RI
);
2767 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_NI
);
2768 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2769 host
->dma_ops
->complete((void *)host
);
2772 pending
= mci_readl(host
, IDSTS
);
2773 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2774 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_TI
|
2775 SDMMC_IDMAC_INT_RI
);
2776 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_NI
);
2777 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2778 host
->dma_ops
->complete((void *)host
);
2785 static int dw_mci_init_slot_caps(struct dw_mci_slot
*slot
)
2787 struct dw_mci
*host
= slot
->host
;
2788 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2789 struct mmc_host
*mmc
= slot
->mmc
;
2792 if (host
->pdata
->caps
)
2793 mmc
->caps
= host
->pdata
->caps
;
2796 * Support MMC_CAP_ERASE by default.
2797 * It needs to use trim/discard/erase commands.
2799 mmc
->caps
|= MMC_CAP_ERASE
;
2801 if (host
->pdata
->pm_caps
)
2802 mmc
->pm_caps
= host
->pdata
->pm_caps
;
2804 if (host
->dev
->of_node
) {
2805 ctrl_id
= of_alias_get_id(host
->dev
->of_node
, "mshc");
2809 ctrl_id
= to_platform_device(host
->dev
)->id
;
2811 if (drv_data
&& drv_data
->caps
)
2812 mmc
->caps
|= drv_data
->caps
[ctrl_id
];
2814 if (host
->pdata
->caps2
)
2815 mmc
->caps2
= host
->pdata
->caps2
;
2817 /* Process SDIO IRQs through the sdio_irq_work. */
2818 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
)
2819 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
2824 static int dw_mci_init_slot(struct dw_mci
*host
)
2826 struct mmc_host
*mmc
;
2827 struct dw_mci_slot
*slot
;
2831 mmc
= mmc_alloc_host(sizeof(struct dw_mci_slot
), host
->dev
);
2835 slot
= mmc_priv(mmc
);
2837 slot
->sdio_id
= host
->sdio_id0
+ slot
->id
;
2842 mmc
->ops
= &dw_mci_ops
;
2843 if (device_property_read_u32_array(host
->dev
, "clock-freq-min-max",
2845 mmc
->f_min
= DW_MCI_FREQ_MIN
;
2846 mmc
->f_max
= DW_MCI_FREQ_MAX
;
2849 "'clock-freq-min-max' property was deprecated.\n");
2850 mmc
->f_min
= freq
[0];
2851 mmc
->f_max
= freq
[1];
2854 /*if there are external regulators, get them*/
2855 ret
= mmc_regulator_get_supply(mmc
);
2857 goto err_host_allocated
;
2859 if (!mmc
->ocr_avail
)
2860 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2862 ret
= mmc_of_parse(mmc
);
2864 goto err_host_allocated
;
2866 ret
= dw_mci_init_slot_caps(slot
);
2868 goto err_host_allocated
;
2870 /* Useful defaults if platform data is unset. */
2871 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2872 mmc
->max_segs
= host
->ring_size
;
2873 mmc
->max_blk_size
= 65535;
2874 mmc
->max_seg_size
= 0x1000;
2875 mmc
->max_req_size
= mmc
->max_seg_size
* host
->ring_size
;
2876 mmc
->max_blk_count
= mmc
->max_req_size
/ 512;
2877 } else if (host
->use_dma
== TRANS_MODE_EDMAC
) {
2879 mmc
->max_blk_size
= 65535;
2880 mmc
->max_blk_count
= 65535;
2882 mmc
->max_blk_size
* mmc
->max_blk_count
;
2883 mmc
->max_seg_size
= mmc
->max_req_size
;
2885 /* TRANS_MODE_PIO */
2887 mmc
->max_blk_size
= 65535; /* BLKSIZ is 16 bits */
2888 mmc
->max_blk_count
= 512;
2889 mmc
->max_req_size
= mmc
->max_blk_size
*
2891 mmc
->max_seg_size
= mmc
->max_req_size
;
2896 ret
= mmc_add_host(mmc
);
2898 goto err_host_allocated
;
2900 #if defined(CONFIG_DEBUG_FS)
2901 dw_mci_init_debugfs(slot
);
2911 static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot
)
2913 /* Debugfs stuff is cleaned up by mmc core */
2914 mmc_remove_host(slot
->mmc
);
2915 slot
->host
->slot
= NULL
;
2916 mmc_free_host(slot
->mmc
);
2919 static void dw_mci_init_dma(struct dw_mci
*host
)
2922 struct device
*dev
= host
->dev
;
2925 * Check tansfer mode from HCON[17:16]
2926 * Clear the ambiguous description of dw_mmc databook:
2927 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2928 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2929 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2930 * 2b'11: Non DW DMA Interface -> pio only
2931 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2932 * simpler request/acknowledge handshake mechanism and both of them
2933 * are regarded as external dma master for dw_mmc.
2935 host
->use_dma
= SDMMC_GET_TRANS_MODE(mci_readl(host
, HCON
));
2936 if (host
->use_dma
== DMA_INTERFACE_IDMA
) {
2937 host
->use_dma
= TRANS_MODE_IDMAC
;
2938 } else if (host
->use_dma
== DMA_INTERFACE_DWDMA
||
2939 host
->use_dma
== DMA_INTERFACE_GDMA
) {
2940 host
->use_dma
= TRANS_MODE_EDMAC
;
2945 /* Determine which DMA interface to use */
2946 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2948 * Check ADDR_CONFIG bit in HCON to find
2949 * IDMAC address bus width
2951 addr_config
= SDMMC_GET_ADDR_CONFIG(mci_readl(host
, HCON
));
2953 if (addr_config
== 1) {
2954 /* host supports IDMAC in 64-bit address mode */
2955 host
->dma_64bit_address
= 1;
2957 "IDMAC supports 64-bit address mode.\n");
2958 if (!dma_set_mask(host
->dev
, DMA_BIT_MASK(64)))
2959 dma_set_coherent_mask(host
->dev
,
2962 /* host supports IDMAC in 32-bit address mode */
2963 host
->dma_64bit_address
= 0;
2965 "IDMAC supports 32-bit address mode.\n");
2968 /* Alloc memory for sg translation */
2969 host
->sg_cpu
= dmam_alloc_coherent(host
->dev
,
2971 &host
->sg_dma
, GFP_KERNEL
);
2972 if (!host
->sg_cpu
) {
2974 "%s: could not alloc DMA memory\n",
2979 host
->dma_ops
= &dw_mci_idmac_ops
;
2980 dev_info(host
->dev
, "Using internal DMA controller.\n");
2982 /* TRANS_MODE_EDMAC: check dma bindings again */
2983 if ((device_property_read_string_array(dev
, "dma-names",
2985 !device_property_present(dev
, "dmas")) {
2988 host
->dma_ops
= &dw_mci_edmac_ops
;
2989 dev_info(host
->dev
, "Using external DMA controller.\n");
2992 if (host
->dma_ops
->init
&& host
->dma_ops
->start
&&
2993 host
->dma_ops
->stop
&& host
->dma_ops
->cleanup
) {
2994 if (host
->dma_ops
->init(host
)) {
2995 dev_err(host
->dev
, "%s: Unable to initialize DMA Controller.\n",
3000 dev_err(host
->dev
, "DMA initialization not found.\n");
3007 dev_info(host
->dev
, "Using PIO mode.\n");
3008 host
->use_dma
= TRANS_MODE_PIO
;
3011 static void dw_mci_cmd11_timer(struct timer_list
*t
)
3013 struct dw_mci
*host
= from_timer(host
, t
, cmd11_timer
);
3015 if (host
->state
!= STATE_SENDING_CMD11
) {
3016 dev_warn(host
->dev
, "Unexpected CMD11 timeout\n");
3020 host
->cmd_status
= SDMMC_INT_RTO
;
3021 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
3022 tasklet_schedule(&host
->tasklet
);
3025 static void dw_mci_cto_timer(struct timer_list
*t
)
3027 struct dw_mci
*host
= from_timer(host
, t
, cto_timer
);
3028 unsigned long irqflags
;
3031 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3034 * If somehow we have very bad interrupt latency it's remotely possible
3035 * that the timer could fire while the interrupt is still pending or
3036 * while the interrupt is midway through running. Let's be paranoid
3037 * and detect those two cases. Note that this is paranoia is somewhat
3038 * justified because in this function we don't actually cancel the
3039 * pending command in the controller--we just assume it will never come.
3041 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
3042 if (pending
& (DW_MCI_CMD_ERROR_FLAGS
| SDMMC_INT_CMD_DONE
)) {
3043 /* The interrupt should fire; no need to act but we can warn */
3044 dev_warn(host
->dev
, "Unexpected interrupt latency\n");
3047 if (test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
)) {
3048 /* Presumably interrupt handler couldn't delete the timer */
3049 dev_warn(host
->dev
, "CTO timeout when already completed\n");
3054 * Continued paranoia to make sure we're in the state we expect.
3055 * This paranoia isn't really justified but it seems good to be safe.
3057 switch (host
->state
) {
3058 case STATE_SENDING_CMD11
:
3059 case STATE_SENDING_CMD
:
3060 case STATE_SENDING_STOP
:
3062 * If CMD_DONE interrupt does NOT come in sending command
3063 * state, we should notify the driver to terminate current
3064 * transfer and report a command timeout to the core.
3066 host
->cmd_status
= SDMMC_INT_RTO
;
3067 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
3068 tasklet_schedule(&host
->tasklet
);
3071 dev_warn(host
->dev
, "Unexpected command timeout, state %d\n",
3077 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3080 static void dw_mci_dto_timer(struct timer_list
*t
)
3082 struct dw_mci
*host
= from_timer(host
, t
, dto_timer
);
3083 unsigned long irqflags
;
3086 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3089 * The DTO timer is much longer than the CTO timer, so it's even less
3090 * likely that we'll these cases, but it pays to be paranoid.
3092 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
3093 if (pending
& SDMMC_INT_DATA_OVER
) {
3094 /* The interrupt should fire; no need to act but we can warn */
3095 dev_warn(host
->dev
, "Unexpected data interrupt latency\n");
3098 if (test_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
)) {
3099 /* Presumably interrupt handler couldn't delete the timer */
3100 dev_warn(host
->dev
, "DTO timeout when already completed\n");
3105 * Continued paranoia to make sure we're in the state we expect.
3106 * This paranoia isn't really justified but it seems good to be safe.
3108 switch (host
->state
) {
3109 case STATE_SENDING_DATA
:
3110 case STATE_DATA_BUSY
:
3112 * If DTO interrupt does NOT come in sending data state,
3113 * we should notify the driver to terminate current transfer
3114 * and report a data timeout to the core.
3116 host
->data_status
= SDMMC_INT_DRTO
;
3117 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
3118 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
3119 tasklet_schedule(&host
->tasklet
);
3122 dev_warn(host
->dev
, "Unexpected data timeout, state %d\n",
3128 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3132 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
3134 struct dw_mci_board
*pdata
;
3135 struct device
*dev
= host
->dev
;
3136 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
3138 u32 clock_frequency
;
3140 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
3142 return ERR_PTR(-ENOMEM
);
3144 /* find reset controller when exist */
3145 pdata
->rstc
= devm_reset_control_get_optional_exclusive(dev
, "reset");
3146 if (IS_ERR(pdata
->rstc
)) {
3147 if (PTR_ERR(pdata
->rstc
) == -EPROBE_DEFER
)
3148 return ERR_PTR(-EPROBE_DEFER
);
3151 /* find out number of slots supported */
3152 if (!device_property_read_u32(dev
, "num-slots", &pdata
->num_slots
))
3153 dev_info(dev
, "'num-slots' was deprecated.\n");
3155 if (device_property_read_u32(dev
, "fifo-depth", &pdata
->fifo_depth
))
3157 "fifo-depth property not found, using value of FIFOTH register as default\n");
3159 device_property_read_u32(dev
, "card-detect-delay",
3160 &pdata
->detect_delay_ms
);
3162 device_property_read_u32(dev
, "data-addr", &host
->data_addr_override
);
3164 if (device_property_present(dev
, "fifo-watermark-aligned"))
3165 host
->wm_aligned
= true;
3167 if (!device_property_read_u32(dev
, "clock-frequency", &clock_frequency
))
3168 pdata
->bus_hz
= clock_frequency
;
3170 if (drv_data
&& drv_data
->parse_dt
) {
3171 ret
= drv_data
->parse_dt(host
);
3173 return ERR_PTR(ret
);
3179 #else /* CONFIG_OF */
3180 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
3182 return ERR_PTR(-EINVAL
);
3184 #endif /* CONFIG_OF */
3186 static void dw_mci_enable_cd(struct dw_mci
*host
)
3188 unsigned long irqflags
;
3192 * No need for CD if all slots have a non-error GPIO
3193 * as well as broken card detection is found.
3195 if (host
->slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
)
3198 if (mmc_gpio_get_cd(host
->slot
->mmc
) < 0) {
3199 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3200 temp
= mci_readl(host
, INTMASK
);
3201 temp
|= SDMMC_INT_CD
;
3202 mci_writel(host
, INTMASK
, temp
);
3203 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3207 int dw_mci_probe(struct dw_mci
*host
)
3209 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
3210 int width
, i
, ret
= 0;
3214 host
->pdata
= dw_mci_parse_dt(host
);
3215 if (PTR_ERR(host
->pdata
) == -EPROBE_DEFER
) {
3216 return -EPROBE_DEFER
;
3217 } else if (IS_ERR(host
->pdata
)) {
3218 dev_err(host
->dev
, "platform data not available\n");
3223 host
->biu_clk
= devm_clk_get(host
->dev
, "biu");
3224 if (IS_ERR(host
->biu_clk
)) {
3225 dev_dbg(host
->dev
, "biu clock not available\n");
3227 ret
= clk_prepare_enable(host
->biu_clk
);
3229 dev_err(host
->dev
, "failed to enable biu clock\n");
3234 host
->ciu_clk
= devm_clk_get(host
->dev
, "ciu");
3235 if (IS_ERR(host
->ciu_clk
)) {
3236 dev_dbg(host
->dev
, "ciu clock not available\n");
3237 host
->bus_hz
= host
->pdata
->bus_hz
;
3239 ret
= clk_prepare_enable(host
->ciu_clk
);
3241 dev_err(host
->dev
, "failed to enable ciu clock\n");
3245 if (host
->pdata
->bus_hz
) {
3246 ret
= clk_set_rate(host
->ciu_clk
, host
->pdata
->bus_hz
);
3249 "Unable to set bus rate to %uHz\n",
3250 host
->pdata
->bus_hz
);
3252 host
->bus_hz
= clk_get_rate(host
->ciu_clk
);
3255 if (!host
->bus_hz
) {
3257 "Platform data must supply bus speed\n");
3262 if (!IS_ERR(host
->pdata
->rstc
)) {
3263 reset_control_assert(host
->pdata
->rstc
);
3264 usleep_range(10, 50);
3265 reset_control_deassert(host
->pdata
->rstc
);
3268 if (drv_data
&& drv_data
->init
) {
3269 ret
= drv_data
->init(host
);
3272 "implementation specific init failed\n");
3277 timer_setup(&host
->cmd11_timer
, dw_mci_cmd11_timer
, 0);
3278 timer_setup(&host
->cto_timer
, dw_mci_cto_timer
, 0);
3279 timer_setup(&host
->dto_timer
, dw_mci_dto_timer
, 0);
3281 spin_lock_init(&host
->lock
);
3282 spin_lock_init(&host
->irq_lock
);
3283 INIT_LIST_HEAD(&host
->queue
);
3286 * Get the host data width - this assumes that HCON has been set with
3287 * the correct values.
3289 i
= SDMMC_GET_HDATA_WIDTH(mci_readl(host
, HCON
));
3291 host
->push_data
= dw_mci_push_data16
;
3292 host
->pull_data
= dw_mci_pull_data16
;
3294 host
->data_shift
= 1;
3295 } else if (i
== 2) {
3296 host
->push_data
= dw_mci_push_data64
;
3297 host
->pull_data
= dw_mci_pull_data64
;
3299 host
->data_shift
= 3;
3301 /* Check for a reserved value, and warn if it is */
3303 "HCON reports a reserved host data width!\n"
3304 "Defaulting to 32-bit access.\n");
3305 host
->push_data
= dw_mci_push_data32
;
3306 host
->pull_data
= dw_mci_pull_data32
;
3308 host
->data_shift
= 2;
3311 /* Reset all blocks */
3312 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3317 host
->dma_ops
= host
->pdata
->dma_ops
;
3318 dw_mci_init_dma(host
);
3320 /* Clear the interrupts for the host controller */
3321 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3322 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3324 /* Put in max timeout */
3325 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3328 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3329 * Tx Mark = fifo_size / 2 DMA Size = 8
3331 if (!host
->pdata
->fifo_depth
) {
3333 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3334 * have been overwritten by the bootloader, just like we're
3335 * about to do, so if you know the value for your hardware, you
3336 * should put it in the platform data.
3338 fifo_size
= mci_readl(host
, FIFOTH
);
3339 fifo_size
= 1 + ((fifo_size
>> 16) & 0xfff);
3341 fifo_size
= host
->pdata
->fifo_depth
;
3343 host
->fifo_depth
= fifo_size
;
3345 SDMMC_SET_FIFOTH(0x2, fifo_size
/ 2 - 1, fifo_size
/ 2);
3346 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3348 /* disable clock to CIU */
3349 mci_writel(host
, CLKENA
, 0);
3350 mci_writel(host
, CLKSRC
, 0);
3353 * In 2.40a spec, Data offset is changed.
3354 * Need to check the version-id and set data-offset for DATA register.
3356 host
->verid
= SDMMC_GET_VERID(mci_readl(host
, VERID
));
3357 dev_info(host
->dev
, "Version ID is %04x\n", host
->verid
);
3359 if (host
->data_addr_override
)
3360 host
->fifo_reg
= host
->regs
+ host
->data_addr_override
;
3361 else if (host
->verid
< DW_MMC_240A
)
3362 host
->fifo_reg
= host
->regs
+ DATA_OFFSET
;
3364 host
->fifo_reg
= host
->regs
+ DATA_240A_OFFSET
;
3366 tasklet_init(&host
->tasklet
, dw_mci_tasklet_func
, (unsigned long)host
);
3367 ret
= devm_request_irq(host
->dev
, host
->irq
, dw_mci_interrupt
,
3368 host
->irq_flags
, "dw-mci", host
);
3373 * Enable interrupts for command done, data over, data empty,
3374 * receive ready and error such as transmit, receive timeout, crc error
3376 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3377 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3378 DW_MCI_ERROR_FLAGS
);
3379 /* Enable mci interrupt */
3380 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3383 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3384 host
->irq
, width
, fifo_size
);
3386 /* We need at least one slot to succeed */
3387 ret
= dw_mci_init_slot(host
);
3389 dev_dbg(host
->dev
, "slot %d init failed\n", i
);
3393 /* Now that slots are all setup, we can enable card detect */
3394 dw_mci_enable_cd(host
);
3399 if (host
->use_dma
&& host
->dma_ops
->exit
)
3400 host
->dma_ops
->exit(host
);
3402 if (!IS_ERR(host
->pdata
->rstc
))
3403 reset_control_assert(host
->pdata
->rstc
);
3406 clk_disable_unprepare(host
->ciu_clk
);
3409 clk_disable_unprepare(host
->biu_clk
);
3413 EXPORT_SYMBOL(dw_mci_probe
);
3415 void dw_mci_remove(struct dw_mci
*host
)
3417 dev_dbg(host
->dev
, "remove slot\n");
3419 dw_mci_cleanup_slot(host
->slot
);
3421 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3422 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3424 /* disable clock to CIU */
3425 mci_writel(host
, CLKENA
, 0);
3426 mci_writel(host
, CLKSRC
, 0);
3428 if (host
->use_dma
&& host
->dma_ops
->exit
)
3429 host
->dma_ops
->exit(host
);
3431 if (!IS_ERR(host
->pdata
->rstc
))
3432 reset_control_assert(host
->pdata
->rstc
);
3434 clk_disable_unprepare(host
->ciu_clk
);
3435 clk_disable_unprepare(host
->biu_clk
);
3437 EXPORT_SYMBOL(dw_mci_remove
);
3442 int dw_mci_runtime_suspend(struct device
*dev
)
3444 struct dw_mci
*host
= dev_get_drvdata(dev
);
3446 if (host
->use_dma
&& host
->dma_ops
->exit
)
3447 host
->dma_ops
->exit(host
);
3449 clk_disable_unprepare(host
->ciu_clk
);
3452 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3453 !mmc_card_is_removable(host
->slot
->mmc
)))
3454 clk_disable_unprepare(host
->biu_clk
);
3458 EXPORT_SYMBOL(dw_mci_runtime_suspend
);
3460 int dw_mci_runtime_resume(struct device
*dev
)
3463 struct dw_mci
*host
= dev_get_drvdata(dev
);
3466 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3467 !mmc_card_is_removable(host
->slot
->mmc
))) {
3468 ret
= clk_prepare_enable(host
->biu_clk
);
3473 ret
= clk_prepare_enable(host
->ciu_clk
);
3477 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3478 clk_disable_unprepare(host
->ciu_clk
);
3483 if (host
->use_dma
&& host
->dma_ops
->init
)
3484 host
->dma_ops
->init(host
);
3487 * Restore the initial value at FIFOTH register
3488 * And Invalidate the prev_blksz with zero
3490 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3491 host
->prev_blksz
= 0;
3493 /* Put in max timeout */
3494 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3496 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3497 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3498 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3499 DW_MCI_ERROR_FLAGS
);
3500 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3503 if (host
->slot
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)
3504 dw_mci_set_ios(host
->slot
->mmc
, &host
->slot
->mmc
->ios
);
3506 /* Force setup bus to guarantee available clock output */
3507 dw_mci_setup_bus(host
->slot
, true);
3509 /* Now that slots are all setup, we can enable card detect */
3510 dw_mci_enable_cd(host
);
3516 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3517 !mmc_card_is_removable(host
->slot
->mmc
)))
3518 clk_disable_unprepare(host
->biu_clk
);
3522 EXPORT_SYMBOL(dw_mci_runtime_resume
);
3523 #endif /* CONFIG_PM */
3525 static int __init
dw_mci_init(void)
3527 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3531 static void __exit
dw_mci_exit(void)
3535 module_init(dw_mci_init
);
3536 module_exit(dw_mci_exit
);
3538 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3539 MODULE_AUTHOR("NXP Semiconductor VietNam");
3540 MODULE_AUTHOR("Imagination Technologies Ltd");
3541 MODULE_LICENSE("GPL v2");