]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/mmc/host/dw_mmc.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: dw_mmc: fix card threshold control configuration
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
56
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ PAGE_SIZE
66
67 struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89 __le32 des0; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
97
98 __le32 des1; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102 __le32 des2; /* buffer 1 physical address */
103
104 __le32 des3; /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149 }
150
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
152 {
153 return single_open(file, dw_mci_req_show, inode->i_private);
154 }
155
156 static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162 };
163
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
165 {
166 struct dw_mci *host = s->private;
167
168 pm_runtime_get_sync(host->dev);
169
170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
176
177 pm_runtime_put_autosuspend(host->dev);
178
179 return 0;
180 }
181
182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
183 {
184 return single_open(file, dw_mci_regs_show, inode->i_private);
185 }
186
187 static const struct file_operations dw_mci_regs_fops = {
188 .owner = THIS_MODULE,
189 .open = dw_mci_regs_open,
190 .read = seq_read,
191 .llseek = seq_lseek,
192 .release = single_release,
193 };
194
195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
196 {
197 struct mmc_host *mmc = slot->mmc;
198 struct dw_mci *host = slot->host;
199 struct dentry *root;
200 struct dentry *node;
201
202 root = mmc->debugfs_root;
203 if (!root)
204 return;
205
206 node = debugfs_create_file("regs", S_IRUSR, root, host,
207 &dw_mci_regs_fops);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_file("req", S_IRUSR, root, slot,
212 &dw_mci_req_fops);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
217 if (!node)
218 goto err;
219
220 node = debugfs_create_x32("pending_events", S_IRUSR, root,
221 (u32 *)&host->pending_events);
222 if (!node)
223 goto err;
224
225 node = debugfs_create_x32("completed_events", S_IRUSR, root,
226 (u32 *)&host->completed_events);
227 if (!node)
228 goto err;
229
230 return;
231
232 err:
233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
234 }
235 #endif /* defined(CONFIG_DEBUG_FS) */
236
237 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
238 {
239 u32 ctrl;
240
241 ctrl = mci_readl(host, CTRL);
242 ctrl |= reset;
243 mci_writel(host, CTRL, ctrl);
244
245 /* wait till resets clear */
246 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
247 !(ctrl & reset),
248 1, 500 * USEC_PER_MSEC)) {
249 dev_err(host->dev,
250 "Timeout resetting block (ctrl reset %#x)\n",
251 ctrl & reset);
252 return false;
253 }
254
255 return true;
256 }
257
258 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
259 {
260 u32 status;
261
262 /*
263 * Databook says that before issuing a new data transfer command
264 * we need to check to see if the card is busy. Data transfer commands
265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
266 *
267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
268 * expected.
269 */
270 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
271 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
272 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
273 status,
274 !(status & SDMMC_STATUS_BUSY),
275 10, 500 * USEC_PER_MSEC))
276 dev_err(host->dev, "Busy; trying anyway\n");
277 }
278 }
279
280 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
281 {
282 struct dw_mci *host = slot->host;
283 unsigned int cmd_status = 0;
284
285 mci_writel(host, CMDARG, arg);
286 wmb(); /* drain writebuffer */
287 dw_mci_wait_while_busy(host, cmd);
288 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
289
290 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
291 !(cmd_status & SDMMC_CMD_START),
292 1, 500 * USEC_PER_MSEC))
293 dev_err(&slot->mmc->class_dev,
294 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
295 cmd, arg, cmd_status);
296 }
297
298 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
299 {
300 struct dw_mci_slot *slot = mmc_priv(mmc);
301 struct dw_mci *host = slot->host;
302 u32 cmdr;
303
304 cmd->error = -EINPROGRESS;
305 cmdr = cmd->opcode;
306
307 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
308 cmd->opcode == MMC_GO_IDLE_STATE ||
309 cmd->opcode == MMC_GO_INACTIVE_STATE ||
310 (cmd->opcode == SD_IO_RW_DIRECT &&
311 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
312 cmdr |= SDMMC_CMD_STOP;
313 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
314 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
315
316 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
317 u32 clk_en_a;
318
319 /* Special bit makes CMD11 not die */
320 cmdr |= SDMMC_CMD_VOLT_SWITCH;
321
322 /* Change state to continue to handle CMD11 weirdness */
323 WARN_ON(slot->host->state != STATE_SENDING_CMD);
324 slot->host->state = STATE_SENDING_CMD11;
325
326 /*
327 * We need to disable low power mode (automatic clock stop)
328 * while doing voltage switch so we don't confuse the card,
329 * since stopping the clock is a specific part of the UHS
330 * voltage change dance.
331 *
332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
333 * unconditionally turned back on in dw_mci_setup_bus() if it's
334 * ever called with a non-zero clock. That shouldn't happen
335 * until the voltage change is all done.
336 */
337 clk_en_a = mci_readl(host, CLKENA);
338 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
339 mci_writel(host, CLKENA, clk_en_a);
340 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
341 SDMMC_CMD_PRV_DAT_WAIT, 0);
342 }
343
344 if (cmd->flags & MMC_RSP_PRESENT) {
345 /* We expect a response, so set this bit */
346 cmdr |= SDMMC_CMD_RESP_EXP;
347 if (cmd->flags & MMC_RSP_136)
348 cmdr |= SDMMC_CMD_RESP_LONG;
349 }
350
351 if (cmd->flags & MMC_RSP_CRC)
352 cmdr |= SDMMC_CMD_RESP_CRC;
353
354 if (cmd->data) {
355 cmdr |= SDMMC_CMD_DAT_EXP;
356 if (cmd->data->flags & MMC_DATA_WRITE)
357 cmdr |= SDMMC_CMD_DAT_WR;
358 }
359
360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
361 cmdr |= SDMMC_CMD_USE_HOLD_REG;
362
363 return cmdr;
364 }
365
366 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
367 {
368 struct mmc_command *stop;
369 u32 cmdr;
370
371 if (!cmd->data)
372 return 0;
373
374 stop = &host->stop_abort;
375 cmdr = cmd->opcode;
376 memset(stop, 0, sizeof(struct mmc_command));
377
378 if (cmdr == MMC_READ_SINGLE_BLOCK ||
379 cmdr == MMC_READ_MULTIPLE_BLOCK ||
380 cmdr == MMC_WRITE_BLOCK ||
381 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
382 cmdr == MMC_SEND_TUNING_BLOCK ||
383 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
384 stop->opcode = MMC_STOP_TRANSMISSION;
385 stop->arg = 0;
386 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
387 } else if (cmdr == SD_IO_RW_EXTENDED) {
388 stop->opcode = SD_IO_RW_DIRECT;
389 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
390 ((cmd->arg >> 28) & 0x7);
391 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
392 } else {
393 return 0;
394 }
395
396 cmdr = stop->opcode | SDMMC_CMD_STOP |
397 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
398
399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
400 cmdr |= SDMMC_CMD_USE_HOLD_REG;
401
402 return cmdr;
403 }
404
405 static inline void dw_mci_set_cto(struct dw_mci *host)
406 {
407 unsigned int cto_clks;
408 unsigned int cto_div;
409 unsigned int cto_ms;
410 unsigned long irqflags;
411
412 cto_clks = mci_readl(host, TMOUT) & 0xff;
413 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
414 if (cto_div == 0)
415 cto_div = 1;
416
417 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
418 host->bus_hz);
419
420 /* add a bit spare time */
421 cto_ms += 10;
422
423 /*
424 * The durations we're working with are fairly short so we have to be
425 * extra careful about synchronization here. Specifically in hardware a
426 * command timeout is _at most_ 5.1 ms, so that means we expect an
427 * interrupt (either command done or timeout) to come rather quickly
428 * after the mci_writel. ...but just in case we have a long interrupt
429 * latency let's add a bit of paranoia.
430 *
431 * In general we'll assume that at least an interrupt will be asserted
432 * in hardware by the time the cto_timer runs. ...and if it hasn't
433 * been asserted in hardware by that time then we'll assume it'll never
434 * come.
435 */
436 spin_lock_irqsave(&host->irq_lock, irqflags);
437 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
438 mod_timer(&host->cto_timer,
439 jiffies + msecs_to_jiffies(cto_ms) + 1);
440 spin_unlock_irqrestore(&host->irq_lock, irqflags);
441 }
442
443 static void dw_mci_start_command(struct dw_mci *host,
444 struct mmc_command *cmd, u32 cmd_flags)
445 {
446 host->cmd = cmd;
447 dev_vdbg(host->dev,
448 "start command: ARGR=0x%08x CMDR=0x%08x\n",
449 cmd->arg, cmd_flags);
450
451 mci_writel(host, CMDARG, cmd->arg);
452 wmb(); /* drain writebuffer */
453 dw_mci_wait_while_busy(host, cmd_flags);
454
455 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
456
457 /* response expected command only */
458 if (cmd_flags & SDMMC_CMD_RESP_EXP)
459 dw_mci_set_cto(host);
460 }
461
462 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
463 {
464 struct mmc_command *stop = &host->stop_abort;
465
466 dw_mci_start_command(host, stop, host->stop_cmdr);
467 }
468
469 /* DMA interface functions */
470 static void dw_mci_stop_dma(struct dw_mci *host)
471 {
472 if (host->using_dma) {
473 host->dma_ops->stop(host);
474 host->dma_ops->cleanup(host);
475 }
476
477 /* Data transfer was stopped by the interrupt handler */
478 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
479 }
480
481 static void dw_mci_dma_cleanup(struct dw_mci *host)
482 {
483 struct mmc_data *data = host->data;
484
485 if (data && data->host_cookie == COOKIE_MAPPED) {
486 dma_unmap_sg(host->dev,
487 data->sg,
488 data->sg_len,
489 mmc_get_dma_dir(data));
490 data->host_cookie = COOKIE_UNMAPPED;
491 }
492 }
493
494 static void dw_mci_idmac_reset(struct dw_mci *host)
495 {
496 u32 bmod = mci_readl(host, BMOD);
497 /* Software reset of DMA */
498 bmod |= SDMMC_IDMAC_SWRESET;
499 mci_writel(host, BMOD, bmod);
500 }
501
502 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
503 {
504 u32 temp;
505
506 /* Disable and reset the IDMAC interface */
507 temp = mci_readl(host, CTRL);
508 temp &= ~SDMMC_CTRL_USE_IDMAC;
509 temp |= SDMMC_CTRL_DMA_RESET;
510 mci_writel(host, CTRL, temp);
511
512 /* Stop the IDMAC running */
513 temp = mci_readl(host, BMOD);
514 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
515 temp |= SDMMC_IDMAC_SWRESET;
516 mci_writel(host, BMOD, temp);
517 }
518
519 static void dw_mci_dmac_complete_dma(void *arg)
520 {
521 struct dw_mci *host = arg;
522 struct mmc_data *data = host->data;
523
524 dev_vdbg(host->dev, "DMA complete\n");
525
526 if ((host->use_dma == TRANS_MODE_EDMAC) &&
527 data && (data->flags & MMC_DATA_READ))
528 /* Invalidate cache after read */
529 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
530 data->sg,
531 data->sg_len,
532 DMA_FROM_DEVICE);
533
534 host->dma_ops->cleanup(host);
535
536 /*
537 * If the card was removed, data will be NULL. No point in trying to
538 * send the stop command or waiting for NBUSY in this case.
539 */
540 if (data) {
541 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
542 tasklet_schedule(&host->tasklet);
543 }
544 }
545
546 static int dw_mci_idmac_init(struct dw_mci *host)
547 {
548 int i;
549
550 if (host->dma_64bit_address == 1) {
551 struct idmac_desc_64addr *p;
552 /* Number of descriptors in the ring buffer */
553 host->ring_size =
554 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
555
556 /* Forward link the descriptor list */
557 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
558 i++, p++) {
559 p->des6 = (host->sg_dma +
560 (sizeof(struct idmac_desc_64addr) *
561 (i + 1))) & 0xffffffff;
562
563 p->des7 = (u64)(host->sg_dma +
564 (sizeof(struct idmac_desc_64addr) *
565 (i + 1))) >> 32;
566 /* Initialize reserved and buffer size fields to "0" */
567 p->des0 = 0;
568 p->des1 = 0;
569 p->des2 = 0;
570 p->des3 = 0;
571 }
572
573 /* Set the last descriptor as the end-of-ring descriptor */
574 p->des6 = host->sg_dma & 0xffffffff;
575 p->des7 = (u64)host->sg_dma >> 32;
576 p->des0 = IDMAC_DES0_ER;
577
578 } else {
579 struct idmac_desc *p;
580 /* Number of descriptors in the ring buffer */
581 host->ring_size =
582 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
583
584 /* Forward link the descriptor list */
585 for (i = 0, p = host->sg_cpu;
586 i < host->ring_size - 1;
587 i++, p++) {
588 p->des3 = cpu_to_le32(host->sg_dma +
589 (sizeof(struct idmac_desc) * (i + 1)));
590 p->des0 = 0;
591 p->des1 = 0;
592 }
593
594 /* Set the last descriptor as the end-of-ring descriptor */
595 p->des3 = cpu_to_le32(host->sg_dma);
596 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
597 }
598
599 dw_mci_idmac_reset(host);
600
601 if (host->dma_64bit_address == 1) {
602 /* Mask out interrupts - get Tx & Rx complete only */
603 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
604 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
605 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
606
607 /* Set the descriptor base address */
608 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
609 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
610
611 } else {
612 /* Mask out interrupts - get Tx & Rx complete only */
613 mci_writel(host, IDSTS, IDMAC_INT_CLR);
614 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
615 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
616
617 /* Set the descriptor base address */
618 mci_writel(host, DBADDR, host->sg_dma);
619 }
620
621 return 0;
622 }
623
624 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
625 struct mmc_data *data,
626 unsigned int sg_len)
627 {
628 unsigned int desc_len;
629 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
630 u32 val;
631 int i;
632
633 desc_first = desc_last = desc = host->sg_cpu;
634
635 for (i = 0; i < sg_len; i++) {
636 unsigned int length = sg_dma_len(&data->sg[i]);
637
638 u64 mem_addr = sg_dma_address(&data->sg[i]);
639
640 for ( ; length ; desc++) {
641 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
642 length : DW_MCI_DESC_DATA_LENGTH;
643
644 length -= desc_len;
645
646 /*
647 * Wait for the former clear OWN bit operation
648 * of IDMAC to make sure that this descriptor
649 * isn't still owned by IDMAC as IDMAC's write
650 * ops and CPU's read ops are asynchronous.
651 */
652 if (readl_poll_timeout_atomic(&desc->des0, val,
653 !(val & IDMAC_DES0_OWN),
654 10, 100 * USEC_PER_MSEC))
655 goto err_own_bit;
656
657 /*
658 * Set the OWN bit and disable interrupts
659 * for this descriptor
660 */
661 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
662 IDMAC_DES0_CH;
663
664 /* Buffer length */
665 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
666
667 /* Physical address to DMA to/from */
668 desc->des4 = mem_addr & 0xffffffff;
669 desc->des5 = mem_addr >> 32;
670
671 /* Update physical address for the next desc */
672 mem_addr += desc_len;
673
674 /* Save pointer to the last descriptor */
675 desc_last = desc;
676 }
677 }
678
679 /* Set first descriptor */
680 desc_first->des0 |= IDMAC_DES0_FD;
681
682 /* Set last descriptor */
683 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
684 desc_last->des0 |= IDMAC_DES0_LD;
685
686 return 0;
687 err_own_bit:
688 /* restore the descriptor chain as it's polluted */
689 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
690 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
691 dw_mci_idmac_init(host);
692 return -EINVAL;
693 }
694
695
696 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
697 struct mmc_data *data,
698 unsigned int sg_len)
699 {
700 unsigned int desc_len;
701 struct idmac_desc *desc_first, *desc_last, *desc;
702 u32 val;
703 int i;
704
705 desc_first = desc_last = desc = host->sg_cpu;
706
707 for (i = 0; i < sg_len; i++) {
708 unsigned int length = sg_dma_len(&data->sg[i]);
709
710 u32 mem_addr = sg_dma_address(&data->sg[i]);
711
712 for ( ; length ; desc++) {
713 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
714 length : DW_MCI_DESC_DATA_LENGTH;
715
716 length -= desc_len;
717
718 /*
719 * Wait for the former clear OWN bit operation
720 * of IDMAC to make sure that this descriptor
721 * isn't still owned by IDMAC as IDMAC's write
722 * ops and CPU's read ops are asynchronous.
723 */
724 if (readl_poll_timeout_atomic(&desc->des0, val,
725 IDMAC_OWN_CLR64(val),
726 10,
727 100 * USEC_PER_MSEC))
728 goto err_own_bit;
729
730 /*
731 * Set the OWN bit and disable interrupts
732 * for this descriptor
733 */
734 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
735 IDMAC_DES0_DIC |
736 IDMAC_DES0_CH);
737
738 /* Buffer length */
739 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
740
741 /* Physical address to DMA to/from */
742 desc->des2 = cpu_to_le32(mem_addr);
743
744 /* Update physical address for the next desc */
745 mem_addr += desc_len;
746
747 /* Save pointer to the last descriptor */
748 desc_last = desc;
749 }
750 }
751
752 /* Set first descriptor */
753 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
754
755 /* Set last descriptor */
756 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
757 IDMAC_DES0_DIC));
758 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
759
760 return 0;
761 err_own_bit:
762 /* restore the descriptor chain as it's polluted */
763 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
764 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
765 dw_mci_idmac_init(host);
766 return -EINVAL;
767 }
768
769 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
770 {
771 u32 temp;
772 int ret;
773
774 if (host->dma_64bit_address == 1)
775 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
776 else
777 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
778
779 if (ret)
780 goto out;
781
782 /* drain writebuffer */
783 wmb();
784
785 /* Make sure to reset DMA in case we did PIO before this */
786 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
787 dw_mci_idmac_reset(host);
788
789 /* Select IDMAC interface */
790 temp = mci_readl(host, CTRL);
791 temp |= SDMMC_CTRL_USE_IDMAC;
792 mci_writel(host, CTRL, temp);
793
794 /* drain writebuffer */
795 wmb();
796
797 /* Enable the IDMAC */
798 temp = mci_readl(host, BMOD);
799 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
800 mci_writel(host, BMOD, temp);
801
802 /* Start it running */
803 mci_writel(host, PLDMND, 1);
804
805 out:
806 return ret;
807 }
808
809 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
810 .init = dw_mci_idmac_init,
811 .start = dw_mci_idmac_start_dma,
812 .stop = dw_mci_idmac_stop_dma,
813 .complete = dw_mci_dmac_complete_dma,
814 .cleanup = dw_mci_dma_cleanup,
815 };
816
817 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
818 {
819 dmaengine_terminate_async(host->dms->ch);
820 }
821
822 static int dw_mci_edmac_start_dma(struct dw_mci *host,
823 unsigned int sg_len)
824 {
825 struct dma_slave_config cfg;
826 struct dma_async_tx_descriptor *desc = NULL;
827 struct scatterlist *sgl = host->data->sg;
828 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
829 u32 sg_elems = host->data->sg_len;
830 u32 fifoth_val;
831 u32 fifo_offset = host->fifo_reg - host->regs;
832 int ret = 0;
833
834 /* Set external dma config: burst size, burst width */
835 cfg.dst_addr = host->phy_regs + fifo_offset;
836 cfg.src_addr = cfg.dst_addr;
837 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
838 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
839
840 /* Match burst msize with external dma config */
841 fifoth_val = mci_readl(host, FIFOTH);
842 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
843 cfg.src_maxburst = cfg.dst_maxburst;
844
845 if (host->data->flags & MMC_DATA_WRITE)
846 cfg.direction = DMA_MEM_TO_DEV;
847 else
848 cfg.direction = DMA_DEV_TO_MEM;
849
850 ret = dmaengine_slave_config(host->dms->ch, &cfg);
851 if (ret) {
852 dev_err(host->dev, "Failed to config edmac.\n");
853 return -EBUSY;
854 }
855
856 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
857 sg_len, cfg.direction,
858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
859 if (!desc) {
860 dev_err(host->dev, "Can't prepare slave sg.\n");
861 return -EBUSY;
862 }
863
864 /* Set dw_mci_dmac_complete_dma as callback */
865 desc->callback = dw_mci_dmac_complete_dma;
866 desc->callback_param = (void *)host;
867 dmaengine_submit(desc);
868
869 /* Flush cache before write */
870 if (host->data->flags & MMC_DATA_WRITE)
871 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
872 sg_elems, DMA_TO_DEVICE);
873
874 dma_async_issue_pending(host->dms->ch);
875
876 return 0;
877 }
878
879 static int dw_mci_edmac_init(struct dw_mci *host)
880 {
881 /* Request external dma channel */
882 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
883 if (!host->dms)
884 return -ENOMEM;
885
886 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
887 if (!host->dms->ch) {
888 dev_err(host->dev, "Failed to get external DMA channel.\n");
889 kfree(host->dms);
890 host->dms = NULL;
891 return -ENXIO;
892 }
893
894 return 0;
895 }
896
897 static void dw_mci_edmac_exit(struct dw_mci *host)
898 {
899 if (host->dms) {
900 if (host->dms->ch) {
901 dma_release_channel(host->dms->ch);
902 host->dms->ch = NULL;
903 }
904 kfree(host->dms);
905 host->dms = NULL;
906 }
907 }
908
909 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
910 .init = dw_mci_edmac_init,
911 .exit = dw_mci_edmac_exit,
912 .start = dw_mci_edmac_start_dma,
913 .stop = dw_mci_edmac_stop_dma,
914 .complete = dw_mci_dmac_complete_dma,
915 .cleanup = dw_mci_dma_cleanup,
916 };
917
918 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
919 struct mmc_data *data,
920 int cookie)
921 {
922 struct scatterlist *sg;
923 unsigned int i, sg_len;
924
925 if (data->host_cookie == COOKIE_PRE_MAPPED)
926 return data->sg_len;
927
928 /*
929 * We don't do DMA on "complex" transfers, i.e. with
930 * non-word-aligned buffers or lengths. Also, we don't bother
931 * with all the DMA setup overhead for short transfers.
932 */
933 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
934 return -EINVAL;
935
936 if (data->blksz & 3)
937 return -EINVAL;
938
939 for_each_sg(data->sg, sg, data->sg_len, i) {
940 if (sg->offset & 3 || sg->length & 3)
941 return -EINVAL;
942 }
943
944 sg_len = dma_map_sg(host->dev,
945 data->sg,
946 data->sg_len,
947 mmc_get_dma_dir(data));
948 if (sg_len == 0)
949 return -EINVAL;
950
951 data->host_cookie = cookie;
952
953 return sg_len;
954 }
955
956 static void dw_mci_pre_req(struct mmc_host *mmc,
957 struct mmc_request *mrq)
958 {
959 struct dw_mci_slot *slot = mmc_priv(mmc);
960 struct mmc_data *data = mrq->data;
961
962 if (!slot->host->use_dma || !data)
963 return;
964
965 /* This data might be unmapped at this time */
966 data->host_cookie = COOKIE_UNMAPPED;
967
968 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
969 COOKIE_PRE_MAPPED) < 0)
970 data->host_cookie = COOKIE_UNMAPPED;
971 }
972
973 static void dw_mci_post_req(struct mmc_host *mmc,
974 struct mmc_request *mrq,
975 int err)
976 {
977 struct dw_mci_slot *slot = mmc_priv(mmc);
978 struct mmc_data *data = mrq->data;
979
980 if (!slot->host->use_dma || !data)
981 return;
982
983 if (data->host_cookie != COOKIE_UNMAPPED)
984 dma_unmap_sg(slot->host->dev,
985 data->sg,
986 data->sg_len,
987 mmc_get_dma_dir(data));
988 data->host_cookie = COOKIE_UNMAPPED;
989 }
990
991 static int dw_mci_get_cd(struct mmc_host *mmc)
992 {
993 int present;
994 struct dw_mci_slot *slot = mmc_priv(mmc);
995 struct dw_mci *host = slot->host;
996 int gpio_cd = mmc_gpio_get_cd(mmc);
997
998 /* Use platform get_cd function, else try onboard card detect */
999 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1000 || !mmc_card_is_removable(mmc))) {
1001 present = 1;
1002
1003 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1004 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1005 dev_info(&mmc->class_dev,
1006 "card is polling.\n");
1007 } else {
1008 dev_info(&mmc->class_dev,
1009 "card is non-removable.\n");
1010 }
1011 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1012 }
1013
1014 return present;
1015 } else if (gpio_cd >= 0)
1016 present = gpio_cd;
1017 else
1018 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1019 == 0 ? 1 : 0;
1020
1021 spin_lock_bh(&host->lock);
1022 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1023 dev_dbg(&mmc->class_dev, "card is present\n");
1024 else if (!present &&
1025 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1026 dev_dbg(&mmc->class_dev, "card is not present\n");
1027 spin_unlock_bh(&host->lock);
1028
1029 return present;
1030 }
1031
1032 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1033 {
1034 unsigned int blksz = data->blksz;
1035 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1036 u32 fifo_width = 1 << host->data_shift;
1037 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1038 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1039 int idx = ARRAY_SIZE(mszs) - 1;
1040
1041 /* pio should ship this scenario */
1042 if (!host->use_dma)
1043 return;
1044
1045 tx_wmark = (host->fifo_depth) / 2;
1046 tx_wmark_invers = host->fifo_depth - tx_wmark;
1047
1048 /*
1049 * MSIZE is '1',
1050 * if blksz is not a multiple of the FIFO width
1051 */
1052 if (blksz % fifo_width)
1053 goto done;
1054
1055 do {
1056 if (!((blksz_depth % mszs[idx]) ||
1057 (tx_wmark_invers % mszs[idx]))) {
1058 msize = idx;
1059 rx_wmark = mszs[idx] - 1;
1060 break;
1061 }
1062 } while (--idx > 0);
1063 /*
1064 * If idx is '0', it won't be tried
1065 * Thus, initial values are uesed
1066 */
1067 done:
1068 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1069 mci_writel(host, FIFOTH, fifoth_val);
1070 }
1071
1072 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1073 {
1074 unsigned int blksz = data->blksz;
1075 u32 blksz_depth, fifo_depth;
1076 u16 thld_size;
1077 u8 enable;
1078
1079 /*
1080 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1081 * in the FIFO region, so we really shouldn't access it).
1082 */
1083 if (host->verid < DW_MMC_240A ||
1084 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1085 return;
1086
1087 /*
1088 * Card write Threshold is introduced since 2.80a
1089 * It's used when HS400 mode is enabled.
1090 */
1091 if (data->flags & MMC_DATA_WRITE &&
1092 host->timing != MMC_TIMING_MMC_HS400)
1093 goto disable;
1094
1095 if (data->flags & MMC_DATA_WRITE)
1096 enable = SDMMC_CARD_WR_THR_EN;
1097 else
1098 enable = SDMMC_CARD_RD_THR_EN;
1099
1100 if (host->timing != MMC_TIMING_MMC_HS200 &&
1101 host->timing != MMC_TIMING_UHS_SDR104 &&
1102 host->timing != MMC_TIMING_MMC_HS400)
1103 goto disable;
1104
1105 blksz_depth = blksz / (1 << host->data_shift);
1106 fifo_depth = host->fifo_depth;
1107
1108 if (blksz_depth > fifo_depth)
1109 goto disable;
1110
1111 /*
1112 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1113 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1114 * Currently just choose blksz.
1115 */
1116 thld_size = blksz;
1117 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1118 return;
1119
1120 disable:
1121 mci_writel(host, CDTHRCTL, 0);
1122 }
1123
1124 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1125 {
1126 unsigned long irqflags;
1127 int sg_len;
1128 u32 temp;
1129
1130 host->using_dma = 0;
1131
1132 /* If we don't have a channel, we can't do DMA */
1133 if (!host->use_dma)
1134 return -ENODEV;
1135
1136 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1137 if (sg_len < 0) {
1138 host->dma_ops->stop(host);
1139 return sg_len;
1140 }
1141
1142 host->using_dma = 1;
1143
1144 if (host->use_dma == TRANS_MODE_IDMAC)
1145 dev_vdbg(host->dev,
1146 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1147 (unsigned long)host->sg_cpu,
1148 (unsigned long)host->sg_dma,
1149 sg_len);
1150
1151 /*
1152 * Decide the MSIZE and RX/TX Watermark.
1153 * If current block size is same with previous size,
1154 * no need to update fifoth.
1155 */
1156 if (host->prev_blksz != data->blksz)
1157 dw_mci_adjust_fifoth(host, data);
1158
1159 /* Enable the DMA interface */
1160 temp = mci_readl(host, CTRL);
1161 temp |= SDMMC_CTRL_DMA_ENABLE;
1162 mci_writel(host, CTRL, temp);
1163
1164 /* Disable RX/TX IRQs, let DMA handle it */
1165 spin_lock_irqsave(&host->irq_lock, irqflags);
1166 temp = mci_readl(host, INTMASK);
1167 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1168 mci_writel(host, INTMASK, temp);
1169 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1170
1171 if (host->dma_ops->start(host, sg_len)) {
1172 host->dma_ops->stop(host);
1173 /* We can't do DMA, try PIO for this one */
1174 dev_dbg(host->dev,
1175 "%s: fall back to PIO mode for current transfer\n",
1176 __func__);
1177 return -ENODEV;
1178 }
1179
1180 return 0;
1181 }
1182
1183 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1184 {
1185 unsigned long irqflags;
1186 int flags = SG_MITER_ATOMIC;
1187 u32 temp;
1188
1189 data->error = -EINPROGRESS;
1190
1191 WARN_ON(host->data);
1192 host->sg = NULL;
1193 host->data = data;
1194
1195 if (data->flags & MMC_DATA_READ)
1196 host->dir_status = DW_MCI_RECV_STATUS;
1197 else
1198 host->dir_status = DW_MCI_SEND_STATUS;
1199
1200 dw_mci_ctrl_thld(host, data);
1201
1202 if (dw_mci_submit_data_dma(host, data)) {
1203 if (host->data->flags & MMC_DATA_READ)
1204 flags |= SG_MITER_TO_SG;
1205 else
1206 flags |= SG_MITER_FROM_SG;
1207
1208 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1209 host->sg = data->sg;
1210 host->part_buf_start = 0;
1211 host->part_buf_count = 0;
1212
1213 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1214
1215 spin_lock_irqsave(&host->irq_lock, irqflags);
1216 temp = mci_readl(host, INTMASK);
1217 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1218 mci_writel(host, INTMASK, temp);
1219 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1220
1221 temp = mci_readl(host, CTRL);
1222 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1223 mci_writel(host, CTRL, temp);
1224
1225 /*
1226 * Use the initial fifoth_val for PIO mode. If wm_algined
1227 * is set, we set watermark same as data size.
1228 * If next issued data may be transfered by DMA mode,
1229 * prev_blksz should be invalidated.
1230 */
1231 if (host->wm_aligned)
1232 dw_mci_adjust_fifoth(host, data);
1233 else
1234 mci_writel(host, FIFOTH, host->fifoth_val);
1235 host->prev_blksz = 0;
1236 } else {
1237 /*
1238 * Keep the current block size.
1239 * It will be used to decide whether to update
1240 * fifoth register next time.
1241 */
1242 host->prev_blksz = data->blksz;
1243 }
1244 }
1245
1246 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1247 {
1248 struct dw_mci *host = slot->host;
1249 unsigned int clock = slot->clock;
1250 u32 div;
1251 u32 clk_en_a;
1252 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1253
1254 /* We must continue to set bit 28 in CMD until the change is complete */
1255 if (host->state == STATE_WAITING_CMD11_DONE)
1256 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1257
1258 if (!clock) {
1259 mci_writel(host, CLKENA, 0);
1260 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1261 } else if (clock != host->current_speed || force_clkinit) {
1262 div = host->bus_hz / clock;
1263 if (host->bus_hz % clock && host->bus_hz > clock)
1264 /*
1265 * move the + 1 after the divide to prevent
1266 * over-clocking the card.
1267 */
1268 div += 1;
1269
1270 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1271
1272 if ((clock != slot->__clk_old &&
1273 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1274 force_clkinit) {
1275 /* Silent the verbose log if calling from PM context */
1276 if (!force_clkinit)
1277 dev_info(&slot->mmc->class_dev,
1278 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1279 slot->id, host->bus_hz, clock,
1280 div ? ((host->bus_hz / div) >> 1) :
1281 host->bus_hz, div);
1282
1283 /*
1284 * If card is polling, display the message only
1285 * one time at boot time.
1286 */
1287 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1288 slot->mmc->f_min == clock)
1289 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1290 }
1291
1292 /* disable clock */
1293 mci_writel(host, CLKENA, 0);
1294 mci_writel(host, CLKSRC, 0);
1295
1296 /* inform CIU */
1297 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1298
1299 /* set clock to desired speed */
1300 mci_writel(host, CLKDIV, div);
1301
1302 /* inform CIU */
1303 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1304
1305 /* enable clock; only low power if no SDIO */
1306 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1307 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1308 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1309 mci_writel(host, CLKENA, clk_en_a);
1310
1311 /* inform CIU */
1312 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1313
1314 /* keep the last clock value that was requested from core */
1315 slot->__clk_old = clock;
1316 }
1317
1318 host->current_speed = clock;
1319
1320 /* Set the current slot bus width */
1321 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1322 }
1323
1324 static void __dw_mci_start_request(struct dw_mci *host,
1325 struct dw_mci_slot *slot,
1326 struct mmc_command *cmd)
1327 {
1328 struct mmc_request *mrq;
1329 struct mmc_data *data;
1330 u32 cmdflags;
1331
1332 mrq = slot->mrq;
1333
1334 host->mrq = mrq;
1335
1336 host->pending_events = 0;
1337 host->completed_events = 0;
1338 host->cmd_status = 0;
1339 host->data_status = 0;
1340 host->dir_status = 0;
1341
1342 data = cmd->data;
1343 if (data) {
1344 mci_writel(host, TMOUT, 0xFFFFFFFF);
1345 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1346 mci_writel(host, BLKSIZ, data->blksz);
1347 }
1348
1349 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1350
1351 /* this is the first command, send the initialization clock */
1352 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1353 cmdflags |= SDMMC_CMD_INIT;
1354
1355 if (data) {
1356 dw_mci_submit_data(host, data);
1357 wmb(); /* drain writebuffer */
1358 }
1359
1360 dw_mci_start_command(host, cmd, cmdflags);
1361
1362 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1363 unsigned long irqflags;
1364
1365 /*
1366 * Databook says to fail after 2ms w/ no response, but evidence
1367 * shows that sometimes the cmd11 interrupt takes over 130ms.
1368 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1369 * is just about to roll over.
1370 *
1371 * We do this whole thing under spinlock and only if the
1372 * command hasn't already completed (indicating the the irq
1373 * already ran so we don't want the timeout).
1374 */
1375 spin_lock_irqsave(&host->irq_lock, irqflags);
1376 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1377 mod_timer(&host->cmd11_timer,
1378 jiffies + msecs_to_jiffies(500) + 1);
1379 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1380 }
1381
1382 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1383 }
1384
1385 static void dw_mci_start_request(struct dw_mci *host,
1386 struct dw_mci_slot *slot)
1387 {
1388 struct mmc_request *mrq = slot->mrq;
1389 struct mmc_command *cmd;
1390
1391 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1392 __dw_mci_start_request(host, slot, cmd);
1393 }
1394
1395 /* must be called with host->lock held */
1396 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1397 struct mmc_request *mrq)
1398 {
1399 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1400 host->state);
1401
1402 slot->mrq = mrq;
1403
1404 if (host->state == STATE_WAITING_CMD11_DONE) {
1405 dev_warn(&slot->mmc->class_dev,
1406 "Voltage change didn't complete\n");
1407 /*
1408 * this case isn't expected to happen, so we can
1409 * either crash here or just try to continue on
1410 * in the closest possible state
1411 */
1412 host->state = STATE_IDLE;
1413 }
1414
1415 if (host->state == STATE_IDLE) {
1416 host->state = STATE_SENDING_CMD;
1417 dw_mci_start_request(host, slot);
1418 } else {
1419 list_add_tail(&slot->queue_node, &host->queue);
1420 }
1421 }
1422
1423 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1424 {
1425 struct dw_mci_slot *slot = mmc_priv(mmc);
1426 struct dw_mci *host = slot->host;
1427
1428 WARN_ON(slot->mrq);
1429
1430 /*
1431 * The check for card presence and queueing of the request must be
1432 * atomic, otherwise the card could be removed in between and the
1433 * request wouldn't fail until another card was inserted.
1434 */
1435
1436 if (!dw_mci_get_cd(mmc)) {
1437 mrq->cmd->error = -ENOMEDIUM;
1438 mmc_request_done(mmc, mrq);
1439 return;
1440 }
1441
1442 spin_lock_bh(&host->lock);
1443
1444 dw_mci_queue_request(host, slot, mrq);
1445
1446 spin_unlock_bh(&host->lock);
1447 }
1448
1449 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1450 {
1451 struct dw_mci_slot *slot = mmc_priv(mmc);
1452 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1453 u32 regs;
1454 int ret;
1455
1456 switch (ios->bus_width) {
1457 case MMC_BUS_WIDTH_4:
1458 slot->ctype = SDMMC_CTYPE_4BIT;
1459 break;
1460 case MMC_BUS_WIDTH_8:
1461 slot->ctype = SDMMC_CTYPE_8BIT;
1462 break;
1463 default:
1464 /* set default 1 bit mode */
1465 slot->ctype = SDMMC_CTYPE_1BIT;
1466 }
1467
1468 regs = mci_readl(slot->host, UHS_REG);
1469
1470 /* DDR mode set */
1471 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1472 ios->timing == MMC_TIMING_UHS_DDR50 ||
1473 ios->timing == MMC_TIMING_MMC_HS400)
1474 regs |= ((0x1 << slot->id) << 16);
1475 else
1476 regs &= ~((0x1 << slot->id) << 16);
1477
1478 mci_writel(slot->host, UHS_REG, regs);
1479 slot->host->timing = ios->timing;
1480
1481 /*
1482 * Use mirror of ios->clock to prevent race with mmc
1483 * core ios update when finding the minimum.
1484 */
1485 slot->clock = ios->clock;
1486
1487 if (drv_data && drv_data->set_ios)
1488 drv_data->set_ios(slot->host, ios);
1489
1490 switch (ios->power_mode) {
1491 case MMC_POWER_UP:
1492 if (!IS_ERR(mmc->supply.vmmc)) {
1493 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1494 ios->vdd);
1495 if (ret) {
1496 dev_err(slot->host->dev,
1497 "failed to enable vmmc regulator\n");
1498 /*return, if failed turn on vmmc*/
1499 return;
1500 }
1501 }
1502 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1503 regs = mci_readl(slot->host, PWREN);
1504 regs |= (1 << slot->id);
1505 mci_writel(slot->host, PWREN, regs);
1506 break;
1507 case MMC_POWER_ON:
1508 if (!slot->host->vqmmc_enabled) {
1509 if (!IS_ERR(mmc->supply.vqmmc)) {
1510 ret = regulator_enable(mmc->supply.vqmmc);
1511 if (ret < 0)
1512 dev_err(slot->host->dev,
1513 "failed to enable vqmmc\n");
1514 else
1515 slot->host->vqmmc_enabled = true;
1516
1517 } else {
1518 /* Keep track so we don't reset again */
1519 slot->host->vqmmc_enabled = true;
1520 }
1521
1522 /* Reset our state machine after powering on */
1523 dw_mci_ctrl_reset(slot->host,
1524 SDMMC_CTRL_ALL_RESET_FLAGS);
1525 }
1526
1527 /* Adjust clock / bus width after power is up */
1528 dw_mci_setup_bus(slot, false);
1529
1530 break;
1531 case MMC_POWER_OFF:
1532 /* Turn clock off before power goes down */
1533 dw_mci_setup_bus(slot, false);
1534
1535 if (!IS_ERR(mmc->supply.vmmc))
1536 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1537
1538 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1539 regulator_disable(mmc->supply.vqmmc);
1540 slot->host->vqmmc_enabled = false;
1541
1542 regs = mci_readl(slot->host, PWREN);
1543 regs &= ~(1 << slot->id);
1544 mci_writel(slot->host, PWREN, regs);
1545 break;
1546 default:
1547 break;
1548 }
1549
1550 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1551 slot->host->state = STATE_IDLE;
1552 }
1553
1554 static int dw_mci_card_busy(struct mmc_host *mmc)
1555 {
1556 struct dw_mci_slot *slot = mmc_priv(mmc);
1557 u32 status;
1558
1559 /*
1560 * Check the busy bit which is low when DAT[3:0]
1561 * (the data lines) are 0000
1562 */
1563 status = mci_readl(slot->host, STATUS);
1564
1565 return !!(status & SDMMC_STATUS_BUSY);
1566 }
1567
1568 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1569 {
1570 struct dw_mci_slot *slot = mmc_priv(mmc);
1571 struct dw_mci *host = slot->host;
1572 const struct dw_mci_drv_data *drv_data = host->drv_data;
1573 u32 uhs;
1574 u32 v18 = SDMMC_UHS_18V << slot->id;
1575 int ret;
1576
1577 if (drv_data && drv_data->switch_voltage)
1578 return drv_data->switch_voltage(mmc, ios);
1579
1580 /*
1581 * Program the voltage. Note that some instances of dw_mmc may use
1582 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1583 * does no harm but you need to set the regulator directly. Try both.
1584 */
1585 uhs = mci_readl(host, UHS_REG);
1586 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1587 uhs &= ~v18;
1588 else
1589 uhs |= v18;
1590
1591 if (!IS_ERR(mmc->supply.vqmmc)) {
1592 ret = mmc_regulator_set_vqmmc(mmc, ios);
1593
1594 if (ret) {
1595 dev_dbg(&mmc->class_dev,
1596 "Regulator set error %d - %s V\n",
1597 ret, uhs & v18 ? "1.8" : "3.3");
1598 return ret;
1599 }
1600 }
1601 mci_writel(host, UHS_REG, uhs);
1602
1603 return 0;
1604 }
1605
1606 static int dw_mci_get_ro(struct mmc_host *mmc)
1607 {
1608 int read_only;
1609 struct dw_mci_slot *slot = mmc_priv(mmc);
1610 int gpio_ro = mmc_gpio_get_ro(mmc);
1611
1612 /* Use platform get_ro function, else try on board write protect */
1613 if (gpio_ro >= 0)
1614 read_only = gpio_ro;
1615 else
1616 read_only =
1617 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1618
1619 dev_dbg(&mmc->class_dev, "card is %s\n",
1620 read_only ? "read-only" : "read-write");
1621
1622 return read_only;
1623 }
1624
1625 static void dw_mci_hw_reset(struct mmc_host *mmc)
1626 {
1627 struct dw_mci_slot *slot = mmc_priv(mmc);
1628 struct dw_mci *host = slot->host;
1629 int reset;
1630
1631 if (host->use_dma == TRANS_MODE_IDMAC)
1632 dw_mci_idmac_reset(host);
1633
1634 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1635 SDMMC_CTRL_FIFO_RESET))
1636 return;
1637
1638 /*
1639 * According to eMMC spec, card reset procedure:
1640 * tRstW >= 1us: RST_n pulse width
1641 * tRSCA >= 200us: RST_n to Command time
1642 * tRSTH >= 1us: RST_n high period
1643 */
1644 reset = mci_readl(host, RST_N);
1645 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1646 mci_writel(host, RST_N, reset);
1647 usleep_range(1, 2);
1648 reset |= SDMMC_RST_HWACTIVE << slot->id;
1649 mci_writel(host, RST_N, reset);
1650 usleep_range(200, 300);
1651 }
1652
1653 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1654 {
1655 struct dw_mci_slot *slot = mmc_priv(mmc);
1656 struct dw_mci *host = slot->host;
1657
1658 /*
1659 * Low power mode will stop the card clock when idle. According to the
1660 * description of the CLKENA register we should disable low power mode
1661 * for SDIO cards if we need SDIO interrupts to work.
1662 */
1663 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1664 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1665 u32 clk_en_a_old;
1666 u32 clk_en_a;
1667
1668 clk_en_a_old = mci_readl(host, CLKENA);
1669
1670 if (card->type == MMC_TYPE_SDIO ||
1671 card->type == MMC_TYPE_SD_COMBO) {
1672 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1673 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1674 } else {
1675 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1676 clk_en_a = clk_en_a_old | clken_low_pwr;
1677 }
1678
1679 if (clk_en_a != clk_en_a_old) {
1680 mci_writel(host, CLKENA, clk_en_a);
1681 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1682 SDMMC_CMD_PRV_DAT_WAIT, 0);
1683 }
1684 }
1685 }
1686
1687 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1688 {
1689 struct dw_mci *host = slot->host;
1690 unsigned long irqflags;
1691 u32 int_mask;
1692
1693 spin_lock_irqsave(&host->irq_lock, irqflags);
1694
1695 /* Enable/disable Slot Specific SDIO interrupt */
1696 int_mask = mci_readl(host, INTMASK);
1697 if (enb)
1698 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1699 else
1700 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1701 mci_writel(host, INTMASK, int_mask);
1702
1703 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1704 }
1705
1706 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1707 {
1708 struct dw_mci_slot *slot = mmc_priv(mmc);
1709 struct dw_mci *host = slot->host;
1710
1711 __dw_mci_enable_sdio_irq(slot, enb);
1712
1713 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1714 if (enb)
1715 pm_runtime_get_noresume(host->dev);
1716 else
1717 pm_runtime_put_noidle(host->dev);
1718 }
1719
1720 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1721 {
1722 struct dw_mci_slot *slot = mmc_priv(mmc);
1723
1724 __dw_mci_enable_sdio_irq(slot, 1);
1725 }
1726
1727 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1728 {
1729 struct dw_mci_slot *slot = mmc_priv(mmc);
1730 struct dw_mci *host = slot->host;
1731 const struct dw_mci_drv_data *drv_data = host->drv_data;
1732 int err = -EINVAL;
1733
1734 if (drv_data && drv_data->execute_tuning)
1735 err = drv_data->execute_tuning(slot, opcode);
1736 return err;
1737 }
1738
1739 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1740 struct mmc_ios *ios)
1741 {
1742 struct dw_mci_slot *slot = mmc_priv(mmc);
1743 struct dw_mci *host = slot->host;
1744 const struct dw_mci_drv_data *drv_data = host->drv_data;
1745
1746 if (drv_data && drv_data->prepare_hs400_tuning)
1747 return drv_data->prepare_hs400_tuning(host, ios);
1748
1749 return 0;
1750 }
1751
1752 static bool dw_mci_reset(struct dw_mci *host)
1753 {
1754 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1755 bool ret = false;
1756 u32 status = 0;
1757
1758 /*
1759 * Resetting generates a block interrupt, hence setting
1760 * the scatter-gather pointer to NULL.
1761 */
1762 if (host->sg) {
1763 sg_miter_stop(&host->sg_miter);
1764 host->sg = NULL;
1765 }
1766
1767 if (host->use_dma)
1768 flags |= SDMMC_CTRL_DMA_RESET;
1769
1770 if (dw_mci_ctrl_reset(host, flags)) {
1771 /*
1772 * In all cases we clear the RAWINTS
1773 * register to clear any interrupts.
1774 */
1775 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1776
1777 if (!host->use_dma) {
1778 ret = true;
1779 goto ciu_out;
1780 }
1781
1782 /* Wait for dma_req to be cleared */
1783 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1784 status,
1785 !(status & SDMMC_STATUS_DMA_REQ),
1786 1, 500 * USEC_PER_MSEC)) {
1787 dev_err(host->dev,
1788 "%s: Timeout waiting for dma_req to be cleared\n",
1789 __func__);
1790 goto ciu_out;
1791 }
1792
1793 /* when using DMA next we reset the fifo again */
1794 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1795 goto ciu_out;
1796 } else {
1797 /* if the controller reset bit did clear, then set clock regs */
1798 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1799 dev_err(host->dev,
1800 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1801 __func__);
1802 goto ciu_out;
1803 }
1804 }
1805
1806 if (host->use_dma == TRANS_MODE_IDMAC)
1807 /* It is also required that we reinit idmac */
1808 dw_mci_idmac_init(host);
1809
1810 ret = true;
1811
1812 ciu_out:
1813 /* After a CTRL reset we need to have CIU set clock registers */
1814 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1815
1816 return ret;
1817 }
1818
1819 static const struct mmc_host_ops dw_mci_ops = {
1820 .request = dw_mci_request,
1821 .pre_req = dw_mci_pre_req,
1822 .post_req = dw_mci_post_req,
1823 .set_ios = dw_mci_set_ios,
1824 .get_ro = dw_mci_get_ro,
1825 .get_cd = dw_mci_get_cd,
1826 .hw_reset = dw_mci_hw_reset,
1827 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1828 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1829 .execute_tuning = dw_mci_execute_tuning,
1830 .card_busy = dw_mci_card_busy,
1831 .start_signal_voltage_switch = dw_mci_switch_voltage,
1832 .init_card = dw_mci_init_card,
1833 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1834 };
1835
1836 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1837 __releases(&host->lock)
1838 __acquires(&host->lock)
1839 {
1840 struct dw_mci_slot *slot;
1841 struct mmc_host *prev_mmc = host->slot->mmc;
1842
1843 WARN_ON(host->cmd || host->data);
1844
1845 host->slot->mrq = NULL;
1846 host->mrq = NULL;
1847 if (!list_empty(&host->queue)) {
1848 slot = list_entry(host->queue.next,
1849 struct dw_mci_slot, queue_node);
1850 list_del(&slot->queue_node);
1851 dev_vdbg(host->dev, "list not empty: %s is next\n",
1852 mmc_hostname(slot->mmc));
1853 host->state = STATE_SENDING_CMD;
1854 dw_mci_start_request(host, slot);
1855 } else {
1856 dev_vdbg(host->dev, "list empty\n");
1857
1858 if (host->state == STATE_SENDING_CMD11)
1859 host->state = STATE_WAITING_CMD11_DONE;
1860 else
1861 host->state = STATE_IDLE;
1862 }
1863
1864 spin_unlock(&host->lock);
1865 mmc_request_done(prev_mmc, mrq);
1866 spin_lock(&host->lock);
1867 }
1868
1869 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1870 {
1871 u32 status = host->cmd_status;
1872
1873 host->cmd_status = 0;
1874
1875 /* Read the response from the card (up to 16 bytes) */
1876 if (cmd->flags & MMC_RSP_PRESENT) {
1877 if (cmd->flags & MMC_RSP_136) {
1878 cmd->resp[3] = mci_readl(host, RESP0);
1879 cmd->resp[2] = mci_readl(host, RESP1);
1880 cmd->resp[1] = mci_readl(host, RESP2);
1881 cmd->resp[0] = mci_readl(host, RESP3);
1882 } else {
1883 cmd->resp[0] = mci_readl(host, RESP0);
1884 cmd->resp[1] = 0;
1885 cmd->resp[2] = 0;
1886 cmd->resp[3] = 0;
1887 }
1888 }
1889
1890 if (status & SDMMC_INT_RTO)
1891 cmd->error = -ETIMEDOUT;
1892 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1893 cmd->error = -EILSEQ;
1894 else if (status & SDMMC_INT_RESP_ERR)
1895 cmd->error = -EIO;
1896 else
1897 cmd->error = 0;
1898
1899 return cmd->error;
1900 }
1901
1902 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1903 {
1904 u32 status = host->data_status;
1905
1906 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1907 if (status & SDMMC_INT_DRTO) {
1908 data->error = -ETIMEDOUT;
1909 } else if (status & SDMMC_INT_DCRC) {
1910 data->error = -EILSEQ;
1911 } else if (status & SDMMC_INT_EBE) {
1912 if (host->dir_status ==
1913 DW_MCI_SEND_STATUS) {
1914 /*
1915 * No data CRC status was returned.
1916 * The number of bytes transferred
1917 * will be exaggerated in PIO mode.
1918 */
1919 data->bytes_xfered = 0;
1920 data->error = -ETIMEDOUT;
1921 } else if (host->dir_status ==
1922 DW_MCI_RECV_STATUS) {
1923 data->error = -EILSEQ;
1924 }
1925 } else {
1926 /* SDMMC_INT_SBE is included */
1927 data->error = -EILSEQ;
1928 }
1929
1930 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1931
1932 /*
1933 * After an error, there may be data lingering
1934 * in the FIFO
1935 */
1936 dw_mci_reset(host);
1937 } else {
1938 data->bytes_xfered = data->blocks * data->blksz;
1939 data->error = 0;
1940 }
1941
1942 return data->error;
1943 }
1944
1945 static void dw_mci_set_drto(struct dw_mci *host)
1946 {
1947 unsigned int drto_clks;
1948 unsigned int drto_div;
1949 unsigned int drto_ms;
1950 unsigned long irqflags;
1951
1952 drto_clks = mci_readl(host, TMOUT) >> 8;
1953 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1954 if (drto_div == 0)
1955 drto_div = 1;
1956
1957 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1958 host->bus_hz);
1959
1960 /* add a bit spare time */
1961 drto_ms += 10;
1962
1963 spin_lock_irqsave(&host->irq_lock, irqflags);
1964 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1965 mod_timer(&host->dto_timer,
1966 jiffies + msecs_to_jiffies(drto_ms));
1967 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1968 }
1969
1970 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1971 {
1972 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1973 return false;
1974
1975 /*
1976 * Really be certain that the timer has stopped. This is a bit of
1977 * paranoia and could only really happen if we had really bad
1978 * interrupt latency and the interrupt routine and timeout were
1979 * running concurrently so that the del_timer() in the interrupt
1980 * handler couldn't run.
1981 */
1982 WARN_ON(del_timer_sync(&host->cto_timer));
1983 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1984
1985 return true;
1986 }
1987
1988 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1989 {
1990 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1991 return false;
1992
1993 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1994 WARN_ON(del_timer_sync(&host->dto_timer));
1995 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1996
1997 return true;
1998 }
1999
2000 static void dw_mci_tasklet_func(unsigned long priv)
2001 {
2002 struct dw_mci *host = (struct dw_mci *)priv;
2003 struct mmc_data *data;
2004 struct mmc_command *cmd;
2005 struct mmc_request *mrq;
2006 enum dw_mci_state state;
2007 enum dw_mci_state prev_state;
2008 unsigned int err;
2009
2010 spin_lock(&host->lock);
2011
2012 state = host->state;
2013 data = host->data;
2014 mrq = host->mrq;
2015
2016 do {
2017 prev_state = state;
2018
2019 switch (state) {
2020 case STATE_IDLE:
2021 case STATE_WAITING_CMD11_DONE:
2022 break;
2023
2024 case STATE_SENDING_CMD11:
2025 case STATE_SENDING_CMD:
2026 if (!dw_mci_clear_pending_cmd_complete(host))
2027 break;
2028
2029 cmd = host->cmd;
2030 host->cmd = NULL;
2031 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2032 err = dw_mci_command_complete(host, cmd);
2033 if (cmd == mrq->sbc && !err) {
2034 prev_state = state = STATE_SENDING_CMD;
2035 __dw_mci_start_request(host, host->slot,
2036 mrq->cmd);
2037 goto unlock;
2038 }
2039
2040 if (cmd->data && err) {
2041 /*
2042 * During UHS tuning sequence, sending the stop
2043 * command after the response CRC error would
2044 * throw the system into a confused state
2045 * causing all future tuning phases to report
2046 * failure.
2047 *
2048 * In such case controller will move into a data
2049 * transfer state after a response error or
2050 * response CRC error. Let's let that finish
2051 * before trying to send a stop, so we'll go to
2052 * STATE_SENDING_DATA.
2053 *
2054 * Although letting the data transfer take place
2055 * will waste a bit of time (we already know
2056 * the command was bad), it can't cause any
2057 * errors since it's possible it would have
2058 * taken place anyway if this tasklet got
2059 * delayed. Allowing the transfer to take place
2060 * avoids races and keeps things simple.
2061 */
2062 if ((err != -ETIMEDOUT) &&
2063 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2064 state = STATE_SENDING_DATA;
2065 continue;
2066 }
2067
2068 dw_mci_stop_dma(host);
2069 send_stop_abort(host, data);
2070 state = STATE_SENDING_STOP;
2071 break;
2072 }
2073
2074 if (!cmd->data || err) {
2075 dw_mci_request_end(host, mrq);
2076 goto unlock;
2077 }
2078
2079 prev_state = state = STATE_SENDING_DATA;
2080 /* fall through */
2081
2082 case STATE_SENDING_DATA:
2083 /*
2084 * We could get a data error and never a transfer
2085 * complete so we'd better check for it here.
2086 *
2087 * Note that we don't really care if we also got a
2088 * transfer complete; stopping the DMA and sending an
2089 * abort won't hurt.
2090 */
2091 if (test_and_clear_bit(EVENT_DATA_ERROR,
2092 &host->pending_events)) {
2093 dw_mci_stop_dma(host);
2094 if (!(host->data_status & (SDMMC_INT_DRTO |
2095 SDMMC_INT_EBE)))
2096 send_stop_abort(host, data);
2097 state = STATE_DATA_ERROR;
2098 break;
2099 }
2100
2101 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2102 &host->pending_events)) {
2103 /*
2104 * If all data-related interrupts don't come
2105 * within the given time in reading data state.
2106 */
2107 if (host->dir_status == DW_MCI_RECV_STATUS)
2108 dw_mci_set_drto(host);
2109 break;
2110 }
2111
2112 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2113
2114 /*
2115 * Handle an EVENT_DATA_ERROR that might have shown up
2116 * before the transfer completed. This might not have
2117 * been caught by the check above because the interrupt
2118 * could have gone off between the previous check and
2119 * the check for transfer complete.
2120 *
2121 * Technically this ought not be needed assuming we
2122 * get a DATA_COMPLETE eventually (we'll notice the
2123 * error and end the request), but it shouldn't hurt.
2124 *
2125 * This has the advantage of sending the stop command.
2126 */
2127 if (test_and_clear_bit(EVENT_DATA_ERROR,
2128 &host->pending_events)) {
2129 dw_mci_stop_dma(host);
2130 if (!(host->data_status & (SDMMC_INT_DRTO |
2131 SDMMC_INT_EBE)))
2132 send_stop_abort(host, data);
2133 state = STATE_DATA_ERROR;
2134 break;
2135 }
2136 prev_state = state = STATE_DATA_BUSY;
2137
2138 /* fall through */
2139
2140 case STATE_DATA_BUSY:
2141 if (!dw_mci_clear_pending_data_complete(host)) {
2142 /*
2143 * If data error interrupt comes but data over
2144 * interrupt doesn't come within the given time.
2145 * in reading data state.
2146 */
2147 if (host->dir_status == DW_MCI_RECV_STATUS)
2148 dw_mci_set_drto(host);
2149 break;
2150 }
2151
2152 host->data = NULL;
2153 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2154 err = dw_mci_data_complete(host, data);
2155
2156 if (!err) {
2157 if (!data->stop || mrq->sbc) {
2158 if (mrq->sbc && data->stop)
2159 data->stop->error = 0;
2160 dw_mci_request_end(host, mrq);
2161 goto unlock;
2162 }
2163
2164 /* stop command for open-ended transfer*/
2165 if (data->stop)
2166 send_stop_abort(host, data);
2167 } else {
2168 /*
2169 * If we don't have a command complete now we'll
2170 * never get one since we just reset everything;
2171 * better end the request.
2172 *
2173 * If we do have a command complete we'll fall
2174 * through to the SENDING_STOP command and
2175 * everything will be peachy keen.
2176 */
2177 if (!test_bit(EVENT_CMD_COMPLETE,
2178 &host->pending_events)) {
2179 host->cmd = NULL;
2180 dw_mci_request_end(host, mrq);
2181 goto unlock;
2182 }
2183 }
2184
2185 /*
2186 * If err has non-zero,
2187 * stop-abort command has been already issued.
2188 */
2189 prev_state = state = STATE_SENDING_STOP;
2190
2191 /* fall through */
2192
2193 case STATE_SENDING_STOP:
2194 if (!dw_mci_clear_pending_cmd_complete(host))
2195 break;
2196
2197 /* CMD error in data command */
2198 if (mrq->cmd->error && mrq->data)
2199 dw_mci_reset(host);
2200
2201 host->cmd = NULL;
2202 host->data = NULL;
2203
2204 if (!mrq->sbc && mrq->stop)
2205 dw_mci_command_complete(host, mrq->stop);
2206 else
2207 host->cmd_status = 0;
2208
2209 dw_mci_request_end(host, mrq);
2210 goto unlock;
2211
2212 case STATE_DATA_ERROR:
2213 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2214 &host->pending_events))
2215 break;
2216
2217 state = STATE_DATA_BUSY;
2218 break;
2219 }
2220 } while (state != prev_state);
2221
2222 host->state = state;
2223 unlock:
2224 spin_unlock(&host->lock);
2225
2226 }
2227
2228 /* push final bytes to part_buf, only use during push */
2229 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2230 {
2231 memcpy((void *)&host->part_buf, buf, cnt);
2232 host->part_buf_count = cnt;
2233 }
2234
2235 /* append bytes to part_buf, only use during push */
2236 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2237 {
2238 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2239 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2240 host->part_buf_count += cnt;
2241 return cnt;
2242 }
2243
2244 /* pull first bytes from part_buf, only use during pull */
2245 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2246 {
2247 cnt = min_t(int, cnt, host->part_buf_count);
2248 if (cnt) {
2249 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2250 cnt);
2251 host->part_buf_count -= cnt;
2252 host->part_buf_start += cnt;
2253 }
2254 return cnt;
2255 }
2256
2257 /* pull final bytes from the part_buf, assuming it's just been filled */
2258 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2259 {
2260 memcpy(buf, &host->part_buf, cnt);
2261 host->part_buf_start = cnt;
2262 host->part_buf_count = (1 << host->data_shift) - cnt;
2263 }
2264
2265 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2266 {
2267 struct mmc_data *data = host->data;
2268 int init_cnt = cnt;
2269
2270 /* try and push anything in the part_buf */
2271 if (unlikely(host->part_buf_count)) {
2272 int len = dw_mci_push_part_bytes(host, buf, cnt);
2273
2274 buf += len;
2275 cnt -= len;
2276 if (host->part_buf_count == 2) {
2277 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2278 host->part_buf_count = 0;
2279 }
2280 }
2281 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2282 if (unlikely((unsigned long)buf & 0x1)) {
2283 while (cnt >= 2) {
2284 u16 aligned_buf[64];
2285 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2286 int items = len >> 1;
2287 int i;
2288 /* memcpy from input buffer into aligned buffer */
2289 memcpy(aligned_buf, buf, len);
2290 buf += len;
2291 cnt -= len;
2292 /* push data from aligned buffer into fifo */
2293 for (i = 0; i < items; ++i)
2294 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2295 }
2296 } else
2297 #endif
2298 {
2299 u16 *pdata = buf;
2300
2301 for (; cnt >= 2; cnt -= 2)
2302 mci_fifo_writew(host->fifo_reg, *pdata++);
2303 buf = pdata;
2304 }
2305 /* put anything remaining in the part_buf */
2306 if (cnt) {
2307 dw_mci_set_part_bytes(host, buf, cnt);
2308 /* Push data if we have reached the expected data length */
2309 if ((data->bytes_xfered + init_cnt) ==
2310 (data->blksz * data->blocks))
2311 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2312 }
2313 }
2314
2315 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2316 {
2317 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2318 if (unlikely((unsigned long)buf & 0x1)) {
2319 while (cnt >= 2) {
2320 /* pull data from fifo into aligned buffer */
2321 u16 aligned_buf[64];
2322 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2323 int items = len >> 1;
2324 int i;
2325
2326 for (i = 0; i < items; ++i)
2327 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2328 /* memcpy from aligned buffer into output buffer */
2329 memcpy(buf, aligned_buf, len);
2330 buf += len;
2331 cnt -= len;
2332 }
2333 } else
2334 #endif
2335 {
2336 u16 *pdata = buf;
2337
2338 for (; cnt >= 2; cnt -= 2)
2339 *pdata++ = mci_fifo_readw(host->fifo_reg);
2340 buf = pdata;
2341 }
2342 if (cnt) {
2343 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2344 dw_mci_pull_final_bytes(host, buf, cnt);
2345 }
2346 }
2347
2348 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2349 {
2350 struct mmc_data *data = host->data;
2351 int init_cnt = cnt;
2352
2353 /* try and push anything in the part_buf */
2354 if (unlikely(host->part_buf_count)) {
2355 int len = dw_mci_push_part_bytes(host, buf, cnt);
2356
2357 buf += len;
2358 cnt -= len;
2359 if (host->part_buf_count == 4) {
2360 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2361 host->part_buf_count = 0;
2362 }
2363 }
2364 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2365 if (unlikely((unsigned long)buf & 0x3)) {
2366 while (cnt >= 4) {
2367 u32 aligned_buf[32];
2368 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2369 int items = len >> 2;
2370 int i;
2371 /* memcpy from input buffer into aligned buffer */
2372 memcpy(aligned_buf, buf, len);
2373 buf += len;
2374 cnt -= len;
2375 /* push data from aligned buffer into fifo */
2376 for (i = 0; i < items; ++i)
2377 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2378 }
2379 } else
2380 #endif
2381 {
2382 u32 *pdata = buf;
2383
2384 for (; cnt >= 4; cnt -= 4)
2385 mci_fifo_writel(host->fifo_reg, *pdata++);
2386 buf = pdata;
2387 }
2388 /* put anything remaining in the part_buf */
2389 if (cnt) {
2390 dw_mci_set_part_bytes(host, buf, cnt);
2391 /* Push data if we have reached the expected data length */
2392 if ((data->bytes_xfered + init_cnt) ==
2393 (data->blksz * data->blocks))
2394 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2395 }
2396 }
2397
2398 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2399 {
2400 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2401 if (unlikely((unsigned long)buf & 0x3)) {
2402 while (cnt >= 4) {
2403 /* pull data from fifo into aligned buffer */
2404 u32 aligned_buf[32];
2405 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2406 int items = len >> 2;
2407 int i;
2408
2409 for (i = 0; i < items; ++i)
2410 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2411 /* memcpy from aligned buffer into output buffer */
2412 memcpy(buf, aligned_buf, len);
2413 buf += len;
2414 cnt -= len;
2415 }
2416 } else
2417 #endif
2418 {
2419 u32 *pdata = buf;
2420
2421 for (; cnt >= 4; cnt -= 4)
2422 *pdata++ = mci_fifo_readl(host->fifo_reg);
2423 buf = pdata;
2424 }
2425 if (cnt) {
2426 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2427 dw_mci_pull_final_bytes(host, buf, cnt);
2428 }
2429 }
2430
2431 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2432 {
2433 struct mmc_data *data = host->data;
2434 int init_cnt = cnt;
2435
2436 /* try and push anything in the part_buf */
2437 if (unlikely(host->part_buf_count)) {
2438 int len = dw_mci_push_part_bytes(host, buf, cnt);
2439
2440 buf += len;
2441 cnt -= len;
2442
2443 if (host->part_buf_count == 8) {
2444 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2445 host->part_buf_count = 0;
2446 }
2447 }
2448 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2449 if (unlikely((unsigned long)buf & 0x7)) {
2450 while (cnt >= 8) {
2451 u64 aligned_buf[16];
2452 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2453 int items = len >> 3;
2454 int i;
2455 /* memcpy from input buffer into aligned buffer */
2456 memcpy(aligned_buf, buf, len);
2457 buf += len;
2458 cnt -= len;
2459 /* push data from aligned buffer into fifo */
2460 for (i = 0; i < items; ++i)
2461 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2462 }
2463 } else
2464 #endif
2465 {
2466 u64 *pdata = buf;
2467
2468 for (; cnt >= 8; cnt -= 8)
2469 mci_fifo_writeq(host->fifo_reg, *pdata++);
2470 buf = pdata;
2471 }
2472 /* put anything remaining in the part_buf */
2473 if (cnt) {
2474 dw_mci_set_part_bytes(host, buf, cnt);
2475 /* Push data if we have reached the expected data length */
2476 if ((data->bytes_xfered + init_cnt) ==
2477 (data->blksz * data->blocks))
2478 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2479 }
2480 }
2481
2482 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2483 {
2484 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2485 if (unlikely((unsigned long)buf & 0x7)) {
2486 while (cnt >= 8) {
2487 /* pull data from fifo into aligned buffer */
2488 u64 aligned_buf[16];
2489 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2490 int items = len >> 3;
2491 int i;
2492
2493 for (i = 0; i < items; ++i)
2494 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2495
2496 /* memcpy from aligned buffer into output buffer */
2497 memcpy(buf, aligned_buf, len);
2498 buf += len;
2499 cnt -= len;
2500 }
2501 } else
2502 #endif
2503 {
2504 u64 *pdata = buf;
2505
2506 for (; cnt >= 8; cnt -= 8)
2507 *pdata++ = mci_fifo_readq(host->fifo_reg);
2508 buf = pdata;
2509 }
2510 if (cnt) {
2511 host->part_buf = mci_fifo_readq(host->fifo_reg);
2512 dw_mci_pull_final_bytes(host, buf, cnt);
2513 }
2514 }
2515
2516 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2517 {
2518 int len;
2519
2520 /* get remaining partial bytes */
2521 len = dw_mci_pull_part_bytes(host, buf, cnt);
2522 if (unlikely(len == cnt))
2523 return;
2524 buf += len;
2525 cnt -= len;
2526
2527 /* get the rest of the data */
2528 host->pull_data(host, buf, cnt);
2529 }
2530
2531 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2532 {
2533 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2534 void *buf;
2535 unsigned int offset;
2536 struct mmc_data *data = host->data;
2537 int shift = host->data_shift;
2538 u32 status;
2539 unsigned int len;
2540 unsigned int remain, fcnt;
2541
2542 do {
2543 if (!sg_miter_next(sg_miter))
2544 goto done;
2545
2546 host->sg = sg_miter->piter.sg;
2547 buf = sg_miter->addr;
2548 remain = sg_miter->length;
2549 offset = 0;
2550
2551 do {
2552 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2553 << shift) + host->part_buf_count;
2554 len = min(remain, fcnt);
2555 if (!len)
2556 break;
2557 dw_mci_pull_data(host, (void *)(buf + offset), len);
2558 data->bytes_xfered += len;
2559 offset += len;
2560 remain -= len;
2561 } while (remain);
2562
2563 sg_miter->consumed = offset;
2564 status = mci_readl(host, MINTSTS);
2565 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2566 /* if the RXDR is ready read again */
2567 } while ((status & SDMMC_INT_RXDR) ||
2568 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2569
2570 if (!remain) {
2571 if (!sg_miter_next(sg_miter))
2572 goto done;
2573 sg_miter->consumed = 0;
2574 }
2575 sg_miter_stop(sg_miter);
2576 return;
2577
2578 done:
2579 sg_miter_stop(sg_miter);
2580 host->sg = NULL;
2581 smp_wmb(); /* drain writebuffer */
2582 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2583 }
2584
2585 static void dw_mci_write_data_pio(struct dw_mci *host)
2586 {
2587 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2588 void *buf;
2589 unsigned int offset;
2590 struct mmc_data *data = host->data;
2591 int shift = host->data_shift;
2592 u32 status;
2593 unsigned int len;
2594 unsigned int fifo_depth = host->fifo_depth;
2595 unsigned int remain, fcnt;
2596
2597 do {
2598 if (!sg_miter_next(sg_miter))
2599 goto done;
2600
2601 host->sg = sg_miter->piter.sg;
2602 buf = sg_miter->addr;
2603 remain = sg_miter->length;
2604 offset = 0;
2605
2606 do {
2607 fcnt = ((fifo_depth -
2608 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2609 << shift) - host->part_buf_count;
2610 len = min(remain, fcnt);
2611 if (!len)
2612 break;
2613 host->push_data(host, (void *)(buf + offset), len);
2614 data->bytes_xfered += len;
2615 offset += len;
2616 remain -= len;
2617 } while (remain);
2618
2619 sg_miter->consumed = offset;
2620 status = mci_readl(host, MINTSTS);
2621 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2622 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2623
2624 if (!remain) {
2625 if (!sg_miter_next(sg_miter))
2626 goto done;
2627 sg_miter->consumed = 0;
2628 }
2629 sg_miter_stop(sg_miter);
2630 return;
2631
2632 done:
2633 sg_miter_stop(sg_miter);
2634 host->sg = NULL;
2635 smp_wmb(); /* drain writebuffer */
2636 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2637 }
2638
2639 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2640 {
2641 del_timer(&host->cto_timer);
2642
2643 if (!host->cmd_status)
2644 host->cmd_status = status;
2645
2646 smp_wmb(); /* drain writebuffer */
2647
2648 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2649 tasklet_schedule(&host->tasklet);
2650 }
2651
2652 static void dw_mci_handle_cd(struct dw_mci *host)
2653 {
2654 struct dw_mci_slot *slot = host->slot;
2655
2656 if (slot->mmc->ops->card_event)
2657 slot->mmc->ops->card_event(slot->mmc);
2658 mmc_detect_change(slot->mmc,
2659 msecs_to_jiffies(host->pdata->detect_delay_ms));
2660 }
2661
2662 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2663 {
2664 struct dw_mci *host = dev_id;
2665 u32 pending;
2666 struct dw_mci_slot *slot = host->slot;
2667 unsigned long irqflags;
2668
2669 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2670
2671 if (pending) {
2672 /* Check volt switch first, since it can look like an error */
2673 if ((host->state == STATE_SENDING_CMD11) &&
2674 (pending & SDMMC_INT_VOLT_SWITCH)) {
2675 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2676 pending &= ~SDMMC_INT_VOLT_SWITCH;
2677
2678 /*
2679 * Hold the lock; we know cmd11_timer can't be kicked
2680 * off after the lock is released, so safe to delete.
2681 */
2682 spin_lock_irqsave(&host->irq_lock, irqflags);
2683 dw_mci_cmd_interrupt(host, pending);
2684 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2685
2686 del_timer(&host->cmd11_timer);
2687 }
2688
2689 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2690 spin_lock_irqsave(&host->irq_lock, irqflags);
2691
2692 del_timer(&host->cto_timer);
2693 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2694 host->cmd_status = pending;
2695 smp_wmb(); /* drain writebuffer */
2696 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2697
2698 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2699 }
2700
2701 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2702 /* if there is an error report DATA_ERROR */
2703 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2704 host->data_status = pending;
2705 smp_wmb(); /* drain writebuffer */
2706 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2707 tasklet_schedule(&host->tasklet);
2708 }
2709
2710 if (pending & SDMMC_INT_DATA_OVER) {
2711 spin_lock_irqsave(&host->irq_lock, irqflags);
2712
2713 del_timer(&host->dto_timer);
2714
2715 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2716 if (!host->data_status)
2717 host->data_status = pending;
2718 smp_wmb(); /* drain writebuffer */
2719 if (host->dir_status == DW_MCI_RECV_STATUS) {
2720 if (host->sg != NULL)
2721 dw_mci_read_data_pio(host, true);
2722 }
2723 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2724 tasklet_schedule(&host->tasklet);
2725
2726 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2727 }
2728
2729 if (pending & SDMMC_INT_RXDR) {
2730 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2731 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2732 dw_mci_read_data_pio(host, false);
2733 }
2734
2735 if (pending & SDMMC_INT_TXDR) {
2736 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2737 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2738 dw_mci_write_data_pio(host);
2739 }
2740
2741 if (pending & SDMMC_INT_CMD_DONE) {
2742 spin_lock_irqsave(&host->irq_lock, irqflags);
2743
2744 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2745 dw_mci_cmd_interrupt(host, pending);
2746
2747 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2748 }
2749
2750 if (pending & SDMMC_INT_CD) {
2751 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2752 dw_mci_handle_cd(host);
2753 }
2754
2755 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2756 mci_writel(host, RINTSTS,
2757 SDMMC_INT_SDIO(slot->sdio_id));
2758 __dw_mci_enable_sdio_irq(slot, 0);
2759 sdio_signal_irq(slot->mmc);
2760 }
2761
2762 }
2763
2764 if (host->use_dma != TRANS_MODE_IDMAC)
2765 return IRQ_HANDLED;
2766
2767 /* Handle IDMA interrupts */
2768 if (host->dma_64bit_address == 1) {
2769 pending = mci_readl(host, IDSTS64);
2770 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2771 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2772 SDMMC_IDMAC_INT_RI);
2773 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2774 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2775 host->dma_ops->complete((void *)host);
2776 }
2777 } else {
2778 pending = mci_readl(host, IDSTS);
2779 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2780 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2781 SDMMC_IDMAC_INT_RI);
2782 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2783 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2784 host->dma_ops->complete((void *)host);
2785 }
2786 }
2787
2788 return IRQ_HANDLED;
2789 }
2790
2791 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2792 {
2793 struct dw_mci *host = slot->host;
2794 const struct dw_mci_drv_data *drv_data = host->drv_data;
2795 struct mmc_host *mmc = slot->mmc;
2796 int ctrl_id;
2797
2798 if (host->pdata->caps)
2799 mmc->caps = host->pdata->caps;
2800
2801 /*
2802 * Support MMC_CAP_ERASE by default.
2803 * It needs to use trim/discard/erase commands.
2804 */
2805 mmc->caps |= MMC_CAP_ERASE;
2806
2807 if (host->pdata->pm_caps)
2808 mmc->pm_caps = host->pdata->pm_caps;
2809
2810 if (host->dev->of_node) {
2811 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2812 if (ctrl_id < 0)
2813 ctrl_id = 0;
2814 } else {
2815 ctrl_id = to_platform_device(host->dev)->id;
2816 }
2817
2818 if (drv_data && drv_data->caps) {
2819 if (ctrl_id >= drv_data->num_caps) {
2820 dev_err(host->dev, "invalid controller id %d\n",
2821 ctrl_id);
2822 return -EINVAL;
2823 }
2824 mmc->caps |= drv_data->caps[ctrl_id];
2825 }
2826
2827 if (host->pdata->caps2)
2828 mmc->caps2 = host->pdata->caps2;
2829
2830 /* Process SDIO IRQs through the sdio_irq_work. */
2831 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2832 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2833
2834 return 0;
2835 }
2836
2837 static int dw_mci_init_slot(struct dw_mci *host)
2838 {
2839 struct mmc_host *mmc;
2840 struct dw_mci_slot *slot;
2841 int ret;
2842 u32 freq[2];
2843
2844 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2845 if (!mmc)
2846 return -ENOMEM;
2847
2848 slot = mmc_priv(mmc);
2849 slot->id = 0;
2850 slot->sdio_id = host->sdio_id0 + slot->id;
2851 slot->mmc = mmc;
2852 slot->host = host;
2853 host->slot = slot;
2854
2855 mmc->ops = &dw_mci_ops;
2856 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2857 freq, 2)) {
2858 mmc->f_min = DW_MCI_FREQ_MIN;
2859 mmc->f_max = DW_MCI_FREQ_MAX;
2860 } else {
2861 dev_info(host->dev,
2862 "'clock-freq-min-max' property was deprecated.\n");
2863 mmc->f_min = freq[0];
2864 mmc->f_max = freq[1];
2865 }
2866
2867 /*if there are external regulators, get them*/
2868 ret = mmc_regulator_get_supply(mmc);
2869 if (ret)
2870 goto err_host_allocated;
2871
2872 if (!mmc->ocr_avail)
2873 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2874
2875 ret = mmc_of_parse(mmc);
2876 if (ret)
2877 goto err_host_allocated;
2878
2879 ret = dw_mci_init_slot_caps(slot);
2880 if (ret)
2881 goto err_host_allocated;
2882
2883 /* Useful defaults if platform data is unset. */
2884 if (host->use_dma == TRANS_MODE_IDMAC) {
2885 mmc->max_segs = host->ring_size;
2886 mmc->max_blk_size = 65535;
2887 mmc->max_seg_size = 0x1000;
2888 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2889 mmc->max_blk_count = mmc->max_req_size / 512;
2890 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2891 mmc->max_segs = 64;
2892 mmc->max_blk_size = 65535;
2893 mmc->max_blk_count = 65535;
2894 mmc->max_req_size =
2895 mmc->max_blk_size * mmc->max_blk_count;
2896 mmc->max_seg_size = mmc->max_req_size;
2897 } else {
2898 /* TRANS_MODE_PIO */
2899 mmc->max_segs = 64;
2900 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2901 mmc->max_blk_count = 512;
2902 mmc->max_req_size = mmc->max_blk_size *
2903 mmc->max_blk_count;
2904 mmc->max_seg_size = mmc->max_req_size;
2905 }
2906
2907 dw_mci_get_cd(mmc);
2908
2909 ret = mmc_add_host(mmc);
2910 if (ret)
2911 goto err_host_allocated;
2912
2913 #if defined(CONFIG_DEBUG_FS)
2914 dw_mci_init_debugfs(slot);
2915 #endif
2916
2917 return 0;
2918
2919 err_host_allocated:
2920 mmc_free_host(mmc);
2921 return ret;
2922 }
2923
2924 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2925 {
2926 /* Debugfs stuff is cleaned up by mmc core */
2927 mmc_remove_host(slot->mmc);
2928 slot->host->slot = NULL;
2929 mmc_free_host(slot->mmc);
2930 }
2931
2932 static void dw_mci_init_dma(struct dw_mci *host)
2933 {
2934 int addr_config;
2935 struct device *dev = host->dev;
2936
2937 /*
2938 * Check tansfer mode from HCON[17:16]
2939 * Clear the ambiguous description of dw_mmc databook:
2940 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2941 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2942 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2943 * 2b'11: Non DW DMA Interface -> pio only
2944 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2945 * simpler request/acknowledge handshake mechanism and both of them
2946 * are regarded as external dma master for dw_mmc.
2947 */
2948 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2949 if (host->use_dma == DMA_INTERFACE_IDMA) {
2950 host->use_dma = TRANS_MODE_IDMAC;
2951 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2952 host->use_dma == DMA_INTERFACE_GDMA) {
2953 host->use_dma = TRANS_MODE_EDMAC;
2954 } else {
2955 goto no_dma;
2956 }
2957
2958 /* Determine which DMA interface to use */
2959 if (host->use_dma == TRANS_MODE_IDMAC) {
2960 /*
2961 * Check ADDR_CONFIG bit in HCON to find
2962 * IDMAC address bus width
2963 */
2964 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2965
2966 if (addr_config == 1) {
2967 /* host supports IDMAC in 64-bit address mode */
2968 host->dma_64bit_address = 1;
2969 dev_info(host->dev,
2970 "IDMAC supports 64-bit address mode.\n");
2971 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2972 dma_set_coherent_mask(host->dev,
2973 DMA_BIT_MASK(64));
2974 } else {
2975 /* host supports IDMAC in 32-bit address mode */
2976 host->dma_64bit_address = 0;
2977 dev_info(host->dev,
2978 "IDMAC supports 32-bit address mode.\n");
2979 }
2980
2981 /* Alloc memory for sg translation */
2982 host->sg_cpu = dmam_alloc_coherent(host->dev,
2983 DESC_RING_BUF_SZ,
2984 &host->sg_dma, GFP_KERNEL);
2985 if (!host->sg_cpu) {
2986 dev_err(host->dev,
2987 "%s: could not alloc DMA memory\n",
2988 __func__);
2989 goto no_dma;
2990 }
2991
2992 host->dma_ops = &dw_mci_idmac_ops;
2993 dev_info(host->dev, "Using internal DMA controller.\n");
2994 } else {
2995 /* TRANS_MODE_EDMAC: check dma bindings again */
2996 if ((device_property_read_string_array(dev, "dma-names",
2997 NULL, 0) < 0) ||
2998 !device_property_present(dev, "dmas")) {
2999 goto no_dma;
3000 }
3001 host->dma_ops = &dw_mci_edmac_ops;
3002 dev_info(host->dev, "Using external DMA controller.\n");
3003 }
3004
3005 if (host->dma_ops->init && host->dma_ops->start &&
3006 host->dma_ops->stop && host->dma_ops->cleanup) {
3007 if (host->dma_ops->init(host)) {
3008 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3009 __func__);
3010 goto no_dma;
3011 }
3012 } else {
3013 dev_err(host->dev, "DMA initialization not found.\n");
3014 goto no_dma;
3015 }
3016
3017 return;
3018
3019 no_dma:
3020 dev_info(host->dev, "Using PIO mode.\n");
3021 host->use_dma = TRANS_MODE_PIO;
3022 }
3023
3024 static void dw_mci_cmd11_timer(struct timer_list *t)
3025 {
3026 struct dw_mci *host = from_timer(host, t, cmd11_timer);
3027
3028 if (host->state != STATE_SENDING_CMD11) {
3029 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3030 return;
3031 }
3032
3033 host->cmd_status = SDMMC_INT_RTO;
3034 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3035 tasklet_schedule(&host->tasklet);
3036 }
3037
3038 static void dw_mci_cto_timer(struct timer_list *t)
3039 {
3040 struct dw_mci *host = from_timer(host, t, cto_timer);
3041 unsigned long irqflags;
3042 u32 pending;
3043
3044 spin_lock_irqsave(&host->irq_lock, irqflags);
3045
3046 /*
3047 * If somehow we have very bad interrupt latency it's remotely possible
3048 * that the timer could fire while the interrupt is still pending or
3049 * while the interrupt is midway through running. Let's be paranoid
3050 * and detect those two cases. Note that this is paranoia is somewhat
3051 * justified because in this function we don't actually cancel the
3052 * pending command in the controller--we just assume it will never come.
3053 */
3054 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3055 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3056 /* The interrupt should fire; no need to act but we can warn */
3057 dev_warn(host->dev, "Unexpected interrupt latency\n");
3058 goto exit;
3059 }
3060 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3061 /* Presumably interrupt handler couldn't delete the timer */
3062 dev_warn(host->dev, "CTO timeout when already completed\n");
3063 goto exit;
3064 }
3065
3066 /*
3067 * Continued paranoia to make sure we're in the state we expect.
3068 * This paranoia isn't really justified but it seems good to be safe.
3069 */
3070 switch (host->state) {
3071 case STATE_SENDING_CMD11:
3072 case STATE_SENDING_CMD:
3073 case STATE_SENDING_STOP:
3074 /*
3075 * If CMD_DONE interrupt does NOT come in sending command
3076 * state, we should notify the driver to terminate current
3077 * transfer and report a command timeout to the core.
3078 */
3079 host->cmd_status = SDMMC_INT_RTO;
3080 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3081 tasklet_schedule(&host->tasklet);
3082 break;
3083 default:
3084 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3085 host->state);
3086 break;
3087 }
3088
3089 exit:
3090 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3091 }
3092
3093 static void dw_mci_dto_timer(struct timer_list *t)
3094 {
3095 struct dw_mci *host = from_timer(host, t, dto_timer);
3096 unsigned long irqflags;
3097 u32 pending;
3098
3099 spin_lock_irqsave(&host->irq_lock, irqflags);
3100
3101 /*
3102 * The DTO timer is much longer than the CTO timer, so it's even less
3103 * likely that we'll these cases, but it pays to be paranoid.
3104 */
3105 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3106 if (pending & SDMMC_INT_DATA_OVER) {
3107 /* The interrupt should fire; no need to act but we can warn */
3108 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3109 goto exit;
3110 }
3111 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3112 /* Presumably interrupt handler couldn't delete the timer */
3113 dev_warn(host->dev, "DTO timeout when already completed\n");
3114 goto exit;
3115 }
3116
3117 /*
3118 * Continued paranoia to make sure we're in the state we expect.
3119 * This paranoia isn't really justified but it seems good to be safe.
3120 */
3121 switch (host->state) {
3122 case STATE_SENDING_DATA:
3123 case STATE_DATA_BUSY:
3124 /*
3125 * If DTO interrupt does NOT come in sending data state,
3126 * we should notify the driver to terminate current transfer
3127 * and report a data timeout to the core.
3128 */
3129 host->data_status = SDMMC_INT_DRTO;
3130 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3131 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3132 tasklet_schedule(&host->tasklet);
3133 break;
3134 default:
3135 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3136 host->state);
3137 break;
3138 }
3139
3140 exit:
3141 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3142 }
3143
3144 #ifdef CONFIG_OF
3145 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3146 {
3147 struct dw_mci_board *pdata;
3148 struct device *dev = host->dev;
3149 const struct dw_mci_drv_data *drv_data = host->drv_data;
3150 int ret;
3151 u32 clock_frequency;
3152
3153 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3154 if (!pdata)
3155 return ERR_PTR(-ENOMEM);
3156
3157 /* find reset controller when exist */
3158 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3159 if (IS_ERR(pdata->rstc)) {
3160 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3161 return ERR_PTR(-EPROBE_DEFER);
3162 }
3163
3164 /* find out number of slots supported */
3165 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
3166 dev_info(dev, "'num-slots' was deprecated.\n");
3167
3168 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3169 dev_info(dev,
3170 "fifo-depth property not found, using value of FIFOTH register as default\n");
3171
3172 device_property_read_u32(dev, "card-detect-delay",
3173 &pdata->detect_delay_ms);
3174
3175 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3176
3177 if (device_property_present(dev, "fifo-watermark-aligned"))
3178 host->wm_aligned = true;
3179
3180 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3181 pdata->bus_hz = clock_frequency;
3182
3183 if (drv_data && drv_data->parse_dt) {
3184 ret = drv_data->parse_dt(host);
3185 if (ret)
3186 return ERR_PTR(ret);
3187 }
3188
3189 return pdata;
3190 }
3191
3192 #else /* CONFIG_OF */
3193 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3194 {
3195 return ERR_PTR(-EINVAL);
3196 }
3197 #endif /* CONFIG_OF */
3198
3199 static void dw_mci_enable_cd(struct dw_mci *host)
3200 {
3201 unsigned long irqflags;
3202 u32 temp;
3203
3204 /*
3205 * No need for CD if all slots have a non-error GPIO
3206 * as well as broken card detection is found.
3207 */
3208 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3209 return;
3210
3211 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3212 spin_lock_irqsave(&host->irq_lock, irqflags);
3213 temp = mci_readl(host, INTMASK);
3214 temp |= SDMMC_INT_CD;
3215 mci_writel(host, INTMASK, temp);
3216 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3217 }
3218 }
3219
3220 int dw_mci_probe(struct dw_mci *host)
3221 {
3222 const struct dw_mci_drv_data *drv_data = host->drv_data;
3223 int width, i, ret = 0;
3224 u32 fifo_size;
3225
3226 if (!host->pdata) {
3227 host->pdata = dw_mci_parse_dt(host);
3228 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3229 return -EPROBE_DEFER;
3230 } else if (IS_ERR(host->pdata)) {
3231 dev_err(host->dev, "platform data not available\n");
3232 return -EINVAL;
3233 }
3234 }
3235
3236 host->biu_clk = devm_clk_get(host->dev, "biu");
3237 if (IS_ERR(host->biu_clk)) {
3238 dev_dbg(host->dev, "biu clock not available\n");
3239 } else {
3240 ret = clk_prepare_enable(host->biu_clk);
3241 if (ret) {
3242 dev_err(host->dev, "failed to enable biu clock\n");
3243 return ret;
3244 }
3245 }
3246
3247 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3248 if (IS_ERR(host->ciu_clk)) {
3249 dev_dbg(host->dev, "ciu clock not available\n");
3250 host->bus_hz = host->pdata->bus_hz;
3251 } else {
3252 ret = clk_prepare_enable(host->ciu_clk);
3253 if (ret) {
3254 dev_err(host->dev, "failed to enable ciu clock\n");
3255 goto err_clk_biu;
3256 }
3257
3258 if (host->pdata->bus_hz) {
3259 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3260 if (ret)
3261 dev_warn(host->dev,
3262 "Unable to set bus rate to %uHz\n",
3263 host->pdata->bus_hz);
3264 }
3265 host->bus_hz = clk_get_rate(host->ciu_clk);
3266 }
3267
3268 if (!host->bus_hz) {
3269 dev_err(host->dev,
3270 "Platform data must supply bus speed\n");
3271 ret = -ENODEV;
3272 goto err_clk_ciu;
3273 }
3274
3275 if (!IS_ERR(host->pdata->rstc)) {
3276 reset_control_assert(host->pdata->rstc);
3277 usleep_range(10, 50);
3278 reset_control_deassert(host->pdata->rstc);
3279 }
3280
3281 if (drv_data && drv_data->init) {
3282 ret = drv_data->init(host);
3283 if (ret) {
3284 dev_err(host->dev,
3285 "implementation specific init failed\n");
3286 goto err_clk_ciu;
3287 }
3288 }
3289
3290 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3291 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3292 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3293
3294 spin_lock_init(&host->lock);
3295 spin_lock_init(&host->irq_lock);
3296 INIT_LIST_HEAD(&host->queue);
3297
3298 /*
3299 * Get the host data width - this assumes that HCON has been set with
3300 * the correct values.
3301 */
3302 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3303 if (!i) {
3304 host->push_data = dw_mci_push_data16;
3305 host->pull_data = dw_mci_pull_data16;
3306 width = 16;
3307 host->data_shift = 1;
3308 } else if (i == 2) {
3309 host->push_data = dw_mci_push_data64;
3310 host->pull_data = dw_mci_pull_data64;
3311 width = 64;
3312 host->data_shift = 3;
3313 } else {
3314 /* Check for a reserved value, and warn if it is */
3315 WARN((i != 1),
3316 "HCON reports a reserved host data width!\n"
3317 "Defaulting to 32-bit access.\n");
3318 host->push_data = dw_mci_push_data32;
3319 host->pull_data = dw_mci_pull_data32;
3320 width = 32;
3321 host->data_shift = 2;
3322 }
3323
3324 /* Reset all blocks */
3325 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3326 ret = -ENODEV;
3327 goto err_clk_ciu;
3328 }
3329
3330 host->dma_ops = host->pdata->dma_ops;
3331 dw_mci_init_dma(host);
3332
3333 /* Clear the interrupts for the host controller */
3334 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3335 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3336
3337 /* Put in max timeout */
3338 mci_writel(host, TMOUT, 0xFFFFFFFF);
3339
3340 /*
3341 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3342 * Tx Mark = fifo_size / 2 DMA Size = 8
3343 */
3344 if (!host->pdata->fifo_depth) {
3345 /*
3346 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3347 * have been overwritten by the bootloader, just like we're
3348 * about to do, so if you know the value for your hardware, you
3349 * should put it in the platform data.
3350 */
3351 fifo_size = mci_readl(host, FIFOTH);
3352 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3353 } else {
3354 fifo_size = host->pdata->fifo_depth;
3355 }
3356 host->fifo_depth = fifo_size;
3357 host->fifoth_val =
3358 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3359 mci_writel(host, FIFOTH, host->fifoth_val);
3360
3361 /* disable clock to CIU */
3362 mci_writel(host, CLKENA, 0);
3363 mci_writel(host, CLKSRC, 0);
3364
3365 /*
3366 * In 2.40a spec, Data offset is changed.
3367 * Need to check the version-id and set data-offset for DATA register.
3368 */
3369 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3370 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3371
3372 if (host->data_addr_override)
3373 host->fifo_reg = host->regs + host->data_addr_override;
3374 else if (host->verid < DW_MMC_240A)
3375 host->fifo_reg = host->regs + DATA_OFFSET;
3376 else
3377 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3378
3379 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3380 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3381 host->irq_flags, "dw-mci", host);
3382 if (ret)
3383 goto err_dmaunmap;
3384
3385 /*
3386 * Enable interrupts for command done, data over, data empty,
3387 * receive ready and error such as transmit, receive timeout, crc error
3388 */
3389 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3390 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3391 DW_MCI_ERROR_FLAGS);
3392 /* Enable mci interrupt */
3393 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3394
3395 dev_info(host->dev,
3396 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3397 host->irq, width, fifo_size);
3398
3399 /* We need at least one slot to succeed */
3400 ret = dw_mci_init_slot(host);
3401 if (ret) {
3402 dev_dbg(host->dev, "slot %d init failed\n", i);
3403 goto err_dmaunmap;
3404 }
3405
3406 /* Now that slots are all setup, we can enable card detect */
3407 dw_mci_enable_cd(host);
3408
3409 return 0;
3410
3411 err_dmaunmap:
3412 if (host->use_dma && host->dma_ops->exit)
3413 host->dma_ops->exit(host);
3414
3415 if (!IS_ERR(host->pdata->rstc))
3416 reset_control_assert(host->pdata->rstc);
3417
3418 err_clk_ciu:
3419 clk_disable_unprepare(host->ciu_clk);
3420
3421 err_clk_biu:
3422 clk_disable_unprepare(host->biu_clk);
3423
3424 return ret;
3425 }
3426 EXPORT_SYMBOL(dw_mci_probe);
3427
3428 void dw_mci_remove(struct dw_mci *host)
3429 {
3430 dev_dbg(host->dev, "remove slot\n");
3431 if (host->slot)
3432 dw_mci_cleanup_slot(host->slot);
3433
3434 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3435 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3436
3437 /* disable clock to CIU */
3438 mci_writel(host, CLKENA, 0);
3439 mci_writel(host, CLKSRC, 0);
3440
3441 if (host->use_dma && host->dma_ops->exit)
3442 host->dma_ops->exit(host);
3443
3444 if (!IS_ERR(host->pdata->rstc))
3445 reset_control_assert(host->pdata->rstc);
3446
3447 clk_disable_unprepare(host->ciu_clk);
3448 clk_disable_unprepare(host->biu_clk);
3449 }
3450 EXPORT_SYMBOL(dw_mci_remove);
3451
3452
3453
3454 #ifdef CONFIG_PM
3455 int dw_mci_runtime_suspend(struct device *dev)
3456 {
3457 struct dw_mci *host = dev_get_drvdata(dev);
3458
3459 if (host->use_dma && host->dma_ops->exit)
3460 host->dma_ops->exit(host);
3461
3462 clk_disable_unprepare(host->ciu_clk);
3463
3464 if (host->slot &&
3465 (mmc_can_gpio_cd(host->slot->mmc) ||
3466 !mmc_card_is_removable(host->slot->mmc)))
3467 clk_disable_unprepare(host->biu_clk);
3468
3469 return 0;
3470 }
3471 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3472
3473 int dw_mci_runtime_resume(struct device *dev)
3474 {
3475 int ret = 0;
3476 struct dw_mci *host = dev_get_drvdata(dev);
3477
3478 if (host->slot &&
3479 (mmc_can_gpio_cd(host->slot->mmc) ||
3480 !mmc_card_is_removable(host->slot->mmc))) {
3481 ret = clk_prepare_enable(host->biu_clk);
3482 if (ret)
3483 return ret;
3484 }
3485
3486 ret = clk_prepare_enable(host->ciu_clk);
3487 if (ret)
3488 goto err;
3489
3490 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3491 clk_disable_unprepare(host->ciu_clk);
3492 ret = -ENODEV;
3493 goto err;
3494 }
3495
3496 if (host->use_dma && host->dma_ops->init)
3497 host->dma_ops->init(host);
3498
3499 /*
3500 * Restore the initial value at FIFOTH register
3501 * And Invalidate the prev_blksz with zero
3502 */
3503 mci_writel(host, FIFOTH, host->fifoth_val);
3504 host->prev_blksz = 0;
3505
3506 /* Put in max timeout */
3507 mci_writel(host, TMOUT, 0xFFFFFFFF);
3508
3509 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3510 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3511 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3512 DW_MCI_ERROR_FLAGS);
3513 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3514
3515
3516 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3517 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3518
3519 /* Force setup bus to guarantee available clock output */
3520 dw_mci_setup_bus(host->slot, true);
3521
3522 /* Now that slots are all setup, we can enable card detect */
3523 dw_mci_enable_cd(host);
3524
3525 return 0;
3526
3527 err:
3528 if (host->slot &&
3529 (mmc_can_gpio_cd(host->slot->mmc) ||
3530 !mmc_card_is_removable(host->slot->mmc)))
3531 clk_disable_unprepare(host->biu_clk);
3532
3533 return ret;
3534 }
3535 EXPORT_SYMBOL(dw_mci_runtime_resume);
3536 #endif /* CONFIG_PM */
3537
3538 static int __init dw_mci_init(void)
3539 {
3540 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3541 return 0;
3542 }
3543
3544 static void __exit dw_mci_exit(void)
3545 {
3546 }
3547
3548 module_init(dw_mci_init);
3549 module_exit(dw_mci_exit);
3550
3551 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3552 MODULE_AUTHOR("NXP Semiconductor VietNam");
3553 MODULE_AUTHOR("Imagination Technologies Ltd");
3554 MODULE_LICENSE("GPL v2");
ubuntu-bionic-kernel mirror