2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/ioport.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
35 #include <linux/clk.h>
36 #include <linux/clk-provider.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/reset.h>
39 #include <linux/interrupt.h>
40 #include <linux/bitfield.h>
41 #include <linux/pinctrl/consumer.h>
43 #define DRIVER_NAME "meson-gx-mmc"
45 #define SD_EMMC_CLOCK 0x0
46 #define CLK_DIV_MASK GENMASK(5, 0)
47 #define CLK_SRC_MASK GENMASK(7, 6)
48 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
49 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
50 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
51 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
52 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
53 #define CLK_V2_ALWAYS_ON BIT(24)
55 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
56 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
57 #define CLK_V3_ALWAYS_ON BIT(28)
59 #define CLK_DELAY_STEP_PS 200
60 #define CLK_PHASE_STEP 30
61 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
63 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
64 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
65 #define CLK_ALWAYS_ON(h) (h->data->always_on)
67 #define SD_EMMC_DELAY 0x4
68 #define SD_EMMC_ADJUST 0x8
69 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
70 #define ADJUST_DS_EN BIT(15)
71 #define ADJUST_ADJ_EN BIT(13)
73 #define SD_EMMC_DELAY1 0x4
74 #define SD_EMMC_DELAY2 0x8
75 #define SD_EMMC_V3_ADJUST 0xc
77 #define SD_EMMC_CALOUT 0x10
78 #define SD_EMMC_START 0x40
79 #define START_DESC_INIT BIT(0)
80 #define START_DESC_BUSY BIT(1)
81 #define START_DESC_ADDR_MASK GENMASK(31, 2)
83 #define SD_EMMC_CFG 0x44
84 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
85 #define CFG_BUS_WIDTH_1 0x0
86 #define CFG_BUS_WIDTH_4 0x1
87 #define CFG_BUS_WIDTH_8 0x2
88 #define CFG_DDR BIT(2)
89 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
90 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
91 #define CFG_RC_CC_MASK GENMASK(15, 12)
92 #define CFG_STOP_CLOCK BIT(22)
93 #define CFG_CLK_ALWAYS_ON BIT(18)
94 #define CFG_CHK_DS BIT(20)
95 #define CFG_AUTO_CLK BIT(23)
96 #define CFG_ERR_ABORT BIT(27)
98 #define SD_EMMC_STATUS 0x48
99 #define STATUS_BUSY BIT(31)
100 #define STATUS_DESC_BUSY BIT(30)
101 #define STATUS_DATI GENMASK(23, 16)
103 #define SD_EMMC_IRQ_EN 0x4c
104 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
105 #define IRQ_TXD_ERR BIT(8)
106 #define IRQ_DESC_ERR BIT(9)
107 #define IRQ_RESP_ERR BIT(10)
108 #define IRQ_CRC_ERR \
109 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
110 #define IRQ_RESP_TIMEOUT BIT(11)
111 #define IRQ_DESC_TIMEOUT BIT(12)
112 #define IRQ_TIMEOUTS \
113 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
114 #define IRQ_END_OF_CHAIN BIT(13)
115 #define IRQ_RESP_STATUS BIT(14)
116 #define IRQ_SDIO BIT(15)
117 #define IRQ_EN_MASK \
118 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
121 #define SD_EMMC_CMD_CFG 0x50
122 #define SD_EMMC_CMD_ARG 0x54
123 #define SD_EMMC_CMD_DAT 0x58
124 #define SD_EMMC_CMD_RSP 0x5c
125 #define SD_EMMC_CMD_RSP1 0x60
126 #define SD_EMMC_CMD_RSP2 0x64
127 #define SD_EMMC_CMD_RSP3 0x68
129 #define SD_EMMC_RXD 0x94
130 #define SD_EMMC_TXD 0x94
131 #define SD_EMMC_LAST_REG SD_EMMC_TXD
133 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
134 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
135 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
136 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
137 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
138 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
140 #define SD_EMMC_PRE_REQ_DONE BIT(0)
141 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
143 #define MUX_CLK_NUM_PARENTS 2
145 struct meson_mmc_data
{
146 unsigned int tx_delay_mask
;
147 unsigned int rx_delay_mask
;
148 unsigned int always_on
;
152 struct sd_emmc_desc
{
161 struct meson_mmc_data
*data
;
162 struct mmc_host
*mmc
;
163 struct mmc_command
*cmd
;
166 struct clk
*core_clk
;
170 unsigned long req_rate
;
172 struct pinctrl
*pinctrl
;
173 struct pinctrl_state
*pins_default
;
174 struct pinctrl_state
*pins_clk_gate
;
176 unsigned int bounce_buf_size
;
178 dma_addr_t bounce_dma_addr
;
179 struct sd_emmc_desc
*descs
;
180 dma_addr_t descs_dma_addr
;
187 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
188 #define CMD_CFG_BLOCK_MODE BIT(9)
189 #define CMD_CFG_R1B BIT(10)
190 #define CMD_CFG_END_OF_CHAIN BIT(11)
191 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
192 #define CMD_CFG_NO_RESP BIT(16)
193 #define CMD_CFG_NO_CMD BIT(17)
194 #define CMD_CFG_DATA_IO BIT(18)
195 #define CMD_CFG_DATA_WR BIT(19)
196 #define CMD_CFG_RESP_NOCRC BIT(20)
197 #define CMD_CFG_RESP_128 BIT(21)
198 #define CMD_CFG_RESP_NUM BIT(22)
199 #define CMD_CFG_DATA_NUM BIT(23)
200 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
201 #define CMD_CFG_ERROR BIT(30)
202 #define CMD_CFG_OWNER BIT(31)
204 #define CMD_DATA_MASK GENMASK(31, 2)
205 #define CMD_DATA_BIG_ENDIAN BIT(1)
206 #define CMD_DATA_SRAM BIT(0)
207 #define CMD_RESP_MASK GENMASK(31, 1)
208 #define CMD_RESP_SRAM BIT(0)
210 struct meson_mmc_phase
{
213 unsigned long phase_mask
;
214 unsigned long delay_mask
;
215 unsigned int delay_step_ps
;
218 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
220 static int meson_mmc_clk_get_phase(struct clk_hw
*hw
)
222 struct meson_mmc_phase
*mmc
= to_meson_mmc_phase(hw
);
223 unsigned int phase_num
= 1 << hweight_long(mmc
->phase_mask
);
224 unsigned long period_ps
, p
, d
;
228 val
= readl(mmc
->reg
);
229 p
= (val
& mmc
->phase_mask
) >> __ffs(mmc
->phase_mask
);
230 degrees
= p
* 360 / phase_num
;
232 if (mmc
->delay_mask
) {
233 period_ps
= DIV_ROUND_UP((unsigned long)NSEC_PER_SEC
* 1000,
234 clk_get_rate(hw
->clk
));
235 d
= (val
& mmc
->delay_mask
) >> __ffs(mmc
->delay_mask
);
236 degrees
+= d
* mmc
->delay_step_ps
* 360 / period_ps
;
243 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase
*mmc
,
249 val
= readl(mmc
->reg
);
250 val
&= ~mmc
->phase_mask
;
251 val
|= phase
<< __ffs(mmc
->phase_mask
);
253 if (mmc
->delay_mask
) {
254 val
&= ~mmc
->delay_mask
;
255 val
|= delay
<< __ffs(mmc
->delay_mask
);
258 writel(val
, mmc
->reg
);
261 static int meson_mmc_clk_set_phase(struct clk_hw
*hw
, int degrees
)
263 struct meson_mmc_phase
*mmc
= to_meson_mmc_phase(hw
);
264 unsigned int phase_num
= 1 << hweight_long(mmc
->phase_mask
);
265 unsigned long period_ps
, d
= 0, r
;
270 if (!mmc
->delay_mask
) {
271 p
= DIV_ROUND_CLOSEST_ULL(p
, 360 / phase_num
);
273 period_ps
= DIV_ROUND_UP((unsigned long)NSEC_PER_SEC
* 1000,
274 clk_get_rate(hw
->clk
));
276 /* First compute the phase index (p), the remainder (r) is the
277 * part we'll try to acheive using the delays (d).
279 r
= do_div(p
, 360 / phase_num
);
280 d
= DIV_ROUND_CLOSEST(r
* period_ps
,
281 360 * mmc
->delay_step_ps
);
282 d
= min(d
, mmc
->delay_mask
>> __ffs(mmc
->delay_mask
));
285 meson_mmc_apply_phase_delay(mmc
, p
, d
);
289 static const struct clk_ops meson_mmc_clk_phase_ops
= {
290 .get_phase
= meson_mmc_clk_get_phase
,
291 .set_phase
= meson_mmc_clk_set_phase
,
294 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data
*data
)
296 unsigned int timeout
= data
->timeout_ns
/ NSEC_PER_MSEC
;
299 return SD_EMMC_CMD_TIMEOUT_DATA
;
301 timeout
= roundup_pow_of_two(timeout
);
303 return min(timeout
, 32768U); /* max. 2^15 ms */
306 static struct mmc_command
*meson_mmc_get_next_command(struct mmc_command
*cmd
)
308 if (cmd
->opcode
== MMC_SET_BLOCK_COUNT
&& !cmd
->error
)
309 return cmd
->mrq
->cmd
;
310 else if (mmc_op_multi(cmd
->opcode
) &&
311 (!cmd
->mrq
->sbc
|| cmd
->error
|| cmd
->data
->error
))
312 return cmd
->mrq
->stop
;
317 static void meson_mmc_get_transfer_mode(struct mmc_host
*mmc
,
318 struct mmc_request
*mrq
)
320 struct mmc_data
*data
= mrq
->data
;
321 struct scatterlist
*sg
;
323 bool use_desc_chain_mode
= true;
326 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
327 * reported. For some strange reason this occurs in descriptor
328 * chain mode only. So let's fall back to bounce buffer mode
329 * for command SD_IO_RW_EXTENDED.
331 if (mrq
->cmd
->opcode
== SD_IO_RW_EXTENDED
)
334 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
)
335 /* check for 8 byte alignment */
336 if (sg
->offset
& 7) {
337 WARN_ONCE(1, "unaligned scatterlist buffer\n");
338 use_desc_chain_mode
= false;
342 if (use_desc_chain_mode
)
343 data
->host_cookie
|= SD_EMMC_DESC_CHAIN_MODE
;
346 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data
*data
)
348 return data
->host_cookie
& SD_EMMC_DESC_CHAIN_MODE
;
351 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data
*data
)
353 return data
&& data
->flags
& MMC_DATA_READ
&&
354 !meson_mmc_desc_chain_mode(data
);
357 static void meson_mmc_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
359 struct mmc_data
*data
= mrq
->data
;
364 meson_mmc_get_transfer_mode(mmc
, mrq
);
365 data
->host_cookie
|= SD_EMMC_PRE_REQ_DONE
;
367 if (!meson_mmc_desc_chain_mode(data
))
370 data
->sg_count
= dma_map_sg(mmc_dev(mmc
), data
->sg
, data
->sg_len
,
371 mmc_get_dma_dir(data
));
373 dev_err(mmc_dev(mmc
), "dma_map_sg failed");
376 static void meson_mmc_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
379 struct mmc_data
*data
= mrq
->data
;
381 if (data
&& meson_mmc_desc_chain_mode(data
) && data
->sg_count
)
382 dma_unmap_sg(mmc_dev(mmc
), data
->sg
, data
->sg_len
,
383 mmc_get_dma_dir(data
));
386 static bool meson_mmc_timing_is_ddr(struct mmc_ios
*ios
)
388 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
389 ios
->timing
== MMC_TIMING_UHS_DDR50
||
390 ios
->timing
== MMC_TIMING_MMC_HS400
)
397 * Gating the clock on this controller is tricky. It seems the mmc clock
398 * is also used by the controller. It may crash during some operation if the
399 * clock is stopped. The safest thing to do, whenever possible, is to keep
400 * clock running at stop it at the pad using the pinmux.
402 static void meson_mmc_clk_gate(struct meson_host
*host
)
406 if (host
->pins_clk_gate
) {
407 pinctrl_select_state(host
->pinctrl
, host
->pins_clk_gate
);
410 * If the pinmux is not provided - default to the classic and
413 cfg
= readl(host
->regs
+ SD_EMMC_CFG
);
414 cfg
|= CFG_STOP_CLOCK
;
415 writel(cfg
, host
->regs
+ SD_EMMC_CFG
);
419 static void meson_mmc_clk_ungate(struct meson_host
*host
)
423 if (host
->pins_clk_gate
)
424 pinctrl_select_state(host
->pinctrl
, host
->pins_default
);
426 /* Make sure the clock is not stopped in the controller */
427 cfg
= readl(host
->regs
+ SD_EMMC_CFG
);
428 cfg
&= ~CFG_STOP_CLOCK
;
429 writel(cfg
, host
->regs
+ SD_EMMC_CFG
);
432 static int meson_mmc_clk_set(struct meson_host
*host
, struct mmc_ios
*ios
)
434 struct mmc_host
*mmc
= host
->mmc
;
435 unsigned long rate
= ios
->clock
;
439 /* DDR modes require higher module clock */
440 if (meson_mmc_timing_is_ddr(ios
))
443 /* Same request - bail-out */
444 if (host
->req_rate
== rate
)
448 meson_mmc_clk_gate(host
);
452 mmc
->actual_clock
= 0;
453 /* return with clock being stopped */
457 /* Stop the clock during rate change to avoid glitches */
458 cfg
= readl(host
->regs
+ SD_EMMC_CFG
);
459 cfg
|= CFG_STOP_CLOCK
;
460 writel(cfg
, host
->regs
+ SD_EMMC_CFG
);
462 ret
= clk_set_rate(host
->mmc_clk
, rate
);
464 dev_err(host
->dev
, "Unable to set cfg_div_clk to %lu. ret=%d\n",
469 host
->req_rate
= rate
;
470 mmc
->actual_clock
= clk_get_rate(host
->mmc_clk
);
472 /* We should report the real output frequency of the controller */
473 if (meson_mmc_timing_is_ddr(ios
))
474 mmc
->actual_clock
>>= 1;
476 dev_dbg(host
->dev
, "clk rate: %u Hz\n", mmc
->actual_clock
);
477 if (ios
->clock
!= mmc
->actual_clock
)
478 dev_dbg(host
->dev
, "requested rate was %u\n", ios
->clock
);
480 /* (re)start clock */
481 meson_mmc_clk_ungate(host
);
487 * The SD/eMMC IP block has an internal mux and divider used for
488 * generating the MMC clock. Use the clock framework to create and
489 * manage these clocks.
491 static int meson_mmc_clk_init(struct meson_host
*host
)
493 struct clk_init_data init
;
495 struct clk_divider
*div
;
496 struct meson_mmc_phase
*core
, *tx
, *rx
;
500 const char *mux_parent_names
[MUX_CLK_NUM_PARENTS
];
501 const char *clk_parent
[1];
504 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
506 clk_reg
|= CLK_ALWAYS_ON(host
);
507 clk_reg
|= CLK_DIV_MASK
;
508 writel(clk_reg
, host
->regs
+ SD_EMMC_CLOCK
);
510 /* get the mux parents */
511 for (i
= 0; i
< MUX_CLK_NUM_PARENTS
; i
++) {
515 snprintf(name
, sizeof(name
), "clkin%d", i
);
516 clk
= devm_clk_get(host
->dev
, name
);
518 if (clk
!= ERR_PTR(-EPROBE_DEFER
))
519 dev_err(host
->dev
, "Missing clock %s\n", name
);
523 mux_parent_names
[i
] = __clk_get_name(clk
);
527 mux
= devm_kzalloc(host
->dev
, sizeof(*mux
), GFP_KERNEL
);
531 snprintf(clk_name
, sizeof(clk_name
), "%s#mux", dev_name(host
->dev
));
532 init
.name
= clk_name
;
533 init
.ops
= &clk_mux_ops
;
535 init
.parent_names
= mux_parent_names
;
536 init
.num_parents
= MUX_CLK_NUM_PARENTS
;
538 mux
->reg
= host
->regs
+ SD_EMMC_CLOCK
;
539 mux
->shift
= __ffs(CLK_SRC_MASK
);
540 mux
->mask
= CLK_SRC_MASK
>> mux
->shift
;
541 mux
->hw
.init
= &init
;
543 clk
= devm_clk_register(host
->dev
, &mux
->hw
);
544 if (WARN_ON(IS_ERR(clk
)))
547 /* create the divider */
548 div
= devm_kzalloc(host
->dev
, sizeof(*div
), GFP_KERNEL
);
552 snprintf(clk_name
, sizeof(clk_name
), "%s#div", dev_name(host
->dev
));
553 init
.name
= clk_name
;
554 init
.ops
= &clk_divider_ops
;
555 init
.flags
= CLK_SET_RATE_PARENT
;
556 clk_parent
[0] = __clk_get_name(clk
);
557 init
.parent_names
= clk_parent
;
558 init
.num_parents
= 1;
560 div
->reg
= host
->regs
+ SD_EMMC_CLOCK
;
561 div
->shift
= __ffs(CLK_DIV_MASK
);
562 div
->width
= __builtin_popcountl(CLK_DIV_MASK
);
563 div
->hw
.init
= &init
;
564 div
->flags
= CLK_DIVIDER_ONE_BASED
;
566 clk
= devm_clk_register(host
->dev
, &div
->hw
);
567 if (WARN_ON(IS_ERR(clk
)))
570 /* create the mmc core clock */
571 core
= devm_kzalloc(host
->dev
, sizeof(*core
), GFP_KERNEL
);
575 snprintf(clk_name
, sizeof(clk_name
), "%s#core", dev_name(host
->dev
));
576 init
.name
= clk_name
;
577 init
.ops
= &meson_mmc_clk_phase_ops
;
578 init
.flags
= CLK_SET_RATE_PARENT
;
579 clk_parent
[0] = __clk_get_name(clk
);
580 init
.parent_names
= clk_parent
;
581 init
.num_parents
= 1;
583 core
->reg
= host
->regs
+ SD_EMMC_CLOCK
;
584 core
->phase_mask
= CLK_CORE_PHASE_MASK
;
585 core
->hw
.init
= &init
;
587 host
->mmc_clk
= devm_clk_register(host
->dev
, &core
->hw
);
588 if (WARN_ON(PTR_ERR_OR_ZERO(host
->mmc_clk
)))
589 return PTR_ERR(host
->mmc_clk
);
591 /* create the mmc tx clock */
592 tx
= devm_kzalloc(host
->dev
, sizeof(*tx
), GFP_KERNEL
);
596 snprintf(clk_name
, sizeof(clk_name
), "%s#tx", dev_name(host
->dev
));
597 init
.name
= clk_name
;
598 init
.ops
= &meson_mmc_clk_phase_ops
;
600 clk_parent
[0] = __clk_get_name(host
->mmc_clk
);
601 init
.parent_names
= clk_parent
;
602 init
.num_parents
= 1;
604 tx
->reg
= host
->regs
+ SD_EMMC_CLOCK
;
605 tx
->phase_mask
= CLK_TX_PHASE_MASK
;
606 tx
->delay_mask
= CLK_TX_DELAY_MASK(host
);
607 tx
->delay_step_ps
= CLK_DELAY_STEP_PS
;
610 host
->tx_clk
= devm_clk_register(host
->dev
, &tx
->hw
);
611 if (WARN_ON(PTR_ERR_OR_ZERO(host
->tx_clk
)))
612 return PTR_ERR(host
->tx_clk
);
614 /* create the mmc rx clock */
615 rx
= devm_kzalloc(host
->dev
, sizeof(*rx
), GFP_KERNEL
);
619 snprintf(clk_name
, sizeof(clk_name
), "%s#rx", dev_name(host
->dev
));
620 init
.name
= clk_name
;
621 init
.ops
= &meson_mmc_clk_phase_ops
;
623 clk_parent
[0] = __clk_get_name(host
->mmc_clk
);
624 init
.parent_names
= clk_parent
;
625 init
.num_parents
= 1;
627 rx
->reg
= host
->regs
+ SD_EMMC_CLOCK
;
628 rx
->phase_mask
= CLK_RX_PHASE_MASK
;
629 rx
->delay_mask
= CLK_RX_DELAY_MASK(host
);
630 rx
->delay_step_ps
= CLK_DELAY_STEP_PS
;
633 host
->rx_clk
= devm_clk_register(host
->dev
, &rx
->hw
);
634 if (WARN_ON(PTR_ERR_OR_ZERO(host
->rx_clk
)))
635 return PTR_ERR(host
->rx_clk
);
637 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
638 host
->mmc
->f_min
= clk_round_rate(host
->mmc_clk
, 400000);
639 ret
= clk_set_rate(host
->mmc_clk
, host
->mmc
->f_min
);
643 clk_set_phase(host
->mmc_clk
, 180);
644 clk_set_phase(host
->tx_clk
, 0);
645 clk_set_phase(host
->rx_clk
, 0);
647 return clk_prepare_enable(host
->mmc_clk
);
650 static void meson_mmc_shift_map(unsigned long *map
, unsigned long shift
)
652 DECLARE_BITMAP(left
, CLK_PHASE_POINT_NUM
);
653 DECLARE_BITMAP(right
, CLK_PHASE_POINT_NUM
);
656 * shift the bitmap right and reintroduce the dropped bits on the left
659 bitmap_shift_right(right
, map
, shift
, CLK_PHASE_POINT_NUM
);
660 bitmap_shift_left(left
, map
, CLK_PHASE_POINT_NUM
- shift
,
661 CLK_PHASE_POINT_NUM
);
662 bitmap_or(map
, left
, right
, CLK_PHASE_POINT_NUM
);
665 static void meson_mmc_find_next_region(unsigned long *map
,
666 unsigned long *start
,
669 *start
= find_next_bit(map
, CLK_PHASE_POINT_NUM
, *start
);
670 *stop
= find_next_zero_bit(map
, CLK_PHASE_POINT_NUM
, *start
);
673 static int meson_mmc_find_tuning_point(unsigned long *test
)
675 unsigned long shift
, stop
, offset
= 0, start
= 0, size
= 0;
677 /* Get the all good/all bad situation out the way */
678 if (bitmap_full(test
, CLK_PHASE_POINT_NUM
))
679 return 0; /* All points are good so point 0 will do */
680 else if (bitmap_empty(test
, CLK_PHASE_POINT_NUM
))
681 return -EIO
; /* No successful tuning point */
684 * Now we know there is a least one region find. Make sure it does
685 * not wrap by the shifting the bitmap if necessary
687 shift
= find_first_zero_bit(test
, CLK_PHASE_POINT_NUM
);
689 meson_mmc_shift_map(test
, shift
);
691 while (start
< CLK_PHASE_POINT_NUM
) {
692 meson_mmc_find_next_region(test
, &start
, &stop
);
694 if ((stop
- start
) > size
) {
702 /* Get the center point of the region */
703 offset
+= (size
/ 2);
705 /* Shift the result back */
706 offset
= (offset
+ shift
) % CLK_PHASE_POINT_NUM
;
711 static int meson_mmc_clk_phase_tuning(struct mmc_host
*mmc
, u32 opcode
,
715 DECLARE_BITMAP(test
, CLK_PHASE_POINT_NUM
);
717 dev_dbg(mmc_dev(mmc
), "%s phase/delay tunning...\n",
718 __clk_get_name(clk
));
719 bitmap_zero(test
, CLK_PHASE_POINT_NUM
);
721 /* Explore tuning points */
722 for (point
= 0; point
< CLK_PHASE_POINT_NUM
; point
++) {
723 clk_set_phase(clk
, point
* CLK_PHASE_STEP
);
724 ret
= mmc_send_tuning(mmc
, opcode
, NULL
);
726 set_bit(point
, test
);
729 /* Find the optimal tuning point and apply it */
730 point
= meson_mmc_find_tuning_point(test
);
732 return point
; /* tuning failed */
734 clk_set_phase(clk
, point
* CLK_PHASE_STEP
);
735 dev_dbg(mmc_dev(mmc
), "success with phase: %d\n",
740 static int meson_mmc_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
742 struct meson_host
*host
= mmc_priv(mmc
);
745 /* enable signal resampling w/o delay */
747 writel(adj
, host
->regs
+ host
->data
->adjust
);
749 return meson_mmc_clk_phase_tuning(mmc
, opcode
, host
->rx_clk
);
752 static void meson_mmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
754 struct meson_host
*host
= mmc_priv(mmc
);
759 * GPIO regulator, only controls switching between 1v8 and
760 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
762 switch (ios
->power_mode
) {
764 if (!IS_ERR(mmc
->supply
.vmmc
))
765 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
767 if (!IS_ERR(mmc
->supply
.vqmmc
) && host
->vqmmc_enabled
) {
768 regulator_disable(mmc
->supply
.vqmmc
);
769 host
->vqmmc_enabled
= false;
775 if (!IS_ERR(mmc
->supply
.vmmc
))
776 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, ios
->vdd
);
778 /* disable signal resampling */
779 writel(0, host
->regs
+ host
->data
->adjust
);
782 clk_set_phase(host
->rx_clk
, 0);
787 if (!IS_ERR(mmc
->supply
.vqmmc
) && !host
->vqmmc_enabled
) {
788 int ret
= regulator_enable(mmc
->supply
.vqmmc
);
792 "failed to enable vqmmc regulator\n");
794 host
->vqmmc_enabled
= true;
801 switch (ios
->bus_width
) {
802 case MMC_BUS_WIDTH_1
:
803 bus_width
= CFG_BUS_WIDTH_1
;
805 case MMC_BUS_WIDTH_4
:
806 bus_width
= CFG_BUS_WIDTH_4
;
808 case MMC_BUS_WIDTH_8
:
809 bus_width
= CFG_BUS_WIDTH_8
;
812 dev_err(host
->dev
, "Invalid ios->bus_width: %u. Setting to 4.\n",
814 bus_width
= CFG_BUS_WIDTH_4
;
817 val
= readl(host
->regs
+ SD_EMMC_CFG
);
818 val
&= ~CFG_BUS_WIDTH_MASK
;
819 val
|= FIELD_PREP(CFG_BUS_WIDTH_MASK
, bus_width
);
822 if (meson_mmc_timing_is_ddr(ios
))
826 if (ios
->timing
== MMC_TIMING_MMC_HS400
)
829 err
= meson_mmc_clk_set(host
, ios
);
831 dev_err(host
->dev
, "Failed to set clock: %d\n,", err
);
833 writel(val
, host
->regs
+ SD_EMMC_CFG
);
834 dev_dbg(host
->dev
, "SD_EMMC_CFG: 0x%08x\n", val
);
837 static void meson_mmc_request_done(struct mmc_host
*mmc
,
838 struct mmc_request
*mrq
)
840 struct meson_host
*host
= mmc_priv(mmc
);
843 mmc_request_done(host
->mmc
, mrq
);
846 static void meson_mmc_set_blksz(struct mmc_host
*mmc
, unsigned int blksz
)
848 struct meson_host
*host
= mmc_priv(mmc
);
851 cfg
= readl(host
->regs
+ SD_EMMC_CFG
);
852 blksz_old
= FIELD_GET(CFG_BLK_LEN_MASK
, cfg
);
854 if (!is_power_of_2(blksz
))
855 dev_err(host
->dev
, "blksz %u is not a power of 2\n", blksz
);
857 blksz
= ilog2(blksz
);
859 /* check if block-size matches, if not update */
860 if (blksz
== blksz_old
)
863 dev_dbg(host
->dev
, "%s: update blk_len %d -> %d\n", __func__
,
866 cfg
&= ~CFG_BLK_LEN_MASK
;
867 cfg
|= FIELD_PREP(CFG_BLK_LEN_MASK
, blksz
);
868 writel(cfg
, host
->regs
+ SD_EMMC_CFG
);
871 static void meson_mmc_set_response_bits(struct mmc_command
*cmd
, u32
*cmd_cfg
)
873 if (cmd
->flags
& MMC_RSP_PRESENT
) {
874 if (cmd
->flags
& MMC_RSP_136
)
875 *cmd_cfg
|= CMD_CFG_RESP_128
;
876 *cmd_cfg
|= CMD_CFG_RESP_NUM
;
878 if (!(cmd
->flags
& MMC_RSP_CRC
))
879 *cmd_cfg
|= CMD_CFG_RESP_NOCRC
;
881 if (cmd
->flags
& MMC_RSP_BUSY
)
882 *cmd_cfg
|= CMD_CFG_R1B
;
884 *cmd_cfg
|= CMD_CFG_NO_RESP
;
888 static void meson_mmc_desc_chain_transfer(struct mmc_host
*mmc
, u32 cmd_cfg
)
890 struct meson_host
*host
= mmc_priv(mmc
);
891 struct sd_emmc_desc
*desc
= host
->descs
;
892 struct mmc_data
*data
= host
->cmd
->data
;
893 struct scatterlist
*sg
;
897 if (data
->flags
& MMC_DATA_WRITE
)
898 cmd_cfg
|= CMD_CFG_DATA_WR
;
900 if (data
->blocks
> 1) {
901 cmd_cfg
|= CMD_CFG_BLOCK_MODE
;
902 meson_mmc_set_blksz(mmc
, data
->blksz
);
905 for_each_sg(data
->sg
, sg
, data
->sg_count
, i
) {
906 unsigned int len
= sg_dma_len(sg
);
908 if (data
->blocks
> 1)
911 desc
[i
].cmd_cfg
= cmd_cfg
;
912 desc
[i
].cmd_cfg
|= FIELD_PREP(CMD_CFG_LENGTH_MASK
, len
);
914 desc
[i
].cmd_cfg
|= CMD_CFG_NO_CMD
;
915 desc
[i
].cmd_arg
= host
->cmd
->arg
;
916 desc
[i
].cmd_resp
= 0;
917 desc
[i
].cmd_data
= sg_dma_address(sg
);
919 desc
[data
->sg_count
- 1].cmd_cfg
|= CMD_CFG_END_OF_CHAIN
;
921 dma_wmb(); /* ensure descriptor is written before kicked */
922 start
= host
->descs_dma_addr
| START_DESC_BUSY
;
923 writel(start
, host
->regs
+ SD_EMMC_START
);
926 static void meson_mmc_start_cmd(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
928 struct meson_host
*host
= mmc_priv(mmc
);
929 struct mmc_data
*data
= cmd
->data
;
930 u32 cmd_cfg
= 0, cmd_data
= 0;
931 unsigned int xfer_bytes
= 0;
933 /* Setup descriptors */
938 cmd_cfg
|= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK
, cmd
->opcode
);
939 cmd_cfg
|= CMD_CFG_OWNER
; /* owned by CPU */
940 cmd_cfg
|= CMD_CFG_ERROR
; /* stop in case of error */
942 meson_mmc_set_response_bits(cmd
, &cmd_cfg
);
946 data
->bytes_xfered
= 0;
947 cmd_cfg
|= CMD_CFG_DATA_IO
;
948 cmd_cfg
|= FIELD_PREP(CMD_CFG_TIMEOUT_MASK
,
949 ilog2(meson_mmc_get_timeout_msecs(data
)));
951 if (meson_mmc_desc_chain_mode(data
)) {
952 meson_mmc_desc_chain_transfer(mmc
, cmd_cfg
);
956 if (data
->blocks
> 1) {
957 cmd_cfg
|= CMD_CFG_BLOCK_MODE
;
958 cmd_cfg
|= FIELD_PREP(CMD_CFG_LENGTH_MASK
,
960 meson_mmc_set_blksz(mmc
, data
->blksz
);
962 cmd_cfg
|= FIELD_PREP(CMD_CFG_LENGTH_MASK
, data
->blksz
);
965 xfer_bytes
= data
->blksz
* data
->blocks
;
966 if (data
->flags
& MMC_DATA_WRITE
) {
967 cmd_cfg
|= CMD_CFG_DATA_WR
;
968 WARN_ON(xfer_bytes
> host
->bounce_buf_size
);
969 sg_copy_to_buffer(data
->sg
, data
->sg_len
,
970 host
->bounce_buf
, xfer_bytes
);
974 cmd_data
= host
->bounce_dma_addr
& CMD_DATA_MASK
;
976 cmd_cfg
|= FIELD_PREP(CMD_CFG_TIMEOUT_MASK
,
977 ilog2(SD_EMMC_CMD_TIMEOUT
));
980 /* Last descriptor */
981 cmd_cfg
|= CMD_CFG_END_OF_CHAIN
;
982 writel(cmd_cfg
, host
->regs
+ SD_EMMC_CMD_CFG
);
983 writel(cmd_data
, host
->regs
+ SD_EMMC_CMD_DAT
);
984 writel(0, host
->regs
+ SD_EMMC_CMD_RSP
);
985 wmb(); /* ensure descriptor is written before kicked */
986 writel(cmd
->arg
, host
->regs
+ SD_EMMC_CMD_ARG
);
989 static void meson_mmc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
991 struct meson_host
*host
= mmc_priv(mmc
);
992 bool needs_pre_post_req
= mrq
->data
&&
993 !(mrq
->data
->host_cookie
& SD_EMMC_PRE_REQ_DONE
);
995 if (needs_pre_post_req
) {
996 meson_mmc_get_transfer_mode(mmc
, mrq
);
997 if (!meson_mmc_desc_chain_mode(mrq
->data
))
998 needs_pre_post_req
= false;
1001 if (needs_pre_post_req
)
1002 meson_mmc_pre_req(mmc
, mrq
);
1004 /* Stop execution */
1005 writel(0, host
->regs
+ SD_EMMC_START
);
1007 meson_mmc_start_cmd(mmc
, mrq
->sbc
?: mrq
->cmd
);
1009 if (needs_pre_post_req
)
1010 meson_mmc_post_req(mmc
, mrq
, 0);
1013 static void meson_mmc_read_resp(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
1015 struct meson_host
*host
= mmc_priv(mmc
);
1017 if (cmd
->flags
& MMC_RSP_136
) {
1018 cmd
->resp
[0] = readl(host
->regs
+ SD_EMMC_CMD_RSP3
);
1019 cmd
->resp
[1] = readl(host
->regs
+ SD_EMMC_CMD_RSP2
);
1020 cmd
->resp
[2] = readl(host
->regs
+ SD_EMMC_CMD_RSP1
);
1021 cmd
->resp
[3] = readl(host
->regs
+ SD_EMMC_CMD_RSP
);
1022 } else if (cmd
->flags
& MMC_RSP_PRESENT
) {
1023 cmd
->resp
[0] = readl(host
->regs
+ SD_EMMC_CMD_RSP
);
1027 static irqreturn_t
meson_mmc_irq(int irq
, void *dev_id
)
1029 struct meson_host
*host
= dev_id
;
1030 struct mmc_command
*cmd
;
1031 struct mmc_data
*data
;
1032 u32 irq_en
, status
, raw_status
;
1033 irqreturn_t ret
= IRQ_NONE
;
1035 irq_en
= readl(host
->regs
+ SD_EMMC_IRQ_EN
);
1036 raw_status
= readl(host
->regs
+ SD_EMMC_STATUS
);
1037 status
= raw_status
& irq_en
;
1041 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
1042 irq_en
, raw_status
);
1046 if (WARN_ON(!host
) || WARN_ON(!host
->cmd
))
1052 if (status
& IRQ_CRC_ERR
) {
1053 dev_dbg(host
->dev
, "CRC Error - status 0x%08x\n", status
);
1054 cmd
->error
= -EILSEQ
;
1055 ret
= IRQ_WAKE_THREAD
;
1059 if (status
& IRQ_TIMEOUTS
) {
1060 dev_dbg(host
->dev
, "Timeout - status 0x%08x\n", status
);
1061 cmd
->error
= -ETIMEDOUT
;
1062 ret
= IRQ_WAKE_THREAD
;
1066 meson_mmc_read_resp(host
->mmc
, cmd
);
1068 if (status
& IRQ_SDIO
) {
1069 dev_dbg(host
->dev
, "IRQ: SDIO TODO.\n");
1073 if (status
& (IRQ_END_OF_CHAIN
| IRQ_RESP_STATUS
)) {
1074 if (data
&& !cmd
->error
)
1075 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
1076 if (meson_mmc_bounce_buf_read(data
) ||
1077 meson_mmc_get_next_command(cmd
))
1078 ret
= IRQ_WAKE_THREAD
;
1084 /* ack all enabled interrupts */
1085 writel(irq_en
, host
->regs
+ SD_EMMC_STATUS
);
1088 /* Stop desc in case of errors */
1089 u32 start
= readl(host
->regs
+ SD_EMMC_START
);
1091 start
&= ~START_DESC_BUSY
;
1092 writel(start
, host
->regs
+ SD_EMMC_START
);
1095 if (ret
== IRQ_HANDLED
)
1096 meson_mmc_request_done(host
->mmc
, cmd
->mrq
);
1101 static int meson_mmc_wait_desc_stop(struct meson_host
*host
)
1107 * It may sometimes take a while for it to actually halt. Here, we
1108 * are giving it 5ms to comply
1110 * If we don't confirm the descriptor is stopped, it might raise new
1111 * IRQs after we have called mmc_request_done() which is bad.
1113 for (loop
= 50; loop
; loop
--) {
1114 status
= readl(host
->regs
+ SD_EMMC_STATUS
);
1115 if (status
& (STATUS_BUSY
| STATUS_DESC_BUSY
))
1121 if (status
& (STATUS_BUSY
| STATUS_DESC_BUSY
)) {
1122 dev_err(host
->dev
, "Timed out waiting for host to stop\n");
1129 static irqreturn_t
meson_mmc_irq_thread(int irq
, void *dev_id
)
1131 struct meson_host
*host
= dev_id
;
1132 struct mmc_command
*next_cmd
, *cmd
= host
->cmd
;
1133 struct mmc_data
*data
;
1134 unsigned int xfer_bytes
;
1140 meson_mmc_wait_desc_stop(host
);
1141 meson_mmc_request_done(host
->mmc
, cmd
->mrq
);
1147 if (meson_mmc_bounce_buf_read(data
)) {
1148 xfer_bytes
= data
->blksz
* data
->blocks
;
1149 WARN_ON(xfer_bytes
> host
->bounce_buf_size
);
1150 sg_copy_from_buffer(data
->sg
, data
->sg_len
,
1151 host
->bounce_buf
, xfer_bytes
);
1154 next_cmd
= meson_mmc_get_next_command(cmd
);
1156 meson_mmc_start_cmd(host
->mmc
, next_cmd
);
1158 meson_mmc_request_done(host
->mmc
, cmd
->mrq
);
1164 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1165 * interrupts. For now, the MMC core will use this for polling.
1167 static int meson_mmc_get_cd(struct mmc_host
*mmc
)
1169 int status
= mmc_gpio_get_cd(mmc
);
1171 if (status
== -ENOSYS
)
1172 return 1; /* assume present */
1177 static void meson_mmc_cfg_init(struct meson_host
*host
)
1181 cfg
|= FIELD_PREP(CFG_RESP_TIMEOUT_MASK
,
1182 ilog2(SD_EMMC_CFG_RESP_TIMEOUT
));
1183 cfg
|= FIELD_PREP(CFG_RC_CC_MASK
, ilog2(SD_EMMC_CFG_CMD_GAP
));
1184 cfg
|= FIELD_PREP(CFG_BLK_LEN_MASK
, ilog2(SD_EMMC_CFG_BLK_SIZE
));
1186 /* abort chain on R/W errors */
1187 cfg
|= CFG_ERR_ABORT
;
1189 writel(cfg
, host
->regs
+ SD_EMMC_CFG
);
1192 static int meson_mmc_card_busy(struct mmc_host
*mmc
)
1194 struct meson_host
*host
= mmc_priv(mmc
);
1197 regval
= readl(host
->regs
+ SD_EMMC_STATUS
);
1199 /* We are only interrested in lines 0 to 3, so mask the other ones */
1200 return !(FIELD_GET(STATUS_DATI
, regval
) & 0xf);
1203 static int meson_mmc_voltage_switch(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1205 /* vqmmc regulator is available */
1206 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1208 * The usual amlogic setup uses a GPIO to switch from one
1209 * regulator to the other. While the voltage ramp up is
1210 * pretty fast, care must be taken when switching from 3.3v
1211 * to 1.8v. Please make sure the regulator framework is aware
1212 * of your own regulator constraints
1214 return mmc_regulator_set_vqmmc(mmc
, ios
);
1217 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1218 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1224 static const struct mmc_host_ops meson_mmc_ops
= {
1225 .request
= meson_mmc_request
,
1226 .set_ios
= meson_mmc_set_ios
,
1227 .get_cd
= meson_mmc_get_cd
,
1228 .pre_req
= meson_mmc_pre_req
,
1229 .post_req
= meson_mmc_post_req
,
1230 .execute_tuning
= meson_mmc_execute_tuning
,
1231 .card_busy
= meson_mmc_card_busy
,
1232 .start_signal_voltage_switch
= meson_mmc_voltage_switch
,
1235 static int meson_mmc_probe(struct platform_device
*pdev
)
1237 struct resource
*res
;
1238 struct meson_host
*host
;
1239 struct mmc_host
*mmc
;
1242 mmc
= mmc_alloc_host(sizeof(struct meson_host
), &pdev
->dev
);
1245 host
= mmc_priv(mmc
);
1247 host
->dev
= &pdev
->dev
;
1248 dev_set_drvdata(&pdev
->dev
, host
);
1250 /* Get regulators and the supported OCR mask */
1251 host
->vqmmc_enabled
= false;
1252 ret
= mmc_regulator_get_supply(mmc
);
1256 ret
= mmc_of_parse(mmc
);
1258 if (ret
!= -EPROBE_DEFER
)
1259 dev_warn(&pdev
->dev
, "error parsing DT: %d\n", ret
);
1263 host
->data
= (struct meson_mmc_data
*)
1264 of_device_get_match_data(&pdev
->dev
);
1270 ret
= device_reset_optional(&pdev
->dev
);
1272 if (ret
!= -EPROBE_DEFER
)
1273 dev_err(&pdev
->dev
, "device reset failed: %d\n", ret
);
1278 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1279 host
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1280 if (IS_ERR(host
->regs
)) {
1281 ret
= PTR_ERR(host
->regs
);
1285 host
->irq
= platform_get_irq(pdev
, 0);
1286 if (host
->irq
<= 0) {
1287 dev_err(&pdev
->dev
, "failed to get interrupt resource.\n");
1292 host
->pinctrl
= devm_pinctrl_get(&pdev
->dev
);
1293 if (IS_ERR(host
->pinctrl
)) {
1294 ret
= PTR_ERR(host
->pinctrl
);
1298 host
->pins_default
= pinctrl_lookup_state(host
->pinctrl
,
1299 PINCTRL_STATE_DEFAULT
);
1300 if (IS_ERR(host
->pins_default
)) {
1301 ret
= PTR_ERR(host
->pins_default
);
1305 host
->pins_clk_gate
= pinctrl_lookup_state(host
->pinctrl
,
1307 if (IS_ERR(host
->pins_clk_gate
)) {
1308 dev_warn(&pdev
->dev
,
1309 "can't get clk-gate pinctrl, using clk_stop bit\n");
1310 host
->pins_clk_gate
= NULL
;
1313 host
->core_clk
= devm_clk_get(&pdev
->dev
, "core");
1314 if (IS_ERR(host
->core_clk
)) {
1315 ret
= PTR_ERR(host
->core_clk
);
1319 ret
= clk_prepare_enable(host
->core_clk
);
1323 ret
= meson_mmc_clk_init(host
);
1327 /* set config to sane default */
1328 meson_mmc_cfg_init(host
);
1330 /* Stop execution */
1331 writel(0, host
->regs
+ SD_EMMC_START
);
1333 /* clear, ack and enable interrupts */
1334 writel(0, host
->regs
+ SD_EMMC_IRQ_EN
);
1335 writel(IRQ_CRC_ERR
| IRQ_TIMEOUTS
| IRQ_END_OF_CHAIN
,
1336 host
->regs
+ SD_EMMC_STATUS
);
1337 writel(IRQ_CRC_ERR
| IRQ_TIMEOUTS
| IRQ_END_OF_CHAIN
,
1338 host
->regs
+ SD_EMMC_IRQ_EN
);
1340 ret
= request_threaded_irq(host
->irq
, meson_mmc_irq
,
1341 meson_mmc_irq_thread
, IRQF_SHARED
,
1342 dev_name(&pdev
->dev
), host
);
1346 mmc
->caps
|= MMC_CAP_CMD23
;
1347 mmc
->max_blk_count
= CMD_CFG_LENGTH_MASK
;
1348 mmc
->max_req_size
= mmc
->max_blk_count
* mmc
->max_blk_size
;
1349 mmc
->max_segs
= SD_EMMC_DESC_BUF_LEN
/ sizeof(struct sd_emmc_desc
);
1350 mmc
->max_seg_size
= mmc
->max_req_size
;
1352 /* data bounce buffer */
1353 host
->bounce_buf_size
= mmc
->max_req_size
;
1355 dma_alloc_coherent(host
->dev
, host
->bounce_buf_size
,
1356 &host
->bounce_dma_addr
, GFP_KERNEL
);
1357 if (host
->bounce_buf
== NULL
) {
1358 dev_err(host
->dev
, "Unable to map allocate DMA bounce buffer.\n");
1363 host
->descs
= dma_alloc_coherent(host
->dev
, SD_EMMC_DESC_BUF_LEN
,
1364 &host
->descs_dma_addr
, GFP_KERNEL
);
1366 dev_err(host
->dev
, "Allocating descriptor DMA buffer failed\n");
1368 goto err_bounce_buf
;
1371 mmc
->ops
= &meson_mmc_ops
;
1377 dma_free_coherent(host
->dev
, host
->bounce_buf_size
,
1378 host
->bounce_buf
, host
->bounce_dma_addr
);
1380 free_irq(host
->irq
, host
);
1382 clk_disable_unprepare(host
->mmc_clk
);
1384 clk_disable_unprepare(host
->core_clk
);
1390 static int meson_mmc_remove(struct platform_device
*pdev
)
1392 struct meson_host
*host
= dev_get_drvdata(&pdev
->dev
);
1394 mmc_remove_host(host
->mmc
);
1396 /* disable interrupts */
1397 writel(0, host
->regs
+ SD_EMMC_IRQ_EN
);
1398 free_irq(host
->irq
, host
);
1400 dma_free_coherent(host
->dev
, SD_EMMC_DESC_BUF_LEN
,
1401 host
->descs
, host
->descs_dma_addr
);
1402 dma_free_coherent(host
->dev
, host
->bounce_buf_size
,
1403 host
->bounce_buf
, host
->bounce_dma_addr
);
1405 clk_disable_unprepare(host
->mmc_clk
);
1406 clk_disable_unprepare(host
->core_clk
);
1408 mmc_free_host(host
->mmc
);
1412 static const struct meson_mmc_data meson_gx_data
= {
1413 .tx_delay_mask
= CLK_V2_TX_DELAY_MASK
,
1414 .rx_delay_mask
= CLK_V2_RX_DELAY_MASK
,
1415 .always_on
= CLK_V2_ALWAYS_ON
,
1416 .adjust
= SD_EMMC_ADJUST
,
1419 static const struct meson_mmc_data meson_axg_data
= {
1420 .tx_delay_mask
= CLK_V3_TX_DELAY_MASK
,
1421 .rx_delay_mask
= CLK_V3_RX_DELAY_MASK
,
1422 .always_on
= CLK_V3_ALWAYS_ON
,
1423 .adjust
= SD_EMMC_V3_ADJUST
,
1426 static const struct of_device_id meson_mmc_of_match
[] = {
1427 { .compatible
= "amlogic,meson-gx-mmc", .data
= &meson_gx_data
},
1428 { .compatible
= "amlogic,meson-gxbb-mmc", .data
= &meson_gx_data
},
1429 { .compatible
= "amlogic,meson-gxl-mmc", .data
= &meson_gx_data
},
1430 { .compatible
= "amlogic,meson-gxm-mmc", .data
= &meson_gx_data
},
1431 { .compatible
= "amlogic,meson-axg-mmc", .data
= &meson_axg_data
},
1434 MODULE_DEVICE_TABLE(of
, meson_mmc_of_match
);
1436 static struct platform_driver meson_mmc_driver
= {
1437 .probe
= meson_mmc_probe
,
1438 .remove
= meson_mmc_remove
,
1440 .name
= DRIVER_NAME
,
1441 .of_match_table
= of_match_ptr(meson_mmc_of_match
),
1445 module_platform_driver(meson_mmc_driver
);
1447 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1448 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1449 MODULE_LICENSE("GPL v2");