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Merge tag 'mmc-updates-for-3.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/highmem.h>
22 #include <linux/log2.h>
23 #include <linux/mmc/pm.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/amba/bus.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
29 #include <linux/gpio.h>
30 #include <linux/of_gpio.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/amba/mmci.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/types.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <asm/div64.h>
40 #include <asm/io.h>
41 #include <asm/sizes.h>
42
43 #include "mmci.h"
44
45 #define DRIVER_NAME "mmci-pl18x"
46
47 static unsigned int fmax = 515633;
48
49 /**
50 * struct variant_data - MMCI variant-specific quirks
51 * @clkreg: default value for MCICLOCK register
52 * @clkreg_enable: enable value for MMCICLOCK register
53 * @datalength_bits: number of bits in the MMCIDATALENGTH register
54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
55 * is asserted (likewise for RX)
56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
57 * is asserted (likewise for RX)
58 * @sdio: variant supports SDIO
59 * @st_clkdiv: true if using a ST-specific clock divider algorithm
60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
61 * @pwrreg_powerup: power up value for MMCIPOWER register
62 * @signal_direction: input/out direction of bus signals can be indicated
63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
64 * @busy_detect: true if busy detection on dat0 is supported
65 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
66 */
67 struct variant_data {
68 unsigned int clkreg;
69 unsigned int clkreg_enable;
70 unsigned int datalength_bits;
71 unsigned int fifosize;
72 unsigned int fifohalfsize;
73 bool sdio;
74 bool st_clkdiv;
75 bool blksz_datactrl16;
76 u32 pwrreg_powerup;
77 bool signal_direction;
78 bool pwrreg_clkgate;
79 bool busy_detect;
80 bool pwrreg_nopower;
81 };
82
83 static struct variant_data variant_arm = {
84 .fifosize = 16 * 4,
85 .fifohalfsize = 8 * 4,
86 .datalength_bits = 16,
87 .pwrreg_powerup = MCI_PWR_UP,
88 };
89
90 static struct variant_data variant_arm_extended_fifo = {
91 .fifosize = 128 * 4,
92 .fifohalfsize = 64 * 4,
93 .datalength_bits = 16,
94 .pwrreg_powerup = MCI_PWR_UP,
95 };
96
97 static struct variant_data variant_arm_extended_fifo_hwfc = {
98 .fifosize = 128 * 4,
99 .fifohalfsize = 64 * 4,
100 .clkreg_enable = MCI_ARM_HWFCEN,
101 .datalength_bits = 16,
102 .pwrreg_powerup = MCI_PWR_UP,
103 };
104
105 static struct variant_data variant_u300 = {
106 .fifosize = 16 * 4,
107 .fifohalfsize = 8 * 4,
108 .clkreg_enable = MCI_ST_U300_HWFCEN,
109 .datalength_bits = 16,
110 .sdio = true,
111 .pwrreg_powerup = MCI_PWR_ON,
112 .signal_direction = true,
113 .pwrreg_clkgate = true,
114 .pwrreg_nopower = true,
115 };
116
117 static struct variant_data variant_nomadik = {
118 .fifosize = 16 * 4,
119 .fifohalfsize = 8 * 4,
120 .clkreg = MCI_CLK_ENABLE,
121 .datalength_bits = 24,
122 .sdio = true,
123 .st_clkdiv = true,
124 .pwrreg_powerup = MCI_PWR_ON,
125 .signal_direction = true,
126 .pwrreg_clkgate = true,
127 .pwrreg_nopower = true,
128 };
129
130 static struct variant_data variant_ux500 = {
131 .fifosize = 30 * 4,
132 .fifohalfsize = 8 * 4,
133 .clkreg = MCI_CLK_ENABLE,
134 .clkreg_enable = MCI_ST_UX500_HWFCEN,
135 .datalength_bits = 24,
136 .sdio = true,
137 .st_clkdiv = true,
138 .pwrreg_powerup = MCI_PWR_ON,
139 .signal_direction = true,
140 .pwrreg_clkgate = true,
141 .busy_detect = true,
142 .pwrreg_nopower = true,
143 };
144
145 static struct variant_data variant_ux500v2 = {
146 .fifosize = 30 * 4,
147 .fifohalfsize = 8 * 4,
148 .clkreg = MCI_CLK_ENABLE,
149 .clkreg_enable = MCI_ST_UX500_HWFCEN,
150 .datalength_bits = 24,
151 .sdio = true,
152 .st_clkdiv = true,
153 .blksz_datactrl16 = true,
154 .pwrreg_powerup = MCI_PWR_ON,
155 .signal_direction = true,
156 .pwrreg_clkgate = true,
157 .busy_detect = true,
158 .pwrreg_nopower = true,
159 };
160
161 static int mmci_card_busy(struct mmc_host *mmc)
162 {
163 struct mmci_host *host = mmc_priv(mmc);
164 unsigned long flags;
165 int busy = 0;
166
167 pm_runtime_get_sync(mmc_dev(mmc));
168
169 spin_lock_irqsave(&host->lock, flags);
170 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
171 busy = 1;
172 spin_unlock_irqrestore(&host->lock, flags);
173
174 pm_runtime_mark_last_busy(mmc_dev(mmc));
175 pm_runtime_put_autosuspend(mmc_dev(mmc));
176
177 return busy;
178 }
179
180 /*
181 * Validate mmc prerequisites
182 */
183 static int mmci_validate_data(struct mmci_host *host,
184 struct mmc_data *data)
185 {
186 if (!data)
187 return 0;
188
189 if (!is_power_of_2(data->blksz)) {
190 dev_err(mmc_dev(host->mmc),
191 "unsupported block size (%d bytes)\n", data->blksz);
192 return -EINVAL;
193 }
194
195 return 0;
196 }
197
198 static void mmci_reg_delay(struct mmci_host *host)
199 {
200 /*
201 * According to the spec, at least three feedback clock cycles
202 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
203 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
204 * Worst delay time during card init is at 100 kHz => 30 us.
205 * Worst delay time when up and running is at 25 MHz => 120 ns.
206 */
207 if (host->cclk < 25000000)
208 udelay(30);
209 else
210 ndelay(120);
211 }
212
213 /*
214 * This must be called with host->lock held
215 */
216 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
217 {
218 if (host->clk_reg != clk) {
219 host->clk_reg = clk;
220 writel(clk, host->base + MMCICLOCK);
221 }
222 }
223
224 /*
225 * This must be called with host->lock held
226 */
227 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
228 {
229 if (host->pwr_reg != pwr) {
230 host->pwr_reg = pwr;
231 writel(pwr, host->base + MMCIPOWER);
232 }
233 }
234
235 /*
236 * This must be called with host->lock held
237 */
238 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
239 {
240 /* Keep ST Micro busy mode if enabled */
241 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
242
243 if (host->datactrl_reg != datactrl) {
244 host->datactrl_reg = datactrl;
245 writel(datactrl, host->base + MMCIDATACTRL);
246 }
247 }
248
249 /*
250 * This must be called with host->lock held
251 */
252 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
253 {
254 struct variant_data *variant = host->variant;
255 u32 clk = variant->clkreg;
256
257 /* Make sure cclk reflects the current calculated clock */
258 host->cclk = 0;
259
260 if (desired) {
261 if (desired >= host->mclk) {
262 clk = MCI_CLK_BYPASS;
263 if (variant->st_clkdiv)
264 clk |= MCI_ST_UX500_NEG_EDGE;
265 host->cclk = host->mclk;
266 } else if (variant->st_clkdiv) {
267 /*
268 * DB8500 TRM says f = mclk / (clkdiv + 2)
269 * => clkdiv = (mclk / f) - 2
270 * Round the divider up so we don't exceed the max
271 * frequency
272 */
273 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
274 if (clk >= 256)
275 clk = 255;
276 host->cclk = host->mclk / (clk + 2);
277 } else {
278 /*
279 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
280 * => clkdiv = mclk / (2 * f) - 1
281 */
282 clk = host->mclk / (2 * desired) - 1;
283 if (clk >= 256)
284 clk = 255;
285 host->cclk = host->mclk / (2 * (clk + 1));
286 }
287
288 clk |= variant->clkreg_enable;
289 clk |= MCI_CLK_ENABLE;
290 /* This hasn't proven to be worthwhile */
291 /* clk |= MCI_CLK_PWRSAVE; */
292 }
293
294 /* Set actual clock for debug */
295 host->mmc->actual_clock = host->cclk;
296
297 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
298 clk |= MCI_4BIT_BUS;
299 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
300 clk |= MCI_ST_8BIT_BUS;
301
302 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
303 clk |= MCI_ST_UX500_NEG_EDGE;
304
305 mmci_write_clkreg(host, clk);
306 }
307
308 static void
309 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
310 {
311 writel(0, host->base + MMCICOMMAND);
312
313 BUG_ON(host->data);
314
315 host->mrq = NULL;
316 host->cmd = NULL;
317
318 mmc_request_done(host->mmc, mrq);
319
320 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
321 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
322 }
323
324 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
325 {
326 void __iomem *base = host->base;
327
328 if (host->singleirq) {
329 unsigned int mask0 = readl(base + MMCIMASK0);
330
331 mask0 &= ~MCI_IRQ1MASK;
332 mask0 |= mask;
333
334 writel(mask0, base + MMCIMASK0);
335 }
336
337 writel(mask, base + MMCIMASK1);
338 }
339
340 static void mmci_stop_data(struct mmci_host *host)
341 {
342 mmci_write_datactrlreg(host, 0);
343 mmci_set_mask1(host, 0);
344 host->data = NULL;
345 }
346
347 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
348 {
349 unsigned int flags = SG_MITER_ATOMIC;
350
351 if (data->flags & MMC_DATA_READ)
352 flags |= SG_MITER_TO_SG;
353 else
354 flags |= SG_MITER_FROM_SG;
355
356 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
357 }
358
359 /*
360 * All the DMA operation mode stuff goes inside this ifdef.
361 * This assumes that you have a generic DMA device interface,
362 * no custom DMA interfaces are supported.
363 */
364 #ifdef CONFIG_DMA_ENGINE
365 static void mmci_dma_setup(struct mmci_host *host)
366 {
367 struct mmci_platform_data *plat = host->plat;
368 const char *rxname, *txname;
369 dma_cap_mask_t mask;
370
371 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
372 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
373
374 /* initialize pre request cookie */
375 host->next_data.cookie = 1;
376
377 /* Try to acquire a generic DMA engine slave channel */
378 dma_cap_zero(mask);
379 dma_cap_set(DMA_SLAVE, mask);
380
381 if (plat && plat->dma_filter) {
382 if (!host->dma_rx_channel && plat->dma_rx_param) {
383 host->dma_rx_channel = dma_request_channel(mask,
384 plat->dma_filter,
385 plat->dma_rx_param);
386 /* E.g if no DMA hardware is present */
387 if (!host->dma_rx_channel)
388 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
389 }
390
391 if (!host->dma_tx_channel && plat->dma_tx_param) {
392 host->dma_tx_channel = dma_request_channel(mask,
393 plat->dma_filter,
394 plat->dma_tx_param);
395 if (!host->dma_tx_channel)
396 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
397 }
398 }
399
400 /*
401 * If only an RX channel is specified, the driver will
402 * attempt to use it bidirectionally, however if it is
403 * is specified but cannot be located, DMA will be disabled.
404 */
405 if (host->dma_rx_channel && !host->dma_tx_channel)
406 host->dma_tx_channel = host->dma_rx_channel;
407
408 if (host->dma_rx_channel)
409 rxname = dma_chan_name(host->dma_rx_channel);
410 else
411 rxname = "none";
412
413 if (host->dma_tx_channel)
414 txname = dma_chan_name(host->dma_tx_channel);
415 else
416 txname = "none";
417
418 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
419 rxname, txname);
420
421 /*
422 * Limit the maximum segment size in any SG entry according to
423 * the parameters of the DMA engine device.
424 */
425 if (host->dma_tx_channel) {
426 struct device *dev = host->dma_tx_channel->device->dev;
427 unsigned int max_seg_size = dma_get_max_seg_size(dev);
428
429 if (max_seg_size < host->mmc->max_seg_size)
430 host->mmc->max_seg_size = max_seg_size;
431 }
432 if (host->dma_rx_channel) {
433 struct device *dev = host->dma_rx_channel->device->dev;
434 unsigned int max_seg_size = dma_get_max_seg_size(dev);
435
436 if (max_seg_size < host->mmc->max_seg_size)
437 host->mmc->max_seg_size = max_seg_size;
438 }
439 }
440
441 /*
442 * This is used in or so inline it
443 * so it can be discarded.
444 */
445 static inline void mmci_dma_release(struct mmci_host *host)
446 {
447 struct mmci_platform_data *plat = host->plat;
448
449 if (host->dma_rx_channel)
450 dma_release_channel(host->dma_rx_channel);
451 if (host->dma_tx_channel && plat->dma_tx_param)
452 dma_release_channel(host->dma_tx_channel);
453 host->dma_rx_channel = host->dma_tx_channel = NULL;
454 }
455
456 static void mmci_dma_data_error(struct mmci_host *host)
457 {
458 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
459 dmaengine_terminate_all(host->dma_current);
460 host->dma_current = NULL;
461 host->dma_desc_current = NULL;
462 host->data->host_cookie = 0;
463 }
464
465 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
466 {
467 struct dma_chan *chan;
468 enum dma_data_direction dir;
469
470 if (data->flags & MMC_DATA_READ) {
471 dir = DMA_FROM_DEVICE;
472 chan = host->dma_rx_channel;
473 } else {
474 dir = DMA_TO_DEVICE;
475 chan = host->dma_tx_channel;
476 }
477
478 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
479 }
480
481 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
482 {
483 u32 status;
484 int i;
485
486 /* Wait up to 1ms for the DMA to complete */
487 for (i = 0; ; i++) {
488 status = readl(host->base + MMCISTATUS);
489 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
490 break;
491 udelay(10);
492 }
493
494 /*
495 * Check to see whether we still have some data left in the FIFO -
496 * this catches DMA controllers which are unable to monitor the
497 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
498 * contiguous buffers. On TX, we'll get a FIFO underrun error.
499 */
500 if (status & MCI_RXDATAAVLBLMASK) {
501 mmci_dma_data_error(host);
502 if (!data->error)
503 data->error = -EIO;
504 }
505
506 if (!data->host_cookie)
507 mmci_dma_unmap(host, data);
508
509 /*
510 * Use of DMA with scatter-gather is impossible.
511 * Give up with DMA and switch back to PIO mode.
512 */
513 if (status & MCI_RXDATAAVLBLMASK) {
514 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
515 mmci_dma_release(host);
516 }
517
518 host->dma_current = NULL;
519 host->dma_desc_current = NULL;
520 }
521
522 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
523 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
524 struct dma_chan **dma_chan,
525 struct dma_async_tx_descriptor **dma_desc)
526 {
527 struct variant_data *variant = host->variant;
528 struct dma_slave_config conf = {
529 .src_addr = host->phybase + MMCIFIFO,
530 .dst_addr = host->phybase + MMCIFIFO,
531 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
532 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
533 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
534 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
535 .device_fc = false,
536 };
537 struct dma_chan *chan;
538 struct dma_device *device;
539 struct dma_async_tx_descriptor *desc;
540 enum dma_data_direction buffer_dirn;
541 int nr_sg;
542
543 if (data->flags & MMC_DATA_READ) {
544 conf.direction = DMA_DEV_TO_MEM;
545 buffer_dirn = DMA_FROM_DEVICE;
546 chan = host->dma_rx_channel;
547 } else {
548 conf.direction = DMA_MEM_TO_DEV;
549 buffer_dirn = DMA_TO_DEVICE;
550 chan = host->dma_tx_channel;
551 }
552
553 /* If there's no DMA channel, fall back to PIO */
554 if (!chan)
555 return -EINVAL;
556
557 /* If less than or equal to the fifo size, don't bother with DMA */
558 if (data->blksz * data->blocks <= variant->fifosize)
559 return -EINVAL;
560
561 device = chan->device;
562 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
563 if (nr_sg == 0)
564 return -EINVAL;
565
566 dmaengine_slave_config(chan, &conf);
567 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
568 conf.direction, DMA_CTRL_ACK);
569 if (!desc)
570 goto unmap_exit;
571
572 *dma_chan = chan;
573 *dma_desc = desc;
574
575 return 0;
576
577 unmap_exit:
578 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
579 return -ENOMEM;
580 }
581
582 static inline int mmci_dma_prep_data(struct mmci_host *host,
583 struct mmc_data *data)
584 {
585 /* Check if next job is already prepared. */
586 if (host->dma_current && host->dma_desc_current)
587 return 0;
588
589 /* No job were prepared thus do it now. */
590 return __mmci_dma_prep_data(host, data, &host->dma_current,
591 &host->dma_desc_current);
592 }
593
594 static inline int mmci_dma_prep_next(struct mmci_host *host,
595 struct mmc_data *data)
596 {
597 struct mmci_host_next *nd = &host->next_data;
598 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
599 }
600
601 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
602 {
603 int ret;
604 struct mmc_data *data = host->data;
605
606 ret = mmci_dma_prep_data(host, host->data);
607 if (ret)
608 return ret;
609
610 /* Okay, go for it. */
611 dev_vdbg(mmc_dev(host->mmc),
612 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
613 data->sg_len, data->blksz, data->blocks, data->flags);
614 dmaengine_submit(host->dma_desc_current);
615 dma_async_issue_pending(host->dma_current);
616
617 datactrl |= MCI_DPSM_DMAENABLE;
618
619 /* Trigger the DMA transfer */
620 mmci_write_datactrlreg(host, datactrl);
621
622 /*
623 * Let the MMCI say when the data is ended and it's time
624 * to fire next DMA request. When that happens, MMCI will
625 * call mmci_data_end()
626 */
627 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
628 host->base + MMCIMASK0);
629 return 0;
630 }
631
632 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
633 {
634 struct mmci_host_next *next = &host->next_data;
635
636 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
637 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
638
639 host->dma_desc_current = next->dma_desc;
640 host->dma_current = next->dma_chan;
641 next->dma_desc = NULL;
642 next->dma_chan = NULL;
643 }
644
645 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
646 bool is_first_req)
647 {
648 struct mmci_host *host = mmc_priv(mmc);
649 struct mmc_data *data = mrq->data;
650 struct mmci_host_next *nd = &host->next_data;
651
652 if (!data)
653 return;
654
655 BUG_ON(data->host_cookie);
656
657 if (mmci_validate_data(host, data))
658 return;
659
660 if (!mmci_dma_prep_next(host, data))
661 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
662 }
663
664 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
665 int err)
666 {
667 struct mmci_host *host = mmc_priv(mmc);
668 struct mmc_data *data = mrq->data;
669
670 if (!data || !data->host_cookie)
671 return;
672
673 mmci_dma_unmap(host, data);
674
675 if (err) {
676 struct mmci_host_next *next = &host->next_data;
677 struct dma_chan *chan;
678 if (data->flags & MMC_DATA_READ)
679 chan = host->dma_rx_channel;
680 else
681 chan = host->dma_tx_channel;
682 dmaengine_terminate_all(chan);
683
684 next->dma_desc = NULL;
685 next->dma_chan = NULL;
686 }
687 }
688
689 #else
690 /* Blank functions if the DMA engine is not available */
691 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
692 {
693 }
694 static inline void mmci_dma_setup(struct mmci_host *host)
695 {
696 }
697
698 static inline void mmci_dma_release(struct mmci_host *host)
699 {
700 }
701
702 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
703 {
704 }
705
706 static inline void mmci_dma_finalize(struct mmci_host *host,
707 struct mmc_data *data)
708 {
709 }
710
711 static inline void mmci_dma_data_error(struct mmci_host *host)
712 {
713 }
714
715 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
716 {
717 return -ENOSYS;
718 }
719
720 #define mmci_pre_request NULL
721 #define mmci_post_request NULL
722
723 #endif
724
725 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
726 {
727 struct variant_data *variant = host->variant;
728 unsigned int datactrl, timeout, irqmask;
729 unsigned long long clks;
730 void __iomem *base;
731 int blksz_bits;
732
733 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
734 data->blksz, data->blocks, data->flags);
735
736 host->data = data;
737 host->size = data->blksz * data->blocks;
738 data->bytes_xfered = 0;
739
740 clks = (unsigned long long)data->timeout_ns * host->cclk;
741 do_div(clks, 1000000000UL);
742
743 timeout = data->timeout_clks + (unsigned int)clks;
744
745 base = host->base;
746 writel(timeout, base + MMCIDATATIMER);
747 writel(host->size, base + MMCIDATALENGTH);
748
749 blksz_bits = ffs(data->blksz) - 1;
750 BUG_ON(1 << blksz_bits != data->blksz);
751
752 if (variant->blksz_datactrl16)
753 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
754 else
755 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
756
757 if (data->flags & MMC_DATA_READ)
758 datactrl |= MCI_DPSM_DIRECTION;
759
760 /* The ST Micro variants has a special bit to enable SDIO */
761 if (variant->sdio && host->mmc->card)
762 if (mmc_card_sdio(host->mmc->card)) {
763 /*
764 * The ST Micro variants has a special bit
765 * to enable SDIO.
766 */
767 u32 clk;
768
769 datactrl |= MCI_ST_DPSM_SDIOEN;
770
771 /*
772 * The ST Micro variant for SDIO small write transfers
773 * needs to have clock H/W flow control disabled,
774 * otherwise the transfer will not start. The threshold
775 * depends on the rate of MCLK.
776 */
777 if (data->flags & MMC_DATA_WRITE &&
778 (host->size < 8 ||
779 (host->size <= 8 && host->mclk > 50000000)))
780 clk = host->clk_reg & ~variant->clkreg_enable;
781 else
782 clk = host->clk_reg | variant->clkreg_enable;
783
784 mmci_write_clkreg(host, clk);
785 }
786
787 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
788 datactrl |= MCI_ST_DPSM_DDRMODE;
789
790 /*
791 * Attempt to use DMA operation mode, if this
792 * should fail, fall back to PIO mode
793 */
794 if (!mmci_dma_start_data(host, datactrl))
795 return;
796
797 /* IRQ mode, map the SG list for CPU reading/writing */
798 mmci_init_sg(host, data);
799
800 if (data->flags & MMC_DATA_READ) {
801 irqmask = MCI_RXFIFOHALFFULLMASK;
802
803 /*
804 * If we have less than the fifo 'half-full' threshold to
805 * transfer, trigger a PIO interrupt as soon as any data
806 * is available.
807 */
808 if (host->size < variant->fifohalfsize)
809 irqmask |= MCI_RXDATAAVLBLMASK;
810 } else {
811 /*
812 * We don't actually need to include "FIFO empty" here
813 * since its implicit in "FIFO half empty".
814 */
815 irqmask = MCI_TXFIFOHALFEMPTYMASK;
816 }
817
818 mmci_write_datactrlreg(host, datactrl);
819 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
820 mmci_set_mask1(host, irqmask);
821 }
822
823 static void
824 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
825 {
826 void __iomem *base = host->base;
827
828 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
829 cmd->opcode, cmd->arg, cmd->flags);
830
831 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
832 writel(0, base + MMCICOMMAND);
833 udelay(1);
834 }
835
836 c |= cmd->opcode | MCI_CPSM_ENABLE;
837 if (cmd->flags & MMC_RSP_PRESENT) {
838 if (cmd->flags & MMC_RSP_136)
839 c |= MCI_CPSM_LONGRSP;
840 c |= MCI_CPSM_RESPONSE;
841 }
842 if (/*interrupt*/0)
843 c |= MCI_CPSM_INTERRUPT;
844
845 host->cmd = cmd;
846
847 writel(cmd->arg, base + MMCIARGUMENT);
848 writel(c, base + MMCICOMMAND);
849 }
850
851 static void
852 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
853 unsigned int status)
854 {
855 /* First check for errors */
856 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
857 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
858 u32 remain, success;
859
860 /* Terminate the DMA transfer */
861 if (dma_inprogress(host)) {
862 mmci_dma_data_error(host);
863 mmci_dma_unmap(host, data);
864 }
865
866 /*
867 * Calculate how far we are into the transfer. Note that
868 * the data counter gives the number of bytes transferred
869 * on the MMC bus, not on the host side. On reads, this
870 * can be as much as a FIFO-worth of data ahead. This
871 * matters for FIFO overruns only.
872 */
873 remain = readl(host->base + MMCIDATACNT);
874 success = data->blksz * data->blocks - remain;
875
876 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
877 status, success);
878 if (status & MCI_DATACRCFAIL) {
879 /* Last block was not successful */
880 success -= 1;
881 data->error = -EILSEQ;
882 } else if (status & MCI_DATATIMEOUT) {
883 data->error = -ETIMEDOUT;
884 } else if (status & MCI_STARTBITERR) {
885 data->error = -ECOMM;
886 } else if (status & MCI_TXUNDERRUN) {
887 data->error = -EIO;
888 } else if (status & MCI_RXOVERRUN) {
889 if (success > host->variant->fifosize)
890 success -= host->variant->fifosize;
891 else
892 success = 0;
893 data->error = -EIO;
894 }
895 data->bytes_xfered = round_down(success, data->blksz);
896 }
897
898 if (status & MCI_DATABLOCKEND)
899 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
900
901 if (status & MCI_DATAEND || data->error) {
902 if (dma_inprogress(host))
903 mmci_dma_finalize(host, data);
904 mmci_stop_data(host);
905
906 if (!data->error)
907 /* The error clause is handled above, success! */
908 data->bytes_xfered = data->blksz * data->blocks;
909
910 if (!data->stop || host->mrq->sbc) {
911 mmci_request_end(host, data->mrq);
912 } else {
913 mmci_start_command(host, data->stop, 0);
914 }
915 }
916 }
917
918 static void
919 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
920 unsigned int status)
921 {
922 void __iomem *base = host->base;
923 bool sbc = (cmd == host->mrq->sbc);
924
925 host->cmd = NULL;
926
927 if (status & MCI_CMDTIMEOUT) {
928 cmd->error = -ETIMEDOUT;
929 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
930 cmd->error = -EILSEQ;
931 } else {
932 cmd->resp[0] = readl(base + MMCIRESPONSE0);
933 cmd->resp[1] = readl(base + MMCIRESPONSE1);
934 cmd->resp[2] = readl(base + MMCIRESPONSE2);
935 cmd->resp[3] = readl(base + MMCIRESPONSE3);
936 }
937
938 if ((!sbc && !cmd->data) || cmd->error) {
939 if (host->data) {
940 /* Terminate the DMA transfer */
941 if (dma_inprogress(host)) {
942 mmci_dma_data_error(host);
943 mmci_dma_unmap(host, host->data);
944 }
945 mmci_stop_data(host);
946 }
947 mmci_request_end(host, host->mrq);
948 } else if (sbc) {
949 mmci_start_command(host, host->mrq->cmd, 0);
950 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
951 mmci_start_data(host, cmd->data);
952 }
953 }
954
955 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
956 {
957 void __iomem *base = host->base;
958 char *ptr = buffer;
959 u32 status;
960 int host_remain = host->size;
961
962 do {
963 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
964
965 if (count > remain)
966 count = remain;
967
968 if (count <= 0)
969 break;
970
971 /*
972 * SDIO especially may want to send something that is
973 * not divisible by 4 (as opposed to card sectors
974 * etc). Therefore make sure to always read the last bytes
975 * while only doing full 32-bit reads towards the FIFO.
976 */
977 if (unlikely(count & 0x3)) {
978 if (count < 4) {
979 unsigned char buf[4];
980 ioread32_rep(base + MMCIFIFO, buf, 1);
981 memcpy(ptr, buf, count);
982 } else {
983 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
984 count &= ~0x3;
985 }
986 } else {
987 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
988 }
989
990 ptr += count;
991 remain -= count;
992 host_remain -= count;
993
994 if (remain == 0)
995 break;
996
997 status = readl(base + MMCISTATUS);
998 } while (status & MCI_RXDATAAVLBL);
999
1000 return ptr - buffer;
1001 }
1002
1003 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1004 {
1005 struct variant_data *variant = host->variant;
1006 void __iomem *base = host->base;
1007 char *ptr = buffer;
1008
1009 do {
1010 unsigned int count, maxcnt;
1011
1012 maxcnt = status & MCI_TXFIFOEMPTY ?
1013 variant->fifosize : variant->fifohalfsize;
1014 count = min(remain, maxcnt);
1015
1016 /*
1017 * SDIO especially may want to send something that is
1018 * not divisible by 4 (as opposed to card sectors
1019 * etc), and the FIFO only accept full 32-bit writes.
1020 * So compensate by adding +3 on the count, a single
1021 * byte become a 32bit write, 7 bytes will be two
1022 * 32bit writes etc.
1023 */
1024 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1025
1026 ptr += count;
1027 remain -= count;
1028
1029 if (remain == 0)
1030 break;
1031
1032 status = readl(base + MMCISTATUS);
1033 } while (status & MCI_TXFIFOHALFEMPTY);
1034
1035 return ptr - buffer;
1036 }
1037
1038 /*
1039 * PIO data transfer IRQ handler.
1040 */
1041 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1042 {
1043 struct mmci_host *host = dev_id;
1044 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1045 struct variant_data *variant = host->variant;
1046 void __iomem *base = host->base;
1047 unsigned long flags;
1048 u32 status;
1049
1050 status = readl(base + MMCISTATUS);
1051
1052 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1053
1054 local_irq_save(flags);
1055
1056 do {
1057 unsigned int remain, len;
1058 char *buffer;
1059
1060 /*
1061 * For write, we only need to test the half-empty flag
1062 * here - if the FIFO is completely empty, then by
1063 * definition it is more than half empty.
1064 *
1065 * For read, check for data available.
1066 */
1067 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1068 break;
1069
1070 if (!sg_miter_next(sg_miter))
1071 break;
1072
1073 buffer = sg_miter->addr;
1074 remain = sg_miter->length;
1075
1076 len = 0;
1077 if (status & MCI_RXACTIVE)
1078 len = mmci_pio_read(host, buffer, remain);
1079 if (status & MCI_TXACTIVE)
1080 len = mmci_pio_write(host, buffer, remain, status);
1081
1082 sg_miter->consumed = len;
1083
1084 host->size -= len;
1085 remain -= len;
1086
1087 if (remain)
1088 break;
1089
1090 status = readl(base + MMCISTATUS);
1091 } while (1);
1092
1093 sg_miter_stop(sg_miter);
1094
1095 local_irq_restore(flags);
1096
1097 /*
1098 * If we have less than the fifo 'half-full' threshold to transfer,
1099 * trigger a PIO interrupt as soon as any data is available.
1100 */
1101 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1102 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1103
1104 /*
1105 * If we run out of data, disable the data IRQs; this
1106 * prevents a race where the FIFO becomes empty before
1107 * the chip itself has disabled the data path, and
1108 * stops us racing with our data end IRQ.
1109 */
1110 if (host->size == 0) {
1111 mmci_set_mask1(host, 0);
1112 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1113 }
1114
1115 return IRQ_HANDLED;
1116 }
1117
1118 /*
1119 * Handle completion of command and data transfers.
1120 */
1121 static irqreturn_t mmci_irq(int irq, void *dev_id)
1122 {
1123 struct mmci_host *host = dev_id;
1124 u32 status;
1125 int ret = 0;
1126
1127 spin_lock(&host->lock);
1128
1129 do {
1130 struct mmc_command *cmd;
1131 struct mmc_data *data;
1132
1133 status = readl(host->base + MMCISTATUS);
1134
1135 if (host->singleirq) {
1136 if (status & readl(host->base + MMCIMASK1))
1137 mmci_pio_irq(irq, dev_id);
1138
1139 status &= ~MCI_IRQ1MASK;
1140 }
1141
1142 status &= readl(host->base + MMCIMASK0);
1143 writel(status, host->base + MMCICLEAR);
1144
1145 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1146
1147 data = host->data;
1148 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1149 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1150 MCI_DATABLOCKEND) && data)
1151 mmci_data_irq(host, data, status);
1152
1153 cmd = host->cmd;
1154 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1155 mmci_cmd_irq(host, cmd, status);
1156
1157 ret = 1;
1158 } while (status);
1159
1160 spin_unlock(&host->lock);
1161
1162 return IRQ_RETVAL(ret);
1163 }
1164
1165 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1166 {
1167 struct mmci_host *host = mmc_priv(mmc);
1168 unsigned long flags;
1169
1170 WARN_ON(host->mrq != NULL);
1171
1172 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1173 if (mrq->cmd->error) {
1174 mmc_request_done(mmc, mrq);
1175 return;
1176 }
1177
1178 pm_runtime_get_sync(mmc_dev(mmc));
1179
1180 spin_lock_irqsave(&host->lock, flags);
1181
1182 host->mrq = mrq;
1183
1184 if (mrq->data)
1185 mmci_get_next_data(host, mrq->data);
1186
1187 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1188 mmci_start_data(host, mrq->data);
1189
1190 if (mrq->sbc)
1191 mmci_start_command(host, mrq->sbc, 0);
1192 else
1193 mmci_start_command(host, mrq->cmd, 0);
1194
1195 spin_unlock_irqrestore(&host->lock, flags);
1196 }
1197
1198 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1199 {
1200 struct mmci_host *host = mmc_priv(mmc);
1201 struct variant_data *variant = host->variant;
1202 u32 pwr = 0;
1203 unsigned long flags;
1204 int ret;
1205
1206 pm_runtime_get_sync(mmc_dev(mmc));
1207
1208 if (host->plat->ios_handler &&
1209 host->plat->ios_handler(mmc_dev(mmc), ios))
1210 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1211
1212 switch (ios->power_mode) {
1213 case MMC_POWER_OFF:
1214 if (!IS_ERR(mmc->supply.vmmc))
1215 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1216
1217 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1218 regulator_disable(mmc->supply.vqmmc);
1219 host->vqmmc_enabled = false;
1220 }
1221
1222 break;
1223 case MMC_POWER_UP:
1224 if (!IS_ERR(mmc->supply.vmmc))
1225 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1226
1227 /*
1228 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1229 * and instead uses MCI_PWR_ON so apply whatever value is
1230 * configured in the variant data.
1231 */
1232 pwr |= variant->pwrreg_powerup;
1233
1234 break;
1235 case MMC_POWER_ON:
1236 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1237 ret = regulator_enable(mmc->supply.vqmmc);
1238 if (ret < 0)
1239 dev_err(mmc_dev(mmc),
1240 "failed to enable vqmmc regulator\n");
1241 else
1242 host->vqmmc_enabled = true;
1243 }
1244
1245 pwr |= MCI_PWR_ON;
1246 break;
1247 }
1248
1249 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1250 /*
1251 * The ST Micro variant has some additional bits
1252 * indicating signal direction for the signals in
1253 * the SD/MMC bus and feedback-clock usage.
1254 */
1255 pwr |= host->plat->sigdir;
1256
1257 if (ios->bus_width == MMC_BUS_WIDTH_4)
1258 pwr &= ~MCI_ST_DATA74DIREN;
1259 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1260 pwr &= (~MCI_ST_DATA74DIREN &
1261 ~MCI_ST_DATA31DIREN &
1262 ~MCI_ST_DATA2DIREN);
1263 }
1264
1265 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1266 if (host->hw_designer != AMBA_VENDOR_ST)
1267 pwr |= MCI_ROD;
1268 else {
1269 /*
1270 * The ST Micro variant use the ROD bit for something
1271 * else and only has OD (Open Drain).
1272 */
1273 pwr |= MCI_OD;
1274 }
1275 }
1276
1277 /*
1278 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1279 * gating the clock, the MCI_PWR_ON bit is cleared.
1280 */
1281 if (!ios->clock && variant->pwrreg_clkgate)
1282 pwr &= ~MCI_PWR_ON;
1283
1284 spin_lock_irqsave(&host->lock, flags);
1285
1286 mmci_set_clkreg(host, ios->clock);
1287 mmci_write_pwrreg(host, pwr);
1288 mmci_reg_delay(host);
1289
1290 spin_unlock_irqrestore(&host->lock, flags);
1291
1292 pm_runtime_mark_last_busy(mmc_dev(mmc));
1293 pm_runtime_put_autosuspend(mmc_dev(mmc));
1294 }
1295
1296 static int mmci_get_ro(struct mmc_host *mmc)
1297 {
1298 struct mmci_host *host = mmc_priv(mmc);
1299
1300 if (host->gpio_wp == -ENOSYS)
1301 return -ENOSYS;
1302
1303 return gpio_get_value_cansleep(host->gpio_wp);
1304 }
1305
1306 static int mmci_get_cd(struct mmc_host *mmc)
1307 {
1308 struct mmci_host *host = mmc_priv(mmc);
1309 struct mmci_platform_data *plat = host->plat;
1310 unsigned int status;
1311
1312 if (host->gpio_cd == -ENOSYS) {
1313 if (!plat->status)
1314 return 1; /* Assume always present */
1315
1316 status = plat->status(mmc_dev(host->mmc));
1317 } else
1318 status = !!gpio_get_value_cansleep(host->gpio_cd)
1319 ^ plat->cd_invert;
1320
1321 /*
1322 * Use positive logic throughout - status is zero for no card,
1323 * non-zero for card inserted.
1324 */
1325 return status;
1326 }
1327
1328 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1329 {
1330 int ret = 0;
1331
1332 if (!IS_ERR(mmc->supply.vqmmc)) {
1333
1334 pm_runtime_get_sync(mmc_dev(mmc));
1335
1336 switch (ios->signal_voltage) {
1337 case MMC_SIGNAL_VOLTAGE_330:
1338 ret = regulator_set_voltage(mmc->supply.vqmmc,
1339 2700000, 3600000);
1340 break;
1341 case MMC_SIGNAL_VOLTAGE_180:
1342 ret = regulator_set_voltage(mmc->supply.vqmmc,
1343 1700000, 1950000);
1344 break;
1345 case MMC_SIGNAL_VOLTAGE_120:
1346 ret = regulator_set_voltage(mmc->supply.vqmmc,
1347 1100000, 1300000);
1348 break;
1349 }
1350
1351 if (ret)
1352 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1353
1354 pm_runtime_mark_last_busy(mmc_dev(mmc));
1355 pm_runtime_put_autosuspend(mmc_dev(mmc));
1356 }
1357
1358 return ret;
1359 }
1360
1361 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1362 {
1363 struct mmci_host *host = dev_id;
1364
1365 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1366
1367 return IRQ_HANDLED;
1368 }
1369
1370 static struct mmc_host_ops mmci_ops = {
1371 .request = mmci_request,
1372 .pre_req = mmci_pre_request,
1373 .post_req = mmci_post_request,
1374 .set_ios = mmci_set_ios,
1375 .get_ro = mmci_get_ro,
1376 .get_cd = mmci_get_cd,
1377 .start_signal_voltage_switch = mmci_sig_volt_switch,
1378 };
1379
1380 #ifdef CONFIG_OF
1381 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1382 struct mmci_platform_data *pdata)
1383 {
1384 int bus_width = 0;
1385
1386 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1387 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
1388
1389 if (of_get_property(np, "cd-inverted", NULL))
1390 pdata->cd_invert = true;
1391 else
1392 pdata->cd_invert = false;
1393
1394 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1395 if (!pdata->f_max)
1396 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1397
1398 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1399 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1400 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1401 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1402
1403 of_property_read_u32(np, "bus-width", &bus_width);
1404 switch (bus_width) {
1405 case 0 :
1406 /* No bus-width supplied. */
1407 break;
1408 case 4 :
1409 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1410 break;
1411 case 8 :
1412 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1413 break;
1414 default :
1415 pr_warn("%s: Unsupported bus width\n", np->full_name);
1416 }
1417 }
1418 #else
1419 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1420 struct mmci_platform_data *pdata)
1421 {
1422 return;
1423 }
1424 #endif
1425
1426 static int mmci_probe(struct amba_device *dev,
1427 const struct amba_id *id)
1428 {
1429 struct mmci_platform_data *plat = dev->dev.platform_data;
1430 struct device_node *np = dev->dev.of_node;
1431 struct variant_data *variant = id->data;
1432 struct mmci_host *host;
1433 struct mmc_host *mmc;
1434 int ret;
1435
1436 /* Must have platform data or Device Tree. */
1437 if (!plat && !np) {
1438 dev_err(&dev->dev, "No plat data or DT found\n");
1439 return -EINVAL;
1440 }
1441
1442 if (!plat) {
1443 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1444 if (!plat)
1445 return -ENOMEM;
1446 }
1447
1448 if (np)
1449 mmci_dt_populate_generic_pdata(np, plat);
1450
1451 ret = amba_request_regions(dev, DRIVER_NAME);
1452 if (ret)
1453 goto out;
1454
1455 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1456 if (!mmc) {
1457 ret = -ENOMEM;
1458 goto rel_regions;
1459 }
1460
1461 host = mmc_priv(mmc);
1462 host->mmc = mmc;
1463
1464 host->gpio_wp = -ENOSYS;
1465 host->gpio_cd = -ENOSYS;
1466 host->gpio_cd_irq = -1;
1467
1468 host->hw_designer = amba_manf(dev);
1469 host->hw_revision = amba_rev(dev);
1470 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1471 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1472
1473 host->clk = devm_clk_get(&dev->dev, NULL);
1474 if (IS_ERR(host->clk)) {
1475 ret = PTR_ERR(host->clk);
1476 goto host_free;
1477 }
1478
1479 ret = clk_prepare_enable(host->clk);
1480 if (ret)
1481 goto host_free;
1482
1483 host->plat = plat;
1484 host->variant = variant;
1485 host->mclk = clk_get_rate(host->clk);
1486 /*
1487 * According to the spec, mclk is max 100 MHz,
1488 * so we try to adjust the clock down to this,
1489 * (if possible).
1490 */
1491 if (host->mclk > 100000000) {
1492 ret = clk_set_rate(host->clk, 100000000);
1493 if (ret < 0)
1494 goto clk_disable;
1495 host->mclk = clk_get_rate(host->clk);
1496 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1497 host->mclk);
1498 }
1499 host->phybase = dev->res.start;
1500 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1501 if (!host->base) {
1502 ret = -ENOMEM;
1503 goto clk_disable;
1504 }
1505
1506 if (variant->busy_detect) {
1507 mmci_ops.card_busy = mmci_card_busy;
1508 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1509 }
1510
1511 mmc->ops = &mmci_ops;
1512 /*
1513 * The ARM and ST versions of the block have slightly different
1514 * clock divider equations which means that the minimum divider
1515 * differs too.
1516 */
1517 if (variant->st_clkdiv)
1518 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1519 else
1520 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1521 /*
1522 * If the platform data supplies a maximum operating
1523 * frequency, this takes precedence. Else, we fall back
1524 * to using the module parameter, which has a (low)
1525 * default value in case it is not specified. Either
1526 * value must not exceed the clock rate into the block,
1527 * of course.
1528 */
1529 if (plat->f_max)
1530 mmc->f_max = min(host->mclk, plat->f_max);
1531 else
1532 mmc->f_max = min(host->mclk, fmax);
1533 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1534
1535 /* Get regulators and the supported OCR mask */
1536 mmc_regulator_get_supply(mmc);
1537 if (!mmc->ocr_avail)
1538 mmc->ocr_avail = plat->ocr_mask;
1539 else if (plat->ocr_mask)
1540 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1541
1542 mmc->caps = plat->capabilities;
1543 mmc->caps2 = plat->capabilities2;
1544
1545 /* We support these PM capabilities. */
1546 mmc->pm_caps = MMC_PM_KEEP_POWER;
1547
1548 /*
1549 * We can do SGIO
1550 */
1551 mmc->max_segs = NR_SG;
1552
1553 /*
1554 * Since only a certain number of bits are valid in the data length
1555 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1556 * single request.
1557 */
1558 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1559
1560 /*
1561 * Set the maximum segment size. Since we aren't doing DMA
1562 * (yet) we are only limited by the data length register.
1563 */
1564 mmc->max_seg_size = mmc->max_req_size;
1565
1566 /*
1567 * Block size can be up to 2048 bytes, but must be a power of two.
1568 */
1569 mmc->max_blk_size = 1 << 11;
1570
1571 /*
1572 * Limit the number of blocks transferred so that we don't overflow
1573 * the maximum request size.
1574 */
1575 mmc->max_blk_count = mmc->max_req_size >> 11;
1576
1577 spin_lock_init(&host->lock);
1578
1579 writel(0, host->base + MMCIMASK0);
1580 writel(0, host->base + MMCIMASK1);
1581 writel(0xfff, host->base + MMCICLEAR);
1582
1583 if (plat->gpio_cd == -EPROBE_DEFER) {
1584 ret = -EPROBE_DEFER;
1585 goto err_gpio_cd;
1586 }
1587 if (gpio_is_valid(plat->gpio_cd)) {
1588 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1589 if (ret == 0)
1590 ret = gpio_direction_input(plat->gpio_cd);
1591 if (ret == 0)
1592 host->gpio_cd = plat->gpio_cd;
1593 else if (ret != -ENOSYS)
1594 goto err_gpio_cd;
1595
1596 /*
1597 * A gpio pin that will detect cards when inserted and removed
1598 * will most likely want to trigger on the edges if it is
1599 * 0 when ejected and 1 when inserted (or mutatis mutandis
1600 * for the inverted case) so we request triggers on both
1601 * edges.
1602 */
1603 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1604 mmci_cd_irq,
1605 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1606 DRIVER_NAME " (cd)", host);
1607 if (ret >= 0)
1608 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1609 }
1610 if (plat->gpio_wp == -EPROBE_DEFER) {
1611 ret = -EPROBE_DEFER;
1612 goto err_gpio_wp;
1613 }
1614 if (gpio_is_valid(plat->gpio_wp)) {
1615 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1616 if (ret == 0)
1617 ret = gpio_direction_input(plat->gpio_wp);
1618 if (ret == 0)
1619 host->gpio_wp = plat->gpio_wp;
1620 else if (ret != -ENOSYS)
1621 goto err_gpio_wp;
1622 }
1623
1624 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1625 && host->gpio_cd_irq < 0)
1626 mmc->caps |= MMC_CAP_NEEDS_POLL;
1627
1628 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1629 if (ret)
1630 goto unmap;
1631
1632 if (!dev->irq[1])
1633 host->singleirq = true;
1634 else {
1635 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1636 DRIVER_NAME " (pio)", host);
1637 if (ret)
1638 goto irq0_free;
1639 }
1640
1641 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1642
1643 amba_set_drvdata(dev, mmc);
1644
1645 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1646 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1647 amba_rev(dev), (unsigned long long)dev->res.start,
1648 dev->irq[0], dev->irq[1]);
1649
1650 mmci_dma_setup(host);
1651
1652 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1653 pm_runtime_use_autosuspend(&dev->dev);
1654 pm_runtime_put(&dev->dev);
1655
1656 mmc_add_host(mmc);
1657
1658 return 0;
1659
1660 irq0_free:
1661 free_irq(dev->irq[0], host);
1662 unmap:
1663 if (host->gpio_wp != -ENOSYS)
1664 gpio_free(host->gpio_wp);
1665 err_gpio_wp:
1666 if (host->gpio_cd_irq >= 0)
1667 free_irq(host->gpio_cd_irq, host);
1668 if (host->gpio_cd != -ENOSYS)
1669 gpio_free(host->gpio_cd);
1670 err_gpio_cd:
1671 iounmap(host->base);
1672 clk_disable:
1673 clk_disable_unprepare(host->clk);
1674 host_free:
1675 mmc_free_host(mmc);
1676 rel_regions:
1677 amba_release_regions(dev);
1678 out:
1679 return ret;
1680 }
1681
1682 static int mmci_remove(struct amba_device *dev)
1683 {
1684 struct mmc_host *mmc = amba_get_drvdata(dev);
1685
1686 amba_set_drvdata(dev, NULL);
1687
1688 if (mmc) {
1689 struct mmci_host *host = mmc_priv(mmc);
1690
1691 /*
1692 * Undo pm_runtime_put() in probe. We use the _sync
1693 * version here so that we can access the primecell.
1694 */
1695 pm_runtime_get_sync(&dev->dev);
1696
1697 mmc_remove_host(mmc);
1698
1699 writel(0, host->base + MMCIMASK0);
1700 writel(0, host->base + MMCIMASK1);
1701
1702 writel(0, host->base + MMCICOMMAND);
1703 writel(0, host->base + MMCIDATACTRL);
1704
1705 mmci_dma_release(host);
1706 free_irq(dev->irq[0], host);
1707 if (!host->singleirq)
1708 free_irq(dev->irq[1], host);
1709
1710 if (host->gpio_wp != -ENOSYS)
1711 gpio_free(host->gpio_wp);
1712 if (host->gpio_cd_irq >= 0)
1713 free_irq(host->gpio_cd_irq, host);
1714 if (host->gpio_cd != -ENOSYS)
1715 gpio_free(host->gpio_cd);
1716
1717 iounmap(host->base);
1718 clk_disable_unprepare(host->clk);
1719
1720 mmc_free_host(mmc);
1721
1722 amba_release_regions(dev);
1723 }
1724
1725 return 0;
1726 }
1727
1728 #ifdef CONFIG_SUSPEND
1729 static int mmci_suspend(struct device *dev)
1730 {
1731 struct amba_device *adev = to_amba_device(dev);
1732 struct mmc_host *mmc = amba_get_drvdata(adev);
1733
1734 if (mmc) {
1735 struct mmci_host *host = mmc_priv(mmc);
1736 pm_runtime_get_sync(dev);
1737 writel(0, host->base + MMCIMASK0);
1738 }
1739
1740 return 0;
1741 }
1742
1743 static int mmci_resume(struct device *dev)
1744 {
1745 struct amba_device *adev = to_amba_device(dev);
1746 struct mmc_host *mmc = amba_get_drvdata(adev);
1747
1748 if (mmc) {
1749 struct mmci_host *host = mmc_priv(mmc);
1750 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1751 pm_runtime_put(dev);
1752 }
1753
1754 return 0;
1755 }
1756 #endif
1757
1758 #ifdef CONFIG_PM_RUNTIME
1759 static void mmci_save(struct mmci_host *host)
1760 {
1761 unsigned long flags;
1762
1763 if (host->variant->pwrreg_nopower) {
1764 spin_lock_irqsave(&host->lock, flags);
1765
1766 writel(0, host->base + MMCIMASK0);
1767 writel(0, host->base + MMCIDATACTRL);
1768 writel(0, host->base + MMCIPOWER);
1769 writel(0, host->base + MMCICLOCK);
1770 mmci_reg_delay(host);
1771
1772 spin_unlock_irqrestore(&host->lock, flags);
1773 }
1774
1775 }
1776
1777 static void mmci_restore(struct mmci_host *host)
1778 {
1779 unsigned long flags;
1780
1781 if (host->variant->pwrreg_nopower) {
1782 spin_lock_irqsave(&host->lock, flags);
1783
1784 writel(host->clk_reg, host->base + MMCICLOCK);
1785 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1786 writel(host->pwr_reg, host->base + MMCIPOWER);
1787 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1788 mmci_reg_delay(host);
1789
1790 spin_unlock_irqrestore(&host->lock, flags);
1791 }
1792 }
1793
1794 static int mmci_runtime_suspend(struct device *dev)
1795 {
1796 struct amba_device *adev = to_amba_device(dev);
1797 struct mmc_host *mmc = amba_get_drvdata(adev);
1798
1799 if (mmc) {
1800 struct mmci_host *host = mmc_priv(mmc);
1801 pinctrl_pm_select_sleep_state(dev);
1802 mmci_save(host);
1803 clk_disable_unprepare(host->clk);
1804 }
1805
1806 return 0;
1807 }
1808
1809 static int mmci_runtime_resume(struct device *dev)
1810 {
1811 struct amba_device *adev = to_amba_device(dev);
1812 struct mmc_host *mmc = amba_get_drvdata(adev);
1813
1814 if (mmc) {
1815 struct mmci_host *host = mmc_priv(mmc);
1816 clk_prepare_enable(host->clk);
1817 mmci_restore(host);
1818 pinctrl_pm_select_default_state(dev);
1819 }
1820
1821 return 0;
1822 }
1823 #endif
1824
1825 static const struct dev_pm_ops mmci_dev_pm_ops = {
1826 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
1827 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1828 };
1829
1830 static struct amba_id mmci_ids[] = {
1831 {
1832 .id = 0x00041180,
1833 .mask = 0xff0fffff,
1834 .data = &variant_arm,
1835 },
1836 {
1837 .id = 0x01041180,
1838 .mask = 0xff0fffff,
1839 .data = &variant_arm_extended_fifo,
1840 },
1841 {
1842 .id = 0x02041180,
1843 .mask = 0xff0fffff,
1844 .data = &variant_arm_extended_fifo_hwfc,
1845 },
1846 {
1847 .id = 0x00041181,
1848 .mask = 0x000fffff,
1849 .data = &variant_arm,
1850 },
1851 /* ST Micro variants */
1852 {
1853 .id = 0x00180180,
1854 .mask = 0x00ffffff,
1855 .data = &variant_u300,
1856 },
1857 {
1858 .id = 0x10180180,
1859 .mask = 0xf0ffffff,
1860 .data = &variant_nomadik,
1861 },
1862 {
1863 .id = 0x00280180,
1864 .mask = 0x00ffffff,
1865 .data = &variant_u300,
1866 },
1867 {
1868 .id = 0x00480180,
1869 .mask = 0xf0ffffff,
1870 .data = &variant_ux500,
1871 },
1872 {
1873 .id = 0x10480180,
1874 .mask = 0xf0ffffff,
1875 .data = &variant_ux500v2,
1876 },
1877 { 0, 0 },
1878 };
1879
1880 MODULE_DEVICE_TABLE(amba, mmci_ids);
1881
1882 static struct amba_driver mmci_driver = {
1883 .drv = {
1884 .name = DRIVER_NAME,
1885 .pm = &mmci_dev_pm_ops,
1886 },
1887 .probe = mmci_probe,
1888 .remove = mmci_remove,
1889 .id_table = mmci_ids,
1890 };
1891
1892 module_amba_driver(mmci_driver);
1893
1894 module_param(fmax, uint, 0444);
1895
1896 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1897 MODULE_LICENSE("GPL");
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