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Merge branch 'spi-4.20' into spi-linus
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / mtk-sd.c
1 /*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_gpio.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/interrupt.h>
33
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/sd.h>
39 #include <linux/mmc/sdio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #define MAX_BD_NUM 1024
43
44 /*--------------------------------------------------------------------------*/
45 /* Common Definition */
46 /*--------------------------------------------------------------------------*/
47 #define MSDC_BUS_1BITS 0x0
48 #define MSDC_BUS_4BITS 0x1
49 #define MSDC_BUS_8BITS 0x2
50
51 #define MSDC_BURST_64B 0x6
52
53 /*--------------------------------------------------------------------------*/
54 /* Register Offset */
55 /*--------------------------------------------------------------------------*/
56 #define MSDC_CFG 0x0
57 #define MSDC_IOCON 0x04
58 #define MSDC_PS 0x08
59 #define MSDC_INT 0x0c
60 #define MSDC_INTEN 0x10
61 #define MSDC_FIFOCS 0x14
62 #define SDC_CFG 0x30
63 #define SDC_CMD 0x34
64 #define SDC_ARG 0x38
65 #define SDC_STS 0x3c
66 #define SDC_RESP0 0x40
67 #define SDC_RESP1 0x44
68 #define SDC_RESP2 0x48
69 #define SDC_RESP3 0x4c
70 #define SDC_BLK_NUM 0x50
71 #define SDC_ADV_CFG0 0x64
72 #define EMMC_IOCON 0x7c
73 #define SDC_ACMD_RESP 0x80
74 #define DMA_SA_H4BIT 0x8c
75 #define MSDC_DMA_SA 0x90
76 #define MSDC_DMA_CTRL 0x98
77 #define MSDC_DMA_CFG 0x9c
78 #define MSDC_PATCH_BIT 0xb0
79 #define MSDC_PATCH_BIT1 0xb4
80 #define MSDC_PATCH_BIT2 0xb8
81 #define MSDC_PAD_TUNE 0xec
82 #define MSDC_PAD_TUNE0 0xf0
83 #define PAD_DS_TUNE 0x188
84 #define PAD_CMD_TUNE 0x18c
85 #define EMMC50_CFG0 0x208
86 #define EMMC50_CFG3 0x220
87 #define SDC_FIFO_CFG 0x228
88
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL 0x00
93 #define EMMC_TOP_CMD 0x04
94 #define EMMC50_PAD_DS_TUNE 0x0c
95
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask */
98 /*--------------------------------------------------------------------------*/
99
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
102 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
103 #define MSDC_CFG_RST (0x1 << 2) /* RW */
104 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
105 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
106 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
107 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
108 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
109 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
110 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
111 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
113 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
114 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
115
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
118 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
119 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
120 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
121 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
122 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
123 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
124 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
125 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
126 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
127 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
128 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
129 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
130 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
131 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
132 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
133
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
136 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
137 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
138 #define MSDC_PS_DAT (0xff << 16) /* R */
139 #define MSDC_PS_CMD (0x1 << 24) /* R */
140 #define MSDC_PS_WP (0x1 << 31) /* R */
141
142 /* MSDC_INT mask */
143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
153 #define MSDC_INT_CSTA (0x1 << 11) /* R */
154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
162
163 /* MSDC_INTEN mask */
164 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
165 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
166 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
167 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
168 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
169 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
170 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
171 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
172 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
173 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
174 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
175 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
176 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
177 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
178 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
179 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
180 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
181 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
182 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
183
184 /* MSDC_FIFOCS mask */
185 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
186 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
187 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
188
189 /* SDC_CFG mask */
190 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
191 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
192 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
193 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
194 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
195 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
196 #define SDC_CFG_DTOC (0xff << 24) /* RW */
197
198 /* SDC_STS mask */
199 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
200 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
201 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
202
203 /* SDC_ADV_CFG0 mask */
204 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
205
206 /* DMA_SA_H4BIT mask */
207 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
208
209 /* MSDC_DMA_CTRL mask */
210 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
211 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
212 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
213 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
214 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
215 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
216
217 /* MSDC_DMA_CFG mask */
218 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
219 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
220 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
221 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
222 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
223
224 /* MSDC_PATCH_BIT mask */
225 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
226 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
227 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
228 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
229 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
230 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
231 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
232 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
233 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
234 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
235 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
236 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
237
238 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
239
240 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
241 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
242 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
243 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
244 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
245 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
246
247 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
248 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
249 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
250 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
251 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
252 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
253 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
254 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
255
256 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
257 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
258 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
259
260 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
261
262 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
263 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
264 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
265
266 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
267
268 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
269 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
270
271 /* EMMC_TOP_CONTROL mask */
272 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */
273 #define DELAY_EN (0x1 << 1) /* RW */
274 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
275 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
276 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
277 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
278 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
279 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */
280
281 /* EMMC_TOP_CMD mask */
282 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
283 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */
284 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
285 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
286 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
287
288 #define REQ_CMD_EIO (0x1 << 0)
289 #define REQ_CMD_TMO (0x1 << 1)
290 #define REQ_DAT_ERR (0x1 << 2)
291 #define REQ_STOP_EIO (0x1 << 3)
292 #define REQ_STOP_TMO (0x1 << 4)
293 #define REQ_CMD_BUSY (0x1 << 5)
294
295 #define MSDC_PREPARE_FLAG (0x1 << 0)
296 #define MSDC_ASYNC_FLAG (0x1 << 1)
297 #define MSDC_MMAP_FLAG (0x1 << 2)
298
299 #define MTK_MMC_AUTOSUSPEND_DELAY 50
300 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
301 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
302
303 #define PAD_DELAY_MAX 32 /* PAD delay cells */
304 /*--------------------------------------------------------------------------*/
305 /* Descriptor Structure */
306 /*--------------------------------------------------------------------------*/
307 struct mt_gpdma_desc {
308 u32 gpd_info;
309 #define GPDMA_DESC_HWO (0x1 << 0)
310 #define GPDMA_DESC_BDP (0x1 << 1)
311 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
312 #define GPDMA_DESC_INT (0x1 << 16)
313 #define GPDMA_DESC_NEXT_H4 (0xf << 24)
314 #define GPDMA_DESC_PTR_H4 (0xf << 28)
315 u32 next;
316 u32 ptr;
317 u32 gpd_data_len;
318 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
319 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
320 u32 arg;
321 u32 blknum;
322 u32 cmd;
323 };
324
325 struct mt_bdma_desc {
326 u32 bd_info;
327 #define BDMA_DESC_EOL (0x1 << 0)
328 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
329 #define BDMA_DESC_BLKPAD (0x1 << 17)
330 #define BDMA_DESC_DWPAD (0x1 << 18)
331 #define BDMA_DESC_NEXT_H4 (0xf << 24)
332 #define BDMA_DESC_PTR_H4 (0xf << 28)
333 u32 next;
334 u32 ptr;
335 u32 bd_data_len;
336 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
337 };
338
339 struct msdc_dma {
340 struct scatterlist *sg; /* I/O scatter list */
341 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
342 struct mt_bdma_desc *bd; /* pointer to bd array */
343 dma_addr_t gpd_addr; /* the physical address of gpd array */
344 dma_addr_t bd_addr; /* the physical address of bd array */
345 };
346
347 struct msdc_save_para {
348 u32 msdc_cfg;
349 u32 iocon;
350 u32 sdc_cfg;
351 u32 pad_tune;
352 u32 patch_bit0;
353 u32 patch_bit1;
354 u32 patch_bit2;
355 u32 pad_ds_tune;
356 u32 pad_cmd_tune;
357 u32 emmc50_cfg0;
358 u32 emmc50_cfg3;
359 u32 sdc_fifo_cfg;
360 u32 emmc_top_control;
361 u32 emmc_top_cmd;
362 u32 emmc50_pad_ds_tune;
363 };
364
365 struct mtk_mmc_compatible {
366 u8 clk_div_bits;
367 bool hs400_tune; /* only used for MT8173 */
368 u32 pad_tune_reg;
369 bool async_fifo;
370 bool data_tune;
371 bool busy_check;
372 bool stop_clk_fix;
373 bool enhance_rx;
374 bool support_64g;
375 };
376
377 struct msdc_tune_para {
378 u32 iocon;
379 u32 pad_tune;
380 u32 pad_cmd_tune;
381 u32 emmc_top_control;
382 u32 emmc_top_cmd;
383 };
384
385 struct msdc_delay_phase {
386 u8 maxlen;
387 u8 start;
388 u8 final_phase;
389 };
390
391 struct msdc_host {
392 struct device *dev;
393 const struct mtk_mmc_compatible *dev_comp;
394 struct mmc_host *mmc; /* mmc structure */
395 int cmd_rsp;
396
397 spinlock_t lock;
398 struct mmc_request *mrq;
399 struct mmc_command *cmd;
400 struct mmc_data *data;
401 int error;
402
403 void __iomem *base; /* host base address */
404 void __iomem *top_base; /* host top register base address */
405
406 struct msdc_dma dma; /* dma channel */
407 u64 dma_mask;
408
409 u32 timeout_ns; /* data timeout ns */
410 u32 timeout_clks; /* data timeout clks */
411
412 struct pinctrl *pinctrl;
413 struct pinctrl_state *pins_default;
414 struct pinctrl_state *pins_uhs;
415 struct delayed_work req_timeout;
416 int irq; /* host interrupt */
417
418 struct clk *src_clk; /* msdc source clock */
419 struct clk *h_clk; /* msdc h_clk */
420 struct clk *bus_clk; /* bus clock which used to access register */
421 struct clk *src_clk_cg; /* msdc source clock control gate */
422 u32 mclk; /* mmc subsystem clock frequency */
423 u32 src_clk_freq; /* source clock frequency */
424 unsigned char timing;
425 bool vqmmc_enabled;
426 u32 latch_ck;
427 u32 hs400_ds_delay;
428 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
429 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
430 bool hs400_cmd_resp_sel_rising;
431 /* cmd response sample selection for HS400 */
432 bool hs400_mode; /* current eMMC will run at hs400 mode */
433 struct msdc_save_para save_para; /* used when gate HCLK */
434 struct msdc_tune_para def_tune_para; /* default tune setting */
435 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
436 };
437
438 static const struct mtk_mmc_compatible mt8135_compat = {
439 .clk_div_bits = 8,
440 .hs400_tune = false,
441 .pad_tune_reg = MSDC_PAD_TUNE,
442 .async_fifo = false,
443 .data_tune = false,
444 .busy_check = false,
445 .stop_clk_fix = false,
446 .enhance_rx = false,
447 .support_64g = false,
448 };
449
450 static const struct mtk_mmc_compatible mt8173_compat = {
451 .clk_div_bits = 8,
452 .hs400_tune = true,
453 .pad_tune_reg = MSDC_PAD_TUNE,
454 .async_fifo = false,
455 .data_tune = false,
456 .busy_check = false,
457 .stop_clk_fix = false,
458 .enhance_rx = false,
459 .support_64g = false,
460 };
461
462 static const struct mtk_mmc_compatible mt8183_compat = {
463 .clk_div_bits = 12,
464 .hs400_tune = false,
465 .pad_tune_reg = MSDC_PAD_TUNE0,
466 .async_fifo = true,
467 .data_tune = true,
468 .busy_check = true,
469 .stop_clk_fix = true,
470 .enhance_rx = true,
471 .support_64g = true,
472 };
473
474 static const struct mtk_mmc_compatible mt2701_compat = {
475 .clk_div_bits = 12,
476 .hs400_tune = false,
477 .pad_tune_reg = MSDC_PAD_TUNE0,
478 .async_fifo = true,
479 .data_tune = true,
480 .busy_check = false,
481 .stop_clk_fix = false,
482 .enhance_rx = false,
483 .support_64g = false,
484 };
485
486 static const struct mtk_mmc_compatible mt2712_compat = {
487 .clk_div_bits = 12,
488 .hs400_tune = false,
489 .pad_tune_reg = MSDC_PAD_TUNE0,
490 .async_fifo = true,
491 .data_tune = true,
492 .busy_check = true,
493 .stop_clk_fix = true,
494 .enhance_rx = true,
495 .support_64g = true,
496 };
497
498 static const struct mtk_mmc_compatible mt7622_compat = {
499 .clk_div_bits = 12,
500 .hs400_tune = false,
501 .pad_tune_reg = MSDC_PAD_TUNE0,
502 .async_fifo = true,
503 .data_tune = true,
504 .busy_check = true,
505 .stop_clk_fix = true,
506 .enhance_rx = true,
507 .support_64g = false,
508 };
509
510 static const struct of_device_id msdc_of_ids[] = {
511 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
512 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
513 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
514 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
515 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
516 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
517 {}
518 };
519 MODULE_DEVICE_TABLE(of, msdc_of_ids);
520
521 static void sdr_set_bits(void __iomem *reg, u32 bs)
522 {
523 u32 val = readl(reg);
524
525 val |= bs;
526 writel(val, reg);
527 }
528
529 static void sdr_clr_bits(void __iomem *reg, u32 bs)
530 {
531 u32 val = readl(reg);
532
533 val &= ~bs;
534 writel(val, reg);
535 }
536
537 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
538 {
539 unsigned int tv = readl(reg);
540
541 tv &= ~field;
542 tv |= ((val) << (ffs((unsigned int)field) - 1));
543 writel(tv, reg);
544 }
545
546 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
547 {
548 unsigned int tv = readl(reg);
549
550 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
551 }
552
553 static void msdc_reset_hw(struct msdc_host *host)
554 {
555 u32 val;
556
557 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
558 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
559 cpu_relax();
560
561 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
562 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
563 cpu_relax();
564
565 val = readl(host->base + MSDC_INT);
566 writel(val, host->base + MSDC_INT);
567 }
568
569 static void msdc_cmd_next(struct msdc_host *host,
570 struct mmc_request *mrq, struct mmc_command *cmd);
571
572 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
573 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
574 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
575 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
576 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
577 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
578
579 static u8 msdc_dma_calcs(u8 *buf, u32 len)
580 {
581 u32 i, sum = 0;
582
583 for (i = 0; i < len; i++)
584 sum += buf[i];
585 return 0xff - (u8) sum;
586 }
587
588 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
589 struct mmc_data *data)
590 {
591 unsigned int j, dma_len;
592 dma_addr_t dma_address;
593 u32 dma_ctrl;
594 struct scatterlist *sg;
595 struct mt_gpdma_desc *gpd;
596 struct mt_bdma_desc *bd;
597
598 sg = data->sg;
599
600 gpd = dma->gpd;
601 bd = dma->bd;
602
603 /* modify gpd */
604 gpd->gpd_info |= GPDMA_DESC_HWO;
605 gpd->gpd_info |= GPDMA_DESC_BDP;
606 /* need to clear first. use these bits to calc checksum */
607 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
608 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
609
610 /* modify bd */
611 for_each_sg(data->sg, sg, data->sg_count, j) {
612 dma_address = sg_dma_address(sg);
613 dma_len = sg_dma_len(sg);
614
615 /* init bd */
616 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
617 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
618 bd[j].ptr = lower_32_bits(dma_address);
619 if (host->dev_comp->support_64g) {
620 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
621 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
622 << 28;
623 }
624 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
625 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
626
627 if (j == data->sg_count - 1) /* the last bd */
628 bd[j].bd_info |= BDMA_DESC_EOL;
629 else
630 bd[j].bd_info &= ~BDMA_DESC_EOL;
631
632 /* checksume need to clear first */
633 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
634 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
635 }
636
637 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
638 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
639 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
640 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
641 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
642 if (host->dev_comp->support_64g)
643 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
644 upper_32_bits(dma->gpd_addr) & 0xf);
645 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
646 }
647
648 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
649 {
650 struct mmc_data *data = mrq->data;
651
652 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
653 data->host_cookie |= MSDC_PREPARE_FLAG;
654 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
655 mmc_get_dma_dir(data));
656 }
657 }
658
659 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
660 {
661 struct mmc_data *data = mrq->data;
662
663 if (data->host_cookie & MSDC_ASYNC_FLAG)
664 return;
665
666 if (data->host_cookie & MSDC_PREPARE_FLAG) {
667 dma_unmap_sg(host->dev, data->sg, data->sg_len,
668 mmc_get_dma_dir(data));
669 data->host_cookie &= ~MSDC_PREPARE_FLAG;
670 }
671 }
672
673 /* clock control primitives */
674 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
675 {
676 u32 timeout, clk_ns;
677 u32 mode = 0;
678
679 host->timeout_ns = ns;
680 host->timeout_clks = clks;
681 if (host->mmc->actual_clock == 0) {
682 timeout = 0;
683 } else {
684 clk_ns = 1000000000UL / host->mmc->actual_clock;
685 timeout = (ns + clk_ns - 1) / clk_ns + clks;
686 /* in 1048576 sclk cycle unit */
687 timeout = (timeout + (0x1 << 20) - 1) >> 20;
688 if (host->dev_comp->clk_div_bits == 8)
689 sdr_get_field(host->base + MSDC_CFG,
690 MSDC_CFG_CKMOD, &mode);
691 else
692 sdr_get_field(host->base + MSDC_CFG,
693 MSDC_CFG_CKMOD_EXTRA, &mode);
694 /*DDR mode will double the clk cycles for data timeout */
695 timeout = mode >= 2 ? timeout * 2 : timeout;
696 timeout = timeout > 1 ? timeout - 1 : 0;
697 timeout = timeout > 255 ? 255 : timeout;
698 }
699 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
700 }
701
702 static void msdc_gate_clock(struct msdc_host *host)
703 {
704 clk_disable_unprepare(host->src_clk_cg);
705 clk_disable_unprepare(host->src_clk);
706 clk_disable_unprepare(host->bus_clk);
707 clk_disable_unprepare(host->h_clk);
708 }
709
710 static void msdc_ungate_clock(struct msdc_host *host)
711 {
712 clk_prepare_enable(host->h_clk);
713 clk_prepare_enable(host->bus_clk);
714 clk_prepare_enable(host->src_clk);
715 clk_prepare_enable(host->src_clk_cg);
716 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
717 cpu_relax();
718 }
719
720 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
721 {
722 u32 mode;
723 u32 flags;
724 u32 div;
725 u32 sclk;
726 u32 tune_reg = host->dev_comp->pad_tune_reg;
727
728 if (!hz) {
729 dev_dbg(host->dev, "set mclk to 0\n");
730 host->mclk = 0;
731 host->mmc->actual_clock = 0;
732 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
733 return;
734 }
735
736 flags = readl(host->base + MSDC_INTEN);
737 sdr_clr_bits(host->base + MSDC_INTEN, flags);
738 if (host->dev_comp->clk_div_bits == 8)
739 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
740 else
741 sdr_clr_bits(host->base + MSDC_CFG,
742 MSDC_CFG_HS400_CK_MODE_EXTRA);
743 if (timing == MMC_TIMING_UHS_DDR50 ||
744 timing == MMC_TIMING_MMC_DDR52 ||
745 timing == MMC_TIMING_MMC_HS400) {
746 if (timing == MMC_TIMING_MMC_HS400)
747 mode = 0x3;
748 else
749 mode = 0x2; /* ddr mode and use divisor */
750
751 if (hz >= (host->src_clk_freq >> 2)) {
752 div = 0; /* mean div = 1/4 */
753 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
754 } else {
755 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
756 sclk = (host->src_clk_freq >> 2) / div;
757 div = (div >> 1);
758 }
759
760 if (timing == MMC_TIMING_MMC_HS400 &&
761 hz >= (host->src_clk_freq >> 1)) {
762 if (host->dev_comp->clk_div_bits == 8)
763 sdr_set_bits(host->base + MSDC_CFG,
764 MSDC_CFG_HS400_CK_MODE);
765 else
766 sdr_set_bits(host->base + MSDC_CFG,
767 MSDC_CFG_HS400_CK_MODE_EXTRA);
768 sclk = host->src_clk_freq >> 1;
769 div = 0; /* div is ignore when bit18 is set */
770 }
771 } else if (hz >= host->src_clk_freq) {
772 mode = 0x1; /* no divisor */
773 div = 0;
774 sclk = host->src_clk_freq;
775 } else {
776 mode = 0x0; /* use divisor */
777 if (hz >= (host->src_clk_freq >> 1)) {
778 div = 0; /* mean div = 1/2 */
779 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
780 } else {
781 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
782 sclk = (host->src_clk_freq >> 2) / div;
783 }
784 }
785 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
786 /*
787 * As src_clk/HCLK use the same bit to gate/ungate,
788 * So if want to only gate src_clk, need gate its parent(mux).
789 */
790 if (host->src_clk_cg)
791 clk_disable_unprepare(host->src_clk_cg);
792 else
793 clk_disable_unprepare(clk_get_parent(host->src_clk));
794 if (host->dev_comp->clk_div_bits == 8)
795 sdr_set_field(host->base + MSDC_CFG,
796 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
797 (mode << 8) | div);
798 else
799 sdr_set_field(host->base + MSDC_CFG,
800 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
801 (mode << 12) | div);
802 if (host->src_clk_cg)
803 clk_prepare_enable(host->src_clk_cg);
804 else
805 clk_prepare_enable(clk_get_parent(host->src_clk));
806
807 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
808 cpu_relax();
809 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
810 host->mmc->actual_clock = sclk;
811 host->mclk = hz;
812 host->timing = timing;
813 /* need because clk changed. */
814 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
815 sdr_set_bits(host->base + MSDC_INTEN, flags);
816
817 /*
818 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
819 * tune result of hs200/200Mhz is not suitable for 50Mhz
820 */
821 if (host->mmc->actual_clock <= 52000000) {
822 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
823 if (host->top_base) {
824 writel(host->def_tune_para.emmc_top_control,
825 host->top_base + EMMC_TOP_CONTROL);
826 writel(host->def_tune_para.emmc_top_cmd,
827 host->top_base + EMMC_TOP_CMD);
828 } else {
829 writel(host->def_tune_para.pad_tune,
830 host->base + tune_reg);
831 }
832 } else {
833 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
834 writel(host->saved_tune_para.pad_cmd_tune,
835 host->base + PAD_CMD_TUNE);
836 if (host->top_base) {
837 writel(host->saved_tune_para.emmc_top_control,
838 host->top_base + EMMC_TOP_CONTROL);
839 writel(host->saved_tune_para.emmc_top_cmd,
840 host->top_base + EMMC_TOP_CMD);
841 } else {
842 writel(host->saved_tune_para.pad_tune,
843 host->base + tune_reg);
844 }
845 }
846
847 if (timing == MMC_TIMING_MMC_HS400 &&
848 host->dev_comp->hs400_tune)
849 sdr_set_field(host->base + PAD_CMD_TUNE,
850 MSDC_PAD_TUNE_CMDRRDLY,
851 host->hs400_cmd_int_delay);
852 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
853 timing);
854 }
855
856 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
857 struct mmc_request *mrq, struct mmc_command *cmd)
858 {
859 u32 resp;
860
861 switch (mmc_resp_type(cmd)) {
862 /* Actually, R1, R5, R6, R7 are the same */
863 case MMC_RSP_R1:
864 resp = 0x1;
865 break;
866 case MMC_RSP_R1B:
867 resp = 0x7;
868 break;
869 case MMC_RSP_R2:
870 resp = 0x2;
871 break;
872 case MMC_RSP_R3:
873 resp = 0x3;
874 break;
875 case MMC_RSP_NONE:
876 default:
877 resp = 0x0;
878 break;
879 }
880
881 return resp;
882 }
883
884 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
885 struct mmc_request *mrq, struct mmc_command *cmd)
886 {
887 /* rawcmd :
888 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
889 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
890 */
891 u32 opcode = cmd->opcode;
892 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
893 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
894
895 host->cmd_rsp = resp;
896
897 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
898 opcode == MMC_STOP_TRANSMISSION)
899 rawcmd |= (0x1 << 14);
900 else if (opcode == SD_SWITCH_VOLTAGE)
901 rawcmd |= (0x1 << 30);
902 else if (opcode == SD_APP_SEND_SCR ||
903 opcode == SD_APP_SEND_NUM_WR_BLKS ||
904 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
905 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
906 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
907 rawcmd |= (0x1 << 11);
908
909 if (cmd->data) {
910 struct mmc_data *data = cmd->data;
911
912 if (mmc_op_multi(opcode)) {
913 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
914 !(mrq->sbc->arg & 0xFFFF0000))
915 rawcmd |= 0x2 << 28; /* AutoCMD23 */
916 }
917
918 rawcmd |= ((data->blksz & 0xFFF) << 16);
919 if (data->flags & MMC_DATA_WRITE)
920 rawcmd |= (0x1 << 13);
921 if (data->blocks > 1)
922 rawcmd |= (0x2 << 11);
923 else
924 rawcmd |= (0x1 << 11);
925 /* Always use dma mode */
926 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
927
928 if (host->timeout_ns != data->timeout_ns ||
929 host->timeout_clks != data->timeout_clks)
930 msdc_set_timeout(host, data->timeout_ns,
931 data->timeout_clks);
932
933 writel(data->blocks, host->base + SDC_BLK_NUM);
934 }
935 return rawcmd;
936 }
937
938 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
939 struct mmc_command *cmd, struct mmc_data *data)
940 {
941 bool read;
942
943 WARN_ON(host->data);
944 host->data = data;
945 read = data->flags & MMC_DATA_READ;
946
947 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
948 msdc_dma_setup(host, &host->dma, data);
949 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
950 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
951 dev_dbg(host->dev, "DMA start\n");
952 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
953 __func__, cmd->opcode, data->blocks, read);
954 }
955
956 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
957 struct mmc_command *cmd)
958 {
959 u32 *rsp = cmd->resp;
960
961 rsp[0] = readl(host->base + SDC_ACMD_RESP);
962
963 if (events & MSDC_INT_ACMDRDY) {
964 cmd->error = 0;
965 } else {
966 msdc_reset_hw(host);
967 if (events & MSDC_INT_ACMDCRCERR) {
968 cmd->error = -EILSEQ;
969 host->error |= REQ_STOP_EIO;
970 } else if (events & MSDC_INT_ACMDTMO) {
971 cmd->error = -ETIMEDOUT;
972 host->error |= REQ_STOP_TMO;
973 }
974 dev_err(host->dev,
975 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
976 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
977 }
978 return cmd->error;
979 }
980
981 static void msdc_track_cmd_data(struct msdc_host *host,
982 struct mmc_command *cmd, struct mmc_data *data)
983 {
984 if (host->error)
985 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
986 __func__, cmd->opcode, cmd->arg, host->error);
987 }
988
989 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
990 {
991 unsigned long flags;
992 bool ret;
993
994 ret = cancel_delayed_work(&host->req_timeout);
995 if (!ret) {
996 /* delay work already running */
997 return;
998 }
999 spin_lock_irqsave(&host->lock, flags);
1000 host->mrq = NULL;
1001 spin_unlock_irqrestore(&host->lock, flags);
1002
1003 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1004 if (mrq->data)
1005 msdc_unprepare_data(host, mrq);
1006 mmc_request_done(host->mmc, mrq);
1007 }
1008
1009 /* returns true if command is fully handled; returns false otherwise */
1010 static bool msdc_cmd_done(struct msdc_host *host, int events,
1011 struct mmc_request *mrq, struct mmc_command *cmd)
1012 {
1013 bool done = false;
1014 bool sbc_error;
1015 unsigned long flags;
1016 u32 *rsp = cmd->resp;
1017
1018 if (mrq->sbc && cmd == mrq->cmd &&
1019 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1020 | MSDC_INT_ACMDTMO)))
1021 msdc_auto_cmd_done(host, events, mrq->sbc);
1022
1023 sbc_error = mrq->sbc && mrq->sbc->error;
1024
1025 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1026 | MSDC_INT_RSPCRCERR
1027 | MSDC_INT_CMDTMO)))
1028 return done;
1029
1030 spin_lock_irqsave(&host->lock, flags);
1031 done = !host->cmd;
1032 host->cmd = NULL;
1033 spin_unlock_irqrestore(&host->lock, flags);
1034
1035 if (done)
1036 return true;
1037
1038 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1039
1040 if (cmd->flags & MMC_RSP_PRESENT) {
1041 if (cmd->flags & MMC_RSP_136) {
1042 rsp[0] = readl(host->base + SDC_RESP3);
1043 rsp[1] = readl(host->base + SDC_RESP2);
1044 rsp[2] = readl(host->base + SDC_RESP1);
1045 rsp[3] = readl(host->base + SDC_RESP0);
1046 } else {
1047 rsp[0] = readl(host->base + SDC_RESP0);
1048 }
1049 }
1050
1051 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1052 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1053 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1054 /*
1055 * should not clear fifo/interrupt as the tune data
1056 * may have alreay come.
1057 */
1058 msdc_reset_hw(host);
1059 if (events & MSDC_INT_RSPCRCERR) {
1060 cmd->error = -EILSEQ;
1061 host->error |= REQ_CMD_EIO;
1062 } else if (events & MSDC_INT_CMDTMO) {
1063 cmd->error = -ETIMEDOUT;
1064 host->error |= REQ_CMD_TMO;
1065 }
1066 }
1067 if (cmd->error)
1068 dev_dbg(host->dev,
1069 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1070 __func__, cmd->opcode, cmd->arg, rsp[0],
1071 cmd->error);
1072
1073 msdc_cmd_next(host, mrq, cmd);
1074 return true;
1075 }
1076
1077 /* It is the core layer's responsibility to ensure card status
1078 * is correct before issue a request. but host design do below
1079 * checks recommended.
1080 */
1081 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1082 struct mmc_request *mrq, struct mmc_command *cmd)
1083 {
1084 /* The max busy time we can endure is 20ms */
1085 unsigned long tmo = jiffies + msecs_to_jiffies(20);
1086
1087 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1088 time_before(jiffies, tmo))
1089 cpu_relax();
1090 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1091 dev_err(host->dev, "CMD bus busy detected\n");
1092 host->error |= REQ_CMD_BUSY;
1093 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1094 return false;
1095 }
1096
1097 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1098 tmo = jiffies + msecs_to_jiffies(20);
1099 /* R1B or with data, should check SDCBUSY */
1100 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1101 time_before(jiffies, tmo))
1102 cpu_relax();
1103 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1104 dev_err(host->dev, "Controller busy detected\n");
1105 host->error |= REQ_CMD_BUSY;
1106 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1107 return false;
1108 }
1109 }
1110 return true;
1111 }
1112
1113 static void msdc_start_command(struct msdc_host *host,
1114 struct mmc_request *mrq, struct mmc_command *cmd)
1115 {
1116 u32 rawcmd;
1117
1118 WARN_ON(host->cmd);
1119 host->cmd = cmd;
1120
1121 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1122 if (!msdc_cmd_is_ready(host, mrq, cmd))
1123 return;
1124
1125 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1126 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1127 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1128 msdc_reset_hw(host);
1129 }
1130
1131 cmd->error = 0;
1132 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1133
1134 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1135 writel(cmd->arg, host->base + SDC_ARG);
1136 writel(rawcmd, host->base + SDC_CMD);
1137 }
1138
1139 static void msdc_cmd_next(struct msdc_host *host,
1140 struct mmc_request *mrq, struct mmc_command *cmd)
1141 {
1142 if ((cmd->error &&
1143 !(cmd->error == -EILSEQ &&
1144 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1145 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1146 (mrq->sbc && mrq->sbc->error))
1147 msdc_request_done(host, mrq);
1148 else if (cmd == mrq->sbc)
1149 msdc_start_command(host, mrq, mrq->cmd);
1150 else if (!cmd->data)
1151 msdc_request_done(host, mrq);
1152 else
1153 msdc_start_data(host, mrq, cmd, cmd->data);
1154 }
1155
1156 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1157 {
1158 struct msdc_host *host = mmc_priv(mmc);
1159
1160 host->error = 0;
1161 WARN_ON(host->mrq);
1162 host->mrq = mrq;
1163
1164 if (mrq->data)
1165 msdc_prepare_data(host, mrq);
1166
1167 /* if SBC is required, we have HW option and SW option.
1168 * if HW option is enabled, and SBC does not have "special" flags,
1169 * use HW option, otherwise use SW option
1170 */
1171 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1172 (mrq->sbc->arg & 0xFFFF0000)))
1173 msdc_start_command(host, mrq, mrq->sbc);
1174 else
1175 msdc_start_command(host, mrq, mrq->cmd);
1176 }
1177
1178 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1179 {
1180 struct msdc_host *host = mmc_priv(mmc);
1181 struct mmc_data *data = mrq->data;
1182
1183 if (!data)
1184 return;
1185
1186 msdc_prepare_data(host, mrq);
1187 data->host_cookie |= MSDC_ASYNC_FLAG;
1188 }
1189
1190 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1191 int err)
1192 {
1193 struct msdc_host *host = mmc_priv(mmc);
1194 struct mmc_data *data;
1195
1196 data = mrq->data;
1197 if (!data)
1198 return;
1199 if (data->host_cookie) {
1200 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1201 msdc_unprepare_data(host, mrq);
1202 }
1203 }
1204
1205 static void msdc_data_xfer_next(struct msdc_host *host,
1206 struct mmc_request *mrq, struct mmc_data *data)
1207 {
1208 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1209 !mrq->sbc)
1210 msdc_start_command(host, mrq, mrq->stop);
1211 else
1212 msdc_request_done(host, mrq);
1213 }
1214
1215 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1216 struct mmc_request *mrq, struct mmc_data *data)
1217 {
1218 struct mmc_command *stop = data->stop;
1219 unsigned long flags;
1220 bool done;
1221 unsigned int check_data = events &
1222 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1223 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1224 | MSDC_INT_DMA_PROTECT);
1225
1226 spin_lock_irqsave(&host->lock, flags);
1227 done = !host->data;
1228 if (check_data)
1229 host->data = NULL;
1230 spin_unlock_irqrestore(&host->lock, flags);
1231
1232 if (done)
1233 return true;
1234
1235 if (check_data || (stop && stop->error)) {
1236 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1237 readl(host->base + MSDC_DMA_CFG));
1238 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1239 1);
1240 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1241 cpu_relax();
1242 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1243 dev_dbg(host->dev, "DMA stop\n");
1244
1245 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1246 data->bytes_xfered = data->blocks * data->blksz;
1247 } else {
1248 dev_dbg(host->dev, "interrupt events: %x\n", events);
1249 msdc_reset_hw(host);
1250 host->error |= REQ_DAT_ERR;
1251 data->bytes_xfered = 0;
1252
1253 if (events & MSDC_INT_DATTMO)
1254 data->error = -ETIMEDOUT;
1255 else if (events & MSDC_INT_DATCRCERR)
1256 data->error = -EILSEQ;
1257
1258 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1259 __func__, mrq->cmd->opcode, data->blocks);
1260 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1261 (int)data->error, data->bytes_xfered);
1262 }
1263
1264 msdc_data_xfer_next(host, mrq, data);
1265 done = true;
1266 }
1267 return done;
1268 }
1269
1270 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1271 {
1272 u32 val = readl(host->base + SDC_CFG);
1273
1274 val &= ~SDC_CFG_BUSWIDTH;
1275
1276 switch (width) {
1277 default:
1278 case MMC_BUS_WIDTH_1:
1279 val |= (MSDC_BUS_1BITS << 16);
1280 break;
1281 case MMC_BUS_WIDTH_4:
1282 val |= (MSDC_BUS_4BITS << 16);
1283 break;
1284 case MMC_BUS_WIDTH_8:
1285 val |= (MSDC_BUS_8BITS << 16);
1286 break;
1287 }
1288
1289 writel(val, host->base + SDC_CFG);
1290 dev_dbg(host->dev, "Bus Width = %d", width);
1291 }
1292
1293 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1294 {
1295 struct msdc_host *host = mmc_priv(mmc);
1296 int ret = 0;
1297
1298 if (!IS_ERR(mmc->supply.vqmmc)) {
1299 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1300 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1301 dev_err(host->dev, "Unsupported signal voltage!\n");
1302 return -EINVAL;
1303 }
1304
1305 ret = mmc_regulator_set_vqmmc(mmc, ios);
1306 if (ret) {
1307 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1308 ret, ios->signal_voltage);
1309 } else {
1310 /* Apply different pinctrl settings for different signal voltage */
1311 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1312 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1313 else
1314 pinctrl_select_state(host->pinctrl, host->pins_default);
1315 }
1316 }
1317 return ret;
1318 }
1319
1320 static int msdc_card_busy(struct mmc_host *mmc)
1321 {
1322 struct msdc_host *host = mmc_priv(mmc);
1323 u32 status = readl(host->base + MSDC_PS);
1324
1325 /* only check if data0 is low */
1326 return !(status & BIT(16));
1327 }
1328
1329 static void msdc_request_timeout(struct work_struct *work)
1330 {
1331 struct msdc_host *host = container_of(work, struct msdc_host,
1332 req_timeout.work);
1333
1334 /* simulate HW timeout status */
1335 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1336 if (host->mrq) {
1337 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1338 host->mrq, host->mrq->cmd->opcode);
1339 if (host->cmd) {
1340 dev_err(host->dev, "%s: aborting cmd=%d\n",
1341 __func__, host->cmd->opcode);
1342 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1343 host->cmd);
1344 } else if (host->data) {
1345 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1346 __func__, host->mrq->cmd->opcode,
1347 host->data->blocks);
1348 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1349 host->data);
1350 }
1351 }
1352 }
1353
1354 static irqreturn_t msdc_irq(int irq, void *dev_id)
1355 {
1356 struct msdc_host *host = (struct msdc_host *) dev_id;
1357
1358 while (true) {
1359 unsigned long flags;
1360 struct mmc_request *mrq;
1361 struct mmc_command *cmd;
1362 struct mmc_data *data;
1363 u32 events, event_mask;
1364
1365 spin_lock_irqsave(&host->lock, flags);
1366 events = readl(host->base + MSDC_INT);
1367 event_mask = readl(host->base + MSDC_INTEN);
1368 /* clear interrupts */
1369 writel(events & event_mask, host->base + MSDC_INT);
1370
1371 mrq = host->mrq;
1372 cmd = host->cmd;
1373 data = host->data;
1374 spin_unlock_irqrestore(&host->lock, flags);
1375
1376 if (!(events & event_mask))
1377 break;
1378
1379 if (!mrq) {
1380 dev_err(host->dev,
1381 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1382 __func__, events, event_mask);
1383 WARN_ON(1);
1384 break;
1385 }
1386
1387 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1388
1389 if (cmd)
1390 msdc_cmd_done(host, events, mrq, cmd);
1391 else if (data)
1392 msdc_data_xfer_done(host, events, mrq, data);
1393 }
1394
1395 return IRQ_HANDLED;
1396 }
1397
1398 static void msdc_init_hw(struct msdc_host *host)
1399 {
1400 u32 val;
1401 u32 tune_reg = host->dev_comp->pad_tune_reg;
1402
1403 /* Configure to MMC/SD mode, clock free running */
1404 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1405
1406 /* Reset */
1407 msdc_reset_hw(host);
1408
1409 /* Disable card detection */
1410 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1411
1412 /* Disable and clear all interrupts */
1413 writel(0, host->base + MSDC_INTEN);
1414 val = readl(host->base + MSDC_INT);
1415 writel(val, host->base + MSDC_INT);
1416
1417 if (host->top_base) {
1418 writel(0, host->top_base + EMMC_TOP_CONTROL);
1419 writel(0, host->top_base + EMMC_TOP_CMD);
1420 } else {
1421 writel(0, host->base + tune_reg);
1422 }
1423 writel(0, host->base + MSDC_IOCON);
1424 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1425 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1426 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1427 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1428 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1429
1430 if (host->dev_comp->stop_clk_fix) {
1431 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1432 MSDC_PATCH_BIT1_STOP_DLY, 3);
1433 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1434 SDC_FIFO_CFG_WRVALIDSEL);
1435 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1436 SDC_FIFO_CFG_RDVALIDSEL);
1437 }
1438
1439 if (host->dev_comp->busy_check)
1440 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1441
1442 if (host->dev_comp->async_fifo) {
1443 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1444 MSDC_PB2_RESPWAIT, 3);
1445 if (host->dev_comp->enhance_rx) {
1446 if (host->top_base)
1447 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1448 SDC_RX_ENH_EN);
1449 else
1450 sdr_set_bits(host->base + SDC_ADV_CFG0,
1451 SDC_RX_ENHANCE_EN);
1452 } else {
1453 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1454 MSDC_PB2_RESPSTSENSEL, 2);
1455 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1456 MSDC_PB2_CRCSTSENSEL, 2);
1457 }
1458 /* use async fifo, then no need tune internal delay */
1459 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1460 MSDC_PATCH_BIT2_CFGRESP);
1461 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1462 MSDC_PATCH_BIT2_CFGCRCSTS);
1463 }
1464
1465 if (host->dev_comp->support_64g)
1466 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1467 MSDC_PB2_SUPPORT_64G);
1468 if (host->dev_comp->data_tune) {
1469 if (host->top_base) {
1470 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1471 PAD_DAT_RD_RXDLY_SEL);
1472 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1473 DATA_K_VALUE_SEL);
1474 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1475 PAD_CMD_RD_RXDLY_SEL);
1476 } else {
1477 sdr_set_bits(host->base + tune_reg,
1478 MSDC_PAD_TUNE_RD_SEL |
1479 MSDC_PAD_TUNE_CMD_SEL);
1480 }
1481 } else {
1482 /* choose clock tune */
1483 if (host->top_base)
1484 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1485 PAD_RXDLY_SEL);
1486 else
1487 sdr_set_bits(host->base + tune_reg,
1488 MSDC_PAD_TUNE_RXDLYSEL);
1489 }
1490
1491 /* Configure to enable SDIO mode.
1492 * it's must otherwise sdio cmd5 failed
1493 */
1494 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1495
1496 /* disable detect SDIO device interrupt function */
1497 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1498
1499 /* Configure to default data timeout */
1500 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1501
1502 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1503 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1504 if (host->top_base) {
1505 host->def_tune_para.emmc_top_control =
1506 readl(host->top_base + EMMC_TOP_CONTROL);
1507 host->def_tune_para.emmc_top_cmd =
1508 readl(host->top_base + EMMC_TOP_CMD);
1509 host->saved_tune_para.emmc_top_control =
1510 readl(host->top_base + EMMC_TOP_CONTROL);
1511 host->saved_tune_para.emmc_top_cmd =
1512 readl(host->top_base + EMMC_TOP_CMD);
1513 } else {
1514 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1515 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1516 }
1517 dev_dbg(host->dev, "init hardware done!");
1518 }
1519
1520 static void msdc_deinit_hw(struct msdc_host *host)
1521 {
1522 u32 val;
1523 /* Disable and clear all interrupts */
1524 writel(0, host->base + MSDC_INTEN);
1525
1526 val = readl(host->base + MSDC_INT);
1527 writel(val, host->base + MSDC_INT);
1528 }
1529
1530 /* init gpd and bd list in msdc_drv_probe */
1531 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1532 {
1533 struct mt_gpdma_desc *gpd = dma->gpd;
1534 struct mt_bdma_desc *bd = dma->bd;
1535 dma_addr_t dma_addr;
1536 int i;
1537
1538 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1539
1540 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1541 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1542 /* gpd->next is must set for desc DMA
1543 * That's why must alloc 2 gpd structure.
1544 */
1545 gpd->next = lower_32_bits(dma_addr);
1546 if (host->dev_comp->support_64g)
1547 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1548
1549 dma_addr = dma->bd_addr;
1550 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1551 if (host->dev_comp->support_64g)
1552 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1553
1554 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1555 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1556 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1557 bd[i].next = lower_32_bits(dma_addr);
1558 if (host->dev_comp->support_64g)
1559 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1560 }
1561 }
1562
1563 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1564 {
1565 struct msdc_host *host = mmc_priv(mmc);
1566 int ret;
1567
1568 msdc_set_buswidth(host, ios->bus_width);
1569
1570 /* Suspend/Resume will do power off/on */
1571 switch (ios->power_mode) {
1572 case MMC_POWER_UP:
1573 if (!IS_ERR(mmc->supply.vmmc)) {
1574 msdc_init_hw(host);
1575 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1576 ios->vdd);
1577 if (ret) {
1578 dev_err(host->dev, "Failed to set vmmc power!\n");
1579 return;
1580 }
1581 }
1582 break;
1583 case MMC_POWER_ON:
1584 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1585 ret = regulator_enable(mmc->supply.vqmmc);
1586 if (ret)
1587 dev_err(host->dev, "Failed to set vqmmc power!\n");
1588 else
1589 host->vqmmc_enabled = true;
1590 }
1591 break;
1592 case MMC_POWER_OFF:
1593 if (!IS_ERR(mmc->supply.vmmc))
1594 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1595
1596 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1597 regulator_disable(mmc->supply.vqmmc);
1598 host->vqmmc_enabled = false;
1599 }
1600 break;
1601 default:
1602 break;
1603 }
1604
1605 if (host->mclk != ios->clock || host->timing != ios->timing)
1606 msdc_set_mclk(host, ios->timing, ios->clock);
1607 }
1608
1609 static u32 test_delay_bit(u32 delay, u32 bit)
1610 {
1611 bit %= PAD_DELAY_MAX;
1612 return delay & (1 << bit);
1613 }
1614
1615 static int get_delay_len(u32 delay, u32 start_bit)
1616 {
1617 int i;
1618
1619 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1620 if (test_delay_bit(delay, start_bit + i) == 0)
1621 return i;
1622 }
1623 return PAD_DELAY_MAX - start_bit;
1624 }
1625
1626 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1627 {
1628 int start = 0, len = 0;
1629 int start_final = 0, len_final = 0;
1630 u8 final_phase = 0xff;
1631 struct msdc_delay_phase delay_phase = { 0, };
1632
1633 if (delay == 0) {
1634 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1635 delay_phase.final_phase = final_phase;
1636 return delay_phase;
1637 }
1638
1639 while (start < PAD_DELAY_MAX) {
1640 len = get_delay_len(delay, start);
1641 if (len_final < len) {
1642 start_final = start;
1643 len_final = len;
1644 }
1645 start += len ? len : 1;
1646 if (len >= 12 && start_final < 4)
1647 break;
1648 }
1649
1650 /* The rule is that to find the smallest delay cell */
1651 if (start_final == 0)
1652 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1653 else
1654 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1655 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1656 delay, len_final, final_phase);
1657
1658 delay_phase.maxlen = len_final;
1659 delay_phase.start = start_final;
1660 delay_phase.final_phase = final_phase;
1661 return delay_phase;
1662 }
1663
1664 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1665 {
1666 u32 tune_reg = host->dev_comp->pad_tune_reg;
1667
1668 if (host->top_base)
1669 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1670 value);
1671 else
1672 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1673 value);
1674 }
1675
1676 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1677 {
1678 u32 tune_reg = host->dev_comp->pad_tune_reg;
1679
1680 if (host->top_base)
1681 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1682 PAD_DAT_RD_RXDLY, value);
1683 else
1684 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1685 value);
1686 }
1687
1688 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1689 {
1690 struct msdc_host *host = mmc_priv(mmc);
1691 u32 rise_delay = 0, fall_delay = 0;
1692 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1693 struct msdc_delay_phase internal_delay_phase;
1694 u8 final_delay, final_maxlen;
1695 u32 internal_delay = 0;
1696 u32 tune_reg = host->dev_comp->pad_tune_reg;
1697 int cmd_err;
1698 int i, j;
1699
1700 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1701 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1702 sdr_set_field(host->base + tune_reg,
1703 MSDC_PAD_TUNE_CMDRRDLY,
1704 host->hs200_cmd_int_delay);
1705
1706 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1707 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1708 msdc_set_cmd_delay(host, i);
1709 /*
1710 * Using the same parameters, it may sometimes pass the test,
1711 * but sometimes it may fail. To make sure the parameters are
1712 * more stable, we test each set of parameters 3 times.
1713 */
1714 for (j = 0; j < 3; j++) {
1715 mmc_send_tuning(mmc, opcode, &cmd_err);
1716 if (!cmd_err) {
1717 rise_delay |= (1 << i);
1718 } else {
1719 rise_delay &= ~(1 << i);
1720 break;
1721 }
1722 }
1723 }
1724 final_rise_delay = get_best_delay(host, rise_delay);
1725 /* if rising edge has enough margin, then do not scan falling edge */
1726 if (final_rise_delay.maxlen >= 12 ||
1727 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1728 goto skip_fall;
1729
1730 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1731 for (i = 0; i < PAD_DELAY_MAX; i++) {
1732 msdc_set_cmd_delay(host, i);
1733 /*
1734 * Using the same parameters, it may sometimes pass the test,
1735 * but sometimes it may fail. To make sure the parameters are
1736 * more stable, we test each set of parameters 3 times.
1737 */
1738 for (j = 0; j < 3; j++) {
1739 mmc_send_tuning(mmc, opcode, &cmd_err);
1740 if (!cmd_err) {
1741 fall_delay |= (1 << i);
1742 } else {
1743 fall_delay &= ~(1 << i);
1744 break;
1745 }
1746 }
1747 }
1748 final_fall_delay = get_best_delay(host, fall_delay);
1749
1750 skip_fall:
1751 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1752 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1753 final_maxlen = final_fall_delay.maxlen;
1754 if (final_maxlen == final_rise_delay.maxlen) {
1755 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1756 final_delay = final_rise_delay.final_phase;
1757 } else {
1758 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1759 final_delay = final_fall_delay.final_phase;
1760 }
1761 msdc_set_cmd_delay(host, final_delay);
1762
1763 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1764 goto skip_internal;
1765
1766 for (i = 0; i < PAD_DELAY_MAX; i++) {
1767 sdr_set_field(host->base + tune_reg,
1768 MSDC_PAD_TUNE_CMDRRDLY, i);
1769 mmc_send_tuning(mmc, opcode, &cmd_err);
1770 if (!cmd_err)
1771 internal_delay |= (1 << i);
1772 }
1773 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1774 internal_delay_phase = get_best_delay(host, internal_delay);
1775 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1776 internal_delay_phase.final_phase);
1777 skip_internal:
1778 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1779 return final_delay == 0xff ? -EIO : 0;
1780 }
1781
1782 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1783 {
1784 struct msdc_host *host = mmc_priv(mmc);
1785 u32 cmd_delay = 0;
1786 struct msdc_delay_phase final_cmd_delay = { 0,};
1787 u8 final_delay;
1788 int cmd_err;
1789 int i, j;
1790
1791 /* select EMMC50 PAD CMD tune */
1792 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1793
1794 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1795 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1796 sdr_set_field(host->base + MSDC_PAD_TUNE,
1797 MSDC_PAD_TUNE_CMDRRDLY,
1798 host->hs200_cmd_int_delay);
1799
1800 if (host->hs400_cmd_resp_sel_rising)
1801 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1802 else
1803 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1804 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1805 sdr_set_field(host->base + PAD_CMD_TUNE,
1806 PAD_CMD_TUNE_RX_DLY3, i);
1807 /*
1808 * Using the same parameters, it may sometimes pass the test,
1809 * but sometimes it may fail. To make sure the parameters are
1810 * more stable, we test each set of parameters 3 times.
1811 */
1812 for (j = 0; j < 3; j++) {
1813 mmc_send_tuning(mmc, opcode, &cmd_err);
1814 if (!cmd_err) {
1815 cmd_delay |= (1 << i);
1816 } else {
1817 cmd_delay &= ~(1 << i);
1818 break;
1819 }
1820 }
1821 }
1822 final_cmd_delay = get_best_delay(host, cmd_delay);
1823 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1824 final_cmd_delay.final_phase);
1825 final_delay = final_cmd_delay.final_phase;
1826
1827 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1828 return final_delay == 0xff ? -EIO : 0;
1829 }
1830
1831 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1832 {
1833 struct msdc_host *host = mmc_priv(mmc);
1834 u32 rise_delay = 0, fall_delay = 0;
1835 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1836 u8 final_delay, final_maxlen;
1837 int i, ret;
1838
1839 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1840 host->latch_ck);
1841 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1842 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1843 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1844 msdc_set_data_delay(host, i);
1845 ret = mmc_send_tuning(mmc, opcode, NULL);
1846 if (!ret)
1847 rise_delay |= (1 << i);
1848 }
1849 final_rise_delay = get_best_delay(host, rise_delay);
1850 /* if rising edge has enough margin, then do not scan falling edge */
1851 if (final_rise_delay.maxlen >= 12 ||
1852 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1853 goto skip_fall;
1854
1855 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1856 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1857 for (i = 0; i < PAD_DELAY_MAX; i++) {
1858 msdc_set_data_delay(host, i);
1859 ret = mmc_send_tuning(mmc, opcode, NULL);
1860 if (!ret)
1861 fall_delay |= (1 << i);
1862 }
1863 final_fall_delay = get_best_delay(host, fall_delay);
1864
1865 skip_fall:
1866 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1867 if (final_maxlen == final_rise_delay.maxlen) {
1868 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1869 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1870 final_delay = final_rise_delay.final_phase;
1871 } else {
1872 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1873 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1874 final_delay = final_fall_delay.final_phase;
1875 }
1876 msdc_set_data_delay(host, final_delay);
1877
1878 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1879 return final_delay == 0xff ? -EIO : 0;
1880 }
1881
1882 /*
1883 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1884 * together, which can save the tuning time.
1885 */
1886 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
1887 {
1888 struct msdc_host *host = mmc_priv(mmc);
1889 u32 rise_delay = 0, fall_delay = 0;
1890 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1891 u8 final_delay, final_maxlen;
1892 int i, ret;
1893
1894 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1895 host->latch_ck);
1896
1897 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1898 sdr_clr_bits(host->base + MSDC_IOCON,
1899 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1900 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1901 msdc_set_cmd_delay(host, i);
1902 msdc_set_data_delay(host, i);
1903 ret = mmc_send_tuning(mmc, opcode, NULL);
1904 if (!ret)
1905 rise_delay |= (1 << i);
1906 }
1907 final_rise_delay = get_best_delay(host, rise_delay);
1908 /* if rising edge has enough margin, then do not scan falling edge */
1909 if (final_rise_delay.maxlen >= 12 ||
1910 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1911 goto skip_fall;
1912
1913 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1914 sdr_set_bits(host->base + MSDC_IOCON,
1915 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1916 for (i = 0; i < PAD_DELAY_MAX; i++) {
1917 msdc_set_cmd_delay(host, i);
1918 msdc_set_data_delay(host, i);
1919 ret = mmc_send_tuning(mmc, opcode, NULL);
1920 if (!ret)
1921 fall_delay |= (1 << i);
1922 }
1923 final_fall_delay = get_best_delay(host, fall_delay);
1924
1925 skip_fall:
1926 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1927 if (final_maxlen == final_rise_delay.maxlen) {
1928 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1929 sdr_clr_bits(host->base + MSDC_IOCON,
1930 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1931 final_delay = final_rise_delay.final_phase;
1932 } else {
1933 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1934 sdr_set_bits(host->base + MSDC_IOCON,
1935 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1936 final_delay = final_fall_delay.final_phase;
1937 }
1938
1939 msdc_set_cmd_delay(host, final_delay);
1940 msdc_set_data_delay(host, final_delay);
1941
1942 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
1943 return final_delay == 0xff ? -EIO : 0;
1944 }
1945
1946 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1947 {
1948 struct msdc_host *host = mmc_priv(mmc);
1949 int ret;
1950 u32 tune_reg = host->dev_comp->pad_tune_reg;
1951
1952 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1953 ret = msdc_tune_together(mmc, opcode);
1954 if (host->hs400_mode) {
1955 sdr_clr_bits(host->base + MSDC_IOCON,
1956 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1957 msdc_set_data_delay(host, 0);
1958 }
1959 goto tune_done;
1960 }
1961 if (host->hs400_mode &&
1962 host->dev_comp->hs400_tune)
1963 ret = hs400_tune_response(mmc, opcode);
1964 else
1965 ret = msdc_tune_response(mmc, opcode);
1966 if (ret == -EIO) {
1967 dev_err(host->dev, "Tune response fail!\n");
1968 return ret;
1969 }
1970 if (host->hs400_mode == false) {
1971 ret = msdc_tune_data(mmc, opcode);
1972 if (ret == -EIO)
1973 dev_err(host->dev, "Tune data fail!\n");
1974 }
1975
1976 tune_done:
1977 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1978 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1979 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1980 if (host->top_base) {
1981 host->saved_tune_para.emmc_top_control = readl(host->top_base +
1982 EMMC_TOP_CONTROL);
1983 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
1984 EMMC_TOP_CMD);
1985 }
1986 return ret;
1987 }
1988
1989 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1990 {
1991 struct msdc_host *host = mmc_priv(mmc);
1992 host->hs400_mode = true;
1993
1994 if (host->top_base)
1995 writel(host->hs400_ds_delay,
1996 host->top_base + EMMC50_PAD_DS_TUNE);
1997 else
1998 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1999 /* hs400 mode must set it to 0 */
2000 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2001 /* to improve read performance, set outstanding to 2 */
2002 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2003
2004 return 0;
2005 }
2006
2007 static void msdc_hw_reset(struct mmc_host *mmc)
2008 {
2009 struct msdc_host *host = mmc_priv(mmc);
2010
2011 sdr_set_bits(host->base + EMMC_IOCON, 1);
2012 udelay(10); /* 10us is enough */
2013 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2014 }
2015
2016 static const struct mmc_host_ops mt_msdc_ops = {
2017 .post_req = msdc_post_req,
2018 .pre_req = msdc_pre_req,
2019 .request = msdc_ops_request,
2020 .set_ios = msdc_ops_set_ios,
2021 .get_ro = mmc_gpio_get_ro,
2022 .get_cd = mmc_gpio_get_cd,
2023 .start_signal_voltage_switch = msdc_ops_switch_volt,
2024 .card_busy = msdc_card_busy,
2025 .execute_tuning = msdc_execute_tuning,
2026 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2027 .hw_reset = msdc_hw_reset,
2028 };
2029
2030 static void msdc_of_property_parse(struct platform_device *pdev,
2031 struct msdc_host *host)
2032 {
2033 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2034 &host->latch_ck);
2035
2036 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2037 &host->hs400_ds_delay);
2038
2039 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2040 &host->hs200_cmd_int_delay);
2041
2042 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2043 &host->hs400_cmd_int_delay);
2044
2045 if (of_property_read_bool(pdev->dev.of_node,
2046 "mediatek,hs400-cmd-resp-sel-rising"))
2047 host->hs400_cmd_resp_sel_rising = true;
2048 else
2049 host->hs400_cmd_resp_sel_rising = false;
2050 }
2051
2052 static int msdc_drv_probe(struct platform_device *pdev)
2053 {
2054 struct mmc_host *mmc;
2055 struct msdc_host *host;
2056 struct resource *res;
2057 int ret;
2058
2059 if (!pdev->dev.of_node) {
2060 dev_err(&pdev->dev, "No DT found\n");
2061 return -EINVAL;
2062 }
2063
2064 /* Allocate MMC host for this device */
2065 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2066 if (!mmc)
2067 return -ENOMEM;
2068
2069 host = mmc_priv(mmc);
2070 ret = mmc_of_parse(mmc);
2071 if (ret)
2072 goto host_free;
2073
2074 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2075 host->base = devm_ioremap_resource(&pdev->dev, res);
2076 if (IS_ERR(host->base)) {
2077 ret = PTR_ERR(host->base);
2078 goto host_free;
2079 }
2080
2081 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2082 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2083 if (IS_ERR(host->top_base))
2084 host->top_base = NULL;
2085
2086 ret = mmc_regulator_get_supply(mmc);
2087 if (ret)
2088 goto host_free;
2089
2090 host->src_clk = devm_clk_get(&pdev->dev, "source");
2091 if (IS_ERR(host->src_clk)) {
2092 ret = PTR_ERR(host->src_clk);
2093 goto host_free;
2094 }
2095
2096 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2097 if (IS_ERR(host->h_clk)) {
2098 ret = PTR_ERR(host->h_clk);
2099 goto host_free;
2100 }
2101
2102 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2103 if (IS_ERR(host->bus_clk))
2104 host->bus_clk = NULL;
2105 /*source clock control gate is optional clock*/
2106 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2107 if (IS_ERR(host->src_clk_cg))
2108 host->src_clk_cg = NULL;
2109
2110 host->irq = platform_get_irq(pdev, 0);
2111 if (host->irq < 0) {
2112 ret = -EINVAL;
2113 goto host_free;
2114 }
2115
2116 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2117 if (IS_ERR(host->pinctrl)) {
2118 ret = PTR_ERR(host->pinctrl);
2119 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2120 goto host_free;
2121 }
2122
2123 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2124 if (IS_ERR(host->pins_default)) {
2125 ret = PTR_ERR(host->pins_default);
2126 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2127 goto host_free;
2128 }
2129
2130 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2131 if (IS_ERR(host->pins_uhs)) {
2132 ret = PTR_ERR(host->pins_uhs);
2133 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2134 goto host_free;
2135 }
2136
2137 msdc_of_property_parse(pdev, host);
2138
2139 host->dev = &pdev->dev;
2140 host->dev_comp = of_device_get_match_data(&pdev->dev);
2141 host->mmc = mmc;
2142 host->src_clk_freq = clk_get_rate(host->src_clk);
2143 /* Set host parameters to mmc */
2144 mmc->ops = &mt_msdc_ops;
2145 if (host->dev_comp->clk_div_bits == 8)
2146 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2147 else
2148 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2149
2150 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
2151 /* MMC core transfer sizes tunable parameters */
2152 mmc->max_segs = MAX_BD_NUM;
2153 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2154 mmc->max_blk_size = 2048;
2155 mmc->max_req_size = 512 * 1024;
2156 mmc->max_blk_count = mmc->max_req_size / 512;
2157 if (host->dev_comp->support_64g)
2158 host->dma_mask = DMA_BIT_MASK(36);
2159 else
2160 host->dma_mask = DMA_BIT_MASK(32);
2161 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2162
2163 host->timeout_clks = 3 * 1048576;
2164 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2165 2 * sizeof(struct mt_gpdma_desc),
2166 &host->dma.gpd_addr, GFP_KERNEL);
2167 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2168 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2169 &host->dma.bd_addr, GFP_KERNEL);
2170 if (!host->dma.gpd || !host->dma.bd) {
2171 ret = -ENOMEM;
2172 goto release_mem;
2173 }
2174 msdc_init_gpd_bd(host, &host->dma);
2175 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2176 spin_lock_init(&host->lock);
2177
2178 platform_set_drvdata(pdev, mmc);
2179 msdc_ungate_clock(host);
2180 msdc_init_hw(host);
2181
2182 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2183 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
2184 if (ret)
2185 goto release;
2186
2187 pm_runtime_set_active(host->dev);
2188 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2189 pm_runtime_use_autosuspend(host->dev);
2190 pm_runtime_enable(host->dev);
2191 ret = mmc_add_host(mmc);
2192
2193 if (ret)
2194 goto end;
2195
2196 return 0;
2197 end:
2198 pm_runtime_disable(host->dev);
2199 release:
2200 platform_set_drvdata(pdev, NULL);
2201 msdc_deinit_hw(host);
2202 msdc_gate_clock(host);
2203 release_mem:
2204 if (host->dma.gpd)
2205 dma_free_coherent(&pdev->dev,
2206 2 * sizeof(struct mt_gpdma_desc),
2207 host->dma.gpd, host->dma.gpd_addr);
2208 if (host->dma.bd)
2209 dma_free_coherent(&pdev->dev,
2210 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2211 host->dma.bd, host->dma.bd_addr);
2212 host_free:
2213 mmc_free_host(mmc);
2214
2215 return ret;
2216 }
2217
2218 static int msdc_drv_remove(struct platform_device *pdev)
2219 {
2220 struct mmc_host *mmc;
2221 struct msdc_host *host;
2222
2223 mmc = platform_get_drvdata(pdev);
2224 host = mmc_priv(mmc);
2225
2226 pm_runtime_get_sync(host->dev);
2227
2228 platform_set_drvdata(pdev, NULL);
2229 mmc_remove_host(host->mmc);
2230 msdc_deinit_hw(host);
2231 msdc_gate_clock(host);
2232
2233 pm_runtime_disable(host->dev);
2234 pm_runtime_put_noidle(host->dev);
2235 dma_free_coherent(&pdev->dev,
2236 2 * sizeof(struct mt_gpdma_desc),
2237 host->dma.gpd, host->dma.gpd_addr);
2238 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2239 host->dma.bd, host->dma.bd_addr);
2240
2241 mmc_free_host(host->mmc);
2242
2243 return 0;
2244 }
2245
2246 #ifdef CONFIG_PM
2247 static void msdc_save_reg(struct msdc_host *host)
2248 {
2249 u32 tune_reg = host->dev_comp->pad_tune_reg;
2250
2251 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2252 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2253 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2254 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2255 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2256 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2257 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2258 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2259 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2260 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2261 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2262 if (host->top_base) {
2263 host->save_para.emmc_top_control =
2264 readl(host->top_base + EMMC_TOP_CONTROL);
2265 host->save_para.emmc_top_cmd =
2266 readl(host->top_base + EMMC_TOP_CMD);
2267 host->save_para.emmc50_pad_ds_tune =
2268 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2269 } else {
2270 host->save_para.pad_tune = readl(host->base + tune_reg);
2271 }
2272 }
2273
2274 static void msdc_restore_reg(struct msdc_host *host)
2275 {
2276 u32 tune_reg = host->dev_comp->pad_tune_reg;
2277
2278 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2279 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2280 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2281 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2282 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2283 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2284 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2285 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2286 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2287 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2288 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2289 if (host->top_base) {
2290 writel(host->save_para.emmc_top_control,
2291 host->top_base + EMMC_TOP_CONTROL);
2292 writel(host->save_para.emmc_top_cmd,
2293 host->top_base + EMMC_TOP_CMD);
2294 writel(host->save_para.emmc50_pad_ds_tune,
2295 host->top_base + EMMC50_PAD_DS_TUNE);
2296 } else {
2297 writel(host->save_para.pad_tune, host->base + tune_reg);
2298 }
2299 }
2300
2301 static int msdc_runtime_suspend(struct device *dev)
2302 {
2303 struct mmc_host *mmc = dev_get_drvdata(dev);
2304 struct msdc_host *host = mmc_priv(mmc);
2305
2306 msdc_save_reg(host);
2307 msdc_gate_clock(host);
2308 return 0;
2309 }
2310
2311 static int msdc_runtime_resume(struct device *dev)
2312 {
2313 struct mmc_host *mmc = dev_get_drvdata(dev);
2314 struct msdc_host *host = mmc_priv(mmc);
2315
2316 msdc_ungate_clock(host);
2317 msdc_restore_reg(host);
2318 return 0;
2319 }
2320 #endif
2321
2322 static const struct dev_pm_ops msdc_dev_pm_ops = {
2323 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2324 pm_runtime_force_resume)
2325 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2326 };
2327
2328 static struct platform_driver mt_msdc_driver = {
2329 .probe = msdc_drv_probe,
2330 .remove = msdc_drv_remove,
2331 .driver = {
2332 .name = "mtk-msdc",
2333 .of_match_table = msdc_of_ids,
2334 .pm = &msdc_dev_pm_ops,
2335 },
2336 };
2337
2338 module_platform_driver(mt_msdc_driver);
2339 MODULE_LICENSE("GPL v2");
2340 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
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