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[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / omap.c
1 /*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/of.h>
26 #include <linux/omap-dma.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/clk.h>
31 #include <linux/scatterlist.h>
32 #include <linux/slab.h>
33 #include <linux/platform_data/mmc-omap.h>
34
35
36 #define OMAP_MMC_REG_CMD 0x00
37 #define OMAP_MMC_REG_ARGL 0x01
38 #define OMAP_MMC_REG_ARGH 0x02
39 #define OMAP_MMC_REG_CON 0x03
40 #define OMAP_MMC_REG_STAT 0x04
41 #define OMAP_MMC_REG_IE 0x05
42 #define OMAP_MMC_REG_CTO 0x06
43 #define OMAP_MMC_REG_DTO 0x07
44 #define OMAP_MMC_REG_DATA 0x08
45 #define OMAP_MMC_REG_BLEN 0x09
46 #define OMAP_MMC_REG_NBLK 0x0a
47 #define OMAP_MMC_REG_BUF 0x0b
48 #define OMAP_MMC_REG_SDIO 0x0d
49 #define OMAP_MMC_REG_REV 0x0f
50 #define OMAP_MMC_REG_RSP0 0x10
51 #define OMAP_MMC_REG_RSP1 0x11
52 #define OMAP_MMC_REG_RSP2 0x12
53 #define OMAP_MMC_REG_RSP3 0x13
54 #define OMAP_MMC_REG_RSP4 0x14
55 #define OMAP_MMC_REG_RSP5 0x15
56 #define OMAP_MMC_REG_RSP6 0x16
57 #define OMAP_MMC_REG_RSP7 0x17
58 #define OMAP_MMC_REG_IOSR 0x18
59 #define OMAP_MMC_REG_SYSC 0x19
60 #define OMAP_MMC_REG_SYSS 0x1a
61
62 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
63 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
64 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
65 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
66 #define OMAP_MMC_STAT_A_FULL (1 << 10)
67 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
68 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
69 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
70 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
71 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
72 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
73 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
74 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
75
76 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
77 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
78 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
79 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
80 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
81 #define mmc_omap2() (!mmc_omap1())
82
83 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
84 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
85 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
86
87 /*
88 * Command types
89 */
90 #define OMAP_MMC_CMDTYPE_BC 0
91 #define OMAP_MMC_CMDTYPE_BCR 1
92 #define OMAP_MMC_CMDTYPE_AC 2
93 #define OMAP_MMC_CMDTYPE_ADTC 3
94
95 #define DRIVER_NAME "mmci-omap"
96
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_COVER_POLL_DELAY 500
100
101 struct mmc_omap_host;
102
103 struct mmc_omap_slot {
104 int id;
105 unsigned int vdd;
106 u16 saved_con;
107 u16 bus_mode;
108 unsigned int fclk_freq;
109
110 struct tasklet_struct cover_tasklet;
111 struct timer_list cover_timer;
112 unsigned cover_open;
113
114 struct mmc_request *mrq;
115 struct mmc_omap_host *host;
116 struct mmc_host *mmc;
117 struct omap_mmc_slot_data *pdata;
118 };
119
120 struct mmc_omap_host {
121 int initialized;
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
126 struct device * dev;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
128 struct clk * iclk;
129 struct clk * fclk;
130 struct dma_chan *dma_rx;
131 u32 dma_rx_burst;
132 struct dma_chan *dma_tx;
133 u32 dma_tx_burst;
134 void __iomem *virt_base;
135 unsigned int phys_base;
136 int irq;
137 unsigned char bus_mode;
138 unsigned int reg_shift;
139
140 struct work_struct cmd_abort_work;
141 unsigned abort:1;
142 struct timer_list cmd_abort_timer;
143
144 struct work_struct slot_release_work;
145 struct mmc_omap_slot *next_slot;
146 struct work_struct send_stop_work;
147 struct mmc_data *stop_data;
148
149 unsigned int sg_len;
150 int sg_idx;
151 u16 * buffer;
152 u32 buffer_bytes_left;
153 u32 total_bytes_left;
154
155 unsigned features;
156 unsigned brs_received:1, dma_done:1;
157 unsigned dma_in_use:1;
158 spinlock_t dma_lock;
159
160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
161 struct mmc_omap_slot *current_slot;
162 spinlock_t slot_lock;
163 wait_queue_head_t slot_wq;
164 int nr_slots;
165
166 struct timer_list clk_timer;
167 spinlock_t clk_lock; /* for changing enabled state */
168 unsigned int fclk_enabled:1;
169 struct workqueue_struct *mmc_omap_wq;
170
171 struct omap_mmc_platform_data *pdata;
172 };
173
174
175 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
176 {
177 unsigned long tick_ns;
178
179 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
180 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
181 ndelay(8 * tick_ns);
182 }
183 }
184
185 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
186 {
187 unsigned long flags;
188
189 spin_lock_irqsave(&host->clk_lock, flags);
190 if (host->fclk_enabled != enable) {
191 host->fclk_enabled = enable;
192 if (enable)
193 clk_enable(host->fclk);
194 else
195 clk_disable(host->fclk);
196 }
197 spin_unlock_irqrestore(&host->clk_lock, flags);
198 }
199
200 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
201 {
202 struct mmc_omap_host *host = slot->host;
203 unsigned long flags;
204
205 if (claimed)
206 goto no_claim;
207 spin_lock_irqsave(&host->slot_lock, flags);
208 while (host->mmc != NULL) {
209 spin_unlock_irqrestore(&host->slot_lock, flags);
210 wait_event(host->slot_wq, host->mmc == NULL);
211 spin_lock_irqsave(&host->slot_lock, flags);
212 }
213 host->mmc = slot->mmc;
214 spin_unlock_irqrestore(&host->slot_lock, flags);
215 no_claim:
216 del_timer(&host->clk_timer);
217 if (host->current_slot != slot || !claimed)
218 mmc_omap_fclk_offdelay(host->current_slot);
219
220 if (host->current_slot != slot) {
221 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
222 if (host->pdata->switch_slot != NULL)
223 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
224 host->current_slot = slot;
225 }
226
227 if (claimed) {
228 mmc_omap_fclk_enable(host, 1);
229
230 /* Doing the dummy read here seems to work around some bug
231 * at least in OMAP24xx silicon where the command would not
232 * start after writing the CMD register. Sigh. */
233 OMAP_MMC_READ(host, CON);
234
235 OMAP_MMC_WRITE(host, CON, slot->saved_con);
236 } else
237 mmc_omap_fclk_enable(host, 0);
238 }
239
240 static void mmc_omap_start_request(struct mmc_omap_host *host,
241 struct mmc_request *req);
242
243 static void mmc_omap_slot_release_work(struct work_struct *work)
244 {
245 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
246 slot_release_work);
247 struct mmc_omap_slot *next_slot = host->next_slot;
248 struct mmc_request *rq;
249
250 host->next_slot = NULL;
251 mmc_omap_select_slot(next_slot, 1);
252
253 rq = next_slot->mrq;
254 next_slot->mrq = NULL;
255 mmc_omap_start_request(host, rq);
256 }
257
258 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
259 {
260 struct mmc_omap_host *host = slot->host;
261 unsigned long flags;
262 int i;
263
264 BUG_ON(slot == NULL || host->mmc == NULL);
265
266 if (clk_enabled)
267 /* Keeps clock running for at least 8 cycles on valid freq */
268 mod_timer(&host->clk_timer, jiffies + HZ/10);
269 else {
270 del_timer(&host->clk_timer);
271 mmc_omap_fclk_offdelay(slot);
272 mmc_omap_fclk_enable(host, 0);
273 }
274
275 spin_lock_irqsave(&host->slot_lock, flags);
276 /* Check for any pending requests */
277 for (i = 0; i < host->nr_slots; i++) {
278 struct mmc_omap_slot *new_slot;
279
280 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
281 continue;
282
283 BUG_ON(host->next_slot != NULL);
284 new_slot = host->slots[i];
285 /* The current slot should not have a request in queue */
286 BUG_ON(new_slot == host->current_slot);
287
288 host->next_slot = new_slot;
289 host->mmc = new_slot->mmc;
290 spin_unlock_irqrestore(&host->slot_lock, flags);
291 queue_work(host->mmc_omap_wq, &host->slot_release_work);
292 return;
293 }
294
295 host->mmc = NULL;
296 wake_up(&host->slot_wq);
297 spin_unlock_irqrestore(&host->slot_lock, flags);
298 }
299
300 static inline
301 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
302 {
303 if (slot->pdata->get_cover_state)
304 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
305 slot->id);
306 return 0;
307 }
308
309 static ssize_t
310 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
311 char *buf)
312 {
313 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
314 struct mmc_omap_slot *slot = mmc_priv(mmc);
315
316 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
317 "closed");
318 }
319
320 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
321
322 static ssize_t
323 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
324 char *buf)
325 {
326 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
327 struct mmc_omap_slot *slot = mmc_priv(mmc);
328
329 return sprintf(buf, "%s\n", slot->pdata->name);
330 }
331
332 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
333
334 static void
335 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
336 {
337 u32 cmdreg;
338 u32 resptype;
339 u32 cmdtype;
340 u16 irq_mask;
341
342 host->cmd = cmd;
343
344 resptype = 0;
345 cmdtype = 0;
346
347 /* Our hardware needs to know exact type */
348 switch (mmc_resp_type(cmd)) {
349 case MMC_RSP_NONE:
350 break;
351 case MMC_RSP_R1:
352 case MMC_RSP_R1B:
353 /* resp 1, 1b, 6, 7 */
354 resptype = 1;
355 break;
356 case MMC_RSP_R2:
357 resptype = 2;
358 break;
359 case MMC_RSP_R3:
360 resptype = 3;
361 break;
362 default:
363 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
364 break;
365 }
366
367 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
368 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
369 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
370 cmdtype = OMAP_MMC_CMDTYPE_BC;
371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
372 cmdtype = OMAP_MMC_CMDTYPE_BCR;
373 } else {
374 cmdtype = OMAP_MMC_CMDTYPE_AC;
375 }
376
377 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
378
379 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
380 cmdreg |= 1 << 6;
381
382 if (cmd->flags & MMC_RSP_BUSY)
383 cmdreg |= 1 << 11;
384
385 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
386 cmdreg |= 1 << 15;
387
388 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
389
390 OMAP_MMC_WRITE(host, CTO, 200);
391 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
392 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
393 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
394 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
395 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
396 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
397 OMAP_MMC_STAT_END_OF_DATA;
398 if (cmd->opcode == MMC_ERASE)
399 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
400 OMAP_MMC_WRITE(host, IE, irq_mask);
401 OMAP_MMC_WRITE(host, CMD, cmdreg);
402 }
403
404 static void
405 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
406 int abort)
407 {
408 enum dma_data_direction dma_data_dir;
409 struct device *dev = mmc_dev(host->mmc);
410 struct dma_chan *c;
411
412 if (data->flags & MMC_DATA_WRITE) {
413 dma_data_dir = DMA_TO_DEVICE;
414 c = host->dma_tx;
415 } else {
416 dma_data_dir = DMA_FROM_DEVICE;
417 c = host->dma_rx;
418 }
419 if (c) {
420 if (data->error) {
421 dmaengine_terminate_all(c);
422 /* Claim nothing transferred on error... */
423 data->bytes_xfered = 0;
424 }
425 dev = c->device->dev;
426 }
427 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
428 }
429
430 static void mmc_omap_send_stop_work(struct work_struct *work)
431 {
432 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
433 send_stop_work);
434 struct mmc_omap_slot *slot = host->current_slot;
435 struct mmc_data *data = host->stop_data;
436 unsigned long tick_ns;
437
438 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
439 ndelay(8*tick_ns);
440
441 mmc_omap_start_command(host, data->stop);
442 }
443
444 static void
445 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
446 {
447 if (host->dma_in_use)
448 mmc_omap_release_dma(host, data, data->error);
449
450 host->data = NULL;
451 host->sg_len = 0;
452
453 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
454 * dozens of requests until the card finishes writing data.
455 * It'd be cheaper to just wait till an EOFB interrupt arrives...
456 */
457
458 if (!data->stop) {
459 struct mmc_host *mmc;
460
461 host->mrq = NULL;
462 mmc = host->mmc;
463 mmc_omap_release_slot(host->current_slot, 1);
464 mmc_request_done(mmc, data->mrq);
465 return;
466 }
467
468 host->stop_data = data;
469 queue_work(host->mmc_omap_wq, &host->send_stop_work);
470 }
471
472 static void
473 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
474 {
475 struct mmc_omap_slot *slot = host->current_slot;
476 unsigned int restarts, passes, timeout;
477 u16 stat = 0;
478
479 /* Sending abort takes 80 clocks. Have some extra and round up */
480 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
481 restarts = 0;
482 while (restarts < maxloops) {
483 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
484 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
485
486 passes = 0;
487 while (passes < timeout) {
488 stat = OMAP_MMC_READ(host, STAT);
489 if (stat & OMAP_MMC_STAT_END_OF_CMD)
490 goto out;
491 udelay(1);
492 passes++;
493 }
494
495 restarts++;
496 }
497 out:
498 OMAP_MMC_WRITE(host, STAT, stat);
499 }
500
501 static void
502 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
503 {
504 if (host->dma_in_use)
505 mmc_omap_release_dma(host, data, 1);
506
507 host->data = NULL;
508 host->sg_len = 0;
509
510 mmc_omap_send_abort(host, 10000);
511 }
512
513 static void
514 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
515 {
516 unsigned long flags;
517 int done;
518
519 if (!host->dma_in_use) {
520 mmc_omap_xfer_done(host, data);
521 return;
522 }
523 done = 0;
524 spin_lock_irqsave(&host->dma_lock, flags);
525 if (host->dma_done)
526 done = 1;
527 else
528 host->brs_received = 1;
529 spin_unlock_irqrestore(&host->dma_lock, flags);
530 if (done)
531 mmc_omap_xfer_done(host, data);
532 }
533
534 static void
535 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
536 {
537 unsigned long flags;
538 int done;
539
540 done = 0;
541 spin_lock_irqsave(&host->dma_lock, flags);
542 if (host->brs_received)
543 done = 1;
544 else
545 host->dma_done = 1;
546 spin_unlock_irqrestore(&host->dma_lock, flags);
547 if (done)
548 mmc_omap_xfer_done(host, data);
549 }
550
551 static void
552 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
553 {
554 host->cmd = NULL;
555
556 del_timer(&host->cmd_abort_timer);
557
558 if (cmd->flags & MMC_RSP_PRESENT) {
559 if (cmd->flags & MMC_RSP_136) {
560 /* response type 2 */
561 cmd->resp[3] =
562 OMAP_MMC_READ(host, RSP0) |
563 (OMAP_MMC_READ(host, RSP1) << 16);
564 cmd->resp[2] =
565 OMAP_MMC_READ(host, RSP2) |
566 (OMAP_MMC_READ(host, RSP3) << 16);
567 cmd->resp[1] =
568 OMAP_MMC_READ(host, RSP4) |
569 (OMAP_MMC_READ(host, RSP5) << 16);
570 cmd->resp[0] =
571 OMAP_MMC_READ(host, RSP6) |
572 (OMAP_MMC_READ(host, RSP7) << 16);
573 } else {
574 /* response types 1, 1b, 3, 4, 5, 6 */
575 cmd->resp[0] =
576 OMAP_MMC_READ(host, RSP6) |
577 (OMAP_MMC_READ(host, RSP7) << 16);
578 }
579 }
580
581 if (host->data == NULL || cmd->error) {
582 struct mmc_host *mmc;
583
584 if (host->data != NULL)
585 mmc_omap_abort_xfer(host, host->data);
586 host->mrq = NULL;
587 mmc = host->mmc;
588 mmc_omap_release_slot(host->current_slot, 1);
589 mmc_request_done(mmc, cmd->mrq);
590 }
591 }
592
593 /*
594 * Abort stuck command. Can occur when card is removed while it is being
595 * read.
596 */
597 static void mmc_omap_abort_command(struct work_struct *work)
598 {
599 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
600 cmd_abort_work);
601 BUG_ON(!host->cmd);
602
603 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
604 host->cmd->opcode);
605
606 if (host->cmd->error == 0)
607 host->cmd->error = -ETIMEDOUT;
608
609 if (host->data == NULL) {
610 struct mmc_command *cmd;
611 struct mmc_host *mmc;
612
613 cmd = host->cmd;
614 host->cmd = NULL;
615 mmc_omap_send_abort(host, 10000);
616
617 host->mrq = NULL;
618 mmc = host->mmc;
619 mmc_omap_release_slot(host->current_slot, 1);
620 mmc_request_done(mmc, cmd->mrq);
621 } else
622 mmc_omap_cmd_done(host, host->cmd);
623
624 host->abort = 0;
625 enable_irq(host->irq);
626 }
627
628 static void
629 mmc_omap_cmd_timer(unsigned long data)
630 {
631 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
632 unsigned long flags;
633
634 spin_lock_irqsave(&host->slot_lock, flags);
635 if (host->cmd != NULL && !host->abort) {
636 OMAP_MMC_WRITE(host, IE, 0);
637 disable_irq(host->irq);
638 host->abort = 1;
639 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
640 }
641 spin_unlock_irqrestore(&host->slot_lock, flags);
642 }
643
644 /* PIO only */
645 static void
646 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
647 {
648 struct scatterlist *sg;
649
650 sg = host->data->sg + host->sg_idx;
651 host->buffer_bytes_left = sg->length;
652 host->buffer = sg_virt(sg);
653 if (host->buffer_bytes_left > host->total_bytes_left)
654 host->buffer_bytes_left = host->total_bytes_left;
655 }
656
657 static void
658 mmc_omap_clk_timer(unsigned long data)
659 {
660 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
661
662 mmc_omap_fclk_enable(host, 0);
663 }
664
665 /* PIO only */
666 static void
667 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
668 {
669 int n, nwords;
670
671 if (host->buffer_bytes_left == 0) {
672 host->sg_idx++;
673 BUG_ON(host->sg_idx == host->sg_len);
674 mmc_omap_sg_to_buf(host);
675 }
676 n = 64;
677 if (n > host->buffer_bytes_left)
678 n = host->buffer_bytes_left;
679
680 /* Round up to handle odd number of bytes to transfer */
681 nwords = DIV_ROUND_UP(n, 2);
682
683 host->buffer_bytes_left -= n;
684 host->total_bytes_left -= n;
685 host->data->bytes_xfered += n;
686
687 if (write) {
688 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
690 } else {
691 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
692 host->buffer, nwords);
693 }
694
695 host->buffer += nwords;
696 }
697
698 #ifdef CONFIG_MMC_DEBUG
699 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
700 {
701 static const char *mmc_omap_status_bits[] = {
702 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
703 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
704 };
705 int i;
706 char res[64], *buf = res;
707
708 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
709
710 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
711 if (status & (1 << i))
712 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
713 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
714 }
715 #else
716 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
717 {
718 }
719 #endif
720
721
722 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
723 {
724 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
725 u16 status;
726 int end_command;
727 int end_transfer;
728 int transfer_error, cmd_error;
729
730 if (host->cmd == NULL && host->data == NULL) {
731 status = OMAP_MMC_READ(host, STAT);
732 dev_info(mmc_dev(host->slots[0]->mmc),
733 "Spurious IRQ 0x%04x\n", status);
734 if (status != 0) {
735 OMAP_MMC_WRITE(host, STAT, status);
736 OMAP_MMC_WRITE(host, IE, 0);
737 }
738 return IRQ_HANDLED;
739 }
740
741 end_command = 0;
742 end_transfer = 0;
743 transfer_error = 0;
744 cmd_error = 0;
745
746 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
747 int cmd;
748
749 OMAP_MMC_WRITE(host, STAT, status);
750 if (host->cmd != NULL)
751 cmd = host->cmd->opcode;
752 else
753 cmd = -1;
754 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
755 status, cmd);
756 mmc_omap_report_irq(host, status);
757
758 if (host->total_bytes_left) {
759 if ((status & OMAP_MMC_STAT_A_FULL) ||
760 (status & OMAP_MMC_STAT_END_OF_DATA))
761 mmc_omap_xfer_data(host, 0);
762 if (status & OMAP_MMC_STAT_A_EMPTY)
763 mmc_omap_xfer_data(host, 1);
764 }
765
766 if (status & OMAP_MMC_STAT_END_OF_DATA)
767 end_transfer = 1;
768
769 if (status & OMAP_MMC_STAT_DATA_TOUT) {
770 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
771 cmd);
772 if (host->data) {
773 host->data->error = -ETIMEDOUT;
774 transfer_error = 1;
775 }
776 }
777
778 if (status & OMAP_MMC_STAT_DATA_CRC) {
779 if (host->data) {
780 host->data->error = -EILSEQ;
781 dev_dbg(mmc_dev(host->mmc),
782 "data CRC error, bytes left %d\n",
783 host->total_bytes_left);
784 transfer_error = 1;
785 } else {
786 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
787 }
788 }
789
790 if (status & OMAP_MMC_STAT_CMD_TOUT) {
791 /* Timeouts are routine with some commands */
792 if (host->cmd) {
793 struct mmc_omap_slot *slot =
794 host->current_slot;
795 if (slot == NULL ||
796 !mmc_omap_cover_is_open(slot))
797 dev_err(mmc_dev(host->mmc),
798 "command timeout (CMD%d)\n",
799 cmd);
800 host->cmd->error = -ETIMEDOUT;
801 end_command = 1;
802 cmd_error = 1;
803 }
804 }
805
806 if (status & OMAP_MMC_STAT_CMD_CRC) {
807 if (host->cmd) {
808 dev_err(mmc_dev(host->mmc),
809 "command CRC error (CMD%d, arg 0x%08x)\n",
810 cmd, host->cmd->arg);
811 host->cmd->error = -EILSEQ;
812 end_command = 1;
813 cmd_error = 1;
814 } else
815 dev_err(mmc_dev(host->mmc),
816 "command CRC error without cmd?\n");
817 }
818
819 if (status & OMAP_MMC_STAT_CARD_ERR) {
820 dev_dbg(mmc_dev(host->mmc),
821 "ignoring card status error (CMD%d)\n",
822 cmd);
823 end_command = 1;
824 }
825
826 /*
827 * NOTE: On 1610 the END_OF_CMD may come too early when
828 * starting a write
829 */
830 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
831 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
832 end_command = 1;
833 }
834 }
835
836 if (cmd_error && host->data) {
837 del_timer(&host->cmd_abort_timer);
838 host->abort = 1;
839 OMAP_MMC_WRITE(host, IE, 0);
840 disable_irq_nosync(host->irq);
841 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
842 return IRQ_HANDLED;
843 }
844
845 if (end_command && host->cmd)
846 mmc_omap_cmd_done(host, host->cmd);
847 if (host->data != NULL) {
848 if (transfer_error)
849 mmc_omap_xfer_done(host, host->data);
850 else if (end_transfer)
851 mmc_omap_end_of_data(host, host->data);
852 }
853
854 return IRQ_HANDLED;
855 }
856
857 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
858 {
859 int cover_open;
860 struct mmc_omap_host *host = dev_get_drvdata(dev);
861 struct mmc_omap_slot *slot = host->slots[num];
862
863 BUG_ON(num >= host->nr_slots);
864
865 /* Other subsystems can call in here before we're initialised. */
866 if (host->nr_slots == 0 || !host->slots[num])
867 return;
868
869 cover_open = mmc_omap_cover_is_open(slot);
870 if (cover_open != slot->cover_open) {
871 slot->cover_open = cover_open;
872 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
873 }
874
875 tasklet_hi_schedule(&slot->cover_tasklet);
876 }
877
878 static void mmc_omap_cover_timer(unsigned long arg)
879 {
880 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
881 tasklet_schedule(&slot->cover_tasklet);
882 }
883
884 static void mmc_omap_cover_handler(unsigned long param)
885 {
886 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
887 int cover_open = mmc_omap_cover_is_open(slot);
888
889 mmc_detect_change(slot->mmc, 0);
890 if (!cover_open)
891 return;
892
893 /*
894 * If no card is inserted, we postpone polling until
895 * the cover has been closed.
896 */
897 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
898 return;
899
900 mod_timer(&slot->cover_timer,
901 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
902 }
903
904 static void mmc_omap_dma_callback(void *priv)
905 {
906 struct mmc_omap_host *host = priv;
907 struct mmc_data *data = host->data;
908
909 /* If we got to the end of DMA, assume everything went well */
910 data->bytes_xfered += data->blocks * data->blksz;
911
912 mmc_omap_dma_done(host, data);
913 }
914
915 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
916 {
917 u16 reg;
918
919 reg = OMAP_MMC_READ(host, SDIO);
920 reg &= ~(1 << 5);
921 OMAP_MMC_WRITE(host, SDIO, reg);
922 /* Set maximum timeout */
923 OMAP_MMC_WRITE(host, CTO, 0xff);
924 }
925
926 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
927 {
928 unsigned int timeout, cycle_ns;
929 u16 reg;
930
931 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
932 timeout = req->data->timeout_ns / cycle_ns;
933 timeout += req->data->timeout_clks;
934
935 /* Check if we need to use timeout multiplier register */
936 reg = OMAP_MMC_READ(host, SDIO);
937 if (timeout > 0xffff) {
938 reg |= (1 << 5);
939 timeout /= 1024;
940 } else
941 reg &= ~(1 << 5);
942 OMAP_MMC_WRITE(host, SDIO, reg);
943 OMAP_MMC_WRITE(host, DTO, timeout);
944 }
945
946 static void
947 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
948 {
949 struct mmc_data *data = req->data;
950 int i, use_dma = 1, block_size;
951 struct scatterlist *sg;
952 unsigned sg_len;
953
954 host->data = data;
955 if (data == NULL) {
956 OMAP_MMC_WRITE(host, BLEN, 0);
957 OMAP_MMC_WRITE(host, NBLK, 0);
958 OMAP_MMC_WRITE(host, BUF, 0);
959 host->dma_in_use = 0;
960 set_cmd_timeout(host, req);
961 return;
962 }
963
964 block_size = data->blksz;
965
966 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
967 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
968 set_data_timeout(host, req);
969
970 /* cope with calling layer confusion; it issues "single
971 * block" writes using multi-block scatterlists.
972 */
973 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
974
975 /* Only do DMA for entire blocks */
976 for_each_sg(data->sg, sg, sg_len, i) {
977 if ((sg->length % block_size) != 0) {
978 use_dma = 0;
979 break;
980 }
981 }
982
983 host->sg_idx = 0;
984 if (use_dma) {
985 enum dma_data_direction dma_data_dir;
986 struct dma_async_tx_descriptor *tx;
987 struct dma_chan *c;
988 u32 burst, *bp;
989 u16 buf;
990
991 /*
992 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
993 * and 24xx. Use 16 or 32 word frames when the
994 * blocksize is at least that large. Blocksize is
995 * usually 512 bytes; but not for some SD reads.
996 */
997 burst = mmc_omap15xx() ? 32 : 64;
998 if (burst > data->blksz)
999 burst = data->blksz;
1000
1001 burst >>= 1;
1002
1003 if (data->flags & MMC_DATA_WRITE) {
1004 c = host->dma_tx;
1005 bp = &host->dma_tx_burst;
1006 buf = 0x0f80 | (burst - 1) << 0;
1007 dma_data_dir = DMA_TO_DEVICE;
1008 } else {
1009 c = host->dma_rx;
1010 bp = &host->dma_rx_burst;
1011 buf = 0x800f | (burst - 1) << 8;
1012 dma_data_dir = DMA_FROM_DEVICE;
1013 }
1014
1015 if (!c)
1016 goto use_pio;
1017
1018 /* Only reconfigure if we have a different burst size */
1019 if (*bp != burst) {
1020 struct dma_slave_config cfg;
1021
1022 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1024 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1026 cfg.src_maxburst = burst;
1027 cfg.dst_maxburst = burst;
1028
1029 if (dmaengine_slave_config(c, &cfg))
1030 goto use_pio;
1031
1032 *bp = burst;
1033 }
1034
1035 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1036 dma_data_dir);
1037 if (host->sg_len == 0)
1038 goto use_pio;
1039
1040 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1041 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1042 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1043 if (!tx)
1044 goto use_pio;
1045
1046 OMAP_MMC_WRITE(host, BUF, buf);
1047
1048 tx->callback = mmc_omap_dma_callback;
1049 tx->callback_param = host;
1050 dmaengine_submit(tx);
1051 host->brs_received = 0;
1052 host->dma_done = 0;
1053 host->dma_in_use = 1;
1054 return;
1055 }
1056 use_pio:
1057
1058 /* Revert to PIO? */
1059 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1060 host->total_bytes_left = data->blocks * block_size;
1061 host->sg_len = sg_len;
1062 mmc_omap_sg_to_buf(host);
1063 host->dma_in_use = 0;
1064 }
1065
1066 static void mmc_omap_start_request(struct mmc_omap_host *host,
1067 struct mmc_request *req)
1068 {
1069 BUG_ON(host->mrq != NULL);
1070
1071 host->mrq = req;
1072
1073 /* only touch fifo AFTER the controller readies it */
1074 mmc_omap_prepare_data(host, req);
1075 mmc_omap_start_command(host, req->cmd);
1076 if (host->dma_in_use) {
1077 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1078 host->dma_tx : host->dma_rx;
1079
1080 dma_async_issue_pending(c);
1081 }
1082 }
1083
1084 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1085 {
1086 struct mmc_omap_slot *slot = mmc_priv(mmc);
1087 struct mmc_omap_host *host = slot->host;
1088 unsigned long flags;
1089
1090 spin_lock_irqsave(&host->slot_lock, flags);
1091 if (host->mmc != NULL) {
1092 BUG_ON(slot->mrq != NULL);
1093 slot->mrq = req;
1094 spin_unlock_irqrestore(&host->slot_lock, flags);
1095 return;
1096 } else
1097 host->mmc = mmc;
1098 spin_unlock_irqrestore(&host->slot_lock, flags);
1099 mmc_omap_select_slot(slot, 1);
1100 mmc_omap_start_request(host, req);
1101 }
1102
1103 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1104 int vdd)
1105 {
1106 struct mmc_omap_host *host;
1107
1108 host = slot->host;
1109
1110 if (slot->pdata->set_power != NULL)
1111 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1112 vdd);
1113 if (mmc_omap2()) {
1114 u16 w;
1115
1116 if (power_on) {
1117 w = OMAP_MMC_READ(host, CON);
1118 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1119 } else {
1120 w = OMAP_MMC_READ(host, CON);
1121 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1122 }
1123 }
1124 }
1125
1126 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1127 {
1128 struct mmc_omap_slot *slot = mmc_priv(mmc);
1129 struct mmc_omap_host *host = slot->host;
1130 int func_clk_rate = clk_get_rate(host->fclk);
1131 int dsor;
1132
1133 if (ios->clock == 0)
1134 return 0;
1135
1136 dsor = func_clk_rate / ios->clock;
1137 if (dsor < 1)
1138 dsor = 1;
1139
1140 if (func_clk_rate / dsor > ios->clock)
1141 dsor++;
1142
1143 if (dsor > 250)
1144 dsor = 250;
1145
1146 slot->fclk_freq = func_clk_rate / dsor;
1147
1148 if (ios->bus_width == MMC_BUS_WIDTH_4)
1149 dsor |= 1 << 15;
1150
1151 return dsor;
1152 }
1153
1154 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1155 {
1156 struct mmc_omap_slot *slot = mmc_priv(mmc);
1157 struct mmc_omap_host *host = slot->host;
1158 int i, dsor;
1159 int clk_enabled;
1160
1161 mmc_omap_select_slot(slot, 0);
1162
1163 dsor = mmc_omap_calc_divisor(mmc, ios);
1164
1165 if (ios->vdd != slot->vdd)
1166 slot->vdd = ios->vdd;
1167
1168 clk_enabled = 0;
1169 switch (ios->power_mode) {
1170 case MMC_POWER_OFF:
1171 mmc_omap_set_power(slot, 0, ios->vdd);
1172 break;
1173 case MMC_POWER_UP:
1174 /* Cannot touch dsor yet, just power up MMC */
1175 mmc_omap_set_power(slot, 1, ios->vdd);
1176 goto exit;
1177 case MMC_POWER_ON:
1178 mmc_omap_fclk_enable(host, 1);
1179 clk_enabled = 1;
1180 dsor |= 1 << 11;
1181 break;
1182 }
1183
1184 if (slot->bus_mode != ios->bus_mode) {
1185 if (slot->pdata->set_bus_mode != NULL)
1186 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1187 ios->bus_mode);
1188 slot->bus_mode = ios->bus_mode;
1189 }
1190
1191 /* On insanely high arm_per frequencies something sometimes
1192 * goes somehow out of sync, and the POW bit is not being set,
1193 * which results in the while loop below getting stuck.
1194 * Writing to the CON register twice seems to do the trick. */
1195 for (i = 0; i < 2; i++)
1196 OMAP_MMC_WRITE(host, CON, dsor);
1197 slot->saved_con = dsor;
1198 if (ios->power_mode == MMC_POWER_ON) {
1199 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1200 int usecs = 250;
1201
1202 /* Send clock cycles, poll completion */
1203 OMAP_MMC_WRITE(host, IE, 0);
1204 OMAP_MMC_WRITE(host, STAT, 0xffff);
1205 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1206 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1207 udelay(1);
1208 usecs--;
1209 }
1210 OMAP_MMC_WRITE(host, STAT, 1);
1211 }
1212
1213 exit:
1214 mmc_omap_release_slot(slot, clk_enabled);
1215 }
1216
1217 static const struct mmc_host_ops mmc_omap_ops = {
1218 .request = mmc_omap_request,
1219 .set_ios = mmc_omap_set_ios,
1220 };
1221
1222 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1223 {
1224 struct mmc_omap_slot *slot = NULL;
1225 struct mmc_host *mmc;
1226 int r;
1227
1228 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1229 if (mmc == NULL)
1230 return -ENOMEM;
1231
1232 slot = mmc_priv(mmc);
1233 slot->host = host;
1234 slot->mmc = mmc;
1235 slot->id = id;
1236 slot->pdata = &host->pdata->slots[id];
1237
1238 host->slots[id] = slot;
1239
1240 mmc->caps = 0;
1241 if (host->pdata->slots[id].wires >= 4)
1242 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
1243
1244 mmc->ops = &mmc_omap_ops;
1245 mmc->f_min = 400000;
1246
1247 if (mmc_omap2())
1248 mmc->f_max = 48000000;
1249 else
1250 mmc->f_max = 24000000;
1251 if (host->pdata->max_freq)
1252 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1253 mmc->ocr_avail = slot->pdata->ocr_mask;
1254
1255 /* Use scatterlist DMA to reduce per-transfer costs.
1256 * NOTE max_seg_size assumption that small blocks aren't
1257 * normally used (except e.g. for reading SD registers).
1258 */
1259 mmc->max_segs = 32;
1260 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1261 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1262 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1263 mmc->max_seg_size = mmc->max_req_size;
1264
1265 if (slot->pdata->get_cover_state != NULL) {
1266 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1267 (unsigned long)slot);
1268 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1269 (unsigned long)slot);
1270 }
1271
1272 r = mmc_add_host(mmc);
1273 if (r < 0)
1274 goto err_remove_host;
1275
1276 if (slot->pdata->name != NULL) {
1277 r = device_create_file(&mmc->class_dev,
1278 &dev_attr_slot_name);
1279 if (r < 0)
1280 goto err_remove_host;
1281 }
1282
1283 if (slot->pdata->get_cover_state != NULL) {
1284 r = device_create_file(&mmc->class_dev,
1285 &dev_attr_cover_switch);
1286 if (r < 0)
1287 goto err_remove_slot_name;
1288 tasklet_schedule(&slot->cover_tasklet);
1289 }
1290
1291 return 0;
1292
1293 err_remove_slot_name:
1294 if (slot->pdata->name != NULL)
1295 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1296 err_remove_host:
1297 mmc_remove_host(mmc);
1298 mmc_free_host(mmc);
1299 return r;
1300 }
1301
1302 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1303 {
1304 struct mmc_host *mmc = slot->mmc;
1305
1306 if (slot->pdata->name != NULL)
1307 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1308 if (slot->pdata->get_cover_state != NULL)
1309 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1310
1311 tasklet_kill(&slot->cover_tasklet);
1312 del_timer_sync(&slot->cover_timer);
1313 flush_workqueue(slot->host->mmc_omap_wq);
1314
1315 mmc_remove_host(mmc);
1316 mmc_free_host(mmc);
1317 }
1318
1319 static int mmc_omap_probe(struct platform_device *pdev)
1320 {
1321 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1322 struct mmc_omap_host *host = NULL;
1323 struct resource *res;
1324 dma_cap_mask_t mask;
1325 unsigned sig = 0;
1326 int i, ret = 0;
1327 int irq;
1328
1329 if (pdata == NULL) {
1330 dev_err(&pdev->dev, "platform data missing\n");
1331 return -ENXIO;
1332 }
1333 if (pdata->nr_slots == 0) {
1334 dev_err(&pdev->dev, "no slots\n");
1335 return -EPROBE_DEFER;
1336 }
1337
1338 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1339 GFP_KERNEL);
1340 if (host == NULL)
1341 return -ENOMEM;
1342
1343 irq = platform_get_irq(pdev, 0);
1344 if (irq < 0)
1345 return -ENXIO;
1346
1347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1348 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1349 if (IS_ERR(host->virt_base))
1350 return PTR_ERR(host->virt_base);
1351
1352 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1353 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1354
1355 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1356 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1357 (unsigned long) host);
1358
1359 spin_lock_init(&host->clk_lock);
1360 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1361
1362 spin_lock_init(&host->dma_lock);
1363 spin_lock_init(&host->slot_lock);
1364 init_waitqueue_head(&host->slot_wq);
1365
1366 host->pdata = pdata;
1367 host->features = host->pdata->slots[0].features;
1368 host->dev = &pdev->dev;
1369 platform_set_drvdata(pdev, host);
1370
1371 host->id = pdev->id;
1372 host->irq = irq;
1373 host->phys_base = res->start;
1374 host->iclk = clk_get(&pdev->dev, "ick");
1375 if (IS_ERR(host->iclk))
1376 return PTR_ERR(host->iclk);
1377 clk_enable(host->iclk);
1378
1379 host->fclk = clk_get(&pdev->dev, "fck");
1380 if (IS_ERR(host->fclk)) {
1381 ret = PTR_ERR(host->fclk);
1382 goto err_free_iclk;
1383 }
1384
1385 dma_cap_zero(mask);
1386 dma_cap_set(DMA_SLAVE, mask);
1387
1388 host->dma_tx_burst = -1;
1389 host->dma_rx_burst = -1;
1390
1391 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1392 if (res)
1393 sig = res->start;
1394 host->dma_tx = dma_request_slave_channel_compat(mask,
1395 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1396 if (!host->dma_tx)
1397 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1398 sig);
1399
1400 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1401 if (res)
1402 sig = res->start;
1403 host->dma_rx = dma_request_slave_channel_compat(mask,
1404 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1405 if (!host->dma_rx)
1406 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1407 sig);
1408
1409 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1410 if (ret)
1411 goto err_free_dma;
1412
1413 if (pdata->init != NULL) {
1414 ret = pdata->init(&pdev->dev);
1415 if (ret < 0)
1416 goto err_free_irq;
1417 }
1418
1419 host->nr_slots = pdata->nr_slots;
1420 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1421
1422 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1423 if (!host->mmc_omap_wq)
1424 goto err_plat_cleanup;
1425
1426 for (i = 0; i < pdata->nr_slots; i++) {
1427 ret = mmc_omap_new_slot(host, i);
1428 if (ret < 0) {
1429 while (--i >= 0)
1430 mmc_omap_remove_slot(host->slots[i]);
1431
1432 goto err_destroy_wq;
1433 }
1434 }
1435
1436 return 0;
1437
1438 err_destroy_wq:
1439 destroy_workqueue(host->mmc_omap_wq);
1440 err_plat_cleanup:
1441 if (pdata->cleanup)
1442 pdata->cleanup(&pdev->dev);
1443 err_free_irq:
1444 free_irq(host->irq, host);
1445 err_free_dma:
1446 if (host->dma_tx)
1447 dma_release_channel(host->dma_tx);
1448 if (host->dma_rx)
1449 dma_release_channel(host->dma_rx);
1450 clk_put(host->fclk);
1451 err_free_iclk:
1452 clk_disable(host->iclk);
1453 clk_put(host->iclk);
1454 return ret;
1455 }
1456
1457 static int mmc_omap_remove(struct platform_device *pdev)
1458 {
1459 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1460 int i;
1461
1462 BUG_ON(host == NULL);
1463
1464 for (i = 0; i < host->nr_slots; i++)
1465 mmc_omap_remove_slot(host->slots[i]);
1466
1467 if (host->pdata->cleanup)
1468 host->pdata->cleanup(&pdev->dev);
1469
1470 mmc_omap_fclk_enable(host, 0);
1471 free_irq(host->irq, host);
1472 clk_put(host->fclk);
1473 clk_disable(host->iclk);
1474 clk_put(host->iclk);
1475
1476 if (host->dma_tx)
1477 dma_release_channel(host->dma_tx);
1478 if (host->dma_rx)
1479 dma_release_channel(host->dma_rx);
1480
1481 destroy_workqueue(host->mmc_omap_wq);
1482
1483 return 0;
1484 }
1485
1486 #if IS_BUILTIN(CONFIG_OF)
1487 static const struct of_device_id mmc_omap_match[] = {
1488 { .compatible = "ti,omap2420-mmc", },
1489 { },
1490 };
1491 #endif
1492
1493 static struct platform_driver mmc_omap_driver = {
1494 .probe = mmc_omap_probe,
1495 .remove = mmc_omap_remove,
1496 .driver = {
1497 .name = DRIVER_NAME,
1498 .of_match_table = of_match_ptr(mmc_omap_match),
1499 },
1500 };
1501
1502 module_platform_driver(mmc_omap_driver);
1503 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1504 MODULE_LICENSE("GPL");
1505 MODULE_ALIAS("platform:" DRIVER_NAME);
1506 MODULE_AUTHOR("Juha Yrjölä");
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