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omap_hsmmc: clear interrupt status after init sequence
[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/io.h>
32 #include <linux/semaphore.h>
33 #include <mach/dma.h>
34 #include <mach/hardware.h>
35 #include <mach/board.h>
36 #include <mach/mmc.h>
37 #include <mach/cpu.h>
38
39 /* OMAP HSMMC Host Controller Registers */
40 #define OMAP_HSMMC_SYSCONFIG 0x0010
41 #define OMAP_HSMMC_SYSSTATUS 0x0014
42 #define OMAP_HSMMC_CON 0x002C
43 #define OMAP_HSMMC_BLK 0x0104
44 #define OMAP_HSMMC_ARG 0x0108
45 #define OMAP_HSMMC_CMD 0x010C
46 #define OMAP_HSMMC_RSP10 0x0110
47 #define OMAP_HSMMC_RSP32 0x0114
48 #define OMAP_HSMMC_RSP54 0x0118
49 #define OMAP_HSMMC_RSP76 0x011C
50 #define OMAP_HSMMC_DATA 0x0120
51 #define OMAP_HSMMC_HCTL 0x0128
52 #define OMAP_HSMMC_SYSCTL 0x012C
53 #define OMAP_HSMMC_STAT 0x0130
54 #define OMAP_HSMMC_IE 0x0134
55 #define OMAP_HSMMC_ISE 0x0138
56 #define OMAP_HSMMC_CAPA 0x0140
57
58 #define VS18 (1 << 26)
59 #define VS30 (1 << 25)
60 #define SDVS18 (0x5 << 9)
61 #define SDVS30 (0x6 << 9)
62 #define SDVS33 (0x7 << 9)
63 #define SDVS_MASK 0x00000E00
64 #define SDVSCLR 0xFFFFF1FF
65 #define SDVSDET 0x00000400
66 #define AUTOIDLE 0x1
67 #define SDBP (1 << 8)
68 #define DTO 0xe
69 #define ICE 0x1
70 #define ICS 0x2
71 #define CEN (1 << 2)
72 #define CLKD_MASK 0x0000FFC0
73 #define CLKD_SHIFT 6
74 #define DTO_MASK 0x000F0000
75 #define DTO_SHIFT 16
76 #define INT_EN_MASK 0x307F0033
77 #define BWR_ENABLE (1 << 4)
78 #define BRR_ENABLE (1 << 5)
79 #define INIT_STREAM (1 << 1)
80 #define DP_SELECT (1 << 21)
81 #define DDIR (1 << 4)
82 #define DMA_EN 0x1
83 #define MSBS (1 << 5)
84 #define BCE (1 << 1)
85 #define FOUR_BIT (1 << 1)
86 #define DW8 (1 << 5)
87 #define CC 0x1
88 #define TC 0x02
89 #define OD 0x1
90 #define ERR (1 << 15)
91 #define CMD_TIMEOUT (1 << 16)
92 #define DATA_TIMEOUT (1 << 20)
93 #define CMD_CRC (1 << 17)
94 #define DATA_CRC (1 << 21)
95 #define CARD_ERR (1 << 28)
96 #define STAT_CLEAR 0xFFFFFFFF
97 #define INIT_STREAM_CMD 0x00000000
98 #define DUAL_VOLT_OCR_BIT 7
99 #define SRC (1 << 25)
100 #define SRD (1 << 26)
101 #define SOFTRESET (1 << 1)
102 #define RESETDONE (1 << 0)
103
104 /*
105 * FIXME: Most likely all the data using these _DEVID defines should come
106 * from the platform_data, or implemented in controller and slot specific
107 * functions.
108 */
109 #define OMAP_MMC1_DEVID 0
110 #define OMAP_MMC2_DEVID 1
111 #define OMAP_MMC3_DEVID 2
112
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MASTER_CLOCK 96000000
115 #define DRIVER_NAME "mmci-omap-hs"
116
117 /* Timeouts for entering power saving states on inactivity, msec */
118 #define OMAP_MMC_DISABLED_TIMEOUT 100
119 #define OMAP_MMC_SLEEP_TIMEOUT 1000
120 #define OMAP_MMC_OFF_TIMEOUT 8000
121
122 /*
123 * One controller can have multiple slots, like on some omap boards using
124 * omap.c controller driver. Luckily this is not currently done on any known
125 * omap_hsmmc.c device.
126 */
127 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
128
129 /*
130 * MMC Host controller read/write API's
131 */
132 #define OMAP_HSMMC_READ(base, reg) \
133 __raw_readl((base) + OMAP_HSMMC_##reg)
134
135 #define OMAP_HSMMC_WRITE(base, reg, val) \
136 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
137
138 struct mmc_omap_host {
139 struct device *dev;
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
144 struct clk *fclk;
145 struct clk *iclk;
146 struct clk *dbclk;
147 struct semaphore sem;
148 struct work_struct mmc_carddetect_work;
149 void __iomem *base;
150 resource_size_t mapbase;
151 unsigned int id;
152 unsigned int dma_len;
153 unsigned int dma_sg_idx;
154 unsigned char bus_mode;
155 unsigned char power_mode;
156 u32 *buffer;
157 u32 bytesleft;
158 int suspended;
159 int irq;
160 int use_dma, dma_ch;
161 int dma_line_tx, dma_line_rx;
162 int slot_id;
163 int dbclk_enabled;
164 int response_busy;
165 int context_loss;
166 int dpm_state;
167 int vdd;
168
169 struct omap_mmc_platform_data *pdata;
170 };
171
172 /*
173 * Stop clock to the card
174 */
175 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
176 {
177 OMAP_HSMMC_WRITE(host->base, SYSCTL,
178 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
179 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
180 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
181 }
182
183 #ifdef CONFIG_PM
184
185 /*
186 * Restore the MMC host context, if it was lost as result of a
187 * power state change.
188 */
189 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
190 {
191 struct mmc_ios *ios = &host->mmc->ios;
192 struct omap_mmc_platform_data *pdata = host->pdata;
193 int context_loss = 0;
194 u32 hctl, capa, con;
195 u16 dsor = 0;
196 unsigned long timeout;
197
198 if (pdata->get_context_loss_count) {
199 context_loss = pdata->get_context_loss_count(host->dev);
200 if (context_loss < 0)
201 return 1;
202 }
203
204 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
205 context_loss == host->context_loss ? "not " : "");
206 if (host->context_loss == context_loss)
207 return 1;
208
209 /* Wait for hardware reset */
210 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
211 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
212 && time_before(jiffies, timeout))
213 ;
214
215 /* Do software reset */
216 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
217 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
218 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
219 && time_before(jiffies, timeout))
220 ;
221
222 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
223 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
224
225 if (host->id == OMAP_MMC1_DEVID) {
226 if (host->power_mode != MMC_POWER_OFF &&
227 (1 << ios->vdd) <= MMC_VDD_23_24)
228 hctl = SDVS18;
229 else
230 hctl = SDVS30;
231 capa = VS30 | VS18;
232 } else {
233 hctl = SDVS18;
234 capa = VS18;
235 }
236
237 OMAP_HSMMC_WRITE(host->base, HCTL,
238 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
239
240 OMAP_HSMMC_WRITE(host->base, CAPA,
241 OMAP_HSMMC_READ(host->base, CAPA) | capa);
242
243 OMAP_HSMMC_WRITE(host->base, HCTL,
244 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
245
246 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
247 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
248 && time_before(jiffies, timeout))
249 ;
250
251 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
252 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
253 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
254
255 /* Do not initialize card-specific things if the power is off */
256 if (host->power_mode == MMC_POWER_OFF)
257 goto out;
258
259 con = OMAP_HSMMC_READ(host->base, CON);
260 switch (ios->bus_width) {
261 case MMC_BUS_WIDTH_8:
262 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
263 break;
264 case MMC_BUS_WIDTH_4:
265 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
266 OMAP_HSMMC_WRITE(host->base, HCTL,
267 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
268 break;
269 case MMC_BUS_WIDTH_1:
270 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
271 OMAP_HSMMC_WRITE(host->base, HCTL,
272 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
273 break;
274 }
275
276 if (ios->clock) {
277 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
278 if (dsor < 1)
279 dsor = 1;
280
281 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
282 dsor++;
283
284 if (dsor > 250)
285 dsor = 250;
286 }
287
288 OMAP_HSMMC_WRITE(host->base, SYSCTL,
289 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
290 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
291 OMAP_HSMMC_WRITE(host->base, SYSCTL,
292 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
293
294 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
295 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
296 && time_before(jiffies, timeout))
297 ;
298
299 OMAP_HSMMC_WRITE(host->base, SYSCTL,
300 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
301
302 con = OMAP_HSMMC_READ(host->base, CON);
303 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
304 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
305 else
306 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
307 out:
308 host->context_loss = context_loss;
309
310 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
311 return 0;
312 }
313
314 /*
315 * Save the MMC host context (store the number of power state changes so far).
316 */
317 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
318 {
319 struct omap_mmc_platform_data *pdata = host->pdata;
320 int context_loss;
321
322 if (pdata->get_context_loss_count) {
323 context_loss = pdata->get_context_loss_count(host->dev);
324 if (context_loss < 0)
325 return;
326 host->context_loss = context_loss;
327 }
328 }
329
330 #else
331
332 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
333 {
334 return 0;
335 }
336
337 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
338 {
339 }
340
341 #endif
342
343 /*
344 * Send init stream sequence to card
345 * before sending IDLE command
346 */
347 static void send_init_stream(struct mmc_omap_host *host)
348 {
349 int reg = 0;
350 unsigned long timeout;
351
352 disable_irq(host->irq);
353 OMAP_HSMMC_WRITE(host->base, CON,
354 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
355 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
356
357 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
358 while ((reg != CC) && time_before(jiffies, timeout))
359 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
360
361 OMAP_HSMMC_WRITE(host->base, CON,
362 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
363
364 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
365 OMAP_HSMMC_READ(host->base, STAT);
366
367 enable_irq(host->irq);
368 }
369
370 static inline
371 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
372 {
373 int r = 1;
374
375 if (mmc_slot(host).get_cover_state)
376 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
377 return r;
378 }
379
380 static ssize_t
381 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
382 char *buf)
383 {
384 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
385 struct mmc_omap_host *host = mmc_priv(mmc);
386
387 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
388 "open");
389 }
390
391 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
392
393 static ssize_t
394 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
395 char *buf)
396 {
397 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
398 struct mmc_omap_host *host = mmc_priv(mmc);
399
400 return sprintf(buf, "%s\n", mmc_slot(host).name);
401 }
402
403 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
404
405 /*
406 * Configure the response type and send the cmd.
407 */
408 static void
409 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
410 struct mmc_data *data)
411 {
412 int cmdreg = 0, resptype = 0, cmdtype = 0;
413
414 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
415 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
416 host->cmd = cmd;
417
418 /*
419 * Clear status bits and enable interrupts
420 */
421 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
422 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
423
424 if (host->use_dma)
425 OMAP_HSMMC_WRITE(host->base, IE,
426 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
427 else
428 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
429
430 host->response_busy = 0;
431 if (cmd->flags & MMC_RSP_PRESENT) {
432 if (cmd->flags & MMC_RSP_136)
433 resptype = 1;
434 else if (cmd->flags & MMC_RSP_BUSY) {
435 resptype = 3;
436 host->response_busy = 1;
437 } else
438 resptype = 2;
439 }
440
441 /*
442 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
443 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
444 * a val of 0x3, rest 0x0.
445 */
446 if (cmd == host->mrq->stop)
447 cmdtype = 0x3;
448
449 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
450
451 if (data) {
452 cmdreg |= DP_SELECT | MSBS | BCE;
453 if (data->flags & MMC_DATA_READ)
454 cmdreg |= DDIR;
455 else
456 cmdreg &= ~(DDIR);
457 }
458
459 if (host->use_dma)
460 cmdreg |= DMA_EN;
461
462 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
463 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
464 }
465
466 static int
467 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
468 {
469 if (data->flags & MMC_DATA_WRITE)
470 return DMA_TO_DEVICE;
471 else
472 return DMA_FROM_DEVICE;
473 }
474
475 /*
476 * Notify the transfer complete to MMC core
477 */
478 static void
479 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
480 {
481 if (!data) {
482 struct mmc_request *mrq = host->mrq;
483
484 host->mrq = NULL;
485 mmc_request_done(host->mmc, mrq);
486 return;
487 }
488
489 host->data = NULL;
490
491 if (host->use_dma && host->dma_ch != -1)
492 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
493 mmc_omap_get_dma_dir(host, data));
494
495 if (!data->error)
496 data->bytes_xfered += data->blocks * (data->blksz);
497 else
498 data->bytes_xfered = 0;
499
500 if (!data->stop) {
501 host->mrq = NULL;
502 mmc_request_done(host->mmc, data->mrq);
503 return;
504 }
505 mmc_omap_start_command(host, data->stop, NULL);
506 }
507
508 /*
509 * Notify the core about command completion
510 */
511 static void
512 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
513 {
514 host->cmd = NULL;
515
516 if (cmd->flags & MMC_RSP_PRESENT) {
517 if (cmd->flags & MMC_RSP_136) {
518 /* response type 2 */
519 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
520 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
521 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
522 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
523 } else {
524 /* response types 1, 1b, 3, 4, 5, 6 */
525 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
526 }
527 }
528 if ((host->data == NULL && !host->response_busy) || cmd->error) {
529 host->mrq = NULL;
530 mmc_request_done(host->mmc, cmd->mrq);
531 }
532 }
533
534 /*
535 * DMA clean up for command errors
536 */
537 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
538 {
539 host->data->error = errno;
540
541 if (host->use_dma && host->dma_ch != -1) {
542 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
543 mmc_omap_get_dma_dir(host, host->data));
544 omap_free_dma(host->dma_ch);
545 host->dma_ch = -1;
546 up(&host->sem);
547 }
548 host->data = NULL;
549 }
550
551 /*
552 * Readable error output
553 */
554 #ifdef CONFIG_MMC_DEBUG
555 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
556 {
557 /* --- means reserved bit without definition at documentation */
558 static const char *mmc_omap_status_bits[] = {
559 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
560 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
561 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
562 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
563 };
564 char res[256];
565 char *buf = res;
566 int len, i;
567
568 len = sprintf(buf, "MMC IRQ 0x%x :", status);
569 buf += len;
570
571 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
572 if (status & (1 << i)) {
573 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
574 buf += len;
575 }
576
577 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
578 }
579 #endif /* CONFIG_MMC_DEBUG */
580
581 /*
582 * MMC controller internal state machines reset
583 *
584 * Used to reset command or data internal state machines, using respectively
585 * SRC or SRD bit of SYSCTL register
586 * Can be called from interrupt context
587 */
588 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
589 unsigned long bit)
590 {
591 unsigned long i = 0;
592 unsigned long limit = (loops_per_jiffy *
593 msecs_to_jiffies(MMC_TIMEOUT_MS));
594
595 OMAP_HSMMC_WRITE(host->base, SYSCTL,
596 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
597
598 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
599 (i++ < limit))
600 cpu_relax();
601
602 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
603 dev_err(mmc_dev(host->mmc),
604 "Timeout waiting on controller reset in %s\n",
605 __func__);
606 }
607
608 /*
609 * MMC controller IRQ handler
610 */
611 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
612 {
613 struct mmc_omap_host *host = dev_id;
614 struct mmc_data *data;
615 int end_cmd = 0, end_trans = 0, status;
616
617 if (host->mrq == NULL) {
618 OMAP_HSMMC_WRITE(host->base, STAT,
619 OMAP_HSMMC_READ(host->base, STAT));
620 /* Flush posted write */
621 OMAP_HSMMC_READ(host->base, STAT);
622 return IRQ_HANDLED;
623 }
624
625 data = host->data;
626 status = OMAP_HSMMC_READ(host->base, STAT);
627 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
628
629 if (status & ERR) {
630 #ifdef CONFIG_MMC_DEBUG
631 mmc_omap_report_irq(host, status);
632 #endif
633 if ((status & CMD_TIMEOUT) ||
634 (status & CMD_CRC)) {
635 if (host->cmd) {
636 if (status & CMD_TIMEOUT) {
637 mmc_omap_reset_controller_fsm(host,
638 SRC);
639 host->cmd->error = -ETIMEDOUT;
640 } else {
641 host->cmd->error = -EILSEQ;
642 }
643 end_cmd = 1;
644 }
645 if (host->data || host->response_busy) {
646 if (host->data)
647 mmc_dma_cleanup(host, -ETIMEDOUT);
648 host->response_busy = 0;
649 mmc_omap_reset_controller_fsm(host, SRD);
650 }
651 }
652 if ((status & DATA_TIMEOUT) ||
653 (status & DATA_CRC)) {
654 if (host->data || host->response_busy) {
655 int err = (status & DATA_TIMEOUT) ?
656 -ETIMEDOUT : -EILSEQ;
657
658 if (host->data)
659 mmc_dma_cleanup(host, err);
660 else
661 host->mrq->cmd->error = err;
662 host->response_busy = 0;
663 mmc_omap_reset_controller_fsm(host, SRD);
664 end_trans = 1;
665 }
666 }
667 if (status & CARD_ERR) {
668 dev_dbg(mmc_dev(host->mmc),
669 "Ignoring card err CMD%d\n", host->cmd->opcode);
670 if (host->cmd)
671 end_cmd = 1;
672 if (host->data)
673 end_trans = 1;
674 }
675 }
676
677 OMAP_HSMMC_WRITE(host->base, STAT, status);
678 /* Flush posted write */
679 OMAP_HSMMC_READ(host->base, STAT);
680
681 if (end_cmd || ((status & CC) && host->cmd))
682 mmc_omap_cmd_done(host, host->cmd);
683 if ((end_trans || (status & TC)) && host->mrq)
684 mmc_omap_xfer_done(host, data);
685
686 return IRQ_HANDLED;
687 }
688
689 static void set_sd_bus_power(struct mmc_omap_host *host)
690 {
691 unsigned long i;
692
693 OMAP_HSMMC_WRITE(host->base, HCTL,
694 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
695 for (i = 0; i < loops_per_jiffy; i++) {
696 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
697 break;
698 cpu_relax();
699 }
700 }
701
702 /*
703 * Switch MMC interface voltage ... only relevant for MMC1.
704 *
705 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
706 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
707 * Some chips, like eMMC ones, use internal transceivers.
708 */
709 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
710 {
711 u32 reg_val = 0;
712 int ret;
713
714 /* Disable the clocks */
715 clk_disable(host->fclk);
716 clk_disable(host->iclk);
717 clk_disable(host->dbclk);
718
719 /* Turn the power off */
720 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
721 if (ret != 0)
722 goto err;
723
724 /* Turn the power ON with given VDD 1.8 or 3.0v */
725 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
726 if (ret != 0)
727 goto err;
728
729 clk_enable(host->fclk);
730 clk_enable(host->iclk);
731 clk_enable(host->dbclk);
732
733 OMAP_HSMMC_WRITE(host->base, HCTL,
734 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
735 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
736
737 /*
738 * If a MMC dual voltage card is detected, the set_ios fn calls
739 * this fn with VDD bit set for 1.8V. Upon card removal from the
740 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
741 *
742 * Cope with a bit of slop in the range ... per data sheets:
743 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
744 * but recommended values are 1.71V to 1.89V
745 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
746 * but recommended values are 2.7V to 3.3V
747 *
748 * Board setup code shouldn't permit anything very out-of-range.
749 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
750 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
751 */
752 if ((1 << vdd) <= MMC_VDD_23_24)
753 reg_val |= SDVS18;
754 else
755 reg_val |= SDVS30;
756
757 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
758 set_sd_bus_power(host);
759
760 return 0;
761 err:
762 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
763 return ret;
764 }
765
766 /*
767 * Work Item to notify the core about card insertion/removal
768 */
769 static void mmc_omap_detect(struct work_struct *work)
770 {
771 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
772 mmc_carddetect_work);
773 struct omap_mmc_slot_data *slot = &mmc_slot(host);
774 int carddetect;
775
776 if (host->suspended)
777 return;
778
779 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
780
781 if (slot->card_detect)
782 carddetect = slot->card_detect(slot->card_detect_irq);
783 else
784 carddetect = -ENOSYS;
785
786 if (carddetect) {
787 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
788 } else {
789 mmc_host_enable(host->mmc);
790 mmc_omap_reset_controller_fsm(host, SRD);
791 mmc_host_lazy_disable(host->mmc);
792 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
793 }
794 }
795
796 /*
797 * ISR for handling card insertion and removal
798 */
799 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
800 {
801 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
802
803 if (host->suspended)
804 return IRQ_HANDLED;
805 schedule_work(&host->mmc_carddetect_work);
806
807 return IRQ_HANDLED;
808 }
809
810 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
811 struct mmc_data *data)
812 {
813 int sync_dev;
814
815 if (data->flags & MMC_DATA_WRITE)
816 sync_dev = host->dma_line_tx;
817 else
818 sync_dev = host->dma_line_rx;
819 return sync_dev;
820 }
821
822 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
823 struct mmc_data *data,
824 struct scatterlist *sgl)
825 {
826 int blksz, nblk, dma_ch;
827
828 dma_ch = host->dma_ch;
829 if (data->flags & MMC_DATA_WRITE) {
830 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
831 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
832 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
833 sg_dma_address(sgl), 0, 0);
834 } else {
835 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
836 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
837 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
838 sg_dma_address(sgl), 0, 0);
839 }
840
841 blksz = host->data->blksz;
842 nblk = sg_dma_len(sgl) / blksz;
843
844 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
845 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
846 mmc_omap_get_dma_sync_dev(host, data),
847 !(data->flags & MMC_DATA_WRITE));
848
849 omap_start_dma(dma_ch);
850 }
851
852 /*
853 * DMA call back function
854 */
855 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
856 {
857 struct mmc_omap_host *host = data;
858
859 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
860 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
861
862 if (host->dma_ch < 0)
863 return;
864
865 host->dma_sg_idx++;
866 if (host->dma_sg_idx < host->dma_len) {
867 /* Fire up the next transfer. */
868 mmc_omap_config_dma_params(host, host->data,
869 host->data->sg + host->dma_sg_idx);
870 return;
871 }
872
873 omap_free_dma(host->dma_ch);
874 host->dma_ch = -1;
875 /*
876 * DMA Callback: run in interrupt context.
877 * mutex_unlock will throw a kernel warning if used.
878 */
879 up(&host->sem);
880 }
881
882 /*
883 * Routine to configure and start DMA for the MMC card
884 */
885 static int
886 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
887 {
888 int dma_ch = 0, ret = 0, err = 1, i;
889 struct mmc_data *data = req->data;
890
891 /* Sanity check: all the SG entries must be aligned by block size. */
892 for (i = 0; i < data->sg_len; i++) {
893 struct scatterlist *sgl;
894
895 sgl = data->sg + i;
896 if (sgl->length % data->blksz)
897 return -EINVAL;
898 }
899 if ((data->blksz % 4) != 0)
900 /* REVISIT: The MMC buffer increments only when MSB is written.
901 * Return error for blksz which is non multiple of four.
902 */
903 return -EINVAL;
904
905 /*
906 * If for some reason the DMA transfer is still active,
907 * we wait for timeout period and free the dma
908 */
909 if (host->dma_ch != -1) {
910 set_current_state(TASK_UNINTERRUPTIBLE);
911 schedule_timeout(100);
912 if (down_trylock(&host->sem)) {
913 omap_free_dma(host->dma_ch);
914 host->dma_ch = -1;
915 up(&host->sem);
916 return err;
917 }
918 } else {
919 if (down_trylock(&host->sem))
920 return err;
921 }
922
923 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
924 mmc_omap_dma_cb, host, &dma_ch);
925 if (ret != 0) {
926 dev_err(mmc_dev(host->mmc),
927 "%s: omap_request_dma() failed with %d\n",
928 mmc_hostname(host->mmc), ret);
929 return ret;
930 }
931
932 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
933 data->sg_len, mmc_omap_get_dma_dir(host, data));
934 host->dma_ch = dma_ch;
935 host->dma_sg_idx = 0;
936
937 mmc_omap_config_dma_params(host, data, data->sg);
938
939 return 0;
940 }
941
942 static void set_data_timeout(struct mmc_omap_host *host,
943 struct mmc_request *req)
944 {
945 unsigned int timeout, cycle_ns;
946 uint32_t reg, clkd, dto = 0;
947
948 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
949 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
950 if (clkd == 0)
951 clkd = 1;
952
953 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
954 timeout = req->data->timeout_ns / cycle_ns;
955 timeout += req->data->timeout_clks;
956 if (timeout) {
957 while ((timeout & 0x80000000) == 0) {
958 dto += 1;
959 timeout <<= 1;
960 }
961 dto = 31 - dto;
962 timeout <<= 1;
963 if (timeout && dto)
964 dto += 1;
965 if (dto >= 13)
966 dto -= 13;
967 else
968 dto = 0;
969 if (dto > 14)
970 dto = 14;
971 }
972
973 reg &= ~DTO_MASK;
974 reg |= dto << DTO_SHIFT;
975 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
976 }
977
978 /*
979 * Configure block length for MMC/SD cards and initiate the transfer.
980 */
981 static int
982 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
983 {
984 int ret;
985 host->data = req->data;
986
987 if (req->data == NULL) {
988 OMAP_HSMMC_WRITE(host->base, BLK, 0);
989 return 0;
990 }
991
992 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
993 | (req->data->blocks << 16));
994 set_data_timeout(host, req);
995
996 if (host->use_dma) {
997 ret = mmc_omap_start_dma_transfer(host, req);
998 if (ret != 0) {
999 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1000 return ret;
1001 }
1002 }
1003 return 0;
1004 }
1005
1006 /*
1007 * Request function. for read/write operation
1008 */
1009 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1010 {
1011 struct mmc_omap_host *host = mmc_priv(mmc);
1012 int err;
1013
1014 WARN_ON(host->mrq != NULL);
1015 host->mrq = req;
1016 err = mmc_omap_prepare_data(host, req);
1017 if (err) {
1018 req->cmd->error = err;
1019 if (req->data)
1020 req->data->error = err;
1021 host->mrq = NULL;
1022 mmc_request_done(mmc, req);
1023 return;
1024 }
1025
1026 mmc_omap_start_command(host, req->cmd, req->data);
1027 }
1028
1029
1030 /* Routine to configure clock values. Exposed API to core */
1031 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1032 {
1033 struct mmc_omap_host *host = mmc_priv(mmc);
1034 u16 dsor = 0;
1035 unsigned long regval;
1036 unsigned long timeout;
1037 u32 con;
1038 int do_send_init_stream = 0;
1039
1040 mmc_host_enable(host->mmc);
1041
1042 if (ios->power_mode != host->power_mode) {
1043 switch (ios->power_mode) {
1044 case MMC_POWER_OFF:
1045 mmc_slot(host).set_power(host->dev, host->slot_id,
1046 0, 0);
1047 host->vdd = 0;
1048 break;
1049 case MMC_POWER_UP:
1050 mmc_slot(host).set_power(host->dev, host->slot_id,
1051 1, ios->vdd);
1052 host->vdd = ios->vdd;
1053 break;
1054 case MMC_POWER_ON:
1055 do_send_init_stream = 1;
1056 break;
1057 }
1058 host->power_mode = ios->power_mode;
1059 }
1060
1061 /* FIXME: set registers based only on changes to ios */
1062
1063 con = OMAP_HSMMC_READ(host->base, CON);
1064 switch (mmc->ios.bus_width) {
1065 case MMC_BUS_WIDTH_8:
1066 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1067 break;
1068 case MMC_BUS_WIDTH_4:
1069 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1070 OMAP_HSMMC_WRITE(host->base, HCTL,
1071 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1072 break;
1073 case MMC_BUS_WIDTH_1:
1074 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1075 OMAP_HSMMC_WRITE(host->base, HCTL,
1076 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1077 break;
1078 }
1079
1080 if (host->id == OMAP_MMC1_DEVID) {
1081 /* Only MMC1 can interface at 3V without some flavor
1082 * of external transceiver; but they all handle 1.8V.
1083 */
1084 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1085 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1086 /*
1087 * The mmc_select_voltage fn of the core does
1088 * not seem to set the power_mode to
1089 * MMC_POWER_UP upon recalculating the voltage.
1090 * vdd 1.8v.
1091 */
1092 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1093 dev_dbg(mmc_dev(host->mmc),
1094 "Switch operation failed\n");
1095 }
1096 }
1097
1098 if (ios->clock) {
1099 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1100 if (dsor < 1)
1101 dsor = 1;
1102
1103 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1104 dsor++;
1105
1106 if (dsor > 250)
1107 dsor = 250;
1108 }
1109 omap_mmc_stop_clock(host);
1110 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1111 regval = regval & ~(CLKD_MASK);
1112 regval = regval | (dsor << 6) | (DTO << 16);
1113 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1114 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1116
1117 /* Wait till the ICS bit is set */
1118 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1119 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1120 && time_before(jiffies, timeout))
1121 msleep(1);
1122
1123 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1124 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1125
1126 if (do_send_init_stream)
1127 send_init_stream(host);
1128
1129 con = OMAP_HSMMC_READ(host->base, CON);
1130 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1131 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1132 else
1133 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1134
1135 if (host->power_mode == MMC_POWER_OFF)
1136 mmc_host_disable(host->mmc);
1137 else
1138 mmc_host_lazy_disable(host->mmc);
1139 }
1140
1141 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1142 {
1143 struct mmc_omap_host *host = mmc_priv(mmc);
1144
1145 if (!mmc_slot(host).card_detect)
1146 return -ENOSYS;
1147 return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
1148 }
1149
1150 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1151 {
1152 struct mmc_omap_host *host = mmc_priv(mmc);
1153
1154 if (!mmc_slot(host).get_ro)
1155 return -ENOSYS;
1156 return mmc_slot(host).get_ro(host->dev, 0);
1157 }
1158
1159 static void omap_hsmmc_init(struct mmc_omap_host *host)
1160 {
1161 u32 hctl, capa, value;
1162
1163 /* Only MMC1 supports 3.0V */
1164 if (host->id == OMAP_MMC1_DEVID) {
1165 hctl = SDVS30;
1166 capa = VS30 | VS18;
1167 } else {
1168 hctl = SDVS18;
1169 capa = VS18;
1170 }
1171
1172 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1173 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1174
1175 value = OMAP_HSMMC_READ(host->base, CAPA);
1176 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1177
1178 /* Set the controller to AUTO IDLE mode */
1179 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1180 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1181
1182 /* Set SD bus power bit */
1183 set_sd_bus_power(host);
1184 }
1185
1186 /*
1187 * Dynamic power saving handling, FSM:
1188 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1189 * ^___________| | |
1190 * |______________________|______________________|
1191 *
1192 * ENABLED: mmc host is fully functional
1193 * DISABLED: fclk is off
1194 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1195 * REGSLEEP: fclk is off, voltage regulator is asleep
1196 * OFF: fclk is off, voltage regulator is off
1197 *
1198 * Transition handlers return the timeout for the next state transition
1199 * or negative error.
1200 */
1201
1202 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1203
1204 /* Handler for [ENABLED -> DISABLED] transition */
1205 static int omap_mmc_enabled_to_disabled(struct mmc_omap_host *host)
1206 {
1207 omap_mmc_save_ctx(host);
1208 clk_disable(host->fclk);
1209 host->dpm_state = DISABLED;
1210
1211 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1212
1213 if (host->power_mode == MMC_POWER_OFF)
1214 return 0;
1215
1216 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1217 }
1218
1219 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1220 static int omap_mmc_disabled_to_sleep(struct mmc_omap_host *host)
1221 {
1222 int err, new_state;
1223
1224 if (!mmc_try_claim_host(host->mmc))
1225 return 0;
1226
1227 clk_enable(host->fclk);
1228 omap_mmc_restore_ctx(host);
1229 if (mmc_card_can_sleep(host->mmc)) {
1230 err = mmc_card_sleep(host->mmc);
1231 if (err < 0) {
1232 clk_disable(host->fclk);
1233 mmc_release_host(host->mmc);
1234 return err;
1235 }
1236 new_state = CARDSLEEP;
1237 } else
1238 new_state = REGSLEEP;
1239 if (mmc_slot(host).set_sleep)
1240 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1241 new_state == CARDSLEEP);
1242 /* FIXME: turn off bus power and perhaps interrupts too */
1243 clk_disable(host->fclk);
1244 host->dpm_state = new_state;
1245
1246 mmc_release_host(host->mmc);
1247
1248 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1249 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1250
1251 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1252 mmc_slot(host).card_detect ||
1253 (mmc_slot(host).get_cover_state &&
1254 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1255 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1256
1257 return 0;
1258 }
1259
1260 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1261 static int omap_mmc_sleep_to_off(struct mmc_omap_host *host)
1262 {
1263 if (!mmc_try_claim_host(host->mmc))
1264 return 0;
1265
1266 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1267 mmc_slot(host).card_detect ||
1268 (mmc_slot(host).get_cover_state &&
1269 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1270 mmc_release_host(host->mmc);
1271 return 0;
1272 }
1273
1274 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1275 host->vdd = 0;
1276 host->power_mode = MMC_POWER_OFF;
1277
1278 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1279 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1280
1281 host->dpm_state = OFF;
1282
1283 mmc_release_host(host->mmc);
1284
1285 return 0;
1286 }
1287
1288 /* Handler for [DISABLED -> ENABLED] transition */
1289 static int omap_mmc_disabled_to_enabled(struct mmc_omap_host *host)
1290 {
1291 int err;
1292
1293 err = clk_enable(host->fclk);
1294 if (err < 0)
1295 return err;
1296
1297 omap_mmc_restore_ctx(host);
1298
1299 host->dpm_state = ENABLED;
1300
1301 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1302
1303 return 0;
1304 }
1305
1306 /* Handler for [SLEEP -> ENABLED] transition */
1307 static int omap_mmc_sleep_to_enabled(struct mmc_omap_host *host)
1308 {
1309 if (!mmc_try_claim_host(host->mmc))
1310 return 0;
1311
1312 clk_enable(host->fclk);
1313 omap_mmc_restore_ctx(host);
1314 if (mmc_slot(host).set_sleep)
1315 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1316 host->vdd, host->dpm_state == CARDSLEEP);
1317 if (mmc_card_can_sleep(host->mmc))
1318 mmc_card_awake(host->mmc);
1319
1320 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1321 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1322
1323 host->dpm_state = ENABLED;
1324
1325 mmc_release_host(host->mmc);
1326
1327 return 0;
1328 }
1329
1330 /* Handler for [OFF -> ENABLED] transition */
1331 static int omap_mmc_off_to_enabled(struct mmc_omap_host *host)
1332 {
1333 clk_enable(host->fclk);
1334
1335 omap_mmc_restore_ctx(host);
1336 omap_hsmmc_init(host);
1337 mmc_power_restore_host(host->mmc);
1338
1339 host->dpm_state = ENABLED;
1340
1341 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1342
1343 return 0;
1344 }
1345
1346 /*
1347 * Bring MMC host to ENABLED from any other PM state.
1348 */
1349 static int omap_mmc_enable(struct mmc_host *mmc)
1350 {
1351 struct mmc_omap_host *host = mmc_priv(mmc);
1352
1353 switch (host->dpm_state) {
1354 case DISABLED:
1355 return omap_mmc_disabled_to_enabled(host);
1356 case CARDSLEEP:
1357 case REGSLEEP:
1358 return omap_mmc_sleep_to_enabled(host);
1359 case OFF:
1360 return omap_mmc_off_to_enabled(host);
1361 default:
1362 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1363 return -EINVAL;
1364 }
1365 }
1366
1367 /*
1368 * Bring MMC host in PM state (one level deeper).
1369 */
1370 static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1371 {
1372 struct mmc_omap_host *host = mmc_priv(mmc);
1373
1374 switch (host->dpm_state) {
1375 case ENABLED: {
1376 int delay;
1377
1378 delay = omap_mmc_enabled_to_disabled(host);
1379 if (lazy || delay < 0)
1380 return delay;
1381 return 0;
1382 }
1383 case DISABLED:
1384 return omap_mmc_disabled_to_sleep(host);
1385 case CARDSLEEP:
1386 case REGSLEEP:
1387 return omap_mmc_sleep_to_off(host);
1388 default:
1389 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1390 return -EINVAL;
1391 }
1392 }
1393
1394 static int omap_mmc_enable_fclk(struct mmc_host *mmc)
1395 {
1396 struct mmc_omap_host *host = mmc_priv(mmc);
1397 int err;
1398
1399 err = clk_enable(host->fclk);
1400 if (err)
1401 return err;
1402 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1403 omap_mmc_restore_ctx(host);
1404 return 0;
1405 }
1406
1407 static int omap_mmc_disable_fclk(struct mmc_host *mmc, int lazy)
1408 {
1409 struct mmc_omap_host *host = mmc_priv(mmc);
1410
1411 omap_mmc_save_ctx(host);
1412 clk_disable(host->fclk);
1413 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1414 return 0;
1415 }
1416
1417 static const struct mmc_host_ops mmc_omap_ops = {
1418 .enable = omap_mmc_enable_fclk,
1419 .disable = omap_mmc_disable_fclk,
1420 .request = omap_mmc_request,
1421 .set_ios = omap_mmc_set_ios,
1422 .get_cd = omap_hsmmc_get_cd,
1423 .get_ro = omap_hsmmc_get_ro,
1424 /* NYET -- enable_sdio_irq */
1425 };
1426
1427 static const struct mmc_host_ops mmc_omap_ps_ops = {
1428 .enable = omap_mmc_enable,
1429 .disable = omap_mmc_disable,
1430 .request = omap_mmc_request,
1431 .set_ios = omap_mmc_set_ios,
1432 .get_cd = omap_hsmmc_get_cd,
1433 .get_ro = omap_hsmmc_get_ro,
1434 /* NYET -- enable_sdio_irq */
1435 };
1436
1437 #ifdef CONFIG_DEBUG_FS
1438
1439 static int mmc_regs_show(struct seq_file *s, void *data)
1440 {
1441 struct mmc_host *mmc = s->private;
1442 struct mmc_omap_host *host = mmc_priv(mmc);
1443 struct omap_mmc_platform_data *pdata = host->pdata;
1444 int context_loss = 0;
1445
1446 if (pdata->get_context_loss_count)
1447 context_loss = pdata->get_context_loss_count(host->dev);
1448
1449 seq_printf(s, "mmc%d:\n"
1450 " enabled:\t%d\n"
1451 " dpm_state:\t%d\n"
1452 " nesting_cnt:\t%d\n"
1453 " ctx_loss:\t%d:%d\n"
1454 "\nregs:\n",
1455 mmc->index, mmc->enabled ? 1 : 0,
1456 host->dpm_state, mmc->nesting_cnt,
1457 host->context_loss, context_loss);
1458
1459 if (host->suspended || host->dpm_state == OFF) {
1460 seq_printf(s, "host suspended, can't read registers\n");
1461 return 0;
1462 }
1463
1464 if (clk_enable(host->fclk) != 0) {
1465 seq_printf(s, "can't read the regs\n");
1466 return 0;
1467 }
1468
1469 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1470 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1471 seq_printf(s, "CON:\t\t0x%08x\n",
1472 OMAP_HSMMC_READ(host->base, CON));
1473 seq_printf(s, "HCTL:\t\t0x%08x\n",
1474 OMAP_HSMMC_READ(host->base, HCTL));
1475 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1476 OMAP_HSMMC_READ(host->base, SYSCTL));
1477 seq_printf(s, "IE:\t\t0x%08x\n",
1478 OMAP_HSMMC_READ(host->base, IE));
1479 seq_printf(s, "ISE:\t\t0x%08x\n",
1480 OMAP_HSMMC_READ(host->base, ISE));
1481 seq_printf(s, "CAPA:\t\t0x%08x\n",
1482 OMAP_HSMMC_READ(host->base, CAPA));
1483
1484 clk_disable(host->fclk);
1485
1486 return 0;
1487 }
1488
1489 static int mmc_regs_open(struct inode *inode, struct file *file)
1490 {
1491 return single_open(file, mmc_regs_show, inode->i_private);
1492 }
1493
1494 static const struct file_operations mmc_regs_fops = {
1495 .open = mmc_regs_open,
1496 .read = seq_read,
1497 .llseek = seq_lseek,
1498 .release = single_release,
1499 };
1500
1501 static void omap_mmc_debugfs(struct mmc_host *mmc)
1502 {
1503 if (mmc->debugfs_root)
1504 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1505 mmc, &mmc_regs_fops);
1506 }
1507
1508 #else
1509
1510 static void omap_mmc_debugfs(struct mmc_host *mmc)
1511 {
1512 }
1513
1514 #endif
1515
1516 static int __init omap_mmc_probe(struct platform_device *pdev)
1517 {
1518 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1519 struct mmc_host *mmc;
1520 struct mmc_omap_host *host = NULL;
1521 struct resource *res;
1522 int ret = 0, irq;
1523
1524 if (pdata == NULL) {
1525 dev_err(&pdev->dev, "Platform Data is missing\n");
1526 return -ENXIO;
1527 }
1528
1529 if (pdata->nr_slots == 0) {
1530 dev_err(&pdev->dev, "No Slots\n");
1531 return -ENXIO;
1532 }
1533
1534 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1535 irq = platform_get_irq(pdev, 0);
1536 if (res == NULL || irq < 0)
1537 return -ENXIO;
1538
1539 res = request_mem_region(res->start, res->end - res->start + 1,
1540 pdev->name);
1541 if (res == NULL)
1542 return -EBUSY;
1543
1544 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1545 if (!mmc) {
1546 ret = -ENOMEM;
1547 goto err;
1548 }
1549
1550 host = mmc_priv(mmc);
1551 host->mmc = mmc;
1552 host->pdata = pdata;
1553 host->dev = &pdev->dev;
1554 host->use_dma = 1;
1555 host->dev->dma_mask = &pdata->dma_mask;
1556 host->dma_ch = -1;
1557 host->irq = irq;
1558 host->id = pdev->id;
1559 host->slot_id = 0;
1560 host->mapbase = res->start;
1561 host->base = ioremap(host->mapbase, SZ_4K);
1562 host->power_mode = -1;
1563
1564 platform_set_drvdata(pdev, host);
1565 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1566
1567 if (mmc_slot(host).power_saving)
1568 mmc->ops = &mmc_omap_ps_ops;
1569 else
1570 mmc->ops = &mmc_omap_ops;
1571
1572 mmc->f_min = 400000;
1573 mmc->f_max = 52000000;
1574
1575 sema_init(&host->sem, 1);
1576
1577 host->iclk = clk_get(&pdev->dev, "ick");
1578 if (IS_ERR(host->iclk)) {
1579 ret = PTR_ERR(host->iclk);
1580 host->iclk = NULL;
1581 goto err1;
1582 }
1583 host->fclk = clk_get(&pdev->dev, "fck");
1584 if (IS_ERR(host->fclk)) {
1585 ret = PTR_ERR(host->fclk);
1586 host->fclk = NULL;
1587 clk_put(host->iclk);
1588 goto err1;
1589 }
1590
1591 omap_mmc_save_ctx(host);
1592
1593 mmc->caps |= MMC_CAP_DISABLE;
1594 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1595 /* we start off in DISABLED state */
1596 host->dpm_state = DISABLED;
1597
1598 if (mmc_host_enable(host->mmc) != 0) {
1599 clk_put(host->iclk);
1600 clk_put(host->fclk);
1601 goto err1;
1602 }
1603
1604 if (clk_enable(host->iclk) != 0) {
1605 mmc_host_disable(host->mmc);
1606 clk_put(host->iclk);
1607 clk_put(host->fclk);
1608 goto err1;
1609 }
1610
1611 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1612 /*
1613 * MMC can still work without debounce clock.
1614 */
1615 if (IS_ERR(host->dbclk))
1616 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1617 else
1618 if (clk_enable(host->dbclk) != 0)
1619 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1620 " clk failed\n");
1621 else
1622 host->dbclk_enabled = 1;
1623
1624 /* Since we do only SG emulation, we can have as many segs
1625 * as we want. */
1626 mmc->max_phys_segs = 1024;
1627 mmc->max_hw_segs = 1024;
1628
1629 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1630 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1631 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1632 mmc->max_seg_size = mmc->max_req_size;
1633
1634 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1635 MMC_CAP_WAIT_WHILE_BUSY;
1636
1637 if (mmc_slot(host).wires >= 8)
1638 mmc->caps |= MMC_CAP_8_BIT_DATA;
1639 else if (mmc_slot(host).wires >= 4)
1640 mmc->caps |= MMC_CAP_4_BIT_DATA;
1641
1642 if (mmc_slot(host).nonremovable)
1643 mmc->caps |= MMC_CAP_NONREMOVABLE;
1644
1645 omap_hsmmc_init(host);
1646
1647 /* Select DMA lines */
1648 switch (host->id) {
1649 case OMAP_MMC1_DEVID:
1650 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1651 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1652 break;
1653 case OMAP_MMC2_DEVID:
1654 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1655 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1656 break;
1657 case OMAP_MMC3_DEVID:
1658 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1659 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1660 break;
1661 default:
1662 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1663 goto err_irq;
1664 }
1665
1666 /* Request IRQ for MMC operations */
1667 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1668 mmc_hostname(mmc), host);
1669 if (ret) {
1670 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1671 goto err_irq;
1672 }
1673
1674 /* initialize power supplies, gpios, etc */
1675 if (pdata->init != NULL) {
1676 if (pdata->init(&pdev->dev) != 0) {
1677 dev_dbg(mmc_dev(host->mmc), "late init error\n");
1678 goto err_irq_cd_init;
1679 }
1680 }
1681 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1682
1683 /* Request IRQ for card detect */
1684 if ((mmc_slot(host).card_detect_irq)) {
1685 ret = request_irq(mmc_slot(host).card_detect_irq,
1686 omap_mmc_cd_handler,
1687 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1688 | IRQF_DISABLED,
1689 mmc_hostname(mmc), host);
1690 if (ret) {
1691 dev_dbg(mmc_dev(host->mmc),
1692 "Unable to grab MMC CD IRQ\n");
1693 goto err_irq_cd;
1694 }
1695 }
1696
1697 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1698 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1699
1700 mmc_host_lazy_disable(host->mmc);
1701
1702 mmc_add_host(mmc);
1703
1704 if (mmc_slot(host).name != NULL) {
1705 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1706 if (ret < 0)
1707 goto err_slot_name;
1708 }
1709 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1710 ret = device_create_file(&mmc->class_dev,
1711 &dev_attr_cover_switch);
1712 if (ret < 0)
1713 goto err_cover_switch;
1714 }
1715
1716 omap_mmc_debugfs(mmc);
1717
1718 return 0;
1719
1720 err_cover_switch:
1721 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1722 err_slot_name:
1723 mmc_remove_host(mmc);
1724 err_irq_cd:
1725 free_irq(mmc_slot(host).card_detect_irq, host);
1726 err_irq_cd_init:
1727 free_irq(host->irq, host);
1728 err_irq:
1729 mmc_host_disable(host->mmc);
1730 clk_disable(host->iclk);
1731 clk_put(host->fclk);
1732 clk_put(host->iclk);
1733 if (host->dbclk_enabled) {
1734 clk_disable(host->dbclk);
1735 clk_put(host->dbclk);
1736 }
1737
1738 err1:
1739 iounmap(host->base);
1740 err:
1741 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1742 release_mem_region(res->start, res->end - res->start + 1);
1743 if (host)
1744 mmc_free_host(mmc);
1745 return ret;
1746 }
1747
1748 static int omap_mmc_remove(struct platform_device *pdev)
1749 {
1750 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1751 struct resource *res;
1752
1753 if (host) {
1754 mmc_host_enable(host->mmc);
1755 mmc_remove_host(host->mmc);
1756 if (host->pdata->cleanup)
1757 host->pdata->cleanup(&pdev->dev);
1758 free_irq(host->irq, host);
1759 if (mmc_slot(host).card_detect_irq)
1760 free_irq(mmc_slot(host).card_detect_irq, host);
1761 flush_scheduled_work();
1762
1763 mmc_host_disable(host->mmc);
1764 clk_disable(host->iclk);
1765 clk_put(host->fclk);
1766 clk_put(host->iclk);
1767 if (host->dbclk_enabled) {
1768 clk_disable(host->dbclk);
1769 clk_put(host->dbclk);
1770 }
1771
1772 mmc_free_host(host->mmc);
1773 iounmap(host->base);
1774 }
1775
1776 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1777 if (res)
1778 release_mem_region(res->start, res->end - res->start + 1);
1779 platform_set_drvdata(pdev, NULL);
1780
1781 return 0;
1782 }
1783
1784 #ifdef CONFIG_PM
1785 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1786 {
1787 int ret = 0;
1788 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1789
1790 if (host && host->suspended)
1791 return 0;
1792
1793 if (host) {
1794 host->suspended = 1;
1795 if (host->pdata->suspend) {
1796 ret = host->pdata->suspend(&pdev->dev,
1797 host->slot_id);
1798 if (ret) {
1799 dev_dbg(mmc_dev(host->mmc),
1800 "Unable to handle MMC board"
1801 " level suspend\n");
1802 host->suspended = 0;
1803 return ret;
1804 }
1805 }
1806 cancel_work_sync(&host->mmc_carddetect_work);
1807 mmc_host_enable(host->mmc);
1808 ret = mmc_suspend_host(host->mmc, state);
1809 if (ret == 0) {
1810 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1811 OMAP_HSMMC_WRITE(host->base, IE, 0);
1812
1813
1814 OMAP_HSMMC_WRITE(host->base, HCTL,
1815 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1816 mmc_host_disable(host->mmc);
1817 clk_disable(host->iclk);
1818 clk_disable(host->dbclk);
1819 } else {
1820 host->suspended = 0;
1821 if (host->pdata->resume) {
1822 ret = host->pdata->resume(&pdev->dev,
1823 host->slot_id);
1824 if (ret)
1825 dev_dbg(mmc_dev(host->mmc),
1826 "Unmask interrupt failed\n");
1827 }
1828 mmc_host_disable(host->mmc);
1829 }
1830
1831 }
1832 return ret;
1833 }
1834
1835 /* Routine to resume the MMC device */
1836 static int omap_mmc_resume(struct platform_device *pdev)
1837 {
1838 int ret = 0;
1839 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1840
1841 if (host && !host->suspended)
1842 return 0;
1843
1844 if (host) {
1845 ret = clk_enable(host->iclk);
1846 if (ret)
1847 goto clk_en_err;
1848
1849 if (clk_enable(host->dbclk) != 0)
1850 dev_dbg(mmc_dev(host->mmc),
1851 "Enabling debounce clk failed\n");
1852
1853 if (mmc_host_enable(host->mmc) != 0) {
1854 clk_disable(host->iclk);
1855 goto clk_en_err;
1856 }
1857
1858 omap_hsmmc_init(host);
1859
1860 if (host->pdata->resume) {
1861 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1862 if (ret)
1863 dev_dbg(mmc_dev(host->mmc),
1864 "Unmask interrupt failed\n");
1865 }
1866
1867 /* Notify the core to resume the host */
1868 ret = mmc_resume_host(host->mmc);
1869 if (ret == 0)
1870 host->suspended = 0;
1871 mmc_host_lazy_disable(host->mmc);
1872 }
1873
1874 return ret;
1875
1876 clk_en_err:
1877 dev_dbg(mmc_dev(host->mmc),
1878 "Failed to enable MMC clocks during resume\n");
1879 return ret;
1880 }
1881
1882 #else
1883 #define omap_mmc_suspend NULL
1884 #define omap_mmc_resume NULL
1885 #endif
1886
1887 static struct platform_driver omap_mmc_driver = {
1888 .remove = omap_mmc_remove,
1889 .suspend = omap_mmc_suspend,
1890 .resume = omap_mmc_resume,
1891 .driver = {
1892 .name = DRIVER_NAME,
1893 .owner = THIS_MODULE,
1894 },
1895 };
1896
1897 static int __init omap_mmc_init(void)
1898 {
1899 /* Register the MMC driver */
1900 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
1901 }
1902
1903 static void __exit omap_mmc_cleanup(void)
1904 {
1905 /* Unregister MMC driver */
1906 platform_driver_unregister(&omap_mmc_driver);
1907 }
1908
1909 module_init(omap_mmc_init);
1910 module_exit(omap_mmc_cleanup);
1911
1912 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1913 MODULE_LICENSE("GPL");
1914 MODULE_ALIAS("platform:" DRIVER_NAME);
1915 MODULE_AUTHOR("Texas Instruments Inc");
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