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[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/slot-gpio.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/pm_wakeirq.h>
46 #include <linux/platform_data/hsmmc-omap.h>
47
48 /* OMAP HSMMC Host Controller Registers */
49 #define OMAP_HSMMC_SYSSTATUS 0x0014
50 #define OMAP_HSMMC_CON 0x002C
51 #define OMAP_HSMMC_SDMASA 0x0100
52 #define OMAP_HSMMC_BLK 0x0104
53 #define OMAP_HSMMC_ARG 0x0108
54 #define OMAP_HSMMC_CMD 0x010C
55 #define OMAP_HSMMC_RSP10 0x0110
56 #define OMAP_HSMMC_RSP32 0x0114
57 #define OMAP_HSMMC_RSP54 0x0118
58 #define OMAP_HSMMC_RSP76 0x011C
59 #define OMAP_HSMMC_DATA 0x0120
60 #define OMAP_HSMMC_PSTATE 0x0124
61 #define OMAP_HSMMC_HCTL 0x0128
62 #define OMAP_HSMMC_SYSCTL 0x012C
63 #define OMAP_HSMMC_STAT 0x0130
64 #define OMAP_HSMMC_IE 0x0134
65 #define OMAP_HSMMC_ISE 0x0138
66 #define OMAP_HSMMC_AC12 0x013C
67 #define OMAP_HSMMC_CAPA 0x0140
68
69 #define VS18 (1 << 26)
70 #define VS30 (1 << 25)
71 #define HSS (1 << 21)
72 #define SDVS18 (0x5 << 9)
73 #define SDVS30 (0x6 << 9)
74 #define SDVS33 (0x7 << 9)
75 #define SDVS_MASK 0x00000E00
76 #define SDVSCLR 0xFFFFF1FF
77 #define SDVSDET 0x00000400
78 #define AUTOIDLE 0x1
79 #define SDBP (1 << 8)
80 #define DTO 0xe
81 #define ICE 0x1
82 #define ICS 0x2
83 #define CEN (1 << 2)
84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
85 #define CLKD_MASK 0x0000FFC0
86 #define CLKD_SHIFT 6
87 #define DTO_MASK 0x000F0000
88 #define DTO_SHIFT 16
89 #define INIT_STREAM (1 << 1)
90 #define ACEN_ACMD23 (2 << 2)
91 #define DP_SELECT (1 << 21)
92 #define DDIR (1 << 4)
93 #define DMAE 0x1
94 #define MSBS (1 << 5)
95 #define BCE (1 << 1)
96 #define FOUR_BIT (1 << 1)
97 #define HSPE (1 << 2)
98 #define IWE (1 << 24)
99 #define DDR (1 << 19)
100 #define CLKEXTFREE (1 << 16)
101 #define CTPL (1 << 11)
102 #define DW8 (1 << 5)
103 #define OD 0x1
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
110
111 /* PSTATE */
112 #define DLEV_DAT(x) (1 << (20 + (x)))
113
114 /* Interrupt masks for IE and ISE register */
115 #define CC_EN (1 << 0)
116 #define TC_EN (1 << 1)
117 #define BWR_EN (1 << 4)
118 #define BRR_EN (1 << 5)
119 #define CIRQ_EN (1 << 8)
120 #define ERR_EN (1 << 15)
121 #define CTO_EN (1 << 16)
122 #define CCRC_EN (1 << 17)
123 #define CEB_EN (1 << 18)
124 #define CIE_EN (1 << 19)
125 #define DTO_EN (1 << 20)
126 #define DCRC_EN (1 << 21)
127 #define DEB_EN (1 << 22)
128 #define ACE_EN (1 << 24)
129 #define CERR_EN (1 << 28)
130 #define BADA_EN (1 << 29)
131
132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
135
136 #define CNI (1 << 7)
137 #define ACIE (1 << 4)
138 #define ACEB (1 << 3)
139 #define ACCE (1 << 2)
140 #define ACTO (1 << 1)
141 #define ACNE (1 << 0)
142
143 #define MMC_AUTOSUSPEND_DELAY 100
144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
146 #define OMAP_MMC_MIN_CLOCK 400000
147 #define OMAP_MMC_MAX_CLOCK 52000000
148 #define DRIVER_NAME "omap_hsmmc"
149
150 #define VDD_1V8 1800000 /* 180000 uV */
151 #define VDD_3V0 3000000 /* 300000 uV */
152 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
153
154 /*
155 * One controller can have multiple slots, like on some omap boards using
156 * omap.c controller driver. Luckily this is not currently done on any known
157 * omap_hsmmc.c device.
158 */
159 #define mmc_pdata(host) host->pdata
160
161 /*
162 * MMC Host controller read/write API's
163 */
164 #define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
166
167 #define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
169
170 struct omap_hsmmc_next {
171 unsigned int dma_len;
172 s32 cookie;
173 };
174
175 struct omap_hsmmc_host {
176 struct device *dev;
177 struct mmc_host *mmc;
178 struct mmc_request *mrq;
179 struct mmc_command *cmd;
180 struct mmc_data *data;
181 struct clk *fclk;
182 struct clk *dbclk;
183 struct regulator *pbias;
184 bool pbias_enabled;
185 void __iomem *base;
186 int vqmmc_enabled;
187 resource_size_t mapbase;
188 spinlock_t irq_lock; /* Prevent races with irq handler */
189 unsigned int dma_len;
190 unsigned int dma_sg_idx;
191 unsigned char bus_mode;
192 unsigned char power_mode;
193 int suspended;
194 u32 con;
195 u32 hctl;
196 u32 sysctl;
197 u32 capa;
198 int irq;
199 int wake_irq;
200 int use_dma, dma_ch;
201 struct dma_chan *tx_chan;
202 struct dma_chan *rx_chan;
203 int response_busy;
204 int context_loss;
205 int protect_card;
206 int reqs_blocked;
207 int req_in_progress;
208 unsigned long clk_rate;
209 unsigned int flags;
210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
212 struct omap_hsmmc_next next_data;
213 struct omap_hsmmc_platform_data *pdata;
214
215 /* return MMC cover switch state, can be NULL if not supported.
216 *
217 * possible return values:
218 * 0 - closed
219 * 1 - open
220 */
221 int (*get_cover_state)(struct device *dev);
222
223 int (*card_detect)(struct device *dev);
224 };
225
226 struct omap_mmc_of_data {
227 u32 reg_offset;
228 u8 controller_flags;
229 };
230
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
232
233 static int omap_hsmmc_card_detect(struct device *dev)
234 {
235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
236
237 return mmc_gpio_get_cd(host->mmc);
238 }
239
240 static int omap_hsmmc_get_cover_state(struct device *dev)
241 {
242 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
243
244 return mmc_gpio_get_cd(host->mmc);
245 }
246
247 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
248 {
249 int ret;
250 struct omap_hsmmc_host *host = mmc_priv(mmc);
251 struct mmc_ios *ios = &mmc->ios;
252
253 if (mmc->supply.vmmc) {
254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
255 if (ret)
256 return ret;
257 }
258
259 /* Enable interface voltage rail, if needed */
260 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
261 ret = regulator_enable(mmc->supply.vqmmc);
262 if (ret) {
263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
264 goto err_vqmmc;
265 }
266 host->vqmmc_enabled = 1;
267 }
268
269 return 0;
270
271 err_vqmmc:
272 if (mmc->supply.vmmc)
273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
274
275 return ret;
276 }
277
278 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
279 {
280 int ret;
281 int status;
282 struct omap_hsmmc_host *host = mmc_priv(mmc);
283
284 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
285 ret = regulator_disable(mmc->supply.vqmmc);
286 if (ret) {
287 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
288 return ret;
289 }
290 host->vqmmc_enabled = 0;
291 }
292
293 if (mmc->supply.vmmc) {
294 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
295 if (ret)
296 goto err_set_ocr;
297 }
298
299 return 0;
300
301 err_set_ocr:
302 if (mmc->supply.vqmmc) {
303 status = regulator_enable(mmc->supply.vqmmc);
304 if (status)
305 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
306 }
307
308 return ret;
309 }
310
311 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
312 int vdd)
313 {
314 int ret;
315
316 if (!host->pbias)
317 return 0;
318
319 if (power_on) {
320 if (vdd <= VDD_165_195)
321 ret = regulator_set_voltage(host->pbias, VDD_1V8,
322 VDD_1V8);
323 else
324 ret = regulator_set_voltage(host->pbias, VDD_3V0,
325 VDD_3V0);
326 if (ret < 0) {
327 dev_err(host->dev, "pbias set voltage fail\n");
328 return ret;
329 }
330
331 if (host->pbias_enabled == 0) {
332 ret = regulator_enable(host->pbias);
333 if (ret) {
334 dev_err(host->dev, "pbias reg enable fail\n");
335 return ret;
336 }
337 host->pbias_enabled = 1;
338 }
339 } else {
340 if (host->pbias_enabled == 1) {
341 ret = regulator_disable(host->pbias);
342 if (ret) {
343 dev_err(host->dev, "pbias reg disable fail\n");
344 return ret;
345 }
346 host->pbias_enabled = 0;
347 }
348 }
349
350 return 0;
351 }
352
353 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,
354 int vdd)
355 {
356 struct mmc_host *mmc = host->mmc;
357 int ret = 0;
358
359 if (mmc_pdata(host)->set_power)
360 return mmc_pdata(host)->set_power(host->dev, power_on, vdd);
361
362 /*
363 * If we don't see a Vcc regulator, assume it's a fixed
364 * voltage always-on regulator.
365 */
366 if (!mmc->supply.vmmc)
367 return 0;
368
369 if (mmc_pdata(host)->before_set_reg)
370 mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd);
371
372 ret = omap_hsmmc_set_pbias(host, false, 0);
373 if (ret)
374 return ret;
375
376 /*
377 * Assume Vcc regulator is used only to power the card ... OMAP
378 * VDDS is used to power the pins, optionally with a transceiver to
379 * support cards using voltages other than VDDS (1.8V nominal). When a
380 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
381 *
382 * In some cases this regulator won't support enable/disable;
383 * e.g. it's a fixed rail for a WLAN chip.
384 *
385 * In other cases vcc_aux switches interface power. Example, for
386 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
387 * chips/cards need an interface voltage rail too.
388 */
389 if (power_on) {
390 ret = omap_hsmmc_enable_supply(mmc);
391 if (ret)
392 return ret;
393
394 ret = omap_hsmmc_set_pbias(host, true, vdd);
395 if (ret)
396 goto err_set_voltage;
397 } else {
398 ret = omap_hsmmc_disable_supply(mmc);
399 if (ret)
400 return ret;
401 }
402
403 if (mmc_pdata(host)->after_set_reg)
404 mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd);
405
406 return 0;
407
408 err_set_voltage:
409 omap_hsmmc_disable_supply(mmc);
410
411 return ret;
412 }
413
414 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
415 {
416 int ret;
417
418 if (!reg)
419 return 0;
420
421 if (regulator_is_enabled(reg)) {
422 ret = regulator_enable(reg);
423 if (ret)
424 return ret;
425
426 ret = regulator_disable(reg);
427 if (ret)
428 return ret;
429 }
430
431 return 0;
432 }
433
434 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
435 {
436 struct mmc_host *mmc = host->mmc;
437 int ret;
438
439 /*
440 * disable regulators enabled during boot and get the usecount
441 * right so that regulators can be enabled/disabled by checking
442 * the return value of regulator_is_enabled
443 */
444 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
445 if (ret) {
446 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
447 return ret;
448 }
449
450 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
451 if (ret) {
452 dev_err(host->dev,
453 "fail to disable boot enabled vmmc_aux reg\n");
454 return ret;
455 }
456
457 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
458 if (ret) {
459 dev_err(host->dev,
460 "failed to disable boot enabled pbias reg\n");
461 return ret;
462 }
463
464 return 0;
465 }
466
467 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
468 {
469 int ocr_value = 0;
470 int ret;
471 struct mmc_host *mmc = host->mmc;
472
473 if (mmc_pdata(host)->set_power)
474 return 0;
475
476 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
477 if (IS_ERR(mmc->supply.vmmc)) {
478 ret = PTR_ERR(mmc->supply.vmmc);
479 if ((ret != -ENODEV) && host->dev->of_node)
480 return ret;
481 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
482 PTR_ERR(mmc->supply.vmmc));
483 mmc->supply.vmmc = NULL;
484 } else {
485 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
486 if (ocr_value > 0)
487 mmc_pdata(host)->ocr_mask = ocr_value;
488 }
489
490 /* Allow an aux regulator */
491 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
492 if (IS_ERR(mmc->supply.vqmmc)) {
493 ret = PTR_ERR(mmc->supply.vqmmc);
494 if ((ret != -ENODEV) && host->dev->of_node)
495 return ret;
496 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
497 PTR_ERR(mmc->supply.vqmmc));
498 mmc->supply.vqmmc = NULL;
499 }
500
501 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
502 if (IS_ERR(host->pbias)) {
503 ret = PTR_ERR(host->pbias);
504 if ((ret != -ENODEV) && host->dev->of_node) {
505 dev_err(host->dev,
506 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
507 return ret;
508 }
509 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
510 PTR_ERR(host->pbias));
511 host->pbias = NULL;
512 }
513
514 /* For eMMC do not power off when not in sleep state */
515 if (mmc_pdata(host)->no_regulator_off_init)
516 return 0;
517
518 ret = omap_hsmmc_disable_boot_regulators(host);
519 if (ret)
520 return ret;
521
522 return 0;
523 }
524
525 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
526
527 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
528 struct omap_hsmmc_host *host,
529 struct omap_hsmmc_platform_data *pdata)
530 {
531 int ret;
532
533 if (gpio_is_valid(pdata->gpio_cod)) {
534 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
535 if (ret)
536 return ret;
537
538 host->get_cover_state = omap_hsmmc_get_cover_state;
539 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
540 } else if (gpio_is_valid(pdata->gpio_cd)) {
541 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
542 if (ret)
543 return ret;
544
545 host->card_detect = omap_hsmmc_card_detect;
546 }
547
548 if (gpio_is_valid(pdata->gpio_wp)) {
549 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
550 if (ret)
551 return ret;
552 }
553
554 return 0;
555 }
556
557 /*
558 * Start clock to the card
559 */
560 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
561 {
562 OMAP_HSMMC_WRITE(host->base, SYSCTL,
563 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
564 }
565
566 /*
567 * Stop clock to the card
568 */
569 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
570 {
571 OMAP_HSMMC_WRITE(host->base, SYSCTL,
572 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
573 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
574 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
575 }
576
577 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
578 struct mmc_command *cmd)
579 {
580 u32 irq_mask = INT_EN_MASK;
581 unsigned long flags;
582
583 if (host->use_dma)
584 irq_mask &= ~(BRR_EN | BWR_EN);
585
586 /* Disable timeout for erases */
587 if (cmd->opcode == MMC_ERASE)
588 irq_mask &= ~DTO_EN;
589
590 spin_lock_irqsave(&host->irq_lock, flags);
591 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
592 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
593
594 /* latch pending CIRQ, but don't signal MMC core */
595 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
596 irq_mask |= CIRQ_EN;
597 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
598 spin_unlock_irqrestore(&host->irq_lock, flags);
599 }
600
601 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
602 {
603 u32 irq_mask = 0;
604 unsigned long flags;
605
606 spin_lock_irqsave(&host->irq_lock, flags);
607 /* no transfer running but need to keep cirq if enabled */
608 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
609 irq_mask |= CIRQ_EN;
610 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
611 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
612 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
613 spin_unlock_irqrestore(&host->irq_lock, flags);
614 }
615
616 /* Calculate divisor for the given clock frequency */
617 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
618 {
619 u16 dsor = 0;
620
621 if (ios->clock) {
622 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
623 if (dsor > CLKD_MAX)
624 dsor = CLKD_MAX;
625 }
626
627 return dsor;
628 }
629
630 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
631 {
632 struct mmc_ios *ios = &host->mmc->ios;
633 unsigned long regval;
634 unsigned long timeout;
635 unsigned long clkdiv;
636
637 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
638
639 omap_hsmmc_stop_clock(host);
640
641 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
642 regval = regval & ~(CLKD_MASK | DTO_MASK);
643 clkdiv = calc_divisor(host, ios);
644 regval = regval | (clkdiv << 6) | (DTO << 16);
645 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
646 OMAP_HSMMC_WRITE(host->base, SYSCTL,
647 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
648
649 /* Wait till the ICS bit is set */
650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
651 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
652 && time_before(jiffies, timeout))
653 cpu_relax();
654
655 /*
656 * Enable High-Speed Support
657 * Pre-Requisites
658 * - Controller should support High-Speed-Enable Bit
659 * - Controller should not be using DDR Mode
660 * - Controller should advertise that it supports High Speed
661 * in capabilities register
662 * - MMC/SD clock coming out of controller > 25MHz
663 */
664 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
665 (ios->timing != MMC_TIMING_MMC_DDR52) &&
666 (ios->timing != MMC_TIMING_UHS_DDR50) &&
667 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
668 regval = OMAP_HSMMC_READ(host->base, HCTL);
669 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
670 regval |= HSPE;
671 else
672 regval &= ~HSPE;
673
674 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
675 }
676
677 omap_hsmmc_start_clock(host);
678 }
679
680 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
681 {
682 struct mmc_ios *ios = &host->mmc->ios;
683 u32 con;
684
685 con = OMAP_HSMMC_READ(host->base, CON);
686 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
687 ios->timing == MMC_TIMING_UHS_DDR50)
688 con |= DDR; /* configure in DDR mode */
689 else
690 con &= ~DDR;
691 switch (ios->bus_width) {
692 case MMC_BUS_WIDTH_8:
693 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
694 break;
695 case MMC_BUS_WIDTH_4:
696 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
697 OMAP_HSMMC_WRITE(host->base, HCTL,
698 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
699 break;
700 case MMC_BUS_WIDTH_1:
701 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
702 OMAP_HSMMC_WRITE(host->base, HCTL,
703 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
704 break;
705 }
706 }
707
708 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
709 {
710 struct mmc_ios *ios = &host->mmc->ios;
711 u32 con;
712
713 con = OMAP_HSMMC_READ(host->base, CON);
714 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
715 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
716 else
717 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
718 }
719
720 #ifdef CONFIG_PM
721
722 /*
723 * Restore the MMC host context, if it was lost as result of a
724 * power state change.
725 */
726 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
727 {
728 struct mmc_ios *ios = &host->mmc->ios;
729 u32 hctl, capa;
730 unsigned long timeout;
731
732 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
733 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
734 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
735 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
736 return 0;
737
738 host->context_loss++;
739
740 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
741 if (host->power_mode != MMC_POWER_OFF &&
742 (1 << ios->vdd) <= MMC_VDD_23_24)
743 hctl = SDVS18;
744 else
745 hctl = SDVS30;
746 capa = VS30 | VS18;
747 } else {
748 hctl = SDVS18;
749 capa = VS18;
750 }
751
752 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
753 hctl |= IWE;
754
755 OMAP_HSMMC_WRITE(host->base, HCTL,
756 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
757
758 OMAP_HSMMC_WRITE(host->base, CAPA,
759 OMAP_HSMMC_READ(host->base, CAPA) | capa);
760
761 OMAP_HSMMC_WRITE(host->base, HCTL,
762 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
763
764 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
765 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
766 && time_before(jiffies, timeout))
767 ;
768
769 OMAP_HSMMC_WRITE(host->base, ISE, 0);
770 OMAP_HSMMC_WRITE(host->base, IE, 0);
771 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
772
773 /* Do not initialize card-specific things if the power is off */
774 if (host->power_mode == MMC_POWER_OFF)
775 goto out;
776
777 omap_hsmmc_set_bus_width(host);
778
779 omap_hsmmc_set_clock(host);
780
781 omap_hsmmc_set_bus_mode(host);
782
783 out:
784 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
785 host->context_loss);
786 return 0;
787 }
788
789 /*
790 * Save the MMC host context (store the number of power state changes so far).
791 */
792 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
793 {
794 host->con = OMAP_HSMMC_READ(host->base, CON);
795 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
796 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
797 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
798 }
799
800 #else
801
802 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
803 {
804 return 0;
805 }
806
807 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
808 {
809 }
810
811 #endif
812
813 /*
814 * Send init stream sequence to card
815 * before sending IDLE command
816 */
817 static void send_init_stream(struct omap_hsmmc_host *host)
818 {
819 int reg = 0;
820 unsigned long timeout;
821
822 if (host->protect_card)
823 return;
824
825 disable_irq(host->irq);
826
827 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
828 OMAP_HSMMC_WRITE(host->base, CON,
829 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
830 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
831
832 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
833 while ((reg != CC_EN) && time_before(jiffies, timeout))
834 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
835
836 OMAP_HSMMC_WRITE(host->base, CON,
837 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
838
839 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
840 OMAP_HSMMC_READ(host->base, STAT);
841
842 enable_irq(host->irq);
843 }
844
845 static inline
846 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
847 {
848 int r = 1;
849
850 if (host->get_cover_state)
851 r = host->get_cover_state(host->dev);
852 return r;
853 }
854
855 static ssize_t
856 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
857 char *buf)
858 {
859 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
860 struct omap_hsmmc_host *host = mmc_priv(mmc);
861
862 return sprintf(buf, "%s\n",
863 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
864 }
865
866 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
867
868 static ssize_t
869 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
870 char *buf)
871 {
872 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
873 struct omap_hsmmc_host *host = mmc_priv(mmc);
874
875 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
876 }
877
878 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
879
880 /*
881 * Configure the response type and send the cmd.
882 */
883 static void
884 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
885 struct mmc_data *data)
886 {
887 int cmdreg = 0, resptype = 0, cmdtype = 0;
888
889 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
890 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
891 host->cmd = cmd;
892
893 omap_hsmmc_enable_irq(host, cmd);
894
895 host->response_busy = 0;
896 if (cmd->flags & MMC_RSP_PRESENT) {
897 if (cmd->flags & MMC_RSP_136)
898 resptype = 1;
899 else if (cmd->flags & MMC_RSP_BUSY) {
900 resptype = 3;
901 host->response_busy = 1;
902 } else
903 resptype = 2;
904 }
905
906 /*
907 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
908 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
909 * a val of 0x3, rest 0x0.
910 */
911 if (cmd == host->mrq->stop)
912 cmdtype = 0x3;
913
914 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
915
916 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
917 host->mrq->sbc) {
918 cmdreg |= ACEN_ACMD23;
919 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
920 }
921 if (data) {
922 cmdreg |= DP_SELECT | MSBS | BCE;
923 if (data->flags & MMC_DATA_READ)
924 cmdreg |= DDIR;
925 else
926 cmdreg &= ~(DDIR);
927 }
928
929 if (host->use_dma)
930 cmdreg |= DMAE;
931
932 host->req_in_progress = 1;
933
934 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
935 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
936 }
937
938 static int
939 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
940 {
941 if (data->flags & MMC_DATA_WRITE)
942 return DMA_TO_DEVICE;
943 else
944 return DMA_FROM_DEVICE;
945 }
946
947 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
948 struct mmc_data *data)
949 {
950 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
951 }
952
953 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
954 {
955 int dma_ch;
956 unsigned long flags;
957
958 spin_lock_irqsave(&host->irq_lock, flags);
959 host->req_in_progress = 0;
960 dma_ch = host->dma_ch;
961 spin_unlock_irqrestore(&host->irq_lock, flags);
962
963 omap_hsmmc_disable_irq(host);
964 /* Do not complete the request if DMA is still in progress */
965 if (mrq->data && host->use_dma && dma_ch != -1)
966 return;
967 host->mrq = NULL;
968 mmc_request_done(host->mmc, mrq);
969 }
970
971 /*
972 * Notify the transfer complete to MMC core
973 */
974 static void
975 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
976 {
977 if (!data) {
978 struct mmc_request *mrq = host->mrq;
979
980 /* TC before CC from CMD6 - don't know why, but it happens */
981 if (host->cmd && host->cmd->opcode == 6 &&
982 host->response_busy) {
983 host->response_busy = 0;
984 return;
985 }
986
987 omap_hsmmc_request_done(host, mrq);
988 return;
989 }
990
991 host->data = NULL;
992
993 if (!data->error)
994 data->bytes_xfered += data->blocks * (data->blksz);
995 else
996 data->bytes_xfered = 0;
997
998 if (data->stop && (data->error || !host->mrq->sbc))
999 omap_hsmmc_start_command(host, data->stop, NULL);
1000 else
1001 omap_hsmmc_request_done(host, data->mrq);
1002 }
1003
1004 /*
1005 * Notify the core about command completion
1006 */
1007 static void
1008 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1009 {
1010 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
1011 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
1012 host->cmd = NULL;
1013 omap_hsmmc_start_dma_transfer(host);
1014 omap_hsmmc_start_command(host, host->mrq->cmd,
1015 host->mrq->data);
1016 return;
1017 }
1018
1019 host->cmd = NULL;
1020
1021 if (cmd->flags & MMC_RSP_PRESENT) {
1022 if (cmd->flags & MMC_RSP_136) {
1023 /* response type 2 */
1024 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1025 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1026 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1027 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1028 } else {
1029 /* response types 1, 1b, 3, 4, 5, 6 */
1030 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1031 }
1032 }
1033 if ((host->data == NULL && !host->response_busy) || cmd->error)
1034 omap_hsmmc_request_done(host, host->mrq);
1035 }
1036
1037 /*
1038 * DMA clean up for command errors
1039 */
1040 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1041 {
1042 int dma_ch;
1043 unsigned long flags;
1044
1045 host->data->error = errno;
1046
1047 spin_lock_irqsave(&host->irq_lock, flags);
1048 dma_ch = host->dma_ch;
1049 host->dma_ch = -1;
1050 spin_unlock_irqrestore(&host->irq_lock, flags);
1051
1052 if (host->use_dma && dma_ch != -1) {
1053 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1054
1055 dmaengine_terminate_all(chan);
1056 dma_unmap_sg(chan->device->dev,
1057 host->data->sg, host->data->sg_len,
1058 omap_hsmmc_get_dma_dir(host, host->data));
1059
1060 host->data->host_cookie = 0;
1061 }
1062 host->data = NULL;
1063 }
1064
1065 /*
1066 * Readable error output
1067 */
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1070 {
1071 /* --- means reserved bit without definition at documentation */
1072 static const char *omap_hsmmc_status_bits[] = {
1073 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1077 };
1078 char res[256];
1079 char *buf = res;
1080 int len, i;
1081
1082 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1083 buf += len;
1084
1085 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086 if (status & (1 << i)) {
1087 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1088 buf += len;
1089 }
1090
1091 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1092 }
1093 #else
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1095 u32 status)
1096 {
1097 }
1098 #endif /* CONFIG_MMC_DEBUG */
1099
1100 /*
1101 * MMC controller internal state machines reset
1102 *
1103 * Used to reset command or data internal state machines, using respectively
1104 * SRC or SRD bit of SYSCTL register
1105 * Can be called from interrupt context
1106 */
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1108 unsigned long bit)
1109 {
1110 unsigned long i = 0;
1111 unsigned long limit = MMC_TIMEOUT_US;
1112
1113 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1114 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1115
1116 /*
1117 * OMAP4 ES2 and greater has an updated reset logic.
1118 * Monitor a 0->1 transition first
1119 */
1120 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1121 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1122 && (i++ < limit))
1123 udelay(1);
1124 }
1125 i = 0;
1126
1127 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1128 (i++ < limit))
1129 udelay(1);
1130
1131 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1132 dev_err(mmc_dev(host->mmc),
1133 "Timeout waiting on controller reset in %s\n",
1134 __func__);
1135 }
1136
1137 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1138 int err, int end_cmd)
1139 {
1140 if (end_cmd) {
1141 omap_hsmmc_reset_controller_fsm(host, SRC);
1142 if (host->cmd)
1143 host->cmd->error = err;
1144 }
1145
1146 if (host->data) {
1147 omap_hsmmc_reset_controller_fsm(host, SRD);
1148 omap_hsmmc_dma_cleanup(host, err);
1149 } else if (host->mrq && host->mrq->cmd)
1150 host->mrq->cmd->error = err;
1151 }
1152
1153 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1154 {
1155 struct mmc_data *data;
1156 int end_cmd = 0, end_trans = 0;
1157 int error = 0;
1158
1159 data = host->data;
1160 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1161
1162 if (status & ERR_EN) {
1163 omap_hsmmc_dbg_report_irq(host, status);
1164
1165 if (status & (CTO_EN | CCRC_EN))
1166 end_cmd = 1;
1167 if (host->data || host->response_busy) {
1168 end_trans = !end_cmd;
1169 host->response_busy = 0;
1170 }
1171 if (status & (CTO_EN | DTO_EN))
1172 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1173 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1174 BADA_EN))
1175 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1176
1177 if (status & ACE_EN) {
1178 u32 ac12;
1179 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1180 if (!(ac12 & ACNE) && host->mrq->sbc) {
1181 end_cmd = 1;
1182 if (ac12 & ACTO)
1183 error = -ETIMEDOUT;
1184 else if (ac12 & (ACCE | ACEB | ACIE))
1185 error = -EILSEQ;
1186 host->mrq->sbc->error = error;
1187 hsmmc_command_incomplete(host, error, end_cmd);
1188 }
1189 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1190 }
1191 }
1192
1193 OMAP_HSMMC_WRITE(host->base, STAT, status);
1194 if (end_cmd || ((status & CC_EN) && host->cmd))
1195 omap_hsmmc_cmd_done(host, host->cmd);
1196 if ((end_trans || (status & TC_EN)) && host->mrq)
1197 omap_hsmmc_xfer_done(host, data);
1198 }
1199
1200 /*
1201 * MMC controller IRQ handler
1202 */
1203 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1204 {
1205 struct omap_hsmmc_host *host = dev_id;
1206 int status;
1207
1208 status = OMAP_HSMMC_READ(host->base, STAT);
1209 while (status & (INT_EN_MASK | CIRQ_EN)) {
1210 if (host->req_in_progress)
1211 omap_hsmmc_do_irq(host, status);
1212
1213 if (status & CIRQ_EN)
1214 mmc_signal_sdio_irq(host->mmc);
1215
1216 /* Flush posted write */
1217 status = OMAP_HSMMC_READ(host->base, STAT);
1218 }
1219
1220 return IRQ_HANDLED;
1221 }
1222
1223 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1224 {
1225 unsigned long i;
1226
1227 OMAP_HSMMC_WRITE(host->base, HCTL,
1228 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1229 for (i = 0; i < loops_per_jiffy; i++) {
1230 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1231 break;
1232 cpu_relax();
1233 }
1234 }
1235
1236 /*
1237 * Switch MMC interface voltage ... only relevant for MMC1.
1238 *
1239 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1240 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1241 * Some chips, like eMMC ones, use internal transceivers.
1242 */
1243 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1244 {
1245 u32 reg_val = 0;
1246 int ret;
1247
1248 /* Disable the clocks */
1249 if (host->dbclk)
1250 clk_disable_unprepare(host->dbclk);
1251
1252 /* Turn the power off */
1253 ret = omap_hsmmc_set_power(host, 0, 0);
1254
1255 /* Turn the power ON with given VDD 1.8 or 3.0v */
1256 if (!ret)
1257 ret = omap_hsmmc_set_power(host, 1, vdd);
1258 if (host->dbclk)
1259 clk_prepare_enable(host->dbclk);
1260
1261 if (ret != 0)
1262 goto err;
1263
1264 OMAP_HSMMC_WRITE(host->base, HCTL,
1265 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1266 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1267
1268 /*
1269 * If a MMC dual voltage card is detected, the set_ios fn calls
1270 * this fn with VDD bit set for 1.8V. Upon card removal from the
1271 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1272 *
1273 * Cope with a bit of slop in the range ... per data sheets:
1274 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1275 * but recommended values are 1.71V to 1.89V
1276 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1277 * but recommended values are 2.7V to 3.3V
1278 *
1279 * Board setup code shouldn't permit anything very out-of-range.
1280 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1281 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1282 */
1283 if ((1 << vdd) <= MMC_VDD_23_24)
1284 reg_val |= SDVS18;
1285 else
1286 reg_val |= SDVS30;
1287
1288 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1289 set_sd_bus_power(host);
1290
1291 return 0;
1292 err:
1293 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1294 return ret;
1295 }
1296
1297 /* Protect the card while the cover is open */
1298 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1299 {
1300 if (!host->get_cover_state)
1301 return;
1302
1303 host->reqs_blocked = 0;
1304 if (host->get_cover_state(host->dev)) {
1305 if (host->protect_card) {
1306 dev_info(host->dev, "%s: cover is closed, "
1307 "card is now accessible\n",
1308 mmc_hostname(host->mmc));
1309 host->protect_card = 0;
1310 }
1311 } else {
1312 if (!host->protect_card) {
1313 dev_info(host->dev, "%s: cover is open, "
1314 "card is now inaccessible\n",
1315 mmc_hostname(host->mmc));
1316 host->protect_card = 1;
1317 }
1318 }
1319 }
1320
1321 /*
1322 * irq handler when (cell-phone) cover is mounted/removed
1323 */
1324 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1325 {
1326 struct omap_hsmmc_host *host = dev_id;
1327
1328 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1329
1330 omap_hsmmc_protect_card(host);
1331 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1332 return IRQ_HANDLED;
1333 }
1334
1335 static void omap_hsmmc_dma_callback(void *param)
1336 {
1337 struct omap_hsmmc_host *host = param;
1338 struct dma_chan *chan;
1339 struct mmc_data *data;
1340 int req_in_progress;
1341
1342 spin_lock_irq(&host->irq_lock);
1343 if (host->dma_ch < 0) {
1344 spin_unlock_irq(&host->irq_lock);
1345 return;
1346 }
1347
1348 data = host->mrq->data;
1349 chan = omap_hsmmc_get_dma_chan(host, data);
1350 if (!data->host_cookie)
1351 dma_unmap_sg(chan->device->dev,
1352 data->sg, data->sg_len,
1353 omap_hsmmc_get_dma_dir(host, data));
1354
1355 req_in_progress = host->req_in_progress;
1356 host->dma_ch = -1;
1357 spin_unlock_irq(&host->irq_lock);
1358
1359 /* If DMA has finished after TC, complete the request */
1360 if (!req_in_progress) {
1361 struct mmc_request *mrq = host->mrq;
1362
1363 host->mrq = NULL;
1364 mmc_request_done(host->mmc, mrq);
1365 }
1366 }
1367
1368 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1369 struct mmc_data *data,
1370 struct omap_hsmmc_next *next,
1371 struct dma_chan *chan)
1372 {
1373 int dma_len;
1374
1375 if (!next && data->host_cookie &&
1376 data->host_cookie != host->next_data.cookie) {
1377 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1378 " host->next_data.cookie %d\n",
1379 __func__, data->host_cookie, host->next_data.cookie);
1380 data->host_cookie = 0;
1381 }
1382
1383 /* Check if next job is already prepared */
1384 if (next || data->host_cookie != host->next_data.cookie) {
1385 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1386 omap_hsmmc_get_dma_dir(host, data));
1387
1388 } else {
1389 dma_len = host->next_data.dma_len;
1390 host->next_data.dma_len = 0;
1391 }
1392
1393
1394 if (dma_len == 0)
1395 return -EINVAL;
1396
1397 if (next) {
1398 next->dma_len = dma_len;
1399 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1400 } else
1401 host->dma_len = dma_len;
1402
1403 return 0;
1404 }
1405
1406 /*
1407 * Routine to configure and start DMA for the MMC card
1408 */
1409 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1410 struct mmc_request *req)
1411 {
1412 struct dma_async_tx_descriptor *tx;
1413 int ret = 0, i;
1414 struct mmc_data *data = req->data;
1415 struct dma_chan *chan;
1416 struct dma_slave_config cfg = {
1417 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1418 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1419 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1420 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1421 .src_maxburst = data->blksz / 4,
1422 .dst_maxburst = data->blksz / 4,
1423 };
1424
1425 /* Sanity check: all the SG entries must be aligned by block size. */
1426 for (i = 0; i < data->sg_len; i++) {
1427 struct scatterlist *sgl;
1428
1429 sgl = data->sg + i;
1430 if (sgl->length % data->blksz)
1431 return -EINVAL;
1432 }
1433 if ((data->blksz % 4) != 0)
1434 /* REVISIT: The MMC buffer increments only when MSB is written.
1435 * Return error for blksz which is non multiple of four.
1436 */
1437 return -EINVAL;
1438
1439 BUG_ON(host->dma_ch != -1);
1440
1441 chan = omap_hsmmc_get_dma_chan(host, data);
1442
1443 ret = dmaengine_slave_config(chan, &cfg);
1444 if (ret)
1445 return ret;
1446
1447 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1448 if (ret)
1449 return ret;
1450
1451 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1452 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1454 if (!tx) {
1455 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1456 /* FIXME: cleanup */
1457 return -1;
1458 }
1459
1460 tx->callback = omap_hsmmc_dma_callback;
1461 tx->callback_param = host;
1462
1463 /* Does not fail */
1464 dmaengine_submit(tx);
1465
1466 host->dma_ch = 1;
1467
1468 return 0;
1469 }
1470
1471 static void set_data_timeout(struct omap_hsmmc_host *host,
1472 unsigned int timeout_ns,
1473 unsigned int timeout_clks)
1474 {
1475 unsigned int timeout, cycle_ns;
1476 uint32_t reg, clkd, dto = 0;
1477
1478 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1479 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1480 if (clkd == 0)
1481 clkd = 1;
1482
1483 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1484 timeout = timeout_ns / cycle_ns;
1485 timeout += timeout_clks;
1486 if (timeout) {
1487 while ((timeout & 0x80000000) == 0) {
1488 dto += 1;
1489 timeout <<= 1;
1490 }
1491 dto = 31 - dto;
1492 timeout <<= 1;
1493 if (timeout && dto)
1494 dto += 1;
1495 if (dto >= 13)
1496 dto -= 13;
1497 else
1498 dto = 0;
1499 if (dto > 14)
1500 dto = 14;
1501 }
1502
1503 reg &= ~DTO_MASK;
1504 reg |= dto << DTO_SHIFT;
1505 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1506 }
1507
1508 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1509 {
1510 struct mmc_request *req = host->mrq;
1511 struct dma_chan *chan;
1512
1513 if (!req->data)
1514 return;
1515 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1516 | (req->data->blocks << 16));
1517 set_data_timeout(host, req->data->timeout_ns,
1518 req->data->timeout_clks);
1519 chan = omap_hsmmc_get_dma_chan(host, req->data);
1520 dma_async_issue_pending(chan);
1521 }
1522
1523 /*
1524 * Configure block length for MMC/SD cards and initiate the transfer.
1525 */
1526 static int
1527 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1528 {
1529 int ret;
1530 host->data = req->data;
1531
1532 if (req->data == NULL) {
1533 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1534 /*
1535 * Set an arbitrary 100ms data timeout for commands with
1536 * busy signal.
1537 */
1538 if (req->cmd->flags & MMC_RSP_BUSY)
1539 set_data_timeout(host, 100000000U, 0);
1540 return 0;
1541 }
1542
1543 if (host->use_dma) {
1544 ret = omap_hsmmc_setup_dma_transfer(host, req);
1545 if (ret != 0) {
1546 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1547 return ret;
1548 }
1549 }
1550 return 0;
1551 }
1552
1553 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1554 int err)
1555 {
1556 struct omap_hsmmc_host *host = mmc_priv(mmc);
1557 struct mmc_data *data = mrq->data;
1558
1559 if (host->use_dma && data->host_cookie) {
1560 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1561
1562 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1563 omap_hsmmc_get_dma_dir(host, data));
1564 data->host_cookie = 0;
1565 }
1566 }
1567
1568 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1569 {
1570 struct omap_hsmmc_host *host = mmc_priv(mmc);
1571
1572 if (mrq->data->host_cookie) {
1573 mrq->data->host_cookie = 0;
1574 return ;
1575 }
1576
1577 if (host->use_dma) {
1578 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1579
1580 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1581 &host->next_data, c))
1582 mrq->data->host_cookie = 0;
1583 }
1584 }
1585
1586 /*
1587 * Request function. for read/write operation
1588 */
1589 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1590 {
1591 struct omap_hsmmc_host *host = mmc_priv(mmc);
1592 int err;
1593
1594 BUG_ON(host->req_in_progress);
1595 BUG_ON(host->dma_ch != -1);
1596 if (host->protect_card) {
1597 if (host->reqs_blocked < 3) {
1598 /*
1599 * Ensure the controller is left in a consistent
1600 * state by resetting the command and data state
1601 * machines.
1602 */
1603 omap_hsmmc_reset_controller_fsm(host, SRD);
1604 omap_hsmmc_reset_controller_fsm(host, SRC);
1605 host->reqs_blocked += 1;
1606 }
1607 req->cmd->error = -EBADF;
1608 if (req->data)
1609 req->data->error = -EBADF;
1610 req->cmd->retries = 0;
1611 mmc_request_done(mmc, req);
1612 return;
1613 } else if (host->reqs_blocked)
1614 host->reqs_blocked = 0;
1615 WARN_ON(host->mrq != NULL);
1616 host->mrq = req;
1617 host->clk_rate = clk_get_rate(host->fclk);
1618 err = omap_hsmmc_prepare_data(host, req);
1619 if (err) {
1620 req->cmd->error = err;
1621 if (req->data)
1622 req->data->error = err;
1623 host->mrq = NULL;
1624 mmc_request_done(mmc, req);
1625 return;
1626 }
1627 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1628 omap_hsmmc_start_command(host, req->sbc, NULL);
1629 return;
1630 }
1631
1632 omap_hsmmc_start_dma_transfer(host);
1633 omap_hsmmc_start_command(host, req->cmd, req->data);
1634 }
1635
1636 /* Routine to configure clock values. Exposed API to core */
1637 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1638 {
1639 struct omap_hsmmc_host *host = mmc_priv(mmc);
1640 int do_send_init_stream = 0;
1641
1642 if (ios->power_mode != host->power_mode) {
1643 switch (ios->power_mode) {
1644 case MMC_POWER_OFF:
1645 omap_hsmmc_set_power(host, 0, 0);
1646 break;
1647 case MMC_POWER_UP:
1648 omap_hsmmc_set_power(host, 1, ios->vdd);
1649 break;
1650 case MMC_POWER_ON:
1651 do_send_init_stream = 1;
1652 break;
1653 }
1654 host->power_mode = ios->power_mode;
1655 }
1656
1657 /* FIXME: set registers based only on changes to ios */
1658
1659 omap_hsmmc_set_bus_width(host);
1660
1661 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1662 /* Only MMC1 can interface at 3V without some flavor
1663 * of external transceiver; but they all handle 1.8V.
1664 */
1665 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1666 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1667 /*
1668 * The mmc_select_voltage fn of the core does
1669 * not seem to set the power_mode to
1670 * MMC_POWER_UP upon recalculating the voltage.
1671 * vdd 1.8v.
1672 */
1673 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1674 dev_dbg(mmc_dev(host->mmc),
1675 "Switch operation failed\n");
1676 }
1677 }
1678
1679 omap_hsmmc_set_clock(host);
1680
1681 if (do_send_init_stream)
1682 send_init_stream(host);
1683
1684 omap_hsmmc_set_bus_mode(host);
1685 }
1686
1687 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1688 {
1689 struct omap_hsmmc_host *host = mmc_priv(mmc);
1690
1691 if (!host->card_detect)
1692 return -ENOSYS;
1693 return host->card_detect(host->dev);
1694 }
1695
1696 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1697 {
1698 struct omap_hsmmc_host *host = mmc_priv(mmc);
1699
1700 if (mmc_pdata(host)->init_card)
1701 mmc_pdata(host)->init_card(card);
1702 }
1703
1704 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1705 {
1706 struct omap_hsmmc_host *host = mmc_priv(mmc);
1707 u32 irq_mask, con;
1708 unsigned long flags;
1709
1710 spin_lock_irqsave(&host->irq_lock, flags);
1711
1712 con = OMAP_HSMMC_READ(host->base, CON);
1713 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1714 if (enable) {
1715 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1716 irq_mask |= CIRQ_EN;
1717 con |= CTPL | CLKEXTFREE;
1718 } else {
1719 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1720 irq_mask &= ~CIRQ_EN;
1721 con &= ~(CTPL | CLKEXTFREE);
1722 }
1723 OMAP_HSMMC_WRITE(host->base, CON, con);
1724 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1725
1726 /*
1727 * if enable, piggy back detection on current request
1728 * but always disable immediately
1729 */
1730 if (!host->req_in_progress || !enable)
1731 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1732
1733 /* flush posted write */
1734 OMAP_HSMMC_READ(host->base, IE);
1735
1736 spin_unlock_irqrestore(&host->irq_lock, flags);
1737 }
1738
1739 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1740 {
1741 int ret;
1742
1743 /*
1744 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1745 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1746 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1747 * with functional clock disabled.
1748 */
1749 if (!host->dev->of_node || !host->wake_irq)
1750 return -ENODEV;
1751
1752 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1753 if (ret) {
1754 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1755 goto err;
1756 }
1757
1758 /*
1759 * Some omaps don't have wake-up path from deeper idle states
1760 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1761 */
1762 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1763 struct pinctrl *p = devm_pinctrl_get(host->dev);
1764 if (!p) {
1765 ret = -ENODEV;
1766 goto err_free_irq;
1767 }
1768 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1769 dev_info(host->dev, "missing default pinctrl state\n");
1770 devm_pinctrl_put(p);
1771 ret = -EINVAL;
1772 goto err_free_irq;
1773 }
1774
1775 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1776 dev_info(host->dev, "missing idle pinctrl state\n");
1777 devm_pinctrl_put(p);
1778 ret = -EINVAL;
1779 goto err_free_irq;
1780 }
1781 devm_pinctrl_put(p);
1782 }
1783
1784 OMAP_HSMMC_WRITE(host->base, HCTL,
1785 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1786 return 0;
1787
1788 err_free_irq:
1789 dev_pm_clear_wake_irq(host->dev);
1790 err:
1791 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1792 host->wake_irq = 0;
1793 return ret;
1794 }
1795
1796 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1797 {
1798 u32 hctl, capa, value;
1799
1800 /* Only MMC1 supports 3.0V */
1801 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1802 hctl = SDVS30;
1803 capa = VS30 | VS18;
1804 } else {
1805 hctl = SDVS18;
1806 capa = VS18;
1807 }
1808
1809 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1810 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1811
1812 value = OMAP_HSMMC_READ(host->base, CAPA);
1813 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1814
1815 /* Set SD bus power bit */
1816 set_sd_bus_power(host);
1817 }
1818
1819 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1820 unsigned int direction, int blk_size)
1821 {
1822 /* This controller can't do multiblock reads due to hw bugs */
1823 if (direction == MMC_DATA_READ)
1824 return 1;
1825
1826 return blk_size;
1827 }
1828
1829 static struct mmc_host_ops omap_hsmmc_ops = {
1830 .post_req = omap_hsmmc_post_req,
1831 .pre_req = omap_hsmmc_pre_req,
1832 .request = omap_hsmmc_request,
1833 .set_ios = omap_hsmmc_set_ios,
1834 .get_cd = omap_hsmmc_get_cd,
1835 .get_ro = mmc_gpio_get_ro,
1836 .init_card = omap_hsmmc_init_card,
1837 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1838 };
1839
1840 #ifdef CONFIG_DEBUG_FS
1841
1842 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1843 {
1844 struct mmc_host *mmc = s->private;
1845 struct omap_hsmmc_host *host = mmc_priv(mmc);
1846
1847 seq_printf(s, "mmc%d:\n", mmc->index);
1848 seq_printf(s, "sdio irq mode\t%s\n",
1849 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1850
1851 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1852 seq_printf(s, "sdio irq \t%s\n",
1853 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1854 : "disabled");
1855 }
1856 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1857
1858 pm_runtime_get_sync(host->dev);
1859 seq_puts(s, "\nregs:\n");
1860 seq_printf(s, "CON:\t\t0x%08x\n",
1861 OMAP_HSMMC_READ(host->base, CON));
1862 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1863 OMAP_HSMMC_READ(host->base, PSTATE));
1864 seq_printf(s, "HCTL:\t\t0x%08x\n",
1865 OMAP_HSMMC_READ(host->base, HCTL));
1866 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1867 OMAP_HSMMC_READ(host->base, SYSCTL));
1868 seq_printf(s, "IE:\t\t0x%08x\n",
1869 OMAP_HSMMC_READ(host->base, IE));
1870 seq_printf(s, "ISE:\t\t0x%08x\n",
1871 OMAP_HSMMC_READ(host->base, ISE));
1872 seq_printf(s, "CAPA:\t\t0x%08x\n",
1873 OMAP_HSMMC_READ(host->base, CAPA));
1874
1875 pm_runtime_mark_last_busy(host->dev);
1876 pm_runtime_put_autosuspend(host->dev);
1877
1878 return 0;
1879 }
1880
1881 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1882 {
1883 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1884 }
1885
1886 static const struct file_operations mmc_regs_fops = {
1887 .open = omap_hsmmc_regs_open,
1888 .read = seq_read,
1889 .llseek = seq_lseek,
1890 .release = single_release,
1891 };
1892
1893 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1894 {
1895 if (mmc->debugfs_root)
1896 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1897 mmc, &mmc_regs_fops);
1898 }
1899
1900 #else
1901
1902 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1903 {
1904 }
1905
1906 #endif
1907
1908 #ifdef CONFIG_OF
1909 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1910 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1911 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1912 };
1913
1914 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1915 .reg_offset = 0x100,
1916 };
1917 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1918 .reg_offset = 0x100,
1919 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1920 };
1921
1922 static const struct of_device_id omap_mmc_of_match[] = {
1923 {
1924 .compatible = "ti,omap2-hsmmc",
1925 },
1926 {
1927 .compatible = "ti,omap3-pre-es3-hsmmc",
1928 .data = &omap3_pre_es3_mmc_of_data,
1929 },
1930 {
1931 .compatible = "ti,omap3-hsmmc",
1932 },
1933 {
1934 .compatible = "ti,omap4-hsmmc",
1935 .data = &omap4_mmc_of_data,
1936 },
1937 {
1938 .compatible = "ti,am33xx-hsmmc",
1939 .data = &am33xx_mmc_of_data,
1940 },
1941 {},
1942 };
1943 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1944
1945 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1946 {
1947 struct omap_hsmmc_platform_data *pdata, *legacy;
1948 struct device_node *np = dev->of_node;
1949
1950 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1951 if (!pdata)
1952 return ERR_PTR(-ENOMEM); /* out of memory */
1953
1954 legacy = dev_get_platdata(dev);
1955 if (legacy && legacy->name)
1956 pdata->name = legacy->name;
1957
1958 if (of_find_property(np, "ti,dual-volt", NULL))
1959 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1960
1961 pdata->gpio_cd = -EINVAL;
1962 pdata->gpio_cod = -EINVAL;
1963 pdata->gpio_wp = -EINVAL;
1964
1965 if (of_find_property(np, "ti,non-removable", NULL)) {
1966 pdata->nonremovable = true;
1967 pdata->no_regulator_off_init = true;
1968 }
1969
1970 if (of_find_property(np, "ti,needs-special-reset", NULL))
1971 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1972
1973 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1974 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1975
1976 return pdata;
1977 }
1978 #else
1979 static inline struct omap_hsmmc_platform_data
1980 *of_get_hsmmc_pdata(struct device *dev)
1981 {
1982 return ERR_PTR(-EINVAL);
1983 }
1984 #endif
1985
1986 static int omap_hsmmc_probe(struct platform_device *pdev)
1987 {
1988 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1989 struct mmc_host *mmc;
1990 struct omap_hsmmc_host *host = NULL;
1991 struct resource *res;
1992 int ret, irq;
1993 const struct of_device_id *match;
1994 const struct omap_mmc_of_data *data;
1995 void __iomem *base;
1996
1997 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1998 if (match) {
1999 pdata = of_get_hsmmc_pdata(&pdev->dev);
2000
2001 if (IS_ERR(pdata))
2002 return PTR_ERR(pdata);
2003
2004 if (match->data) {
2005 data = match->data;
2006 pdata->reg_offset = data->reg_offset;
2007 pdata->controller_flags |= data->controller_flags;
2008 }
2009 }
2010
2011 if (pdata == NULL) {
2012 dev_err(&pdev->dev, "Platform Data is missing\n");
2013 return -ENXIO;
2014 }
2015
2016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2017 irq = platform_get_irq(pdev, 0);
2018 if (res == NULL || irq < 0)
2019 return -ENXIO;
2020
2021 base = devm_ioremap_resource(&pdev->dev, res);
2022 if (IS_ERR(base))
2023 return PTR_ERR(base);
2024
2025 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2026 if (!mmc) {
2027 ret = -ENOMEM;
2028 goto err;
2029 }
2030
2031 ret = mmc_of_parse(mmc);
2032 if (ret)
2033 goto err1;
2034
2035 host = mmc_priv(mmc);
2036 host->mmc = mmc;
2037 host->pdata = pdata;
2038 host->dev = &pdev->dev;
2039 host->use_dma = 1;
2040 host->dma_ch = -1;
2041 host->irq = irq;
2042 host->mapbase = res->start + pdata->reg_offset;
2043 host->base = base + pdata->reg_offset;
2044 host->power_mode = MMC_POWER_OFF;
2045 host->next_data.cookie = 1;
2046 host->pbias_enabled = 0;
2047 host->vqmmc_enabled = 0;
2048
2049 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2050 if (ret)
2051 goto err_gpio;
2052
2053 platform_set_drvdata(pdev, host);
2054
2055 if (pdev->dev.of_node)
2056 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2057
2058 mmc->ops = &omap_hsmmc_ops;
2059
2060 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2061
2062 if (pdata->max_freq > 0)
2063 mmc->f_max = pdata->max_freq;
2064 else if (mmc->f_max == 0)
2065 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2066
2067 spin_lock_init(&host->irq_lock);
2068
2069 host->fclk = devm_clk_get(&pdev->dev, "fck");
2070 if (IS_ERR(host->fclk)) {
2071 ret = PTR_ERR(host->fclk);
2072 host->fclk = NULL;
2073 goto err1;
2074 }
2075
2076 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2077 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2078 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2079 }
2080
2081 device_init_wakeup(&pdev->dev, true);
2082 pm_runtime_enable(host->dev);
2083 pm_runtime_get_sync(host->dev);
2084 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2085 pm_runtime_use_autosuspend(host->dev);
2086
2087 omap_hsmmc_context_save(host);
2088
2089 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2090 /*
2091 * MMC can still work without debounce clock.
2092 */
2093 if (IS_ERR(host->dbclk)) {
2094 host->dbclk = NULL;
2095 } else if (clk_prepare_enable(host->dbclk) != 0) {
2096 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2097 host->dbclk = NULL;
2098 }
2099
2100 /* Since we do only SG emulation, we can have as many segs
2101 * as we want. */
2102 mmc->max_segs = 1024;
2103
2104 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2105 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2106 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2107 mmc->max_seg_size = mmc->max_req_size;
2108
2109 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2110 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2111
2112 mmc->caps |= mmc_pdata(host)->caps;
2113 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2114 mmc->caps |= MMC_CAP_4_BIT_DATA;
2115
2116 if (mmc_pdata(host)->nonremovable)
2117 mmc->caps |= MMC_CAP_NONREMOVABLE;
2118
2119 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2120
2121 omap_hsmmc_conf_bus_power(host);
2122
2123 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
2124 if (IS_ERR(host->rx_chan)) {
2125 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
2126 ret = PTR_ERR(host->rx_chan);
2127 goto err_irq;
2128 }
2129
2130 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
2131 if (IS_ERR(host->tx_chan)) {
2132 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
2133 ret = PTR_ERR(host->tx_chan);
2134 goto err_irq;
2135 }
2136
2137 /* Request IRQ for MMC operations */
2138 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2139 mmc_hostname(mmc), host);
2140 if (ret) {
2141 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2142 goto err_irq;
2143 }
2144
2145 ret = omap_hsmmc_reg_get(host);
2146 if (ret)
2147 goto err_irq;
2148
2149 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2150
2151 omap_hsmmc_disable_irq(host);
2152
2153 /*
2154 * For now, only support SDIO interrupt if we have a separate
2155 * wake-up interrupt configured from device tree. This is because
2156 * the wake-up interrupt is needed for idle state and some
2157 * platforms need special quirks. And we don't want to add new
2158 * legacy mux platform init code callbacks any longer as we
2159 * are moving to DT based booting anyways.
2160 */
2161 ret = omap_hsmmc_configure_wake_irq(host);
2162 if (!ret)
2163 mmc->caps |= MMC_CAP_SDIO_IRQ;
2164
2165 omap_hsmmc_protect_card(host);
2166
2167 mmc_add_host(mmc);
2168
2169 if (mmc_pdata(host)->name != NULL) {
2170 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2171 if (ret < 0)
2172 goto err_slot_name;
2173 }
2174 if (host->get_cover_state) {
2175 ret = device_create_file(&mmc->class_dev,
2176 &dev_attr_cover_switch);
2177 if (ret < 0)
2178 goto err_slot_name;
2179 }
2180
2181 omap_hsmmc_debugfs(mmc);
2182 pm_runtime_mark_last_busy(host->dev);
2183 pm_runtime_put_autosuspend(host->dev);
2184
2185 return 0;
2186
2187 err_slot_name:
2188 mmc_remove_host(mmc);
2189 err_irq:
2190 device_init_wakeup(&pdev->dev, false);
2191 if (!IS_ERR_OR_NULL(host->tx_chan))
2192 dma_release_channel(host->tx_chan);
2193 if (!IS_ERR_OR_NULL(host->rx_chan))
2194 dma_release_channel(host->rx_chan);
2195 pm_runtime_dont_use_autosuspend(host->dev);
2196 pm_runtime_put_sync(host->dev);
2197 pm_runtime_disable(host->dev);
2198 if (host->dbclk)
2199 clk_disable_unprepare(host->dbclk);
2200 err1:
2201 err_gpio:
2202 mmc_free_host(mmc);
2203 err:
2204 return ret;
2205 }
2206
2207 static int omap_hsmmc_remove(struct platform_device *pdev)
2208 {
2209 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2210
2211 pm_runtime_get_sync(host->dev);
2212 mmc_remove_host(host->mmc);
2213
2214 dma_release_channel(host->tx_chan);
2215 dma_release_channel(host->rx_chan);
2216
2217 pm_runtime_dont_use_autosuspend(host->dev);
2218 pm_runtime_put_sync(host->dev);
2219 pm_runtime_disable(host->dev);
2220 device_init_wakeup(&pdev->dev, false);
2221 if (host->dbclk)
2222 clk_disable_unprepare(host->dbclk);
2223
2224 mmc_free_host(host->mmc);
2225
2226 return 0;
2227 }
2228
2229 #ifdef CONFIG_PM_SLEEP
2230 static int omap_hsmmc_suspend(struct device *dev)
2231 {
2232 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2233
2234 if (!host)
2235 return 0;
2236
2237 pm_runtime_get_sync(host->dev);
2238
2239 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2240 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2241 OMAP_HSMMC_WRITE(host->base, IE, 0);
2242 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2243 OMAP_HSMMC_WRITE(host->base, HCTL,
2244 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2245 }
2246
2247 if (host->dbclk)
2248 clk_disable_unprepare(host->dbclk);
2249
2250 pm_runtime_put_sync(host->dev);
2251 return 0;
2252 }
2253
2254 /* Routine to resume the MMC device */
2255 static int omap_hsmmc_resume(struct device *dev)
2256 {
2257 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2258
2259 if (!host)
2260 return 0;
2261
2262 pm_runtime_get_sync(host->dev);
2263
2264 if (host->dbclk)
2265 clk_prepare_enable(host->dbclk);
2266
2267 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2268 omap_hsmmc_conf_bus_power(host);
2269
2270 omap_hsmmc_protect_card(host);
2271 pm_runtime_mark_last_busy(host->dev);
2272 pm_runtime_put_autosuspend(host->dev);
2273 return 0;
2274 }
2275 #endif
2276
2277 static int omap_hsmmc_runtime_suspend(struct device *dev)
2278 {
2279 struct omap_hsmmc_host *host;
2280 unsigned long flags;
2281 int ret = 0;
2282
2283 host = platform_get_drvdata(to_platform_device(dev));
2284 omap_hsmmc_context_save(host);
2285 dev_dbg(dev, "disabled\n");
2286
2287 spin_lock_irqsave(&host->irq_lock, flags);
2288 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2289 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2290 /* disable sdio irq handling to prevent race */
2291 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2292 OMAP_HSMMC_WRITE(host->base, IE, 0);
2293
2294 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2295 /*
2296 * dat1 line low, pending sdio irq
2297 * race condition: possible irq handler running on
2298 * multi-core, abort
2299 */
2300 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2301 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2302 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2303 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2304 pm_runtime_mark_last_busy(dev);
2305 ret = -EBUSY;
2306 goto abort;
2307 }
2308
2309 pinctrl_pm_select_idle_state(dev);
2310 } else {
2311 pinctrl_pm_select_idle_state(dev);
2312 }
2313
2314 abort:
2315 spin_unlock_irqrestore(&host->irq_lock, flags);
2316 return ret;
2317 }
2318
2319 static int omap_hsmmc_runtime_resume(struct device *dev)
2320 {
2321 struct omap_hsmmc_host *host;
2322 unsigned long flags;
2323
2324 host = platform_get_drvdata(to_platform_device(dev));
2325 omap_hsmmc_context_restore(host);
2326 dev_dbg(dev, "enabled\n");
2327
2328 spin_lock_irqsave(&host->irq_lock, flags);
2329 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2330 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2331
2332 pinctrl_pm_select_default_state(host->dev);
2333
2334 /* irq lost, if pinmux incorrect */
2335 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2336 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2337 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2338 } else {
2339 pinctrl_pm_select_default_state(host->dev);
2340 }
2341 spin_unlock_irqrestore(&host->irq_lock, flags);
2342 return 0;
2343 }
2344
2345 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2346 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2347 .runtime_suspend = omap_hsmmc_runtime_suspend,
2348 .runtime_resume = omap_hsmmc_runtime_resume,
2349 };
2350
2351 static struct platform_driver omap_hsmmc_driver = {
2352 .probe = omap_hsmmc_probe,
2353 .remove = omap_hsmmc_remove,
2354 .driver = {
2355 .name = DRIVER_NAME,
2356 .pm = &omap_hsmmc_dev_pm_ops,
2357 .of_match_table = of_match_ptr(omap_mmc_of_match),
2358 },
2359 };
2360
2361 module_platform_driver(omap_hsmmc_driver);
2362 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2363 MODULE_LICENSE("GPL");
2364 MODULE_ALIAS("platform:" DRIVER_NAME);
2365 MODULE_AUTHOR("Texas Instruments Inc");
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