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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/io.h>
34 #include <linux/semaphore.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/pm_runtime.h>
38 #include <plat/dma.h>
39 #include <mach/hardware.h>
40 #include <plat/board.h>
41 #include <plat/mmc.h>
42 #include <plat/cpu.h>
43
44 /* OMAP HSMMC Host Controller Registers */
45 #define OMAP_HSMMC_SYSCONFIG 0x0010
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
62
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
71 #define AUTOIDLE 0x1
72 #define SDBP (1 << 8)
73 #define DTO 0xe
74 #define ICE 0x1
75 #define ICS 0x2
76 #define CEN (1 << 2)
77 #define CLKD_MASK 0x0000FFC0
78 #define CLKD_SHIFT 6
79 #define DTO_MASK 0x000F0000
80 #define DTO_SHIFT 16
81 #define INT_EN_MASK 0x307F0033
82 #define BWR_ENABLE (1 << 4)
83 #define BRR_ENABLE (1 << 5)
84 #define DTO_ENABLE (1 << 20)
85 #define INIT_STREAM (1 << 1)
86 #define DP_SELECT (1 << 21)
87 #define DDIR (1 << 4)
88 #define DMA_EN 0x1
89 #define MSBS (1 << 5)
90 #define BCE (1 << 1)
91 #define FOUR_BIT (1 << 1)
92 #define DW8 (1 << 5)
93 #define CC 0x1
94 #define TC 0x02
95 #define OD 0x1
96 #define ERR (1 << 15)
97 #define CMD_TIMEOUT (1 << 16)
98 #define DATA_TIMEOUT (1 << 20)
99 #define CMD_CRC (1 << 17)
100 #define DATA_CRC (1 << 21)
101 #define CARD_ERR (1 << 28)
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
108 #define RESETDONE (1 << 0)
109
110 /*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115 #define OMAP_MMC1_DEVID 0
116 #define OMAP_MMC2_DEVID 1
117 #define OMAP_MMC3_DEVID 2
118 #define OMAP_MMC4_DEVID 3
119 #define OMAP_MMC5_DEVID 4
120
121 #define MMC_AUTOSUSPEND_DELAY 100
122 #define MMC_TIMEOUT_MS 20
123 #define OMAP_MMC_MASTER_CLOCK 96000000
124 #define OMAP_MMC_MIN_CLOCK 400000
125 #define OMAP_MMC_MAX_CLOCK 52000000
126 #define DRIVER_NAME "omap_hsmmc"
127
128 /*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135 /*
136 * MMC Host controller read/write API's
137 */
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
144 struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147 };
148
149 struct omap_hsmmc_host {
150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
156 struct clk *dbclk;
157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
169 spinlock_t irq_lock; /* Prevent races with irq handler */
170 unsigned int id;
171 unsigned int dma_len;
172 unsigned int dma_sg_idx;
173 unsigned char bus_mode;
174 unsigned char power_mode;
175 u32 *buffer;
176 u32 bytesleft;
177 int suspended;
178 int irq;
179 int use_dma, dma_ch;
180 int dma_line_tx, dma_line_rx;
181 int slot_id;
182 int got_dbclk;
183 int response_busy;
184 int context_loss;
185 int dpm_state;
186 int vdd;
187 int protect_card;
188 int reqs_blocked;
189 int use_reg;
190 int req_in_progress;
191 struct omap_hsmmc_next next_data;
192
193 struct omap_mmc_platform_data *pdata;
194 };
195
196 static int omap_hsmmc_card_detect(struct device *dev, int slot)
197 {
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202 }
203
204 static int omap_hsmmc_get_wp(struct device *dev, int slot)
205 {
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
207
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210 }
211
212 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213 {
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
218 }
219
220 #ifdef CONFIG_PM
221
222 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223 {
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
225
226 disable_irq(mmc->slots[0].card_detect_irq);
227 return 0;
228 }
229
230 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231 {
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
233
234 enable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236 }
237
238 #else
239
240 #define omap_hsmmc_suspend_cdirq NULL
241 #define omap_hsmmc_resume_cdirq NULL
242
243 #endif
244
245 #ifdef CONFIG_REGULATOR
246
247 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 int vdd)
249 {
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
252 int ret;
253
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256
257 if (power_on)
258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
259 else
260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
261
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264
265 return ret;
266 }
267
268 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
269 int vdd)
270 {
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
273 int ret = 0;
274
275 /*
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
278 */
279 if (!host->vcc)
280 return 0;
281
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284
285 /*
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 *
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
293 *
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
297 */
298 if (power_on) {
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0)
304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
306 }
307 } else {
308 /* Shut down the rail */
309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
311 if (!ret) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
316 }
317
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320
321 return ret;
322 }
323
324 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
325 int vdd)
326 {
327 return 0;
328 }
329
330 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
332 {
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336
337 return regulator_set_mode(host->vcc, mode);
338 }
339
340 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
341 int vdd, int cardsleep)
342 {
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
345 int err, mode;
346
347 /*
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
350 */
351 if (!host->vcc)
352 return 0;
353
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355
356 if (!host->vcc_aux)
357 return regulator_set_mode(host->vcc, mode);
358
359 if (cardsleep) {
360 /* VCC can be turned off if card is asleep */
361 if (sleep)
362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
363 else
364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
365 } else
366 err = regulator_set_mode(host->vcc, mode);
367 if (err)
368 return err;
369
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
372
373 if (sleep)
374 return regulator_disable(host->vcc_aux);
375 else
376 return regulator_enable(host->vcc_aux);
377 }
378
379 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
381 {
382 return 0;
383 }
384
385 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386 {
387 struct regulator *reg;
388 int ret = 0;
389 int ocr_value = 0;
390
391 switch (host->id) {
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 break;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
399 case OMAP_MMC5_DEVID:
400 /* Off-chip level shifting, or none */
401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
403 break;
404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
407 default:
408 pr_err("MMC%d configuration not supported!\n", host->id);
409 return -EINVAL;
410 }
411
412 reg = regulator_get(host->dev, "vmmc");
413 if (IS_ERR(reg)) {
414 dev_dbg(host->dev, "vmmc regulator missing\n");
415 /*
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
418 * for MMC2 or MMC3
419 */
420 if (host->id == OMAP_MMC1_DEVID) {
421 ret = PTR_ERR(reg);
422 goto err;
423 }
424 } else {
425 host->vcc = reg;
426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
429 } else {
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
434 return -EINVAL;
435 }
436 }
437
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441
442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
444 return 0;
445 /*
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
452 */
453 if (regulator_is_enabled(host->vcc) > 0 ||
454 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
455 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
456
457 mmc_slot(host).set_power(host->dev, host->slot_id,
458 1, vdd);
459 mmc_slot(host).set_power(host->dev, host->slot_id,
460 0, 0);
461 }
462 }
463
464 return 0;
465
466 err:
467 mmc_slot(host).set_power = NULL;
468 mmc_slot(host).set_sleep = NULL;
469 return ret;
470 }
471
472 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
473 {
474 regulator_put(host->vcc);
475 regulator_put(host->vcc_aux);
476 mmc_slot(host).set_power = NULL;
477 mmc_slot(host).set_sleep = NULL;
478 }
479
480 static inline int omap_hsmmc_have_reg(void)
481 {
482 return 1;
483 }
484
485 #else
486
487 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
488 {
489 return -EINVAL;
490 }
491
492 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
493 {
494 }
495
496 static inline int omap_hsmmc_have_reg(void)
497 {
498 return 0;
499 }
500
501 #endif
502
503 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
504 {
505 int ret;
506
507 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
508 if (pdata->slots[0].cover)
509 pdata->slots[0].get_cover_state =
510 omap_hsmmc_get_cover_state;
511 else
512 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
513 pdata->slots[0].card_detect_irq =
514 gpio_to_irq(pdata->slots[0].switch_pin);
515 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
516 if (ret)
517 return ret;
518 ret = gpio_direction_input(pdata->slots[0].switch_pin);
519 if (ret)
520 goto err_free_sp;
521 } else
522 pdata->slots[0].switch_pin = -EINVAL;
523
524 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
525 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
526 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
527 if (ret)
528 goto err_free_cd;
529 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
530 if (ret)
531 goto err_free_wp;
532 } else
533 pdata->slots[0].gpio_wp = -EINVAL;
534
535 return 0;
536
537 err_free_wp:
538 gpio_free(pdata->slots[0].gpio_wp);
539 err_free_cd:
540 if (gpio_is_valid(pdata->slots[0].switch_pin))
541 err_free_sp:
542 gpio_free(pdata->slots[0].switch_pin);
543 return ret;
544 }
545
546 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
547 {
548 if (gpio_is_valid(pdata->slots[0].gpio_wp))
549 gpio_free(pdata->slots[0].gpio_wp);
550 if (gpio_is_valid(pdata->slots[0].switch_pin))
551 gpio_free(pdata->slots[0].switch_pin);
552 }
553
554 /*
555 * Start clock to the card
556 */
557 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
558 {
559 OMAP_HSMMC_WRITE(host->base, SYSCTL,
560 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
561 }
562
563 /*
564 * Stop clock to the card
565 */
566 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
567 {
568 OMAP_HSMMC_WRITE(host->base, SYSCTL,
569 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
570 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
571 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
572 }
573
574 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
575 struct mmc_command *cmd)
576 {
577 unsigned int irq_mask;
578
579 if (host->use_dma)
580 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
581 else
582 irq_mask = INT_EN_MASK;
583
584 /* Disable timeout for erases */
585 if (cmd->opcode == MMC_ERASE)
586 irq_mask &= ~DTO_ENABLE;
587
588 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
589 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
590 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
591 }
592
593 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
594 {
595 OMAP_HSMMC_WRITE(host->base, ISE, 0);
596 OMAP_HSMMC_WRITE(host->base, IE, 0);
597 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
598 }
599
600 /* Calculate divisor for the given clock frequency */
601 static u16 calc_divisor(struct mmc_ios *ios)
602 {
603 u16 dsor = 0;
604
605 if (ios->clock) {
606 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
607 if (dsor > 250)
608 dsor = 250;
609 }
610
611 return dsor;
612 }
613
614 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
615 {
616 struct mmc_ios *ios = &host->mmc->ios;
617 unsigned long regval;
618 unsigned long timeout;
619
620 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
621
622 omap_hsmmc_stop_clock(host);
623
624 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
625 regval = regval & ~(CLKD_MASK | DTO_MASK);
626 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
627 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
628 OMAP_HSMMC_WRITE(host->base, SYSCTL,
629 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
630
631 /* Wait till the ICS bit is set */
632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
633 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
634 && time_before(jiffies, timeout))
635 cpu_relax();
636
637 omap_hsmmc_start_clock(host);
638 }
639
640 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
641 {
642 struct mmc_ios *ios = &host->mmc->ios;
643 u32 con;
644
645 con = OMAP_HSMMC_READ(host->base, CON);
646 switch (ios->bus_width) {
647 case MMC_BUS_WIDTH_8:
648 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
649 break;
650 case MMC_BUS_WIDTH_4:
651 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
652 OMAP_HSMMC_WRITE(host->base, HCTL,
653 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
654 break;
655 case MMC_BUS_WIDTH_1:
656 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
657 OMAP_HSMMC_WRITE(host->base, HCTL,
658 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
659 break;
660 }
661 }
662
663 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
664 {
665 struct mmc_ios *ios = &host->mmc->ios;
666 u32 con;
667
668 con = OMAP_HSMMC_READ(host->base, CON);
669 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
670 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
671 else
672 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
673 }
674
675 #ifdef CONFIG_PM
676
677 /*
678 * Restore the MMC host context, if it was lost as result of a
679 * power state change.
680 */
681 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
682 {
683 struct mmc_ios *ios = &host->mmc->ios;
684 struct omap_mmc_platform_data *pdata = host->pdata;
685 int context_loss = 0;
686 u32 hctl, capa;
687 unsigned long timeout;
688
689 if (pdata->get_context_loss_count) {
690 context_loss = pdata->get_context_loss_count(host->dev);
691 if (context_loss < 0)
692 return 1;
693 }
694
695 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
696 context_loss == host->context_loss ? "not " : "");
697 if (host->context_loss == context_loss)
698 return 1;
699
700 /* Wait for hardware reset */
701 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
702 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
703 && time_before(jiffies, timeout))
704 ;
705
706 /* Do software reset */
707 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
708 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
709 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
710 && time_before(jiffies, timeout))
711 ;
712
713 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
714 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
715
716 if (host->id == OMAP_MMC1_DEVID) {
717 if (host->power_mode != MMC_POWER_OFF &&
718 (1 << ios->vdd) <= MMC_VDD_23_24)
719 hctl = SDVS18;
720 else
721 hctl = SDVS30;
722 capa = VS30 | VS18;
723 } else {
724 hctl = SDVS18;
725 capa = VS18;
726 }
727
728 OMAP_HSMMC_WRITE(host->base, HCTL,
729 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
730
731 OMAP_HSMMC_WRITE(host->base, CAPA,
732 OMAP_HSMMC_READ(host->base, CAPA) | capa);
733
734 OMAP_HSMMC_WRITE(host->base, HCTL,
735 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
736
737 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
738 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
739 && time_before(jiffies, timeout))
740 ;
741
742 omap_hsmmc_disable_irq(host);
743
744 /* Do not initialize card-specific things if the power is off */
745 if (host->power_mode == MMC_POWER_OFF)
746 goto out;
747
748 omap_hsmmc_set_bus_width(host);
749
750 omap_hsmmc_set_clock(host);
751
752 omap_hsmmc_set_bus_mode(host);
753
754 out:
755 host->context_loss = context_loss;
756
757 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
758 return 0;
759 }
760
761 /*
762 * Save the MMC host context (store the number of power state changes so far).
763 */
764 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
765 {
766 struct omap_mmc_platform_data *pdata = host->pdata;
767 int context_loss;
768
769 if (pdata->get_context_loss_count) {
770 context_loss = pdata->get_context_loss_count(host->dev);
771 if (context_loss < 0)
772 return;
773 host->context_loss = context_loss;
774 }
775 }
776
777 #else
778
779 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
780 {
781 return 0;
782 }
783
784 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
785 {
786 }
787
788 #endif
789
790 /*
791 * Send init stream sequence to card
792 * before sending IDLE command
793 */
794 static void send_init_stream(struct omap_hsmmc_host *host)
795 {
796 int reg = 0;
797 unsigned long timeout;
798
799 if (host->protect_card)
800 return;
801
802 disable_irq(host->irq);
803
804 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
805 OMAP_HSMMC_WRITE(host->base, CON,
806 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
807 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
808
809 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
810 while ((reg != CC) && time_before(jiffies, timeout))
811 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
812
813 OMAP_HSMMC_WRITE(host->base, CON,
814 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
815
816 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
817 OMAP_HSMMC_READ(host->base, STAT);
818
819 enable_irq(host->irq);
820 }
821
822 static inline
823 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
824 {
825 int r = 1;
826
827 if (mmc_slot(host).get_cover_state)
828 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
829 return r;
830 }
831
832 static ssize_t
833 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
834 char *buf)
835 {
836 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
837 struct omap_hsmmc_host *host = mmc_priv(mmc);
838
839 return sprintf(buf, "%s\n",
840 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
841 }
842
843 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
844
845 static ssize_t
846 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
847 char *buf)
848 {
849 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
850 struct omap_hsmmc_host *host = mmc_priv(mmc);
851
852 return sprintf(buf, "%s\n", mmc_slot(host).name);
853 }
854
855 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
856
857 /*
858 * Configure the response type and send the cmd.
859 */
860 static void
861 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
862 struct mmc_data *data)
863 {
864 int cmdreg = 0, resptype = 0, cmdtype = 0;
865
866 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
867 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
868 host->cmd = cmd;
869
870 omap_hsmmc_enable_irq(host, cmd);
871
872 host->response_busy = 0;
873 if (cmd->flags & MMC_RSP_PRESENT) {
874 if (cmd->flags & MMC_RSP_136)
875 resptype = 1;
876 else if (cmd->flags & MMC_RSP_BUSY) {
877 resptype = 3;
878 host->response_busy = 1;
879 } else
880 resptype = 2;
881 }
882
883 /*
884 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
885 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
886 * a val of 0x3, rest 0x0.
887 */
888 if (cmd == host->mrq->stop)
889 cmdtype = 0x3;
890
891 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
892
893 if (data) {
894 cmdreg |= DP_SELECT | MSBS | BCE;
895 if (data->flags & MMC_DATA_READ)
896 cmdreg |= DDIR;
897 else
898 cmdreg &= ~(DDIR);
899 }
900
901 if (host->use_dma)
902 cmdreg |= DMA_EN;
903
904 host->req_in_progress = 1;
905
906 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
907 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
908 }
909
910 static int
911 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
912 {
913 if (data->flags & MMC_DATA_WRITE)
914 return DMA_TO_DEVICE;
915 else
916 return DMA_FROM_DEVICE;
917 }
918
919 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
920 {
921 int dma_ch;
922
923 spin_lock(&host->irq_lock);
924 host->req_in_progress = 0;
925 dma_ch = host->dma_ch;
926 spin_unlock(&host->irq_lock);
927
928 omap_hsmmc_disable_irq(host);
929 /* Do not complete the request if DMA is still in progress */
930 if (mrq->data && host->use_dma && dma_ch != -1)
931 return;
932 host->mrq = NULL;
933 mmc_request_done(host->mmc, mrq);
934 }
935
936 /*
937 * Notify the transfer complete to MMC core
938 */
939 static void
940 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
941 {
942 if (!data) {
943 struct mmc_request *mrq = host->mrq;
944
945 /* TC before CC from CMD6 - don't know why, but it happens */
946 if (host->cmd && host->cmd->opcode == 6 &&
947 host->response_busy) {
948 host->response_busy = 0;
949 return;
950 }
951
952 omap_hsmmc_request_done(host, mrq);
953 return;
954 }
955
956 host->data = NULL;
957
958 if (!data->error)
959 data->bytes_xfered += data->blocks * (data->blksz);
960 else
961 data->bytes_xfered = 0;
962
963 if (!data->stop) {
964 omap_hsmmc_request_done(host, data->mrq);
965 return;
966 }
967 omap_hsmmc_start_command(host, data->stop, NULL);
968 }
969
970 /*
971 * Notify the core about command completion
972 */
973 static void
974 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
975 {
976 host->cmd = NULL;
977
978 if (cmd->flags & MMC_RSP_PRESENT) {
979 if (cmd->flags & MMC_RSP_136) {
980 /* response type 2 */
981 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
982 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
983 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
984 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
985 } else {
986 /* response types 1, 1b, 3, 4, 5, 6 */
987 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
988 }
989 }
990 if ((host->data == NULL && !host->response_busy) || cmd->error)
991 omap_hsmmc_request_done(host, cmd->mrq);
992 }
993
994 /*
995 * DMA clean up for command errors
996 */
997 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
998 {
999 int dma_ch;
1000
1001 host->data->error = errno;
1002
1003 spin_lock(&host->irq_lock);
1004 dma_ch = host->dma_ch;
1005 host->dma_ch = -1;
1006 spin_unlock(&host->irq_lock);
1007
1008 if (host->use_dma && dma_ch != -1) {
1009 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1010 host->data->sg_len,
1011 omap_hsmmc_get_dma_dir(host, host->data));
1012 omap_free_dma(dma_ch);
1013 host->data->host_cookie = 0;
1014 }
1015 host->data = NULL;
1016 }
1017
1018 /*
1019 * Readable error output
1020 */
1021 #ifdef CONFIG_MMC_DEBUG
1022 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1023 {
1024 /* --- means reserved bit without definition at documentation */
1025 static const char *omap_hsmmc_status_bits[] = {
1026 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1030 };
1031 char res[256];
1032 char *buf = res;
1033 int len, i;
1034
1035 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1036 buf += len;
1037
1038 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1039 if (status & (1 << i)) {
1040 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1041 buf += len;
1042 }
1043
1044 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1045 }
1046 #else
1047 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1048 u32 status)
1049 {
1050 }
1051 #endif /* CONFIG_MMC_DEBUG */
1052
1053 /*
1054 * MMC controller internal state machines reset
1055 *
1056 * Used to reset command or data internal state machines, using respectively
1057 * SRC or SRD bit of SYSCTL register
1058 * Can be called from interrupt context
1059 */
1060 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1061 unsigned long bit)
1062 {
1063 unsigned long i = 0;
1064 unsigned long limit = (loops_per_jiffy *
1065 msecs_to_jiffies(MMC_TIMEOUT_MS));
1066
1067 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1068 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1069
1070 /*
1071 * OMAP4 ES2 and greater has an updated reset logic.
1072 * Monitor a 0->1 transition first
1073 */
1074 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1075 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1076 && (i++ < limit))
1077 cpu_relax();
1078 }
1079 i = 0;
1080
1081 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1082 (i++ < limit))
1083 cpu_relax();
1084
1085 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1086 dev_err(mmc_dev(host->mmc),
1087 "Timeout waiting on controller reset in %s\n",
1088 __func__);
1089 }
1090
1091 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1092 {
1093 struct mmc_data *data;
1094 int end_cmd = 0, end_trans = 0;
1095
1096 if (!host->req_in_progress) {
1097 do {
1098 OMAP_HSMMC_WRITE(host->base, STAT, status);
1099 /* Flush posted write */
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1101 } while (status & INT_EN_MASK);
1102 return;
1103 }
1104
1105 data = host->data;
1106 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1107
1108 if (status & ERR) {
1109 omap_hsmmc_dbg_report_irq(host, status);
1110 if ((status & CMD_TIMEOUT) ||
1111 (status & CMD_CRC)) {
1112 if (host->cmd) {
1113 if (status & CMD_TIMEOUT) {
1114 omap_hsmmc_reset_controller_fsm(host,
1115 SRC);
1116 host->cmd->error = -ETIMEDOUT;
1117 } else {
1118 host->cmd->error = -EILSEQ;
1119 }
1120 end_cmd = 1;
1121 }
1122 if (host->data || host->response_busy) {
1123 if (host->data)
1124 omap_hsmmc_dma_cleanup(host,
1125 -ETIMEDOUT);
1126 host->response_busy = 0;
1127 omap_hsmmc_reset_controller_fsm(host, SRD);
1128 }
1129 }
1130 if ((status & DATA_TIMEOUT) ||
1131 (status & DATA_CRC)) {
1132 if (host->data || host->response_busy) {
1133 int err = (status & DATA_TIMEOUT) ?
1134 -ETIMEDOUT : -EILSEQ;
1135
1136 if (host->data)
1137 omap_hsmmc_dma_cleanup(host, err);
1138 else
1139 host->mrq->cmd->error = err;
1140 host->response_busy = 0;
1141 omap_hsmmc_reset_controller_fsm(host, SRD);
1142 end_trans = 1;
1143 }
1144 }
1145 if (status & CARD_ERR) {
1146 dev_dbg(mmc_dev(host->mmc),
1147 "Ignoring card err CMD%d\n", host->cmd->opcode);
1148 if (host->cmd)
1149 end_cmd = 1;
1150 if (host->data)
1151 end_trans = 1;
1152 }
1153 }
1154
1155 OMAP_HSMMC_WRITE(host->base, STAT, status);
1156
1157 if (end_cmd || ((status & CC) && host->cmd))
1158 omap_hsmmc_cmd_done(host, host->cmd);
1159 if ((end_trans || (status & TC)) && host->mrq)
1160 omap_hsmmc_xfer_done(host, data);
1161 }
1162
1163 /*
1164 * MMC controller IRQ handler
1165 */
1166 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1167 {
1168 struct omap_hsmmc_host *host = dev_id;
1169 int status;
1170
1171 status = OMAP_HSMMC_READ(host->base, STAT);
1172 do {
1173 omap_hsmmc_do_irq(host, status);
1174 /* Flush posted write */
1175 status = OMAP_HSMMC_READ(host->base, STAT);
1176 } while (status & INT_EN_MASK);
1177
1178 return IRQ_HANDLED;
1179 }
1180
1181 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1182 {
1183 unsigned long i;
1184
1185 OMAP_HSMMC_WRITE(host->base, HCTL,
1186 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1187 for (i = 0; i < loops_per_jiffy; i++) {
1188 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1189 break;
1190 cpu_relax();
1191 }
1192 }
1193
1194 /*
1195 * Switch MMC interface voltage ... only relevant for MMC1.
1196 *
1197 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1198 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1199 * Some chips, like eMMC ones, use internal transceivers.
1200 */
1201 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1202 {
1203 u32 reg_val = 0;
1204 int ret;
1205
1206 /* Disable the clocks */
1207 pm_runtime_put_sync(host->dev);
1208 if (host->got_dbclk)
1209 clk_disable(host->dbclk);
1210
1211 /* Turn the power off */
1212 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1213
1214 /* Turn the power ON with given VDD 1.8 or 3.0v */
1215 if (!ret)
1216 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1217 vdd);
1218 pm_runtime_get_sync(host->dev);
1219 if (host->got_dbclk)
1220 clk_enable(host->dbclk);
1221
1222 if (ret != 0)
1223 goto err;
1224
1225 OMAP_HSMMC_WRITE(host->base, HCTL,
1226 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1227 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1228
1229 /*
1230 * If a MMC dual voltage card is detected, the set_ios fn calls
1231 * this fn with VDD bit set for 1.8V. Upon card removal from the
1232 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1233 *
1234 * Cope with a bit of slop in the range ... per data sheets:
1235 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1236 * but recommended values are 1.71V to 1.89V
1237 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1238 * but recommended values are 2.7V to 3.3V
1239 *
1240 * Board setup code shouldn't permit anything very out-of-range.
1241 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1242 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1243 */
1244 if ((1 << vdd) <= MMC_VDD_23_24)
1245 reg_val |= SDVS18;
1246 else
1247 reg_val |= SDVS30;
1248
1249 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1250 set_sd_bus_power(host);
1251
1252 return 0;
1253 err:
1254 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1255 return ret;
1256 }
1257
1258 /* Protect the card while the cover is open */
1259 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1260 {
1261 if (!mmc_slot(host).get_cover_state)
1262 return;
1263
1264 host->reqs_blocked = 0;
1265 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1266 if (host->protect_card) {
1267 pr_info("%s: cover is closed, "
1268 "card is now accessible\n",
1269 mmc_hostname(host->mmc));
1270 host->protect_card = 0;
1271 }
1272 } else {
1273 if (!host->protect_card) {
1274 pr_info("%s: cover is open, "
1275 "card is now inaccessible\n",
1276 mmc_hostname(host->mmc));
1277 host->protect_card = 1;
1278 }
1279 }
1280 }
1281
1282 /*
1283 * Work Item to notify the core about card insertion/removal
1284 */
1285 static void omap_hsmmc_detect(struct work_struct *work)
1286 {
1287 struct omap_hsmmc_host *host =
1288 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1289 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1290 int carddetect;
1291
1292 if (host->suspended)
1293 return;
1294
1295 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1296
1297 if (slot->card_detect)
1298 carddetect = slot->card_detect(host->dev, host->slot_id);
1299 else {
1300 omap_hsmmc_protect_card(host);
1301 carddetect = -ENOSYS;
1302 }
1303
1304 if (carddetect)
1305 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1306 else
1307 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1308 }
1309
1310 /*
1311 * ISR for handling card insertion and removal
1312 */
1313 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1314 {
1315 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1316
1317 if (host->suspended)
1318 return IRQ_HANDLED;
1319 schedule_work(&host->mmc_carddetect_work);
1320
1321 return IRQ_HANDLED;
1322 }
1323
1324 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1325 struct mmc_data *data)
1326 {
1327 int sync_dev;
1328
1329 if (data->flags & MMC_DATA_WRITE)
1330 sync_dev = host->dma_line_tx;
1331 else
1332 sync_dev = host->dma_line_rx;
1333 return sync_dev;
1334 }
1335
1336 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1337 struct mmc_data *data,
1338 struct scatterlist *sgl)
1339 {
1340 int blksz, nblk, dma_ch;
1341
1342 dma_ch = host->dma_ch;
1343 if (data->flags & MMC_DATA_WRITE) {
1344 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1345 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1346 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1347 sg_dma_address(sgl), 0, 0);
1348 } else {
1349 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1350 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1351 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1352 sg_dma_address(sgl), 0, 0);
1353 }
1354
1355 blksz = host->data->blksz;
1356 nblk = sg_dma_len(sgl) / blksz;
1357
1358 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1359 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1360 omap_hsmmc_get_dma_sync_dev(host, data),
1361 !(data->flags & MMC_DATA_WRITE));
1362
1363 omap_start_dma(dma_ch);
1364 }
1365
1366 /*
1367 * DMA call back function
1368 */
1369 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1370 {
1371 struct omap_hsmmc_host *host = cb_data;
1372 struct mmc_data *data;
1373 int dma_ch, req_in_progress;
1374
1375 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1376 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1377 ch_status);
1378 return;
1379 }
1380
1381 spin_lock(&host->irq_lock);
1382 if (host->dma_ch < 0) {
1383 spin_unlock(&host->irq_lock);
1384 return;
1385 }
1386
1387 data = host->mrq->data;
1388 host->dma_sg_idx++;
1389 if (host->dma_sg_idx < host->dma_len) {
1390 /* Fire up the next transfer. */
1391 omap_hsmmc_config_dma_params(host, data,
1392 data->sg + host->dma_sg_idx);
1393 spin_unlock(&host->irq_lock);
1394 return;
1395 }
1396
1397 if (!data->host_cookie)
1398 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1399 omap_hsmmc_get_dma_dir(host, data));
1400
1401 req_in_progress = host->req_in_progress;
1402 dma_ch = host->dma_ch;
1403 host->dma_ch = -1;
1404 spin_unlock(&host->irq_lock);
1405
1406 omap_free_dma(dma_ch);
1407
1408 /* If DMA has finished after TC, complete the request */
1409 if (!req_in_progress) {
1410 struct mmc_request *mrq = host->mrq;
1411
1412 host->mrq = NULL;
1413 mmc_request_done(host->mmc, mrq);
1414 }
1415 }
1416
1417 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1418 struct mmc_data *data,
1419 struct omap_hsmmc_next *next)
1420 {
1421 int dma_len;
1422
1423 if (!next && data->host_cookie &&
1424 data->host_cookie != host->next_data.cookie) {
1425 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1426 " host->next_data.cookie %d\n",
1427 __func__, data->host_cookie, host->next_data.cookie);
1428 data->host_cookie = 0;
1429 }
1430
1431 /* Check if next job is already prepared */
1432 if (next ||
1433 (!next && data->host_cookie != host->next_data.cookie)) {
1434 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1435 data->sg_len,
1436 omap_hsmmc_get_dma_dir(host, data));
1437
1438 } else {
1439 dma_len = host->next_data.dma_len;
1440 host->next_data.dma_len = 0;
1441 }
1442
1443
1444 if (dma_len == 0)
1445 return -EINVAL;
1446
1447 if (next) {
1448 next->dma_len = dma_len;
1449 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1450 } else
1451 host->dma_len = dma_len;
1452
1453 return 0;
1454 }
1455
1456 /*
1457 * Routine to configure and start DMA for the MMC card
1458 */
1459 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1460 struct mmc_request *req)
1461 {
1462 int dma_ch = 0, ret = 0, i;
1463 struct mmc_data *data = req->data;
1464
1465 /* Sanity check: all the SG entries must be aligned by block size. */
1466 for (i = 0; i < data->sg_len; i++) {
1467 struct scatterlist *sgl;
1468
1469 sgl = data->sg + i;
1470 if (sgl->length % data->blksz)
1471 return -EINVAL;
1472 }
1473 if ((data->blksz % 4) != 0)
1474 /* REVISIT: The MMC buffer increments only when MSB is written.
1475 * Return error for blksz which is non multiple of four.
1476 */
1477 return -EINVAL;
1478
1479 BUG_ON(host->dma_ch != -1);
1480
1481 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1482 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1483 if (ret != 0) {
1484 dev_err(mmc_dev(host->mmc),
1485 "%s: omap_request_dma() failed with %d\n",
1486 mmc_hostname(host->mmc), ret);
1487 return ret;
1488 }
1489 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1490 if (ret)
1491 return ret;
1492
1493 host->dma_ch = dma_ch;
1494 host->dma_sg_idx = 0;
1495
1496 omap_hsmmc_config_dma_params(host, data, data->sg);
1497
1498 return 0;
1499 }
1500
1501 static void set_data_timeout(struct omap_hsmmc_host *host,
1502 unsigned int timeout_ns,
1503 unsigned int timeout_clks)
1504 {
1505 unsigned int timeout, cycle_ns;
1506 uint32_t reg, clkd, dto = 0;
1507
1508 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1509 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1510 if (clkd == 0)
1511 clkd = 1;
1512
1513 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1514 timeout = timeout_ns / cycle_ns;
1515 timeout += timeout_clks;
1516 if (timeout) {
1517 while ((timeout & 0x80000000) == 0) {
1518 dto += 1;
1519 timeout <<= 1;
1520 }
1521 dto = 31 - dto;
1522 timeout <<= 1;
1523 if (timeout && dto)
1524 dto += 1;
1525 if (dto >= 13)
1526 dto -= 13;
1527 else
1528 dto = 0;
1529 if (dto > 14)
1530 dto = 14;
1531 }
1532
1533 reg &= ~DTO_MASK;
1534 reg |= dto << DTO_SHIFT;
1535 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1536 }
1537
1538 /*
1539 * Configure block length for MMC/SD cards and initiate the transfer.
1540 */
1541 static int
1542 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1543 {
1544 int ret;
1545 host->data = req->data;
1546
1547 if (req->data == NULL) {
1548 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1549 /*
1550 * Set an arbitrary 100ms data timeout for commands with
1551 * busy signal.
1552 */
1553 if (req->cmd->flags & MMC_RSP_BUSY)
1554 set_data_timeout(host, 100000000U, 0);
1555 return 0;
1556 }
1557
1558 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1559 | (req->data->blocks << 16));
1560 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1561
1562 if (host->use_dma) {
1563 ret = omap_hsmmc_start_dma_transfer(host, req);
1564 if (ret != 0) {
1565 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1566 return ret;
1567 }
1568 }
1569 return 0;
1570 }
1571
1572 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1573 int err)
1574 {
1575 struct omap_hsmmc_host *host = mmc_priv(mmc);
1576 struct mmc_data *data = mrq->data;
1577
1578 if (host->use_dma) {
1579 if (data->host_cookie)
1580 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1581 data->sg_len,
1582 omap_hsmmc_get_dma_dir(host, data));
1583 data->host_cookie = 0;
1584 }
1585 }
1586
1587 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1588 bool is_first_req)
1589 {
1590 struct omap_hsmmc_host *host = mmc_priv(mmc);
1591
1592 if (mrq->data->host_cookie) {
1593 mrq->data->host_cookie = 0;
1594 return ;
1595 }
1596
1597 if (host->use_dma)
1598 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1599 &host->next_data))
1600 mrq->data->host_cookie = 0;
1601 }
1602
1603 /*
1604 * Request function. for read/write operation
1605 */
1606 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1607 {
1608 struct omap_hsmmc_host *host = mmc_priv(mmc);
1609 int err;
1610
1611 BUG_ON(host->req_in_progress);
1612 BUG_ON(host->dma_ch != -1);
1613 if (host->protect_card) {
1614 if (host->reqs_blocked < 3) {
1615 /*
1616 * Ensure the controller is left in a consistent
1617 * state by resetting the command and data state
1618 * machines.
1619 */
1620 omap_hsmmc_reset_controller_fsm(host, SRD);
1621 omap_hsmmc_reset_controller_fsm(host, SRC);
1622 host->reqs_blocked += 1;
1623 }
1624 req->cmd->error = -EBADF;
1625 if (req->data)
1626 req->data->error = -EBADF;
1627 req->cmd->retries = 0;
1628 mmc_request_done(mmc, req);
1629 return;
1630 } else if (host->reqs_blocked)
1631 host->reqs_blocked = 0;
1632 WARN_ON(host->mrq != NULL);
1633 host->mrq = req;
1634 err = omap_hsmmc_prepare_data(host, req);
1635 if (err) {
1636 req->cmd->error = err;
1637 if (req->data)
1638 req->data->error = err;
1639 host->mrq = NULL;
1640 mmc_request_done(mmc, req);
1641 return;
1642 }
1643
1644 omap_hsmmc_start_command(host, req->cmd, req->data);
1645 }
1646
1647 /* Routine to configure clock values. Exposed API to core */
1648 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1649 {
1650 struct omap_hsmmc_host *host = mmc_priv(mmc);
1651 int do_send_init_stream = 0;
1652
1653 pm_runtime_get_sync(host->dev);
1654
1655 if (ios->power_mode != host->power_mode) {
1656 switch (ios->power_mode) {
1657 case MMC_POWER_OFF:
1658 mmc_slot(host).set_power(host->dev, host->slot_id,
1659 0, 0);
1660 host->vdd = 0;
1661 break;
1662 case MMC_POWER_UP:
1663 mmc_slot(host).set_power(host->dev, host->slot_id,
1664 1, ios->vdd);
1665 host->vdd = ios->vdd;
1666 break;
1667 case MMC_POWER_ON:
1668 do_send_init_stream = 1;
1669 break;
1670 }
1671 host->power_mode = ios->power_mode;
1672 }
1673
1674 /* FIXME: set registers based only on changes to ios */
1675
1676 omap_hsmmc_set_bus_width(host);
1677
1678 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1679 /* Only MMC1 can interface at 3V without some flavor
1680 * of external transceiver; but they all handle 1.8V.
1681 */
1682 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1683 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1684 /*
1685 * The mmc_select_voltage fn of the core does
1686 * not seem to set the power_mode to
1687 * MMC_POWER_UP upon recalculating the voltage.
1688 * vdd 1.8v.
1689 */
1690 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1691 dev_dbg(mmc_dev(host->mmc),
1692 "Switch operation failed\n");
1693 }
1694 }
1695
1696 omap_hsmmc_set_clock(host);
1697
1698 if (do_send_init_stream)
1699 send_init_stream(host);
1700
1701 omap_hsmmc_set_bus_mode(host);
1702
1703 pm_runtime_put_autosuspend(host->dev);
1704 }
1705
1706 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1707 {
1708 struct omap_hsmmc_host *host = mmc_priv(mmc);
1709
1710 if (!mmc_slot(host).card_detect)
1711 return -ENOSYS;
1712 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1713 }
1714
1715 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1716 {
1717 struct omap_hsmmc_host *host = mmc_priv(mmc);
1718
1719 if (!mmc_slot(host).get_ro)
1720 return -ENOSYS;
1721 return mmc_slot(host).get_ro(host->dev, 0);
1722 }
1723
1724 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1725 {
1726 struct omap_hsmmc_host *host = mmc_priv(mmc);
1727
1728 if (mmc_slot(host).init_card)
1729 mmc_slot(host).init_card(card);
1730 }
1731
1732 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1733 {
1734 u32 hctl, capa, value;
1735
1736 /* Only MMC1 supports 3.0V */
1737 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1738 hctl = SDVS30;
1739 capa = VS30 | VS18;
1740 } else {
1741 hctl = SDVS18;
1742 capa = VS18;
1743 }
1744
1745 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1746 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1747
1748 value = OMAP_HSMMC_READ(host->base, CAPA);
1749 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1750
1751 /* Set the controller to AUTO IDLE mode */
1752 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1753 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1754
1755 /* Set SD bus power bit */
1756 set_sd_bus_power(host);
1757 }
1758
1759 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1760 {
1761 struct omap_hsmmc_host *host = mmc_priv(mmc);
1762
1763 pm_runtime_get_sync(host->dev);
1764
1765 return 0;
1766 }
1767
1768 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1769 {
1770 struct omap_hsmmc_host *host = mmc_priv(mmc);
1771
1772 pm_runtime_mark_last_busy(host->dev);
1773 pm_runtime_put_autosuspend(host->dev);
1774
1775 return 0;
1776 }
1777
1778 static const struct mmc_host_ops omap_hsmmc_ops = {
1779 .enable = omap_hsmmc_enable_fclk,
1780 .disable = omap_hsmmc_disable_fclk,
1781 .post_req = omap_hsmmc_post_req,
1782 .pre_req = omap_hsmmc_pre_req,
1783 .request = omap_hsmmc_request,
1784 .set_ios = omap_hsmmc_set_ios,
1785 .get_cd = omap_hsmmc_get_cd,
1786 .get_ro = omap_hsmmc_get_ro,
1787 .init_card = omap_hsmmc_init_card,
1788 /* NYET -- enable_sdio_irq */
1789 };
1790
1791 #ifdef CONFIG_DEBUG_FS
1792
1793 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1794 {
1795 struct mmc_host *mmc = s->private;
1796 struct omap_hsmmc_host *host = mmc_priv(mmc);
1797 int context_loss = 0;
1798
1799 if (host->pdata->get_context_loss_count)
1800 context_loss = host->pdata->get_context_loss_count(host->dev);
1801
1802 seq_printf(s, "mmc%d:\n"
1803 " enabled:\t%d\n"
1804 " dpm_state:\t%d\n"
1805 " nesting_cnt:\t%d\n"
1806 " ctx_loss:\t%d:%d\n"
1807 "\nregs:\n",
1808 mmc->index, mmc->enabled ? 1 : 0,
1809 host->dpm_state, mmc->nesting_cnt,
1810 host->context_loss, context_loss);
1811
1812 if (host->suspended) {
1813 seq_printf(s, "host suspended, can't read registers\n");
1814 return 0;
1815 }
1816
1817 pm_runtime_get_sync(host->dev);
1818
1819 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1821 seq_printf(s, "CON:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, CON));
1823 seq_printf(s, "HCTL:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, HCTL));
1825 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, SYSCTL));
1827 seq_printf(s, "IE:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, IE));
1829 seq_printf(s, "ISE:\t\t0x%08x\n",
1830 OMAP_HSMMC_READ(host->base, ISE));
1831 seq_printf(s, "CAPA:\t\t0x%08x\n",
1832 OMAP_HSMMC_READ(host->base, CAPA));
1833
1834 pm_runtime_mark_last_busy(host->dev);
1835 pm_runtime_put_autosuspend(host->dev);
1836
1837 return 0;
1838 }
1839
1840 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1841 {
1842 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1843 }
1844
1845 static const struct file_operations mmc_regs_fops = {
1846 .open = omap_hsmmc_regs_open,
1847 .read = seq_read,
1848 .llseek = seq_lseek,
1849 .release = single_release,
1850 };
1851
1852 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1853 {
1854 if (mmc->debugfs_root)
1855 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1856 mmc, &mmc_regs_fops);
1857 }
1858
1859 #else
1860
1861 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1862 {
1863 }
1864
1865 #endif
1866
1867 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1868 {
1869 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1870 struct mmc_host *mmc;
1871 struct omap_hsmmc_host *host = NULL;
1872 struct resource *res;
1873 int ret, irq;
1874
1875 if (pdata == NULL) {
1876 dev_err(&pdev->dev, "Platform Data is missing\n");
1877 return -ENXIO;
1878 }
1879
1880 if (pdata->nr_slots == 0) {
1881 dev_err(&pdev->dev, "No Slots\n");
1882 return -ENXIO;
1883 }
1884
1885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886 irq = platform_get_irq(pdev, 0);
1887 if (res == NULL || irq < 0)
1888 return -ENXIO;
1889
1890 res->start += pdata->reg_offset;
1891 res->end += pdata->reg_offset;
1892 res = request_mem_region(res->start, resource_size(res), pdev->name);
1893 if (res == NULL)
1894 return -EBUSY;
1895
1896 ret = omap_hsmmc_gpio_init(pdata);
1897 if (ret)
1898 goto err;
1899
1900 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1901 if (!mmc) {
1902 ret = -ENOMEM;
1903 goto err_alloc;
1904 }
1905
1906 host = mmc_priv(mmc);
1907 host->mmc = mmc;
1908 host->pdata = pdata;
1909 host->dev = &pdev->dev;
1910 host->use_dma = 1;
1911 host->dev->dma_mask = &pdata->dma_mask;
1912 host->dma_ch = -1;
1913 host->irq = irq;
1914 host->id = pdev->id;
1915 host->slot_id = 0;
1916 host->mapbase = res->start;
1917 host->base = ioremap(host->mapbase, SZ_4K);
1918 host->power_mode = MMC_POWER_OFF;
1919 host->next_data.cookie = 1;
1920
1921 platform_set_drvdata(pdev, host);
1922 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1923
1924 mmc->ops = &omap_hsmmc_ops;
1925
1926 /*
1927 * If regulator_disable can only put vcc_aux to sleep then there is
1928 * no off state.
1929 */
1930 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1931 mmc_slot(host).no_off = 1;
1932
1933 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1934 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1935
1936 spin_lock_init(&host->irq_lock);
1937
1938 host->fclk = clk_get(&pdev->dev, "fck");
1939 if (IS_ERR(host->fclk)) {
1940 ret = PTR_ERR(host->fclk);
1941 host->fclk = NULL;
1942 goto err1;
1943 }
1944
1945 omap_hsmmc_context_save(host);
1946
1947 mmc->caps |= MMC_CAP_DISABLE;
1948 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1949 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1950 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1951 }
1952
1953 pm_runtime_enable(host->dev);
1954 pm_runtime_get_sync(host->dev);
1955 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1956 pm_runtime_use_autosuspend(host->dev);
1957
1958 if (cpu_is_omap2430()) {
1959 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1960 /*
1961 * MMC can still work without debounce clock.
1962 */
1963 if (IS_ERR(host->dbclk))
1964 dev_warn(mmc_dev(host->mmc),
1965 "Failed to get debounce clock\n");
1966 else
1967 host->got_dbclk = 1;
1968
1969 if (host->got_dbclk)
1970 if (clk_enable(host->dbclk) != 0)
1971 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1972 " clk failed\n");
1973 }
1974
1975 /* Since we do only SG emulation, we can have as many segs
1976 * as we want. */
1977 mmc->max_segs = 1024;
1978
1979 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1980 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1981 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1982 mmc->max_seg_size = mmc->max_req_size;
1983
1984 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1985 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1986
1987 mmc->caps |= mmc_slot(host).caps;
1988 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1989 mmc->caps |= MMC_CAP_4_BIT_DATA;
1990
1991 if (mmc_slot(host).nonremovable)
1992 mmc->caps |= MMC_CAP_NONREMOVABLE;
1993
1994 omap_hsmmc_conf_bus_power(host);
1995
1996 /* Select DMA lines */
1997 switch (host->id) {
1998 case OMAP_MMC1_DEVID:
1999 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2000 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2001 break;
2002 case OMAP_MMC2_DEVID:
2003 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2004 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2005 break;
2006 case OMAP_MMC3_DEVID:
2007 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2008 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2009 break;
2010 case OMAP_MMC4_DEVID:
2011 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2012 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2013 break;
2014 case OMAP_MMC5_DEVID:
2015 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2016 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2017 break;
2018 default:
2019 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2020 goto err_irq;
2021 }
2022
2023 /* Request IRQ for MMC operations */
2024 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2025 mmc_hostname(mmc), host);
2026 if (ret) {
2027 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2028 goto err_irq;
2029 }
2030
2031 if (pdata->init != NULL) {
2032 if (pdata->init(&pdev->dev) != 0) {
2033 dev_dbg(mmc_dev(host->mmc),
2034 "Unable to configure MMC IRQs\n");
2035 goto err_irq_cd_init;
2036 }
2037 }
2038
2039 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2040 ret = omap_hsmmc_reg_get(host);
2041 if (ret)
2042 goto err_reg;
2043 host->use_reg = 1;
2044 }
2045
2046 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2047
2048 /* Request IRQ for card detect */
2049 if ((mmc_slot(host).card_detect_irq)) {
2050 ret = request_irq(mmc_slot(host).card_detect_irq,
2051 omap_hsmmc_cd_handler,
2052 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2053 mmc_hostname(mmc), host);
2054 if (ret) {
2055 dev_dbg(mmc_dev(host->mmc),
2056 "Unable to grab MMC CD IRQ\n");
2057 goto err_irq_cd;
2058 }
2059 pdata->suspend = omap_hsmmc_suspend_cdirq;
2060 pdata->resume = omap_hsmmc_resume_cdirq;
2061 }
2062
2063 omap_hsmmc_disable_irq(host);
2064
2065 omap_hsmmc_protect_card(host);
2066
2067 mmc_add_host(mmc);
2068
2069 if (mmc_slot(host).name != NULL) {
2070 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2071 if (ret < 0)
2072 goto err_slot_name;
2073 }
2074 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2075 ret = device_create_file(&mmc->class_dev,
2076 &dev_attr_cover_switch);
2077 if (ret < 0)
2078 goto err_slot_name;
2079 }
2080
2081 omap_hsmmc_debugfs(mmc);
2082 pm_runtime_mark_last_busy(host->dev);
2083 pm_runtime_put_autosuspend(host->dev);
2084
2085 return 0;
2086
2087 err_slot_name:
2088 mmc_remove_host(mmc);
2089 free_irq(mmc_slot(host).card_detect_irq, host);
2090 err_irq_cd:
2091 if (host->use_reg)
2092 omap_hsmmc_reg_put(host);
2093 err_reg:
2094 if (host->pdata->cleanup)
2095 host->pdata->cleanup(&pdev->dev);
2096 err_irq_cd_init:
2097 free_irq(host->irq, host);
2098 err_irq:
2099 pm_runtime_mark_last_busy(host->dev);
2100 pm_runtime_put_autosuspend(host->dev);
2101 clk_put(host->fclk);
2102 if (host->got_dbclk) {
2103 clk_disable(host->dbclk);
2104 clk_put(host->dbclk);
2105 }
2106 err1:
2107 iounmap(host->base);
2108 platform_set_drvdata(pdev, NULL);
2109 mmc_free_host(mmc);
2110 err_alloc:
2111 omap_hsmmc_gpio_free(pdata);
2112 err:
2113 release_mem_region(res->start, resource_size(res));
2114 return ret;
2115 }
2116
2117 static int omap_hsmmc_remove(struct platform_device *pdev)
2118 {
2119 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2120 struct resource *res;
2121
2122 if (host) {
2123 pm_runtime_get_sync(host->dev);
2124 mmc_remove_host(host->mmc);
2125 if (host->use_reg)
2126 omap_hsmmc_reg_put(host);
2127 if (host->pdata->cleanup)
2128 host->pdata->cleanup(&pdev->dev);
2129 free_irq(host->irq, host);
2130 if (mmc_slot(host).card_detect_irq)
2131 free_irq(mmc_slot(host).card_detect_irq, host);
2132 flush_work_sync(&host->mmc_carddetect_work);
2133
2134 pm_runtime_put_sync(host->dev);
2135 pm_runtime_disable(host->dev);
2136 clk_put(host->fclk);
2137 if (host->got_dbclk) {
2138 clk_disable(host->dbclk);
2139 clk_put(host->dbclk);
2140 }
2141
2142 mmc_free_host(host->mmc);
2143 iounmap(host->base);
2144 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2145 }
2146
2147 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2148 if (res)
2149 release_mem_region(res->start, resource_size(res));
2150 platform_set_drvdata(pdev, NULL);
2151
2152 return 0;
2153 }
2154
2155 #ifdef CONFIG_PM
2156 static int omap_hsmmc_suspend(struct device *dev)
2157 {
2158 int ret = 0;
2159 struct platform_device *pdev = to_platform_device(dev);
2160 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2161
2162 if (host && host->suspended)
2163 return 0;
2164
2165 if (host) {
2166 pm_runtime_get_sync(host->dev);
2167 host->suspended = 1;
2168 if (host->pdata->suspend) {
2169 ret = host->pdata->suspend(&pdev->dev,
2170 host->slot_id);
2171 if (ret) {
2172 dev_dbg(mmc_dev(host->mmc),
2173 "Unable to handle MMC board"
2174 " level suspend\n");
2175 host->suspended = 0;
2176 return ret;
2177 }
2178 }
2179 cancel_work_sync(&host->mmc_carddetect_work);
2180 ret = mmc_suspend_host(host->mmc);
2181
2182 if (ret == 0) {
2183 omap_hsmmc_disable_irq(host);
2184 OMAP_HSMMC_WRITE(host->base, HCTL,
2185 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2186 if (host->got_dbclk)
2187 clk_disable(host->dbclk);
2188 } else {
2189 host->suspended = 0;
2190 if (host->pdata->resume) {
2191 ret = host->pdata->resume(&pdev->dev,
2192 host->slot_id);
2193 if (ret)
2194 dev_dbg(mmc_dev(host->mmc),
2195 "Unmask interrupt failed\n");
2196 }
2197 }
2198 pm_runtime_put_sync(host->dev);
2199 }
2200 return ret;
2201 }
2202
2203 /* Routine to resume the MMC device */
2204 static int omap_hsmmc_resume(struct device *dev)
2205 {
2206 int ret = 0;
2207 struct platform_device *pdev = to_platform_device(dev);
2208 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2209
2210 if (host && !host->suspended)
2211 return 0;
2212
2213 if (host) {
2214 pm_runtime_get_sync(host->dev);
2215
2216 if (host->got_dbclk)
2217 clk_enable(host->dbclk);
2218
2219 omap_hsmmc_conf_bus_power(host);
2220
2221 if (host->pdata->resume) {
2222 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2223 if (ret)
2224 dev_dbg(mmc_dev(host->mmc),
2225 "Unmask interrupt failed\n");
2226 }
2227
2228 omap_hsmmc_protect_card(host);
2229
2230 /* Notify the core to resume the host */
2231 ret = mmc_resume_host(host->mmc);
2232 if (ret == 0)
2233 host->suspended = 0;
2234
2235 pm_runtime_mark_last_busy(host->dev);
2236 pm_runtime_put_autosuspend(host->dev);
2237 }
2238
2239 return ret;
2240
2241 }
2242
2243 #else
2244 #define omap_hsmmc_suspend NULL
2245 #define omap_hsmmc_resume NULL
2246 #endif
2247
2248 static int omap_hsmmc_runtime_suspend(struct device *dev)
2249 {
2250 struct omap_hsmmc_host *host;
2251
2252 host = platform_get_drvdata(to_platform_device(dev));
2253 omap_hsmmc_context_save(host);
2254 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2255
2256 return 0;
2257 }
2258
2259 static int omap_hsmmc_runtime_resume(struct device *dev)
2260 {
2261 struct omap_hsmmc_host *host;
2262
2263 host = platform_get_drvdata(to_platform_device(dev));
2264 omap_hsmmc_context_restore(host);
2265 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2266
2267 return 0;
2268 }
2269
2270 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2271 .suspend = omap_hsmmc_suspend,
2272 .resume = omap_hsmmc_resume,
2273 .runtime_suspend = omap_hsmmc_runtime_suspend,
2274 .runtime_resume = omap_hsmmc_runtime_resume,
2275 };
2276
2277 static struct platform_driver omap_hsmmc_driver = {
2278 .remove = omap_hsmmc_remove,
2279 .driver = {
2280 .name = DRIVER_NAME,
2281 .owner = THIS_MODULE,
2282 .pm = &omap_hsmmc_dev_pm_ops,
2283 },
2284 };
2285
2286 static int __init omap_hsmmc_init(void)
2287 {
2288 /* Register the MMC driver */
2289 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2290 }
2291
2292 static void __exit omap_hsmmc_cleanup(void)
2293 {
2294 /* Unregister MMC driver */
2295 platform_driver_unregister(&omap_hsmmc_driver);
2296 }
2297
2298 module_init(omap_hsmmc_init);
2299 module_exit(omap_hsmmc_cleanup);
2300
2301 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2302 MODULE_LICENSE("GPL");
2303 MODULE_ALIAS("platform:" DRIVER_NAME);
2304 MODULE_AUTHOR("Texas Instruments Inc");
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