1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Renesas Electronics Corporation
6 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
10 * Based on "Compaq ASIC3 support":
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mfd/tmio.h>
30 #include <linux/sh_dma.h>
31 #include <linux/delay.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/pinctrl/pinctrl-state.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/sys_soc.h>
37 #include "renesas_sdhi.h"
40 #define HOST_MODE 0xe4
42 #define SDHI_VER_GEN2_SDR50 0x490c
43 #define SDHI_VER_RZ_A1 0x820b
44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
45 #define SDHI_VER_GEN2_SDR104 0xcb0d
46 #define SDHI_VER_GEN3_SD 0xcc10
47 #define SDHI_VER_GEN3_SDMMC 0xcd10
49 struct renesas_sdhi_quirks
{
54 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host
*host
, int width
)
60 * renesas_sdhi_of_data :: dma_buswidth
62 switch (sd_ctrl_read16(host
, CTL_VERSION
)) {
63 case SDHI_VER_GEN2_SDR50
:
64 val
= (width
== 32) ? 0x0001 : 0x0000;
66 case SDHI_VER_GEN2_SDR104
:
67 val
= (width
== 32) ? 0x0000 : 0x0001;
69 case SDHI_VER_GEN3_SD
:
70 case SDHI_VER_GEN3_SDMMC
:
83 sd_ctrl_write16(host
, HOST_MODE
, val
);
86 static int renesas_sdhi_clk_enable(struct tmio_mmc_host
*host
)
88 struct mmc_host
*mmc
= host
->mmc
;
89 struct renesas_sdhi
*priv
= host_to_priv(host
);
90 int ret
= clk_prepare_enable(priv
->clk
);
95 ret
= clk_prepare_enable(priv
->clk_cd
);
97 clk_disable_unprepare(priv
->clk
);
102 * The clock driver may not know what maximum frequency
103 * actually works, so it should be set with the max-frequency
104 * property which will already have been read to f_max. If it
105 * was missing, assume the current frequency is the maximum.
108 mmc
->f_max
= clk_get_rate(priv
->clk
);
111 * Minimum frequency is the minimum input clock frequency
112 * divided by our maximum divider.
114 mmc
->f_min
= max(clk_round_rate(priv
->clk
, 1) / 512, 1L);
116 /* enable 16bit data access on SDBUF as default */
117 renesas_sdhi_sdbuf_width(host
, 16);
122 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host
*host
,
123 unsigned int new_clock
)
125 struct renesas_sdhi
*priv
= host_to_priv(host
);
126 unsigned int freq
, diff
, best_freq
= 0, diff_min
= ~0;
129 /* tested only on R-Car Gen2+ currently; may work for others */
130 if (!(host
->pdata
->flags
& TMIO_MMC_MIN_RCAR2
))
131 return clk_get_rate(priv
->clk
);
134 * We want the bus clock to be as close as possible to, but no
135 * greater than, new_clock. As we can divide by 1 << i for
136 * any i in [0, 9] we want the input clock to be as close as
137 * possible, but no greater than, new_clock << i.
139 for (i
= min(9, ilog2(UINT_MAX
/ new_clock
)); i
>= 0; i
--) {
140 freq
= clk_round_rate(priv
->clk
, new_clock
<< i
);
141 if (freq
> (new_clock
<< i
)) {
142 /* Too fast; look for a slightly slower option */
143 freq
= clk_round_rate(priv
->clk
,
144 (new_clock
<< i
) / 4 * 3);
145 if (freq
> (new_clock
<< i
))
149 diff
= new_clock
- (freq
>> i
);
150 if (diff
<= diff_min
) {
156 ret
= clk_set_rate(priv
->clk
, best_freq
);
158 return ret
== 0 ? best_freq
: clk_get_rate(priv
->clk
);
161 static void renesas_sdhi_set_clock(struct tmio_mmc_host
*host
,
162 unsigned int new_clock
)
166 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, ~CLK_CTL_SCLKEN
&
167 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
172 clock
= renesas_sdhi_clk_update(host
, new_clock
) / 512;
174 for (clk
= 0x80000080; new_clock
>= (clock
<< 1); clk
>>= 1)
177 /* 1/1 clock is option */
178 if ((host
->pdata
->flags
& TMIO_MMC_CLK_ACTUAL
) && ((clk
>> 22) & 0x1)) {
179 if (!(host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
))
185 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, clk
& CLK_CTL_DIV_MASK
);
186 if (!(host
->pdata
->flags
& TMIO_MMC_MIN_RCAR2
))
187 usleep_range(10000, 11000);
189 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
190 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
193 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
194 if (!(host
->pdata
->flags
& TMIO_MMC_MIN_RCAR2
))
195 usleep_range(10000, 11000);
198 static void renesas_sdhi_clk_disable(struct tmio_mmc_host
*host
)
200 struct renesas_sdhi
*priv
= host_to_priv(host
);
202 clk_disable_unprepare(priv
->clk
);
203 clk_disable_unprepare(priv
->clk_cd
);
206 static int renesas_sdhi_card_busy(struct mmc_host
*mmc
)
208 struct tmio_mmc_host
*host
= mmc_priv(mmc
);
210 return !(sd_ctrl_read16_and_16_as_32(host
, CTL_STATUS
) &
214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host
*mmc
,
217 struct tmio_mmc_host
*host
= mmc_priv(mmc
);
218 struct renesas_sdhi
*priv
= host_to_priv(host
);
219 struct pinctrl_state
*pin_state
;
222 switch (ios
->signal_voltage
) {
223 case MMC_SIGNAL_VOLTAGE_330
:
224 pin_state
= priv
->pins_default
;
226 case MMC_SIGNAL_VOLTAGE_180
:
227 pin_state
= priv
->pins_uhs
;
234 * If anything is missing, assume signal voltage is fixed at
235 * 3.3V and succeed/fail accordingly.
237 if (IS_ERR(priv
->pinctrl
) || IS_ERR(pin_state
))
238 return ios
->signal_voltage
==
239 MMC_SIGNAL_VOLTAGE_330
? 0 : -EINVAL
;
241 ret
= mmc_regulator_set_vqmmc(host
->mmc
, ios
);
245 return pinctrl_select_state(priv
->pinctrl
, pin_state
);
249 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
250 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
251 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
252 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
253 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
254 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
255 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
257 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
259 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
260 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
262 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
263 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
264 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
265 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
266 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
267 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
268 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
269 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
270 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
272 static inline u32
sd_scc_read32(struct tmio_mmc_host
*host
,
273 struct renesas_sdhi
*priv
, int addr
)
275 return readl(priv
->scc_ctl
+ (addr
<< host
->bus_shift
));
278 static inline void sd_scc_write32(struct tmio_mmc_host
*host
,
279 struct renesas_sdhi
*priv
,
282 writel(val
, priv
->scc_ctl
+ (addr
<< host
->bus_shift
));
285 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host
*host
)
287 struct renesas_sdhi
*priv
;
289 priv
= host_to_priv(host
);
292 sd_ctrl_write32_as_16_and_16(host
, CTL_STATUS
, 0x0);
294 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, ~CLK_CTL_SCLKEN
&
295 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
297 /* set sampling clock selection range */
298 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DTCNTL
,
299 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN
|
300 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT
);
302 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_CKSEL
,
303 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL
|
304 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_CKSEL
));
306 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
,
307 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN
&
308 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
));
310 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DT2FF
, priv
->scc_tappos
);
312 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
313 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
316 return (sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_DTCNTL
) >>
317 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT
) &
318 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK
;
321 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host
*host
,
324 struct renesas_sdhi
*priv
= host_to_priv(host
);
326 /* Set sampling clock position */
327 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_TAPSET
, tap
);
330 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host
*host
)
332 struct renesas_sdhi
*priv
= host_to_priv(host
);
334 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, ~CLK_CTL_SCLKEN
&
335 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
338 sd_ctrl_write16(host
, CTL_SDIF_MODE
, 0x0001 |
339 sd_ctrl_read16(host
, CTL_SDIF_MODE
));
341 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DT2FF
,
342 priv
->scc_tappos_hs400
);
344 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_TMPPORT2
,
345 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN
|
346 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL
) |
347 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_TMPPORT2
));
349 /* Set the sampling clock selection range of HS400 mode */
350 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DTCNTL
,
351 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN
|
352 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT
);
355 if (host
->pdata
->flags
& TMIO_MMC_HAVE_4TAP_HS400
)
356 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_TAPSET
,
359 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_CKSEL
,
360 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL
|
361 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_CKSEL
));
363 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
364 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
367 static void renesas_sdhi_reset_scc(struct tmio_mmc_host
*host
,
368 struct renesas_sdhi
*priv
)
370 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, ~CLK_CTL_SCLKEN
&
371 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
373 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_CKSEL
,
374 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL
&
375 sd_scc_read32(host
, priv
,
376 SH_MOBILE_SDHI_SCC_CKSEL
));
379 static void renesas_sdhi_disable_scc(struct tmio_mmc_host
*host
)
381 struct renesas_sdhi
*priv
= host_to_priv(host
);
383 renesas_sdhi_reset_scc(host
, priv
);
385 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DTCNTL
,
386 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN
&
387 sd_scc_read32(host
, priv
,
388 SH_MOBILE_SDHI_SCC_DTCNTL
));
390 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
391 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
394 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host
*host
,
395 struct renesas_sdhi
*priv
)
397 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, ~CLK_CTL_SCLKEN
&
398 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
400 /* Reset HS400 mode */
401 sd_ctrl_write16(host
, CTL_SDIF_MODE
, ~0x0001 &
402 sd_ctrl_read16(host
, CTL_SDIF_MODE
));
404 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_DT2FF
, priv
->scc_tappos
);
406 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_TMPPORT2
,
407 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN
|
408 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL
) &
409 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_TMPPORT2
));
411 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
412 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
415 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host
*host
)
417 renesas_sdhi_reset_hs400_mode(host
, host_to_priv(host
));
420 #define SH_MOBILE_SDHI_MAX_TAP 3
422 static int renesas_sdhi_select_tuning(struct tmio_mmc_host
*host
)
424 struct renesas_sdhi
*priv
= host_to_priv(host
);
425 unsigned long tap_cnt
; /* counter of tuning success */
426 unsigned long tap_start
;/* start position of tuning success */
427 unsigned long tap_end
; /* end position of tuning success */
428 unsigned long ntap
; /* temporary counter of tuning success */
431 /* Clear SCC_RVSREQ */
432 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSREQ
, 0);
435 * When tuning CMD19 is issued twice for each tap, merge the
436 * result requiring the tap to be good in both runs before
437 * considering it for tuning selection.
439 for (i
= 0; i
< host
->tap_num
* 2; i
++) {
440 int offset
= host
->tap_num
* (i
< host
->tap_num
? 1 : -1);
442 if (!test_bit(i
, host
->taps
))
443 clear_bit(i
+ offset
, host
->taps
);
447 * Find the longest consecutive run of successful probes. If that
448 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
449 * center index as the tap.
455 for (i
= 0; i
< host
->tap_num
* 2; i
++) {
456 if (test_bit(i
, host
->taps
)) {
459 if (ntap
> tap_cnt
) {
460 tap_start
= i
- ntap
;
468 if (ntap
> tap_cnt
) {
469 tap_start
= i
- ntap
;
474 if (tap_cnt
>= SH_MOBILE_SDHI_MAX_TAP
)
475 host
->tap_set
= (tap_start
+ tap_end
) / 2 % host
->tap_num
;
480 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_TAPSET
, host
->tap_set
);
482 /* Enable auto re-tuning */
483 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
,
484 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN
|
485 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
));
490 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host
*host
)
492 struct renesas_sdhi
*priv
= host_to_priv(host
);
493 bool use_4tap
= host
->pdata
->flags
& TMIO_MMC_HAVE_4TAP_HS400
;
496 * Skip checking SCC errors when running on 4 taps in HS400 mode as
497 * any retuning would still result in the same 4 taps being used.
499 if (!(host
->mmc
->ios
.timing
== MMC_TIMING_UHS_SDR104
) &&
500 !(host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS200
) &&
501 !(host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
&& !use_4tap
))
504 if (mmc_doing_retune(host
->mmc
))
507 /* Check SCC error */
508 if (sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
) &
509 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN
&&
510 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSREQ
) &
511 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR
) {
512 /* Clear SCC error */
513 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSREQ
, 0);
520 static void renesas_sdhi_hw_reset(struct tmio_mmc_host
*host
)
522 struct renesas_sdhi
*priv
;
524 priv
= host_to_priv(host
);
526 renesas_sdhi_reset_scc(host
, priv
);
527 renesas_sdhi_reset_hs400_mode(host
, priv
);
529 sd_ctrl_write16(host
, CTL_SD_CARD_CLK_CTL
, CLK_CTL_SCLKEN
|
530 sd_ctrl_read16(host
, CTL_SD_CARD_CLK_CTL
));
532 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
,
533 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN
&
534 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
));
536 sd_scc_write32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
,
537 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN
&
538 sd_scc_read32(host
, priv
, SH_MOBILE_SDHI_SCC_RVSCNTL
));
540 if (host
->pdata
->flags
& TMIO_MMC_MIN_RCAR2
)
541 sd_ctrl_write32_as_16_and_16(host
, CTL_IRQ_MASK
,
542 TMIO_MASK_INIT_RCAR2
);
545 static int renesas_sdhi_wait_idle(struct tmio_mmc_host
*host
, u32 bit
)
548 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
549 u32 wait_state
= (bit
== TMIO_STAT_CMD_BUSY
? TMIO_STAT_CMD_BUSY
: 0);
551 while (--timeout
&& (sd_ctrl_read16_and_16_as_32(host
, CTL_STATUS
)
552 & bit
) == wait_state
)
556 dev_warn(&host
->pdev
->dev
, "timeout waiting for SD bus idle\n");
563 static int renesas_sdhi_write16_hook(struct tmio_mmc_host
*host
, int addr
)
565 u32 bit
= TMIO_STAT_SCLKDIVEN
;
569 case CTL_STOP_INTERNAL_ACTION
:
570 case CTL_XFER_BLK_COUNT
:
571 case CTL_SD_XFER_LEN
:
572 case CTL_SD_MEM_CARD_OPT
:
573 case CTL_TRANSACTION_CTL
:
576 if (host
->pdata
->flags
& TMIO_MMC_HAVE_CBSY
)
577 bit
= TMIO_STAT_CMD_BUSY
;
579 case CTL_SD_CARD_CLK_CTL
:
580 return renesas_sdhi_wait_idle(host
, bit
);
586 static int renesas_sdhi_multi_io_quirk(struct mmc_card
*card
,
587 unsigned int direction
, int blk_size
)
590 * In Renesas controllers, when performing a
591 * multiple block read of one or two blocks,
592 * depending on the timing with which the
593 * response register is read, the response
594 * value may not be read properly.
595 * Use single block read for this HW bug
597 if ((direction
== MMC_DATA_READ
) &&
604 static void renesas_sdhi_enable_dma(struct tmio_mmc_host
*host
, bool enable
)
606 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
607 int width
= (host
->bus_shift
== 2) ? 64 : 32;
609 sd_ctrl_write16(host
, CTL_DMA_ENABLE
, enable
? DMA_ENABLE_DMASDRW
: 0);
610 renesas_sdhi_sdbuf_width(host
, enable
? width
: 16);
613 static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w_es1
= {
614 .hs400_disabled
= true,
618 static const struct renesas_sdhi_quirks sdhi_quirks_h3_es2
= {
619 .hs400_disabled
= false,
623 static const struct soc_device_attribute sdhi_quirks_match
[] = {
624 { .soc_id
= "r8a7795", .revision
= "ES1.*", .data
= &sdhi_quirks_h3_m3w_es1
},
625 { .soc_id
= "r8a7795", .revision
= "ES2.0", .data
= &sdhi_quirks_h3_es2
},
626 { .soc_id
= "r8a7796", .revision
= "ES1.0", .data
= &sdhi_quirks_h3_m3w_es1
},
627 { .soc_id
= "r8a7796", .revision
= "ES1.1", .data
= &sdhi_quirks_h3_m3w_es1
},
631 int renesas_sdhi_probe(struct platform_device
*pdev
,
632 const struct tmio_mmc_dma_ops
*dma_ops
)
634 struct tmio_mmc_data
*mmd
= pdev
->dev
.platform_data
;
635 const struct renesas_sdhi_quirks
*quirks
= NULL
;
636 const struct renesas_sdhi_of_data
*of_data
;
637 const struct soc_device_attribute
*attr
;
638 struct tmio_mmc_data
*mmc_data
;
639 struct tmio_mmc_dma
*dma_priv
;
640 struct tmio_mmc_host
*host
;
641 struct renesas_sdhi
*priv
;
642 struct resource
*res
;
646 of_data
= of_device_get_match_data(&pdev
->dev
);
648 attr
= soc_device_match(sdhi_quirks_match
);
652 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
656 priv
= devm_kzalloc(&pdev
->dev
, sizeof(struct renesas_sdhi
),
661 mmc_data
= &priv
->mmc_data
;
662 dma_priv
= &priv
->dma_priv
;
664 priv
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
665 if (IS_ERR(priv
->clk
)) {
666 ret
= PTR_ERR(priv
->clk
);
667 dev_err(&pdev
->dev
, "cannot get clock: %d\n", ret
);
672 * Some controllers provide a 2nd clock just to run the internal card
673 * detection logic. Unfortunately, the existing driver architecture does
674 * not support a separation of clocks for runtime PM usage. When
675 * native hotplug is used, the tmio driver assumes that the core
676 * must continue to run for card detect to stay active, so we cannot
678 * Additionally, it is prohibited to supply a clock to the core but not
679 * to the card detect circuit. That leaves us with if separate clocks
680 * are presented, we must treat them both as virtually 1 clock.
682 priv
->clk_cd
= devm_clk_get(&pdev
->dev
, "cd");
683 if (IS_ERR(priv
->clk_cd
))
686 priv
->pinctrl
= devm_pinctrl_get(&pdev
->dev
);
687 if (!IS_ERR(priv
->pinctrl
)) {
688 priv
->pins_default
= pinctrl_lookup_state(priv
->pinctrl
,
689 PINCTRL_STATE_DEFAULT
);
690 priv
->pins_uhs
= pinctrl_lookup_state(priv
->pinctrl
,
694 host
= tmio_mmc_host_alloc(pdev
, mmc_data
);
696 return PTR_ERR(host
);
699 mmc_data
->flags
|= of_data
->tmio_flags
;
700 mmc_data
->ocr_mask
= of_data
->tmio_ocr_mask
;
701 mmc_data
->capabilities
|= of_data
->capabilities
;
702 mmc_data
->capabilities2
|= of_data
->capabilities2
;
703 mmc_data
->dma_rx_offset
= of_data
->dma_rx_offset
;
704 mmc_data
->max_blk_count
= of_data
->max_blk_count
;
705 mmc_data
->max_segs
= of_data
->max_segs
;
706 dma_priv
->dma_buswidth
= of_data
->dma_buswidth
;
707 host
->bus_shift
= of_data
->bus_shift
;
710 host
->write16_hook
= renesas_sdhi_write16_hook
;
711 host
->clk_enable
= renesas_sdhi_clk_enable
;
712 host
->clk_disable
= renesas_sdhi_clk_disable
;
713 host
->set_clock
= renesas_sdhi_set_clock
;
714 host
->multi_io_quirk
= renesas_sdhi_multi_io_quirk
;
715 host
->dma_ops
= dma_ops
;
717 if (quirks
&& quirks
->hs400_disabled
)
718 host
->mmc
->caps2
&= ~(MMC_CAP2_HS400
| MMC_CAP2_HS400_ES
);
720 if (quirks
&& quirks
->hs400_4taps
)
721 mmc_data
->flags
|= TMIO_MMC_HAVE_4TAP_HS400
;
723 /* For some SoC, we disable internal WP. GPIO may override this */
724 if (mmc_can_gpio_ro(host
->mmc
))
725 mmc_data
->capabilities2
&= ~MMC_CAP2_NO_WRITE_PROTECT
;
727 /* SDR speeds are only available on Gen2+ */
728 if (mmc_data
->flags
& TMIO_MMC_MIN_RCAR2
) {
729 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
730 host
->ops
.card_busy
= renesas_sdhi_card_busy
;
731 host
->ops
.start_signal_voltage_switch
=
732 renesas_sdhi_start_signal_voltage_switch
;
733 host
->sdcard_irq_setbit_mask
= TMIO_STAT_ALWAYS_SET_27
;
735 /* SDR and HS200/400 registers requires HW reset */
736 if (of_data
&& of_data
->scc_offset
) {
737 priv
->scc_ctl
= host
->ctl
+ of_data
->scc_offset
;
738 host
->mmc
->caps
|= MMC_CAP_HW_RESET
;
739 host
->hw_reset
= renesas_sdhi_hw_reset
;
743 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
744 if (!host
->bus_shift
&& resource_size(res
) > 0x100) /* old way to determine the shift */
750 dma_priv
->filter
= shdma_chan_filter
;
751 dma_priv
->enable
= renesas_sdhi_enable_dma
;
753 mmc_data
->alignment_shift
= 1; /* 2-byte alignment */
754 mmc_data
->capabilities
|= MMC_CAP_MMC_HIGHSPEED
;
757 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
760 mmc_data
->flags
|= TMIO_MMC_BLKSZ_2BYTES
;
763 * All SDHI blocks support SDIO IRQ signalling.
765 mmc_data
->flags
|= TMIO_MMC_SDIO_IRQ
;
767 /* All SDHI have CMD12 control bit */
768 mmc_data
->flags
|= TMIO_MMC_HAVE_CMD12_CTRL
;
770 /* All SDHI have SDIO status bits which must be 1 */
771 mmc_data
->flags
|= TMIO_MMC_SDIO_STATUS_SETBITS
;
773 ret
= renesas_sdhi_clk_enable(host
);
777 ver
= sd_ctrl_read16(host
, CTL_VERSION
);
778 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
779 if (ver
< SDHI_VER_GEN2_SDR104
&& mmc_data
->max_blk_count
> U16_MAX
)
780 mmc_data
->max_blk_count
= U16_MAX
;
782 ret
= tmio_mmc_host_probe(host
);
786 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
787 if (ver
== SDHI_VER_GEN2_SDR50
)
788 mmc_data
->flags
&= ~TMIO_MMC_HAVE_CBSY
;
790 /* Enable tuning iff we have an SCC and a supported mode */
791 if (of_data
&& of_data
->scc_offset
&&
792 (host
->mmc
->caps
& MMC_CAP_UHS_SDR104
||
793 host
->mmc
->caps2
& (MMC_CAP2_HS200_1_8V_SDR
|
794 MMC_CAP2_HS400_1_8V
))) {
795 const struct renesas_sdhi_scc
*taps
= of_data
->taps
;
798 for (i
= 0; i
< of_data
->taps_num
; i
++) {
799 if (taps
[i
].clk_rate
== 0 ||
800 taps
[i
].clk_rate
== host
->mmc
->f_max
) {
801 priv
->scc_tappos
= taps
->tap
;
802 priv
->scc_tappos_hs400
= taps
->tap_hs400
;
809 dev_warn(&host
->pdev
->dev
, "Unknown clock rate for SDR104\n");
811 host
->init_tuning
= renesas_sdhi_init_tuning
;
812 host
->prepare_tuning
= renesas_sdhi_prepare_tuning
;
813 host
->select_tuning
= renesas_sdhi_select_tuning
;
814 host
->check_scc_error
= renesas_sdhi_check_scc_error
;
815 host
->prepare_hs400_tuning
=
816 renesas_sdhi_prepare_hs400_tuning
;
817 host
->hs400_downgrade
= renesas_sdhi_disable_scc
;
818 host
->hs400_complete
= renesas_sdhi_hs400_complete
;
823 irq
= platform_get_irq(pdev
, i
);
827 ret
= devm_request_irq(&pdev
->dev
, irq
, tmio_mmc_irq
, 0,
828 dev_name(&pdev
->dev
), host
);
833 /* There must be at least one IRQ source */
839 dev_info(&pdev
->dev
, "%s base at 0x%08lx max clock rate %u MHz\n",
840 mmc_hostname(host
->mmc
), (unsigned long)
841 (platform_get_resource(pdev
, IORESOURCE_MEM
, 0)->start
),
842 host
->mmc
->f_max
/ 1000000);
847 tmio_mmc_host_remove(host
);
849 renesas_sdhi_clk_disable(host
);
851 tmio_mmc_host_free(host
);
855 EXPORT_SYMBOL_GPL(renesas_sdhi_probe
);
857 int renesas_sdhi_remove(struct platform_device
*pdev
)
859 struct tmio_mmc_host
*host
= platform_get_drvdata(pdev
);
861 tmio_mmc_host_remove(host
);
862 renesas_sdhi_clk_disable(host
);
866 EXPORT_SYMBOL_GPL(renesas_sdhi_remove
);
868 MODULE_LICENSE("GPL v2");