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[mirror_ubuntu-jammy-kernel.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Realtek PCI-Express SD/MMC Card Interface driver
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10 #include <linux/module.h>
11 #include <linux/slab.h>
12 #include <linux/highmem.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/workqueue.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/mmc.h>
18 #include <linux/mmc/sd.h>
19 #include <linux/mmc/sdio.h>
20 #include <linux/mmc/card.h>
21 #include <linux/rtsx_pci.h>
22 #include <asm/unaligned.h>
23 #include <linux/pm_runtime.h>
24
25 struct realtek_pci_sdmmc {
26 struct platform_device *pdev;
27 struct rtsx_pcr *pcr;
28 struct mmc_host *mmc;
29 struct mmc_request *mrq;
30 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
31
32 struct work_struct work;
33 struct mutex host_mutex;
34
35 u8 ssc_depth;
36 unsigned int clock;
37 bool vpclk;
38 bool double_clk;
39 bool eject;
40 bool initial_mode;
41 int prev_power_state;
42 int sg_count;
43 s32 cookie;
44 int cookie_sg_count;
45 bool using_cookie;
46 };
47
48 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios);
49
50 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
51 {
52 return &(host->pdev->dev);
53 }
54
55 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
56 {
57 rtsx_pci_write_register(host->pcr, CARD_STOP,
58 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
59 }
60
61 #ifdef DEBUG
62 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
63 {
64 u16 len = end - start + 1;
65 int i;
66 u8 data[8];
67
68 for (i = 0; i < len; i += 8) {
69 int j;
70 int n = min(8, len - i);
71
72 memset(&data, 0, sizeof(data));
73 for (j = 0; j < n; j++)
74 rtsx_pci_read_register(host->pcr, start + i + j,
75 data + j);
76 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
77 start + i, n, data);
78 }
79 }
80
81 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
82 {
83 dump_reg_range(host, 0xFDA0, 0xFDB3);
84 dump_reg_range(host, 0xFD52, 0xFD69);
85 }
86 #else
87 #define sd_print_debug_regs(host)
88 #endif /* DEBUG */
89
90 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
91 {
92 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
93 }
94
95 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
96 {
97 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
98 SD_CMD_START | cmd->opcode);
99 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
100 }
101
102 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
103 {
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
108 }
109
110 static int sd_response_type(struct mmc_command *cmd)
111 {
112 switch (mmc_resp_type(cmd)) {
113 case MMC_RSP_NONE:
114 return SD_RSP_TYPE_R0;
115 case MMC_RSP_R1:
116 return SD_RSP_TYPE_R1;
117 case MMC_RSP_R1_NO_CRC:
118 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
119 case MMC_RSP_R1B:
120 return SD_RSP_TYPE_R1b;
121 case MMC_RSP_R2:
122 return SD_RSP_TYPE_R2;
123 case MMC_RSP_R3:
124 return SD_RSP_TYPE_R3;
125 default:
126 return -EINVAL;
127 }
128 }
129
130 static int sd_status_index(int resp_type)
131 {
132 if (resp_type == SD_RSP_TYPE_R0)
133 return 0;
134 else if (resp_type == SD_RSP_TYPE_R2)
135 return 16;
136
137 return 5;
138 }
139 /*
140 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
141 *
142 * @pre: if called in pre_req()
143 * return:
144 * 0 - do dma_map_sg()
145 * 1 - using cookie
146 */
147 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
148 struct mmc_data *data, bool pre)
149 {
150 struct rtsx_pcr *pcr = host->pcr;
151 int read = data->flags & MMC_DATA_READ;
152 int count = 0;
153 int using_cookie = 0;
154
155 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
156 dev_err(sdmmc_dev(host),
157 "error: data->host_cookie = %d, host->cookie = %d\n",
158 data->host_cookie, host->cookie);
159 data->host_cookie = 0;
160 }
161
162 if (pre || data->host_cookie != host->cookie) {
163 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
164 } else {
165 count = host->cookie_sg_count;
166 using_cookie = 1;
167 }
168
169 if (pre) {
170 host->cookie_sg_count = count;
171 if (++host->cookie < 0)
172 host->cookie = 1;
173 data->host_cookie = host->cookie;
174 } else {
175 host->sg_count = count;
176 }
177
178 return using_cookie;
179 }
180
181 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
182 {
183 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
184 struct mmc_data *data = mrq->data;
185
186 if (data->host_cookie) {
187 dev_err(sdmmc_dev(host),
188 "error: reset data->host_cookie = %d\n",
189 data->host_cookie);
190 data->host_cookie = 0;
191 }
192
193 sd_pre_dma_transfer(host, data, true);
194 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
195 }
196
197 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
198 int err)
199 {
200 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
201 struct rtsx_pcr *pcr = host->pcr;
202 struct mmc_data *data = mrq->data;
203 int read = data->flags & MMC_DATA_READ;
204
205 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
206 data->host_cookie = 0;
207 }
208
209 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
210 struct mmc_command *cmd)
211 {
212 struct rtsx_pcr *pcr = host->pcr;
213 u8 cmd_idx = (u8)cmd->opcode;
214 u32 arg = cmd->arg;
215 int err = 0;
216 int timeout = 100;
217 int i;
218 u8 *ptr;
219 int rsp_type;
220 int stat_idx;
221 bool clock_toggled = false;
222
223 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
224 __func__, cmd_idx, arg);
225
226 rsp_type = sd_response_type(cmd);
227 if (rsp_type < 0)
228 goto out;
229
230 stat_idx = sd_status_index(rsp_type);
231
232 if (rsp_type == SD_RSP_TYPE_R1b)
233 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
234
235 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
236 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
237 0xFF, SD_CLK_TOGGLE_EN);
238 if (err < 0)
239 goto out;
240
241 clock_toggled = true;
242 }
243
244 rtsx_pci_init_cmd(pcr);
245 sd_cmd_set_sd_cmd(pcr, cmd);
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
248 0x01, PINGPONG_BUFFER);
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
250 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
251 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
252 SD_TRANSFER_END | SD_STAT_IDLE,
253 SD_TRANSFER_END | SD_STAT_IDLE);
254
255 if (rsp_type == SD_RSP_TYPE_R2) {
256 /* Read data from ping-pong buffer */
257 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
258 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
259 } else if (rsp_type != SD_RSP_TYPE_R0) {
260 /* Read data from SD_CMDx registers */
261 for (i = SD_CMD0; i <= SD_CMD4; i++)
262 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
263 }
264
265 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
266
267 err = rtsx_pci_send_cmd(pcr, timeout);
268 if (err < 0) {
269 sd_print_debug_regs(host);
270 sd_clear_error(host);
271 dev_dbg(sdmmc_dev(host),
272 "rtsx_pci_send_cmd error (err = %d)\n", err);
273 goto out;
274 }
275
276 if (rsp_type == SD_RSP_TYPE_R0) {
277 err = 0;
278 goto out;
279 }
280
281 /* Eliminate returned value of CHECK_REG_CMD */
282 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
283
284 /* Check (Start,Transmission) bit of Response */
285 if ((ptr[0] & 0xC0) != 0) {
286 err = -EILSEQ;
287 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
288 goto out;
289 }
290
291 /* Check CRC7 */
292 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
293 if (ptr[stat_idx] & SD_CRC7_ERR) {
294 err = -EILSEQ;
295 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
296 goto out;
297 }
298 }
299
300 if (rsp_type == SD_RSP_TYPE_R2) {
301 /*
302 * The controller offloads the last byte {CRC-7, end bit 1'b1}
303 * of response type R2. Assign dummy CRC, 0, and end bit to the
304 * byte(ptr[16], goes into the LSB of resp[3] later).
305 */
306 ptr[16] = 1;
307
308 for (i = 0; i < 4; i++) {
309 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
310 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
311 i, cmd->resp[i]);
312 }
313 } else {
314 cmd->resp[0] = get_unaligned_be32(ptr + 1);
315 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
316 cmd->resp[0]);
317 }
318
319 out:
320 cmd->error = err;
321
322 if (err && clock_toggled)
323 rtsx_pci_write_register(pcr, SD_BUS_STAT,
324 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
325 }
326
327 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
328 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
329 {
330 struct rtsx_pcr *pcr = host->pcr;
331 int err;
332 u8 trans_mode;
333
334 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
335 __func__, cmd->opcode, cmd->arg);
336
337 if (!buf)
338 buf_len = 0;
339
340 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
341 trans_mode = SD_TM_AUTO_TUNING;
342 else
343 trans_mode = SD_TM_NORMAL_READ;
344
345 rtsx_pci_init_cmd(pcr);
346 sd_cmd_set_sd_cmd(pcr, cmd);
347 sd_cmd_set_data_len(pcr, 1, byte_cnt);
348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
349 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
350 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
351 if (trans_mode != SD_TM_AUTO_TUNING)
352 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
353 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
354
355 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
356 0xFF, trans_mode | SD_TRANSFER_START);
357 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
358 SD_TRANSFER_END, SD_TRANSFER_END);
359
360 err = rtsx_pci_send_cmd(pcr, timeout);
361 if (err < 0) {
362 sd_print_debug_regs(host);
363 dev_dbg(sdmmc_dev(host),
364 "rtsx_pci_send_cmd fail (err = %d)\n", err);
365 return err;
366 }
367
368 if (buf && buf_len) {
369 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
370 if (err < 0) {
371 dev_dbg(sdmmc_dev(host),
372 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
373 return err;
374 }
375 }
376
377 return 0;
378 }
379
380 static int sd_write_data(struct realtek_pci_sdmmc *host,
381 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
382 int timeout)
383 {
384 struct rtsx_pcr *pcr = host->pcr;
385 int err;
386
387 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
388 __func__, cmd->opcode, cmd->arg);
389
390 if (!buf)
391 buf_len = 0;
392
393 sd_send_cmd_get_rsp(host, cmd);
394 if (cmd->error)
395 return cmd->error;
396
397 if (buf && buf_len) {
398 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
399 if (err < 0) {
400 dev_dbg(sdmmc_dev(host),
401 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
402 return err;
403 }
404 }
405
406 rtsx_pci_init_cmd(pcr);
407 sd_cmd_set_data_len(pcr, 1, byte_cnt);
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
409 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
410 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
412 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
413 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
414 SD_TRANSFER_END, SD_TRANSFER_END);
415
416 err = rtsx_pci_send_cmd(pcr, timeout);
417 if (err < 0) {
418 sd_print_debug_regs(host);
419 dev_dbg(sdmmc_dev(host),
420 "rtsx_pci_send_cmd fail (err = %d)\n", err);
421 return err;
422 }
423
424 return 0;
425 }
426
427 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
428 struct mmc_request *mrq)
429 {
430 struct rtsx_pcr *pcr = host->pcr;
431 struct mmc_host *mmc = host->mmc;
432 struct mmc_card *card = mmc->card;
433 struct mmc_command *cmd = mrq->cmd;
434 struct mmc_data *data = mrq->data;
435 int uhs = mmc_card_uhs(card);
436 u8 cfg2 = 0;
437 int err;
438 int resp_type;
439 size_t data_len = data->blksz * data->blocks;
440
441 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
442 __func__, cmd->opcode, cmd->arg);
443
444 resp_type = sd_response_type(cmd);
445 if (resp_type < 0)
446 return resp_type;
447
448 if (!uhs)
449 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
450
451 rtsx_pci_init_cmd(pcr);
452 sd_cmd_set_sd_cmd(pcr, cmd);
453 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
454 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
455 DMA_DONE_INT, DMA_DONE_INT);
456 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
457 0xFF, (u8)(data_len >> 24));
458 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
459 0xFF, (u8)(data_len >> 16));
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
461 0xFF, (u8)(data_len >> 8));
462 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
464 0x03 | DMA_PACK_SIZE_MASK,
465 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
467 0x01, RING_BUFFER);
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
470 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
471 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
472 SD_TRANSFER_END, SD_TRANSFER_END);
473 rtsx_pci_send_cmd_no_wait(pcr);
474
475 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
476 if (err < 0) {
477 sd_print_debug_regs(host);
478 sd_clear_error(host);
479 return err;
480 }
481
482 return 0;
483 }
484
485 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
486 struct mmc_request *mrq)
487 {
488 struct rtsx_pcr *pcr = host->pcr;
489 struct mmc_host *mmc = host->mmc;
490 struct mmc_card *card = mmc->card;
491 struct mmc_command *cmd = mrq->cmd;
492 struct mmc_data *data = mrq->data;
493 int uhs = mmc_card_uhs(card);
494 u8 cfg2;
495 int err;
496 size_t data_len = data->blksz * data->blocks;
497
498 sd_send_cmd_get_rsp(host, cmd);
499 if (cmd->error)
500 return cmd->error;
501
502 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
503 __func__, cmd->opcode, cmd->arg);
504
505 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
506 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
507
508 if (!uhs)
509 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
510
511 rtsx_pci_init_cmd(pcr);
512 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
513 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
514 DMA_DONE_INT, DMA_DONE_INT);
515 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
516 0xFF, (u8)(data_len >> 24));
517 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
518 0xFF, (u8)(data_len >> 16));
519 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
520 0xFF, (u8)(data_len >> 8));
521 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
523 0x03 | DMA_PACK_SIZE_MASK,
524 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
526 0x01, RING_BUFFER);
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
529 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
530 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
531 SD_TRANSFER_END, SD_TRANSFER_END);
532 rtsx_pci_send_cmd_no_wait(pcr);
533 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
534 if (err < 0) {
535 sd_clear_error(host);
536 return err;
537 }
538
539 return 0;
540 }
541
542 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
543 {
544 rtsx_pci_write_register(host->pcr, SD_CFG1,
545 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
546 }
547
548 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
549 {
550 rtsx_pci_write_register(host->pcr, SD_CFG1,
551 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
552 }
553
554 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
555 {
556 struct mmc_data *data = mrq->data;
557 int err;
558
559 if (host->sg_count < 0) {
560 data->error = host->sg_count;
561 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
562 __func__, host->sg_count);
563 return data->error;
564 }
565
566 if (data->flags & MMC_DATA_READ) {
567 if (host->initial_mode)
568 sd_disable_initial_mode(host);
569
570 err = sd_read_long_data(host, mrq);
571
572 if (host->initial_mode)
573 sd_enable_initial_mode(host);
574
575 return err;
576 }
577
578 return sd_write_long_data(host, mrq);
579 }
580
581 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
582 struct mmc_request *mrq)
583 {
584 struct mmc_command *cmd = mrq->cmd;
585 struct mmc_data *data = mrq->data;
586 u8 *buf;
587
588 buf = kzalloc(data->blksz, GFP_NOIO);
589 if (!buf) {
590 cmd->error = -ENOMEM;
591 return;
592 }
593
594 if (data->flags & MMC_DATA_READ) {
595 if (host->initial_mode)
596 sd_disable_initial_mode(host);
597
598 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
599 data->blksz, 200);
600
601 if (host->initial_mode)
602 sd_enable_initial_mode(host);
603
604 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
605 } else {
606 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
607
608 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
609 data->blksz, 200);
610 }
611
612 kfree(buf);
613 }
614
615 static int sd_change_phase(struct realtek_pci_sdmmc *host,
616 u8 sample_point, bool rx)
617 {
618 struct rtsx_pcr *pcr = host->pcr;
619 u16 SD_VP_CTL = 0;
620 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
621 __func__, rx ? "RX" : "TX", sample_point);
622
623 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
624 if (rx) {
625 SD_VP_CTL = SD_VPRX_CTL;
626 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
627 PHASE_SELECT_MASK, sample_point);
628 } else {
629 SD_VP_CTL = SD_VPTX_CTL;
630 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
631 PHASE_SELECT_MASK, sample_point);
632 }
633 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
634 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
635 PHASE_NOT_RESET);
636 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
637 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
638
639 return 0;
640 }
641
642 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
643 {
644 bit %= RTSX_PHASE_MAX;
645 return phase_map & (1 << bit);
646 }
647
648 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
649 {
650 int i;
651
652 for (i = 0; i < RTSX_PHASE_MAX; i++) {
653 if (test_phase_bit(phase_map, start_bit + i) == 0)
654 return i;
655 }
656 return RTSX_PHASE_MAX;
657 }
658
659 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
660 {
661 int start = 0, len = 0;
662 int start_final = 0, len_final = 0;
663 u8 final_phase = 0xFF;
664
665 if (phase_map == 0) {
666 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
667 return final_phase;
668 }
669
670 while (start < RTSX_PHASE_MAX) {
671 len = sd_get_phase_len(phase_map, start);
672 if (len_final < len) {
673 start_final = start;
674 len_final = len;
675 }
676 start += len ? len : 1;
677 }
678
679 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
680 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
681 phase_map, len_final, final_phase);
682
683 return final_phase;
684 }
685
686 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
687 {
688 int i;
689 u8 val = 0;
690
691 for (i = 0; i < 100; i++) {
692 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
693 if (val & SD_DATA_IDLE)
694 return;
695
696 udelay(100);
697 }
698 }
699
700 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
701 u8 opcode, u8 sample_point)
702 {
703 int err;
704 struct mmc_command cmd = {};
705 struct rtsx_pcr *pcr = host->pcr;
706
707 sd_change_phase(host, sample_point, true);
708
709 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
710 SD_RSP_80CLK_TIMEOUT_EN);
711
712 cmd.opcode = opcode;
713 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
714 if (err < 0) {
715 /* Wait till SD DATA IDLE */
716 sd_wait_data_idle(host);
717 sd_clear_error(host);
718 rtsx_pci_write_register(pcr, SD_CFG3,
719 SD_RSP_80CLK_TIMEOUT_EN, 0);
720 return err;
721 }
722
723 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
724 return 0;
725 }
726
727 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
728 u8 opcode, u32 *phase_map)
729 {
730 int err, i;
731 u32 raw_phase_map = 0;
732
733 for (i = 0; i < RTSX_PHASE_MAX; i++) {
734 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
735 if (err == 0)
736 raw_phase_map |= 1 << i;
737 }
738
739 if (phase_map)
740 *phase_map = raw_phase_map;
741
742 return 0;
743 }
744
745 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
746 {
747 int err, i;
748 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
749 u8 final_phase;
750
751 for (i = 0; i < RX_TUNING_CNT; i++) {
752 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
753 if (err < 0)
754 return err;
755
756 if (raw_phase_map[i] == 0)
757 break;
758 }
759
760 phase_map = 0xFFFFFFFF;
761 for (i = 0; i < RX_TUNING_CNT; i++) {
762 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
763 i, raw_phase_map[i]);
764 phase_map &= raw_phase_map[i];
765 }
766 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
767
768 if (phase_map) {
769 final_phase = sd_search_final_phase(host, phase_map);
770 if (final_phase == 0xFF)
771 return -EINVAL;
772
773 err = sd_change_phase(host, final_phase, true);
774 if (err < 0)
775 return err;
776 } else {
777 return -EINVAL;
778 }
779
780 return 0;
781 }
782
783 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
784 struct mmc_data *data)
785 {
786 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
787 }
788
789 static inline int sd_rw_cmd(struct mmc_command *cmd)
790 {
791 return mmc_op_multi(cmd->opcode) ||
792 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
793 (cmd->opcode == MMC_WRITE_BLOCK);
794 }
795
796 static void sd_request(struct work_struct *work)
797 {
798 struct realtek_pci_sdmmc *host = container_of(work,
799 struct realtek_pci_sdmmc, work);
800 struct rtsx_pcr *pcr = host->pcr;
801
802 struct mmc_host *mmc = host->mmc;
803 struct mmc_request *mrq = host->mrq;
804 struct mmc_command *cmd = mrq->cmd;
805 struct mmc_data *data = mrq->data;
806 struct device *dev = &host->pdev->dev;
807
808 unsigned int data_size = 0;
809 int err;
810
811 if (host->eject || !sd_get_cd_int(host)) {
812 cmd->error = -ENOMEDIUM;
813 goto finish;
814 }
815
816 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
817 if (err) {
818 cmd->error = err;
819 goto finish;
820 }
821
822 mutex_lock(&pcr->pcr_mutex);
823 pm_runtime_get_sync(dev);
824
825 rtsx_pci_start_run(pcr);
826
827 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
828 host->initial_mode, host->double_clk, host->vpclk);
829 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
830 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
831 CARD_SHARE_MASK, CARD_SHARE_48_SD);
832
833 mutex_lock(&host->host_mutex);
834 host->mrq = mrq;
835 mutex_unlock(&host->host_mutex);
836
837 if (mrq->data)
838 data_size = data->blocks * data->blksz;
839
840 if (!data_size) {
841 sd_send_cmd_get_rsp(host, cmd);
842 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
843 cmd->error = sd_rw_multi(host, mrq);
844 if (!host->using_cookie)
845 sdmmc_post_req(host->mmc, host->mrq, 0);
846
847 if (mmc_op_multi(cmd->opcode) && mrq->stop)
848 sd_send_cmd_get_rsp(host, mrq->stop);
849 } else {
850 sd_normal_rw(host, mrq);
851 }
852
853 if (mrq->data) {
854 if (cmd->error || data->error)
855 data->bytes_xfered = 0;
856 else
857 data->bytes_xfered = data->blocks * data->blksz;
858 }
859
860 pm_runtime_mark_last_busy(dev);
861 pm_runtime_put_autosuspend(dev);
862 mutex_unlock(&pcr->pcr_mutex);
863
864 finish:
865 if (cmd->error) {
866 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
867 cmd->opcode, cmd->arg, cmd->error);
868 }
869
870 mutex_lock(&host->host_mutex);
871 host->mrq = NULL;
872 mutex_unlock(&host->host_mutex);
873
874 mmc_request_done(mmc, mrq);
875 }
876
877 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
878 {
879 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
880 struct mmc_data *data = mrq->data;
881
882 mutex_lock(&host->host_mutex);
883 host->mrq = mrq;
884 mutex_unlock(&host->host_mutex);
885
886 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
887 host->using_cookie = sd_pre_dma_transfer(host, data, false);
888
889 schedule_work(&host->work);
890 }
891
892 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
893 unsigned char bus_width)
894 {
895 int err = 0;
896 u8 width[] = {
897 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
898 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
899 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
900 };
901
902 if (bus_width <= MMC_BUS_WIDTH_8)
903 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
904 0x03, width[bus_width]);
905
906 return err;
907 }
908
909 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
910 {
911 struct rtsx_pcr *pcr = host->pcr;
912 struct mmc_host *mmc = host->mmc;
913 int err;
914 u32 val;
915 u8 test_mode;
916
917 if (host->prev_power_state == MMC_POWER_ON)
918 return 0;
919
920 if (host->prev_power_state == MMC_POWER_UP) {
921 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
922 goto finish;
923 }
924
925 msleep(100);
926
927 rtsx_pci_init_cmd(pcr);
928 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
929 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
930 CARD_SHARE_MASK, CARD_SHARE_48_SD);
931 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
932 SD_CLK_EN, SD_CLK_EN);
933 err = rtsx_pci_send_cmd(pcr, 100);
934 if (err < 0)
935 return err;
936
937 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
938 if (err < 0)
939 return err;
940
941 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
942 if (err < 0)
943 return err;
944
945 mdelay(1);
946
947 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
948 if (err < 0)
949 return err;
950
951 /* send at least 74 clocks */
952 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
953
954 if (PCI_PID(pcr) == PID_5261) {
955 /*
956 * If test mode is set switch to SD Express mandatorily,
957 * this is only for factory testing.
958 */
959 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
960 if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) {
961 sdmmc_init_sd_express(mmc, NULL);
962 return 0;
963 }
964 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
965 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
966 /*
967 * HW read wp status when resuming from S3/S4,
968 * and then picks SD legacy interface if it's set
969 * in read-only mode.
970 */
971 val = rtsx_pci_readl(pcr, RTSX_BIPR);
972 if (val & SD_WRITE_PROTECT) {
973 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
974 mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V);
975 }
976 }
977
978 finish:
979 host->prev_power_state = power_mode;
980 return 0;
981 }
982
983 static int sd_power_off(struct realtek_pci_sdmmc *host)
984 {
985 struct rtsx_pcr *pcr = host->pcr;
986 int err;
987
988 host->prev_power_state = MMC_POWER_OFF;
989
990 rtsx_pci_init_cmd(pcr);
991
992 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
993 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
994
995 err = rtsx_pci_send_cmd(pcr, 100);
996 if (err < 0)
997 return err;
998
999 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1000 if (err < 0)
1001 return err;
1002
1003 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1004 }
1005
1006 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
1007 unsigned char power_mode)
1008 {
1009 int err;
1010
1011 if (power_mode == MMC_POWER_OFF)
1012 err = sd_power_off(host);
1013 else
1014 err = sd_power_on(host, power_mode);
1015
1016 return err;
1017 }
1018
1019 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
1020 {
1021 struct rtsx_pcr *pcr = host->pcr;
1022 int err = 0;
1023
1024 rtsx_pci_init_cmd(pcr);
1025
1026 switch (timing) {
1027 case MMC_TIMING_UHS_SDR104:
1028 case MMC_TIMING_UHS_SDR50:
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1030 0x0C | SD_ASYNC_FIFO_NOT_RST,
1031 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1033 CLK_LOW_FREQ, CLK_LOW_FREQ);
1034 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1035 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1037 break;
1038
1039 case MMC_TIMING_MMC_DDR52:
1040 case MMC_TIMING_UHS_DDR50:
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1042 0x0C | SD_ASYNC_FIFO_NOT_RST,
1043 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1045 CLK_LOW_FREQ, CLK_LOW_FREQ);
1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1047 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1048 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1049 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1050 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1051 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1052 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1053 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1054 break;
1055
1056 case MMC_TIMING_MMC_HS:
1057 case MMC_TIMING_SD_HS:
1058 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1059 0x0C, SD_20_MODE);
1060 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1061 CLK_LOW_FREQ, CLK_LOW_FREQ);
1062 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1063 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1064 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1065 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1066 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1067 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1068 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1069 break;
1070
1071 default:
1072 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1073 SD_CFG1, 0x0C, SD_20_MODE);
1074 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1075 CLK_LOW_FREQ, CLK_LOW_FREQ);
1076 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1077 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1078 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1079 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1080 SD_PUSH_POINT_CTL, 0xFF, 0);
1081 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1082 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1083 break;
1084 }
1085
1086 err = rtsx_pci_send_cmd(pcr, 100);
1087
1088 return err;
1089 }
1090
1091 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1092 {
1093 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1094 struct rtsx_pcr *pcr = host->pcr;
1095 struct device *dev = &host->pdev->dev;
1096
1097 if (host->eject)
1098 return;
1099
1100 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1101 return;
1102
1103 mutex_lock(&pcr->pcr_mutex);
1104 pm_runtime_get_sync(dev);
1105
1106 rtsx_pci_start_run(pcr);
1107
1108 sd_set_bus_width(host, ios->bus_width);
1109 sd_set_power_mode(host, ios->power_mode);
1110 sd_set_timing(host, ios->timing);
1111
1112 host->vpclk = false;
1113 host->double_clk = true;
1114
1115 switch (ios->timing) {
1116 case MMC_TIMING_UHS_SDR104:
1117 case MMC_TIMING_UHS_SDR50:
1118 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1119 host->vpclk = true;
1120 host->double_clk = false;
1121 break;
1122 case MMC_TIMING_MMC_DDR52:
1123 case MMC_TIMING_UHS_DDR50:
1124 case MMC_TIMING_UHS_SDR25:
1125 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1126 break;
1127 default:
1128 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1129 break;
1130 }
1131
1132 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1133
1134 host->clock = ios->clock;
1135 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1136 host->initial_mode, host->double_clk, host->vpclk);
1137
1138 pm_runtime_mark_last_busy(dev);
1139 pm_runtime_put_autosuspend(dev);
1140 mutex_unlock(&pcr->pcr_mutex);
1141 }
1142
1143 static int sdmmc_get_ro(struct mmc_host *mmc)
1144 {
1145 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1146 struct rtsx_pcr *pcr = host->pcr;
1147 struct device *dev = &host->pdev->dev;
1148 int ro = 0;
1149 u32 val;
1150
1151 if (host->eject)
1152 return -ENOMEDIUM;
1153
1154 mutex_lock(&pcr->pcr_mutex);
1155 pm_runtime_get_sync(dev);
1156
1157 rtsx_pci_start_run(pcr);
1158
1159 /* Check SD mechanical write-protect switch */
1160 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1161 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1162 if (val & SD_WRITE_PROTECT)
1163 ro = 1;
1164
1165 pm_runtime_mark_last_busy(dev);
1166 pm_runtime_put_autosuspend(dev);
1167 mutex_unlock(&pcr->pcr_mutex);
1168
1169 return ro;
1170 }
1171
1172 static int sdmmc_get_cd(struct mmc_host *mmc)
1173 {
1174 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1175 struct rtsx_pcr *pcr = host->pcr;
1176 struct device *dev = &host->pdev->dev;
1177 int cd = 0;
1178 u32 val;
1179
1180 if (host->eject)
1181 return cd;
1182
1183 mutex_lock(&pcr->pcr_mutex);
1184 pm_runtime_get_sync(dev);
1185
1186 rtsx_pci_start_run(pcr);
1187
1188 /* Check SD card detect */
1189 val = rtsx_pci_card_exist(pcr);
1190 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1191 if (val & SD_EXIST)
1192 cd = 1;
1193
1194 pm_runtime_mark_last_busy(dev);
1195 pm_runtime_put_autosuspend(dev);
1196 mutex_unlock(&pcr->pcr_mutex);
1197
1198 return cd;
1199 }
1200
1201 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1202 {
1203 struct rtsx_pcr *pcr = host->pcr;
1204 int err;
1205 u8 stat;
1206
1207 /* Reference to Signal Voltage Switch Sequence in SD spec.
1208 * Wait for a period of time so that the card can drive SD_CMD and
1209 * SD_DAT[3:0] to low after sending back CMD11 response.
1210 */
1211 mdelay(1);
1212
1213 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1214 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1215 * abort the voltage switch sequence;
1216 */
1217 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1218 if (err < 0)
1219 return err;
1220
1221 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1222 SD_DAT1_STATUS | SD_DAT0_STATUS))
1223 return -EINVAL;
1224
1225 /* Stop toggle SD clock */
1226 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1227 0xFF, SD_CLK_FORCE_STOP);
1228 if (err < 0)
1229 return err;
1230
1231 return 0;
1232 }
1233
1234 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1235 {
1236 struct rtsx_pcr *pcr = host->pcr;
1237 int err;
1238 u8 stat, mask, val;
1239
1240 /* Wait 1.8V output of voltage regulator in card stable */
1241 msleep(50);
1242
1243 /* Toggle SD clock again */
1244 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1245 if (err < 0)
1246 return err;
1247
1248 /* Wait for a period of time so that the card can drive
1249 * SD_DAT[3:0] to high at 1.8V
1250 */
1251 msleep(20);
1252
1253 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1254 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1255 if (err < 0)
1256 return err;
1257
1258 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1259 SD_DAT1_STATUS | SD_DAT0_STATUS;
1260 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1261 SD_DAT1_STATUS | SD_DAT0_STATUS;
1262 if ((stat & mask) != val) {
1263 dev_dbg(sdmmc_dev(host),
1264 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1265 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1266 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1267 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1268 return -EINVAL;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1275 {
1276 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1277 struct rtsx_pcr *pcr = host->pcr;
1278 struct device *dev = &host->pdev->dev;
1279 int err = 0;
1280 u8 voltage;
1281
1282 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1283 __func__, ios->signal_voltage);
1284
1285 if (host->eject)
1286 return -ENOMEDIUM;
1287
1288 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1289 if (err)
1290 return err;
1291
1292 mutex_lock(&pcr->pcr_mutex);
1293 pm_runtime_get_sync(dev);
1294
1295 rtsx_pci_start_run(pcr);
1296
1297 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1298 voltage = OUTPUT_3V3;
1299 else
1300 voltage = OUTPUT_1V8;
1301
1302 if (voltage == OUTPUT_1V8) {
1303 err = sd_wait_voltage_stable_1(host);
1304 if (err < 0)
1305 goto out;
1306 }
1307
1308 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1309 if (err < 0)
1310 goto out;
1311
1312 if (voltage == OUTPUT_1V8) {
1313 err = sd_wait_voltage_stable_2(host);
1314 if (err < 0)
1315 goto out;
1316 }
1317
1318 out:
1319 /* Stop toggle SD clock in idle */
1320 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1321 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1322
1323 pm_runtime_mark_last_busy(dev);
1324 pm_runtime_put_autosuspend(dev);
1325 mutex_unlock(&pcr->pcr_mutex);
1326
1327 return err;
1328 }
1329
1330 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1331 {
1332 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1333 struct rtsx_pcr *pcr = host->pcr;
1334 struct device *dev = &host->pdev->dev;
1335 int err = 0;
1336
1337 if (host->eject)
1338 return -ENOMEDIUM;
1339
1340 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1341 if (err)
1342 return err;
1343
1344 mutex_lock(&pcr->pcr_mutex);
1345 pm_runtime_get_sync(dev);
1346
1347 rtsx_pci_start_run(pcr);
1348
1349 /* Set initial TX phase */
1350 switch (mmc->ios.timing) {
1351 case MMC_TIMING_UHS_SDR104:
1352 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1353 break;
1354
1355 case MMC_TIMING_UHS_SDR50:
1356 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1357 break;
1358
1359 case MMC_TIMING_UHS_DDR50:
1360 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1361 break;
1362
1363 default:
1364 err = 0;
1365 }
1366
1367 if (err)
1368 goto out;
1369
1370 /* Tuning RX phase */
1371 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1372 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1373 err = sd_tuning_rx(host, opcode);
1374 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1375 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1376
1377 out:
1378 pm_runtime_mark_last_busy(dev);
1379 pm_runtime_put_autosuspend(dev);
1380 mutex_unlock(&pcr->pcr_mutex);
1381
1382 return err;
1383 }
1384
1385 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1386 {
1387 u32 relink_time;
1388 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1389 struct rtsx_pcr *pcr = host->pcr;
1390
1391 /* Set relink_time for changing to PCIe card */
1392 relink_time = 0x8FFF;
1393
1394 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
1395 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
1396 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
1397
1398 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
1399 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
1400 RTS5261_LDO1_OCP_THD_MASK,
1401 pcr->option.sd_800mA_ocp_thd);
1402
1403 if (pcr->ops->disable_auto_blink)
1404 pcr->ops->disable_auto_blink(pcr);
1405
1406 /* For PCIe/NVMe mode can't enter delink issue */
1407 pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
1408 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
1409
1410 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
1411 RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN);
1412 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
1413 RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS);
1414 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1415 RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING);
1416 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1417 RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK
1418 | RTS5261_DRIVER_ENABLE_FW,
1419 RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW);
1420 host->eject = true;
1421 return 0;
1422 }
1423
1424 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1425 .pre_req = sdmmc_pre_req,
1426 .post_req = sdmmc_post_req,
1427 .request = sdmmc_request,
1428 .set_ios = sdmmc_set_ios,
1429 .get_ro = sdmmc_get_ro,
1430 .get_cd = sdmmc_get_cd,
1431 .start_signal_voltage_switch = sdmmc_switch_voltage,
1432 .execute_tuning = sdmmc_execute_tuning,
1433 .init_sd_express = sdmmc_init_sd_express,
1434 };
1435
1436 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1437 {
1438 struct mmc_host *mmc = host->mmc;
1439 struct rtsx_pcr *pcr = host->pcr;
1440
1441 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1442
1443 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1444 mmc->caps |= MMC_CAP_UHS_SDR50;
1445 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1446 mmc->caps |= MMC_CAP_UHS_SDR104;
1447 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1448 mmc->caps |= MMC_CAP_UHS_DDR50;
1449 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1450 mmc->caps |= MMC_CAP_1_8V_DDR;
1451 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1452 mmc->caps |= MMC_CAP_8_BIT_DATA;
1453 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1454 mmc->caps2 |= MMC_CAP2_NO_MMC;
1455 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
1456 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
1457 }
1458
1459 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1460 {
1461 struct mmc_host *mmc = host->mmc;
1462 struct rtsx_pcr *pcr = host->pcr;
1463
1464 mmc->f_min = 250000;
1465 mmc->f_max = 208000000;
1466 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1467 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1468 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1469 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1470 if (pcr->rtd3_en)
1471 mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM;
1472 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE |
1473 MMC_CAP2_NO_SDIO;
1474 mmc->max_current_330 = 400;
1475 mmc->max_current_180 = 800;
1476 mmc->ops = &realtek_pci_sdmmc_ops;
1477
1478 init_extra_caps(host);
1479
1480 mmc->max_segs = 256;
1481 mmc->max_seg_size = 65536;
1482 mmc->max_blk_size = 512;
1483 mmc->max_blk_count = 65535;
1484 mmc->max_req_size = 524288;
1485 }
1486
1487 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1488 {
1489 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1490
1491 host->cookie = -1;
1492 mmc_detect_change(host->mmc, 0);
1493 }
1494
1495 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1496 {
1497 struct mmc_host *mmc;
1498 struct realtek_pci_sdmmc *host;
1499 struct rtsx_pcr *pcr;
1500 struct pcr_handle *handle = pdev->dev.platform_data;
1501
1502 if (!handle)
1503 return -ENXIO;
1504
1505 pcr = handle->pcr;
1506 if (!pcr)
1507 return -ENXIO;
1508
1509 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1510
1511 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1512 if (!mmc)
1513 return -ENOMEM;
1514
1515 host = mmc_priv(mmc);
1516 host->pcr = pcr;
1517 mmc->ios.power_delay_ms = 5;
1518 host->mmc = mmc;
1519 host->pdev = pdev;
1520 host->cookie = -1;
1521 host->prev_power_state = MMC_POWER_OFF;
1522 INIT_WORK(&host->work, sd_request);
1523 platform_set_drvdata(pdev, host);
1524 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1525 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1526
1527 mutex_init(&host->host_mutex);
1528
1529 realtek_init_host(host);
1530
1531 pm_runtime_no_callbacks(&pdev->dev);
1532 pm_runtime_set_active(&pdev->dev);
1533 pm_runtime_enable(&pdev->dev);
1534 pm_runtime_set_autosuspend_delay(&pdev->dev, 200);
1535 pm_runtime_mark_last_busy(&pdev->dev);
1536 pm_runtime_use_autosuspend(&pdev->dev);
1537
1538 mmc_add_host(mmc);
1539
1540 return 0;
1541 }
1542
1543 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1544 {
1545 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1546 struct rtsx_pcr *pcr;
1547 struct mmc_host *mmc;
1548
1549 if (!host)
1550 return 0;
1551
1552 pcr = host->pcr;
1553 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1554 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1555 mmc = host->mmc;
1556
1557 cancel_work_sync(&host->work);
1558
1559 mutex_lock(&host->host_mutex);
1560 if (host->mrq) {
1561 dev_dbg(&(pdev->dev),
1562 "%s: Controller removed during transfer\n",
1563 mmc_hostname(mmc));
1564
1565 rtsx_pci_complete_unfinished_transfer(pcr);
1566
1567 host->mrq->cmd->error = -ENOMEDIUM;
1568 if (host->mrq->stop)
1569 host->mrq->stop->error = -ENOMEDIUM;
1570 mmc_request_done(mmc, host->mrq);
1571 }
1572 mutex_unlock(&host->host_mutex);
1573
1574 mmc_remove_host(mmc);
1575 host->eject = true;
1576
1577 flush_work(&host->work);
1578
1579 pm_runtime_dont_use_autosuspend(&pdev->dev);
1580 pm_runtime_disable(&pdev->dev);
1581
1582 mmc_free_host(mmc);
1583
1584 dev_dbg(&(pdev->dev),
1585 ": Realtek PCI-E SDMMC controller has been removed\n");
1586
1587 return 0;
1588 }
1589
1590 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1591 {
1592 .name = DRV_NAME_RTSX_PCI_SDMMC,
1593 }, {
1594 /* sentinel */
1595 }
1596 };
1597 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1598
1599 static struct platform_driver rtsx_pci_sdmmc_driver = {
1600 .probe = rtsx_pci_sdmmc_drv_probe,
1601 .remove = rtsx_pci_sdmmc_drv_remove,
1602 .id_table = rtsx_pci_sdmmc_ids,
1603 .driver = {
1604 .name = DRV_NAME_RTSX_PCI_SDMMC,
1605 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1606 },
1607 };
1608 module_platform_driver(rtsx_pci_sdmmc_driver);
1609
1610 MODULE_LICENSE("GPL");
1611 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1612 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
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