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[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci-msm.c
1 /*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3 *
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
24
25 #include "sdhci-pltfm.h"
26
27 #define CORE_MCI_VERSION 0x50
28 #define CORE_VERSION_MAJOR_SHIFT 28
29 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK 0xff
31
32 #define CORE_HC_MODE 0x78
33 #define HC_MODE_EN 0x1
34 #define CORE_POWER 0x0
35 #define CORE_SW_RST BIT(7)
36 #define FF_CLK_SW_RST_DIS BIT(13)
37
38 #define CORE_PWRCTL_STATUS 0xdc
39 #define CORE_PWRCTL_MASK 0xe0
40 #define CORE_PWRCTL_CLEAR 0xe4
41 #define CORE_PWRCTL_CTL 0xe8
42 #define CORE_PWRCTL_BUS_OFF BIT(0)
43 #define CORE_PWRCTL_BUS_ON BIT(1)
44 #define CORE_PWRCTL_IO_LOW BIT(2)
45 #define CORE_PWRCTL_IO_HIGH BIT(3)
46 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
47 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
48 #define REQ_BUS_OFF BIT(0)
49 #define REQ_BUS_ON BIT(1)
50 #define REQ_IO_LOW BIT(2)
51 #define REQ_IO_HIGH BIT(3)
52 #define INT_MASK 0xf
53 #define MAX_PHASES 16
54 #define CORE_DLL_LOCK BIT(7)
55 #define CORE_DDR_DLL_LOCK BIT(11)
56 #define CORE_DLL_EN BIT(16)
57 #define CORE_CDR_EN BIT(17)
58 #define CORE_CK_OUT_EN BIT(18)
59 #define CORE_CDR_EXT_EN BIT(19)
60 #define CORE_DLL_PDN BIT(29)
61 #define CORE_DLL_RST BIT(30)
62 #define CORE_DLL_CONFIG 0x100
63 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
64 #define CORE_DLL_STATUS 0x108
65
66 #define CORE_DLL_CONFIG_2 0x1b4
67 #define CORE_DDR_CAL_EN BIT(0)
68 #define CORE_FLL_CYCLE_CNT BIT(18)
69 #define CORE_DLL_CLOCK_DISABLE BIT(21)
70
71 #define CORE_VENDOR_SPEC 0x10c
72 #define CORE_CLK_PWRSAVE BIT(1)
73 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
74 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
75 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
76 #define CORE_HC_SELECT_IN_EN BIT(18)
77 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
78 #define CORE_HC_SELECT_IN_MASK (7 << 19)
79
80 #define CORE_CSR_CDC_CTLR_CFG0 0x130
81 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
82 #define CORE_HW_AUTOCAL_ENA BIT(17)
83
84 #define CORE_CSR_CDC_CTLR_CFG1 0x134
85 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
86 #define CORE_TIMER_ENA BIT(16)
87
88 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
89 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
90 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
91 #define CORE_CDC_OFFSET_CFG 0x14C
92 #define CORE_CSR_CDC_DELAY_CFG 0x150
93 #define CORE_CDC_SLAVE_DDA_CFG 0x160
94 #define CORE_CSR_CDC_STATUS0 0x164
95 #define CORE_CALIBRATION_DONE BIT(0)
96
97 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
98
99 #define CORE_CSR_CDC_GEN_CFG 0x178
100 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
101 #define CORE_CDC_SWITCH_RC_EN BIT(1)
102
103 #define CORE_DDR_200_CFG 0x184
104 #define CORE_CDC_T4_DLY_SEL BIT(0)
105 #define CORE_START_CDC_TRAFFIC BIT(6)
106 #define CORE_VENDOR_SPEC3 0x1b0
107 #define CORE_PWRSAVE_DLL BIT(3)
108
109 #define CORE_DDR_CONFIG 0x1b8
110 #define DDR_CONFIG_POR_VAL 0x80040853
111
112 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
113
114 #define INVALID_TUNING_PHASE -1
115 #define SDHCI_MSM_MIN_CLOCK 400000
116 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
117
118 #define CDR_SELEXT_SHIFT 20
119 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
120 #define CMUX_SHIFT_PHASE_SHIFT 24
121 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
122
123 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
124 struct sdhci_msm_host {
125 struct platform_device *pdev;
126 void __iomem *core_mem; /* MSM SDCC mapped address */
127 int pwr_irq; /* power irq */
128 struct clk *clk; /* main SD/MMC bus clock */
129 struct clk *pclk; /* SDHC peripheral bus clock */
130 struct clk *bus_clk; /* SDHC bus voter clock */
131 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
132 unsigned long clk_rate;
133 struct mmc_host *mmc;
134 bool use_14lpp_dll_reset;
135 bool tuning_done;
136 bool calibration_done;
137 u8 saved_tuning_phase;
138 bool use_cdclp533;
139 };
140
141 /* Platform specific tuning */
142 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
143 {
144 u32 wait_cnt = 50;
145 u8 ck_out_en;
146 struct mmc_host *mmc = host->mmc;
147
148 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
149 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
150 CORE_CK_OUT_EN);
151
152 while (ck_out_en != poll) {
153 if (--wait_cnt == 0) {
154 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
155 mmc_hostname(mmc), poll);
156 return -ETIMEDOUT;
157 }
158 udelay(1);
159
160 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
161 CORE_CK_OUT_EN);
162 }
163
164 return 0;
165 }
166
167 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
168 {
169 int rc;
170 static const u8 grey_coded_phase_table[] = {
171 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
172 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
173 };
174 unsigned long flags;
175 u32 config;
176 struct mmc_host *mmc = host->mmc;
177
178 if (phase > 0xf)
179 return -EINVAL;
180
181 spin_lock_irqsave(&host->lock, flags);
182
183 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
184 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
185 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
186 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
187
188 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
189 rc = msm_dll_poll_ck_out_en(host, 0);
190 if (rc)
191 goto err_out;
192
193 /*
194 * Write the selected DLL clock output phase (0 ... 15)
195 * to CDR_SELEXT bit field of DLL_CONFIG register.
196 */
197 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
198 config &= ~CDR_SELEXT_MASK;
199 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
200 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
201
202 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
203 config |= CORE_CK_OUT_EN;
204 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
205
206 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
207 rc = msm_dll_poll_ck_out_en(host, 1);
208 if (rc)
209 goto err_out;
210
211 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
212 config |= CORE_CDR_EN;
213 config &= ~CORE_CDR_EXT_EN;
214 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
215 goto out;
216
217 err_out:
218 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
219 mmc_hostname(mmc), phase);
220 out:
221 spin_unlock_irqrestore(&host->lock, flags);
222 return rc;
223 }
224
225 /*
226 * Find out the greatest range of consecuitive selected
227 * DLL clock output phases that can be used as sampling
228 * setting for SD3.0 UHS-I card read operation (in SDR104
229 * timing mode) or for eMMC4.5 card read operation (in
230 * HS400/HS200 timing mode).
231 * Select the 3/4 of the range and configure the DLL with the
232 * selected DLL clock output phase.
233 */
234
235 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
236 u8 *phase_table, u8 total_phases)
237 {
238 int ret;
239 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
240 u8 phases_per_row[MAX_PHASES] = { 0 };
241 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
242 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
243 bool phase_0_found = false, phase_15_found = false;
244 struct mmc_host *mmc = host->mmc;
245
246 if (!total_phases || (total_phases > MAX_PHASES)) {
247 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
248 mmc_hostname(mmc), total_phases);
249 return -EINVAL;
250 }
251
252 for (cnt = 0; cnt < total_phases; cnt++) {
253 ranges[row_index][col_index] = phase_table[cnt];
254 phases_per_row[row_index] += 1;
255 col_index++;
256
257 if ((cnt + 1) == total_phases) {
258 continue;
259 /* check if next phase in phase_table is consecutive or not */
260 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
261 row_index++;
262 col_index = 0;
263 }
264 }
265
266 if (row_index >= MAX_PHASES)
267 return -EINVAL;
268
269 /* Check if phase-0 is present in first valid window? */
270 if (!ranges[0][0]) {
271 phase_0_found = true;
272 phase_0_raw_index = 0;
273 /* Check if cycle exist between 2 valid windows */
274 for (cnt = 1; cnt <= row_index; cnt++) {
275 if (phases_per_row[cnt]) {
276 for (i = 0; i < phases_per_row[cnt]; i++) {
277 if (ranges[cnt][i] == 15) {
278 phase_15_found = true;
279 phase_15_raw_index = cnt;
280 break;
281 }
282 }
283 }
284 }
285 }
286
287 /* If 2 valid windows form cycle then merge them as single window */
288 if (phase_0_found && phase_15_found) {
289 /* number of phases in raw where phase 0 is present */
290 u8 phases_0 = phases_per_row[phase_0_raw_index];
291 /* number of phases in raw where phase 15 is present */
292 u8 phases_15 = phases_per_row[phase_15_raw_index];
293
294 if (phases_0 + phases_15 >= MAX_PHASES)
295 /*
296 * If there are more than 1 phase windows then total
297 * number of phases in both the windows should not be
298 * more than or equal to MAX_PHASES.
299 */
300 return -EINVAL;
301
302 /* Merge 2 cyclic windows */
303 i = phases_15;
304 for (cnt = 0; cnt < phases_0; cnt++) {
305 ranges[phase_15_raw_index][i] =
306 ranges[phase_0_raw_index][cnt];
307 if (++i >= MAX_PHASES)
308 break;
309 }
310
311 phases_per_row[phase_0_raw_index] = 0;
312 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
313 }
314
315 for (cnt = 0; cnt <= row_index; cnt++) {
316 if (phases_per_row[cnt] > curr_max) {
317 curr_max = phases_per_row[cnt];
318 selected_row_index = cnt;
319 }
320 }
321
322 i = (curr_max * 3) / 4;
323 if (i)
324 i--;
325
326 ret = ranges[selected_row_index][i];
327
328 if (ret >= MAX_PHASES) {
329 ret = -EINVAL;
330 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
331 mmc_hostname(mmc), ret);
332 }
333
334 return ret;
335 }
336
337 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
338 {
339 u32 mclk_freq = 0, config;
340
341 /* Program the MCLK value to MCLK_FREQ bit field */
342 if (host->clock <= 112000000)
343 mclk_freq = 0;
344 else if (host->clock <= 125000000)
345 mclk_freq = 1;
346 else if (host->clock <= 137000000)
347 mclk_freq = 2;
348 else if (host->clock <= 150000000)
349 mclk_freq = 3;
350 else if (host->clock <= 162000000)
351 mclk_freq = 4;
352 else if (host->clock <= 175000000)
353 mclk_freq = 5;
354 else if (host->clock <= 187000000)
355 mclk_freq = 6;
356 else if (host->clock <= 200000000)
357 mclk_freq = 7;
358
359 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
360 config &= ~CMUX_SHIFT_PHASE_MASK;
361 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
362 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
363 }
364
365 /* Initialize the DLL (Programmable Delay Line) */
366 static int msm_init_cm_dll(struct sdhci_host *host)
367 {
368 struct mmc_host *mmc = host->mmc;
369 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
370 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
371 int wait_cnt = 50;
372 unsigned long flags;
373 u32 config;
374
375 spin_lock_irqsave(&host->lock, flags);
376
377 /*
378 * Make sure that clock is always enabled when DLL
379 * tuning is in progress. Keeping PWRSAVE ON may
380 * turn off the clock.
381 */
382 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
383 config &= ~CORE_CLK_PWRSAVE;
384 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
385
386 if (msm_host->use_14lpp_dll_reset) {
387 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
388 config &= ~CORE_CK_OUT_EN;
389 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
390
391 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
392 config |= CORE_DLL_CLOCK_DISABLE;
393 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
394 }
395
396 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
397 config |= CORE_DLL_RST;
398 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
399
400 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
401 config |= CORE_DLL_PDN;
402 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
403 msm_cm_dll_set_freq(host);
404
405 if (msm_host->use_14lpp_dll_reset &&
406 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
407 u32 mclk_freq = 0;
408
409 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
410 config &= CORE_FLL_CYCLE_CNT;
411 if (config)
412 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
413 clk_get_rate(msm_host->xo_clk));
414 else
415 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
416 clk_get_rate(msm_host->xo_clk));
417
418 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
419 config &= ~(0xFF << 10);
420 config |= mclk_freq << 10;
421
422 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
423 /* wait for 5us before enabling DLL clock */
424 udelay(5);
425 }
426
427 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
428 config &= ~CORE_DLL_RST;
429 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
430
431 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
432 config &= ~CORE_DLL_PDN;
433 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
434
435 if (msm_host->use_14lpp_dll_reset) {
436 msm_cm_dll_set_freq(host);
437 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
438 config &= ~CORE_DLL_CLOCK_DISABLE;
439 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
440 }
441
442 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
443 config |= CORE_DLL_EN;
444 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
445
446 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
447 config |= CORE_CK_OUT_EN;
448 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
449
450 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
451 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
452 CORE_DLL_LOCK)) {
453 /* max. wait for 50us sec for LOCK bit to be set */
454 if (--wait_cnt == 0) {
455 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
456 mmc_hostname(mmc));
457 spin_unlock_irqrestore(&host->lock, flags);
458 return -ETIMEDOUT;
459 }
460 udelay(1);
461 }
462
463 spin_unlock_irqrestore(&host->lock, flags);
464 return 0;
465 }
466
467 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
468 {
469 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
470 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
471 u32 config, calib_done;
472 int ret;
473
474 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
475
476 /*
477 * Retuning in HS400 (DDR mode) will fail, just reset the
478 * tuning block and restore the saved tuning phase.
479 */
480 ret = msm_init_cm_dll(host);
481 if (ret)
482 goto out;
483
484 /* Set the selected phase in delay line hw block */
485 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
486 if (ret)
487 goto out;
488
489 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
490 config |= CORE_CMD_DAT_TRACK_SEL;
491 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
492
493 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
494 config &= ~CORE_CDC_T4_DLY_SEL;
495 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
496
497 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
498 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
499 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
500
501 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
502 config |= CORE_CDC_SWITCH_RC_EN;
503 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
504
505 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
506 config &= ~CORE_START_CDC_TRAFFIC;
507 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
508
509 /*
510 * Perform CDC Register Initialization Sequence
511 *
512 * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
513 * CORE_CSR_CDC_CTLR_CFG1 0x3011111
514 * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
515 * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
516 * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
517 * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
518 * CORE_CSR_CDC_DELAY_CFG 0x3AC
519 * CORE_CDC_OFFSET_CFG 0x0
520 * CORE_CDC_SLAVE_DDA_CFG 0x16334
521 */
522
523 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
524 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
525 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
526 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
527 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
528 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
529 writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
530 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
531 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
532
533 /* CDC HW Calibration */
534
535 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
536 config |= CORE_SW_TRIG_FULL_CALIB;
537 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
538
539 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
540 config &= ~CORE_SW_TRIG_FULL_CALIB;
541 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
542
543 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
544 config |= CORE_HW_AUTOCAL_ENA;
545 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
546
547 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
548 config |= CORE_TIMER_ENA;
549 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
550
551 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
552 calib_done,
553 (calib_done & CORE_CALIBRATION_DONE),
554 1, 50);
555
556 if (ret == -ETIMEDOUT) {
557 pr_err("%s: %s: CDC calibration was not completed\n",
558 mmc_hostname(host->mmc), __func__);
559 goto out;
560 }
561
562 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
563 & CORE_CDC_ERROR_CODE_MASK;
564 if (ret) {
565 pr_err("%s: %s: CDC error code %d\n",
566 mmc_hostname(host->mmc), __func__, ret);
567 ret = -EINVAL;
568 goto out;
569 }
570
571 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
572 config |= CORE_START_CDC_TRAFFIC;
573 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
574 out:
575 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
576 __func__, ret);
577 return ret;
578 }
579
580 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
581 {
582 u32 dll_status, config;
583 int ret;
584
585 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
586
587 /*
588 * Currently the CORE_DDR_CONFIG register defaults to desired
589 * configuration on reset. Currently reprogramming the power on
590 * reset (POR) value in case it might have been modified by
591 * bootloaders. In the future, if this changes, then the desired
592 * values will need to be programmed appropriately.
593 */
594 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
595
596 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
597 config |= CORE_DDR_CAL_EN;
598 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
599
600 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
601 dll_status,
602 (dll_status & CORE_DDR_DLL_LOCK),
603 10, 1000);
604
605 if (ret == -ETIMEDOUT) {
606 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
607 mmc_hostname(host->mmc), __func__);
608 goto out;
609 }
610
611 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
612 config |= CORE_PWRSAVE_DLL;
613 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
614
615 /*
616 * Drain writebuffer to ensure above DLL calibration
617 * and PWRSAVE DLL is enabled.
618 */
619 wmb();
620 out:
621 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
622 __func__, ret);
623 return ret;
624 }
625
626 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
627 {
628 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
629 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
630 int ret;
631 u32 config;
632
633 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
634
635 /*
636 * Retuning in HS400 (DDR mode) will fail, just reset the
637 * tuning block and restore the saved tuning phase.
638 */
639 ret = msm_init_cm_dll(host);
640 if (ret)
641 goto out;
642
643 /* Set the selected phase in delay line hw block */
644 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
645 if (ret)
646 goto out;
647
648 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
649 config |= CORE_CMD_DAT_TRACK_SEL;
650 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
651 if (msm_host->use_cdclp533)
652 ret = sdhci_msm_cdclp533_calibration(host);
653 else
654 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
655 out:
656 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
657 __func__, ret);
658 return ret;
659 }
660
661 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
662 {
663 int tuning_seq_cnt = 3;
664 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
665 int rc;
666 struct mmc_host *mmc = host->mmc;
667 struct mmc_ios ios = host->mmc->ios;
668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
669 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
670
671 /*
672 * Tuning is required for SDR104, HS200 and HS400 cards and
673 * if clock frequency is greater than 100MHz in these modes.
674 */
675 if (host->clock <= CORE_FREQ_100MHZ ||
676 !(ios.timing == MMC_TIMING_MMC_HS400 ||
677 ios.timing == MMC_TIMING_MMC_HS200 ||
678 ios.timing == MMC_TIMING_UHS_SDR104))
679 return 0;
680
681 retry:
682 /* First of all reset the tuning block */
683 rc = msm_init_cm_dll(host);
684 if (rc)
685 return rc;
686
687 phase = 0;
688 do {
689 /* Set the phase in delay line hw block */
690 rc = msm_config_cm_dll_phase(host, phase);
691 if (rc)
692 return rc;
693
694 msm_host->saved_tuning_phase = phase;
695 rc = mmc_send_tuning(mmc, opcode, NULL);
696 if (!rc) {
697 /* Tuning is successful at this tuning point */
698 tuned_phases[tuned_phase_cnt++] = phase;
699 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
700 mmc_hostname(mmc), phase);
701 }
702 } while (++phase < ARRAY_SIZE(tuned_phases));
703
704 if (tuned_phase_cnt) {
705 rc = msm_find_most_appropriate_phase(host, tuned_phases,
706 tuned_phase_cnt);
707 if (rc < 0)
708 return rc;
709 else
710 phase = rc;
711
712 /*
713 * Finally set the selected phase in delay
714 * line hw block.
715 */
716 rc = msm_config_cm_dll_phase(host, phase);
717 if (rc)
718 return rc;
719 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
720 mmc_hostname(mmc), phase);
721 } else {
722 if (--tuning_seq_cnt)
723 goto retry;
724 /* Tuning failed */
725 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
726 mmc_hostname(mmc));
727 rc = -EIO;
728 }
729
730 if (!rc)
731 msm_host->tuning_done = true;
732 return rc;
733 }
734
735 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
736 unsigned int uhs)
737 {
738 struct mmc_host *mmc = host->mmc;
739 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
740 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
741 u16 ctrl_2;
742 u32 config;
743
744 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
745 /* Select Bus Speed Mode for host */
746 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
747 switch (uhs) {
748 case MMC_TIMING_UHS_SDR12:
749 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
750 break;
751 case MMC_TIMING_UHS_SDR25:
752 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
753 break;
754 case MMC_TIMING_UHS_SDR50:
755 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
756 break;
757 case MMC_TIMING_MMC_HS400:
758 case MMC_TIMING_MMC_HS200:
759 case MMC_TIMING_UHS_SDR104:
760 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
761 break;
762 case MMC_TIMING_UHS_DDR50:
763 case MMC_TIMING_MMC_DDR52:
764 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
765 break;
766 }
767
768 /*
769 * When clock frequency is less than 100MHz, the feedback clock must be
770 * provided and DLL must not be used so that tuning can be skipped. To
771 * provide feedback clock, the mode selection can be any value less
772 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
773 */
774 if (host->clock <= CORE_FREQ_100MHZ) {
775 if (uhs == MMC_TIMING_MMC_HS400 ||
776 uhs == MMC_TIMING_MMC_HS200 ||
777 uhs == MMC_TIMING_UHS_SDR104)
778 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
779 /*
780 * DLL is not required for clock <= 100MHz
781 * Thus, make sure DLL it is disabled when not required
782 */
783 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
784 config |= CORE_DLL_RST;
785 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
786
787 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
788 config |= CORE_DLL_PDN;
789 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
790
791 /*
792 * The DLL needs to be restored and CDCLP533 recalibrated
793 * when the clock frequency is set back to 400MHz.
794 */
795 msm_host->calibration_done = false;
796 }
797
798 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
799 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
800 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
801
802 spin_unlock_irq(&host->lock);
803 /* CDCLP533 HW calibration is only required for HS400 mode*/
804 if (host->clock > CORE_FREQ_100MHZ &&
805 msm_host->tuning_done && !msm_host->calibration_done &&
806 mmc->ios.timing == MMC_TIMING_MMC_HS400)
807 if (!sdhci_msm_hs400_dll_calibration(host))
808 msm_host->calibration_done = true;
809 spin_lock_irq(&host->lock);
810 }
811
812 static void sdhci_msm_voltage_switch(struct sdhci_host *host)
813 {
814 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
815 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
816 u32 irq_status, irq_ack = 0;
817
818 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
819 irq_status &= INT_MASK;
820
821 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
822
823 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
824 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
825 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
826 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
827
828 /*
829 * The driver has to acknowledge the interrupt, switch voltages and
830 * report back if it succeded or not to this register. The voltage
831 * switches are handled by the sdhci core, so just report success.
832 */
833 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
834 }
835
836 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
837 {
838 struct sdhci_host *host = (struct sdhci_host *)data;
839
840 sdhci_msm_voltage_switch(host);
841
842 return IRQ_HANDLED;
843 }
844
845 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
846 {
847 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
848 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
849
850 return clk_round_rate(msm_host->clk, ULONG_MAX);
851 }
852
853 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
854 {
855 return SDHCI_MSM_MIN_CLOCK;
856 }
857
858 /**
859 * __sdhci_msm_set_clock - sdhci_msm clock control.
860 *
861 * Description:
862 * MSM controller does not use internal divider and
863 * instead directly control the GCC clock as per
864 * HW recommendation.
865 **/
866 void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
867 {
868 u16 clk;
869 /*
870 * Keep actual_clock as zero -
871 * - since there is no divider used so no need of having actual_clock.
872 * - MSM controller uses SDCLK for data timeout calculation. If
873 * actual_clock is zero, host->clock is taken for calculation.
874 */
875 host->mmc->actual_clock = 0;
876
877 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
878
879 if (clock == 0)
880 return;
881
882 /*
883 * MSM controller do not use clock divider.
884 * Thus read SDHCI_CLOCK_CONTROL and only enable
885 * clock with no divider value programmed.
886 */
887 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
888 sdhci_enable_clk(host, clk);
889 }
890
891 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
892 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
893 {
894 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
895 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
896 struct mmc_ios curr_ios = host->mmc->ios;
897 u32 config, dll_lock;
898 int rc;
899
900 if (!clock) {
901 msm_host->clk_rate = clock;
902 goto out;
903 }
904
905 spin_unlock_irq(&host->lock);
906 /*
907 * The SDHC requires internal clock frequency to be double the
908 * actual clock that will be set for DDR mode. The controller
909 * uses the faster clock(100/400MHz) for some of its parts and
910 * send the actual required clock (50/200MHz) to the card.
911 */
912 if (curr_ios.timing == MMC_TIMING_UHS_DDR50 ||
913 curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
914 curr_ios.timing == MMC_TIMING_MMC_HS400)
915 clock *= 2;
916 /*
917 * In general all timing modes are controlled via UHS mode select in
918 * Host Control2 register. eMMC specific HS200/HS400 doesn't have
919 * their respective modes defined here, hence we use these values.
920 *
921 * HS200 - SDR104 (Since they both are equivalent in functionality)
922 * HS400 - This involves multiple configurations
923 * Initially SDR104 - when tuning is required as HS200
924 * Then when switching to DDR @ 400MHz (HS400) we use
925 * the vendor specific HC_SELECT_IN to control the mode.
926 *
927 * In addition to controlling the modes we also need to select the
928 * correct input clock for DLL depending on the mode.
929 *
930 * HS400 - divided clock (free running MCLK/2)
931 * All other modes - default (free running MCLK)
932 */
933 if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
934 /* Select the divided clock (free running MCLK/2) */
935 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
936 config &= ~CORE_HC_MCLK_SEL_MASK;
937 config |= CORE_HC_MCLK_SEL_HS400;
938
939 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
940 /*
941 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
942 * register
943 */
944 if (msm_host->tuning_done && !msm_host->calibration_done) {
945 /*
946 * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
947 * field in VENDOR_SPEC_FUNC
948 */
949 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
950 config |= CORE_HC_SELECT_IN_HS400;
951 config |= CORE_HC_SELECT_IN_EN;
952 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
953 }
954 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
955 /*
956 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
957 * CORE_DLL_STATUS to be set. This should get set
958 * within 15 us at 200 MHz.
959 */
960 rc = readl_relaxed_poll_timeout(host->ioaddr +
961 CORE_DLL_STATUS,
962 dll_lock,
963 (dll_lock &
964 (CORE_DLL_LOCK |
965 CORE_DDR_DLL_LOCK)), 10,
966 1000);
967 if (rc == -ETIMEDOUT)
968 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
969 mmc_hostname(host->mmc), dll_lock);
970 }
971 } else {
972 if (!msm_host->use_cdclp533) {
973 config = readl_relaxed(host->ioaddr +
974 CORE_VENDOR_SPEC3);
975 config &= ~CORE_PWRSAVE_DLL;
976 writel_relaxed(config, host->ioaddr +
977 CORE_VENDOR_SPEC3);
978 }
979
980 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
981 config &= ~CORE_HC_MCLK_SEL_MASK;
982 config |= CORE_HC_MCLK_SEL_DFLT;
983 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
984
985 /*
986 * Disable HC_SELECT_IN to be able to use the UHS mode select
987 * configuration from Host Control2 register for all other
988 * modes.
989 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
990 * in VENDOR_SPEC_FUNC
991 */
992 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
993 config &= ~CORE_HC_SELECT_IN_EN;
994 config &= ~CORE_HC_SELECT_IN_MASK;
995 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
996 }
997
998 /*
999 * Make sure above writes impacting free running MCLK are completed
1000 * before changing the clk_rate at GCC.
1001 */
1002 wmb();
1003
1004 rc = clk_set_rate(msm_host->clk, clock);
1005 if (rc) {
1006 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
1007 mmc_hostname(host->mmc), clock,
1008 curr_ios.timing);
1009 goto out_lock;
1010 }
1011 msm_host->clk_rate = clock;
1012 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
1013 mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
1014 curr_ios.timing);
1015
1016 out_lock:
1017 spin_lock_irq(&host->lock);
1018 out:
1019 __sdhci_msm_set_clock(host, clock);
1020 }
1021
1022 static const struct of_device_id sdhci_msm_dt_match[] = {
1023 { .compatible = "qcom,sdhci-msm-v4" },
1024 {},
1025 };
1026
1027 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1028
1029 static const struct sdhci_ops sdhci_msm_ops = {
1030 .platform_execute_tuning = sdhci_msm_execute_tuning,
1031 .reset = sdhci_reset,
1032 .set_clock = sdhci_msm_set_clock,
1033 .get_min_clock = sdhci_msm_get_min_clock,
1034 .get_max_clock = sdhci_msm_get_max_clock,
1035 .set_bus_width = sdhci_set_bus_width,
1036 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1037 .voltage_switch = sdhci_msm_voltage_switch,
1038 };
1039
1040 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1041 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1042 SDHCI_QUIRK_NO_CARD_NO_RESET |
1043 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1044 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1045 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1046 .ops = &sdhci_msm_ops,
1047 };
1048
1049 static int sdhci_msm_probe(struct platform_device *pdev)
1050 {
1051 struct sdhci_host *host;
1052 struct sdhci_pltfm_host *pltfm_host;
1053 struct sdhci_msm_host *msm_host;
1054 struct resource *core_memres;
1055 int ret;
1056 u16 host_version, core_minor;
1057 u32 core_version, config;
1058 u8 core_major;
1059
1060 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1061 if (IS_ERR(host))
1062 return PTR_ERR(host);
1063
1064 pltfm_host = sdhci_priv(host);
1065 msm_host = sdhci_pltfm_priv(pltfm_host);
1066 msm_host->mmc = host->mmc;
1067 msm_host->pdev = pdev;
1068
1069 ret = mmc_of_parse(host->mmc);
1070 if (ret)
1071 goto pltfm_free;
1072
1073 sdhci_get_of_property(pdev);
1074
1075 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1076
1077 /* Setup SDCC bus voter clock. */
1078 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1079 if (!IS_ERR(msm_host->bus_clk)) {
1080 /* Vote for max. clk rate for max. performance */
1081 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1082 if (ret)
1083 goto pltfm_free;
1084 ret = clk_prepare_enable(msm_host->bus_clk);
1085 if (ret)
1086 goto pltfm_free;
1087 }
1088
1089 /* Setup main peripheral bus clock */
1090 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
1091 if (IS_ERR(msm_host->pclk)) {
1092 ret = PTR_ERR(msm_host->pclk);
1093 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1094 goto bus_clk_disable;
1095 }
1096
1097 ret = clk_prepare_enable(msm_host->pclk);
1098 if (ret)
1099 goto bus_clk_disable;
1100
1101 /* Setup SDC MMC clock */
1102 msm_host->clk = devm_clk_get(&pdev->dev, "core");
1103 if (IS_ERR(msm_host->clk)) {
1104 ret = PTR_ERR(msm_host->clk);
1105 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1106 goto pclk_disable;
1107 }
1108
1109 /*
1110 * xo clock is needed for FLL feature of cm_dll.
1111 * In case if xo clock is not mentioned in DT, warn and proceed.
1112 */
1113 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1114 if (IS_ERR(msm_host->xo_clk)) {
1115 ret = PTR_ERR(msm_host->xo_clk);
1116 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1117 }
1118
1119 /* Vote for maximum clock rate for maximum performance */
1120 ret = clk_set_rate(msm_host->clk, INT_MAX);
1121 if (ret)
1122 dev_warn(&pdev->dev, "core clock boost failed\n");
1123
1124 ret = clk_prepare_enable(msm_host->clk);
1125 if (ret)
1126 goto pclk_disable;
1127
1128 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1129 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1130
1131 if (IS_ERR(msm_host->core_mem)) {
1132 dev_err(&pdev->dev, "Failed to remap registers\n");
1133 ret = PTR_ERR(msm_host->core_mem);
1134 goto clk_disable;
1135 }
1136
1137 config = readl_relaxed(msm_host->core_mem + CORE_POWER);
1138 config |= CORE_SW_RST;
1139 writel_relaxed(config, msm_host->core_mem + CORE_POWER);
1140
1141 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
1142 usleep_range(1000, 5000);
1143 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
1144 dev_err(&pdev->dev, "Stuck in reset\n");
1145 ret = -ETIMEDOUT;
1146 goto clk_disable;
1147 }
1148
1149 /* Set HC_MODE_EN bit in HC_MODE register */
1150 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1151
1152 config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1153 config |= FF_CLK_SW_RST_DIS;
1154 writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1155
1156 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1157 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1158 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1159 SDHCI_VENDOR_VER_SHIFT));
1160
1161 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1162 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1163 CORE_VERSION_MAJOR_SHIFT;
1164 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1165 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1166 core_version, core_major, core_minor);
1167
1168 if (core_major == 1 && core_minor >= 0x42)
1169 msm_host->use_14lpp_dll_reset = true;
1170
1171 /*
1172 * SDCC 5 controller with major version 1, minor version 0x34 and later
1173 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1174 */
1175 if (core_major == 1 && core_minor < 0x34)
1176 msm_host->use_cdclp533 = true;
1177
1178 /*
1179 * Support for some capabilities is not advertised by newer
1180 * controller versions and must be explicitly enabled.
1181 */
1182 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1183 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1184 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1185 writel_relaxed(config, host->ioaddr +
1186 CORE_VENDOR_SPEC_CAPABILITIES0);
1187 }
1188
1189 /* Setup IRQ for handling power/voltage tasks with PMIC */
1190 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1191 if (msm_host->pwr_irq < 0) {
1192 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1193 msm_host->pwr_irq);
1194 ret = msm_host->pwr_irq;
1195 goto clk_disable;
1196 }
1197
1198 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1199 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1200 dev_name(&pdev->dev), host);
1201 if (ret) {
1202 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1203 goto clk_disable;
1204 }
1205
1206 pm_runtime_get_noresume(&pdev->dev);
1207 pm_runtime_set_active(&pdev->dev);
1208 pm_runtime_enable(&pdev->dev);
1209 pm_runtime_set_autosuspend_delay(&pdev->dev,
1210 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1211 pm_runtime_use_autosuspend(&pdev->dev);
1212
1213 ret = sdhci_add_host(host);
1214 if (ret)
1215 goto pm_runtime_disable;
1216
1217 pm_runtime_mark_last_busy(&pdev->dev);
1218 pm_runtime_put_autosuspend(&pdev->dev);
1219
1220 return 0;
1221
1222 pm_runtime_disable:
1223 pm_runtime_disable(&pdev->dev);
1224 pm_runtime_set_suspended(&pdev->dev);
1225 pm_runtime_put_noidle(&pdev->dev);
1226 clk_disable:
1227 clk_disable_unprepare(msm_host->clk);
1228 pclk_disable:
1229 clk_disable_unprepare(msm_host->pclk);
1230 bus_clk_disable:
1231 if (!IS_ERR(msm_host->bus_clk))
1232 clk_disable_unprepare(msm_host->bus_clk);
1233 pltfm_free:
1234 sdhci_pltfm_free(pdev);
1235 return ret;
1236 }
1237
1238 static int sdhci_msm_remove(struct platform_device *pdev)
1239 {
1240 struct sdhci_host *host = platform_get_drvdata(pdev);
1241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1242 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1243 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1244 0xffffffff);
1245
1246 sdhci_remove_host(host, dead);
1247
1248 pm_runtime_get_sync(&pdev->dev);
1249 pm_runtime_disable(&pdev->dev);
1250 pm_runtime_put_noidle(&pdev->dev);
1251
1252 clk_disable_unprepare(msm_host->clk);
1253 clk_disable_unprepare(msm_host->pclk);
1254 if (!IS_ERR(msm_host->bus_clk))
1255 clk_disable_unprepare(msm_host->bus_clk);
1256 sdhci_pltfm_free(pdev);
1257 return 0;
1258 }
1259
1260 #ifdef CONFIG_PM
1261 static int sdhci_msm_runtime_suspend(struct device *dev)
1262 {
1263 struct sdhci_host *host = dev_get_drvdata(dev);
1264 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1265 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1266
1267 clk_disable_unprepare(msm_host->clk);
1268 clk_disable_unprepare(msm_host->pclk);
1269
1270 return 0;
1271 }
1272
1273 static int sdhci_msm_runtime_resume(struct device *dev)
1274 {
1275 struct sdhci_host *host = dev_get_drvdata(dev);
1276 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1277 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1278 int ret;
1279
1280 ret = clk_prepare_enable(msm_host->clk);
1281 if (ret) {
1282 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
1283 return ret;
1284 }
1285 ret = clk_prepare_enable(msm_host->pclk);
1286 if (ret) {
1287 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
1288 clk_disable_unprepare(msm_host->clk);
1289 return ret;
1290 }
1291
1292 return 0;
1293 }
1294 #endif
1295
1296 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1297 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1298 pm_runtime_force_resume)
1299 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1300 sdhci_msm_runtime_resume,
1301 NULL)
1302 };
1303
1304 static struct platform_driver sdhci_msm_driver = {
1305 .probe = sdhci_msm_probe,
1306 .remove = sdhci_msm_remove,
1307 .driver = {
1308 .name = "sdhci_msm",
1309 .of_match_table = sdhci_msm_dt_match,
1310 .pm = &sdhci_msm_pm_ops,
1311 },
1312 };
1313
1314 module_platform_driver(sdhci_msm_driver);
1315
1316 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1317 MODULE_LICENSE("GPL v2");
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