1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/delay.h>
11 #include <linux/mmc/mmc.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
17 #include "sdhci-pltfm.h"
19 #define CORE_MCI_VERSION 0x50
20 #define CORE_VERSION_MAJOR_SHIFT 28
21 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
22 #define CORE_VERSION_MINOR_MASK 0xff
24 #define CORE_MCI_GENERICS 0x70
25 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
27 #define HC_MODE_EN 0x1
28 #define CORE_POWER 0x0
29 #define CORE_SW_RST BIT(7)
30 #define FF_CLK_SW_RST_DIS BIT(13)
32 #define CORE_PWRCTL_BUS_OFF BIT(0)
33 #define CORE_PWRCTL_BUS_ON BIT(1)
34 #define CORE_PWRCTL_IO_LOW BIT(2)
35 #define CORE_PWRCTL_IO_HIGH BIT(3)
36 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
37 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
38 #define REQ_BUS_OFF BIT(0)
39 #define REQ_BUS_ON BIT(1)
40 #define REQ_IO_LOW BIT(2)
41 #define REQ_IO_HIGH BIT(3)
44 #define CORE_DLL_LOCK BIT(7)
45 #define CORE_DDR_DLL_LOCK BIT(11)
46 #define CORE_DLL_EN BIT(16)
47 #define CORE_CDR_EN BIT(17)
48 #define CORE_CK_OUT_EN BIT(18)
49 #define CORE_CDR_EXT_EN BIT(19)
50 #define CORE_DLL_PDN BIT(29)
51 #define CORE_DLL_RST BIT(30)
52 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
54 #define CORE_DDR_CAL_EN BIT(0)
55 #define CORE_FLL_CYCLE_CNT BIT(18)
56 #define CORE_DLL_CLOCK_DISABLE BIT(21)
58 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
59 #define CORE_CLK_PWRSAVE BIT(1)
60 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
61 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
62 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
63 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
64 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
65 #define CORE_HC_SELECT_IN_EN BIT(18)
66 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
67 #define CORE_HC_SELECT_IN_MASK (7 << 19)
69 #define CORE_3_0V_SUPPORT (1 << 25)
70 #define CORE_1_8V_SUPPORT (1 << 26)
71 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
73 #define CORE_CSR_CDC_CTLR_CFG0 0x130
74 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
75 #define CORE_HW_AUTOCAL_ENA BIT(17)
77 #define CORE_CSR_CDC_CTLR_CFG1 0x134
78 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
79 #define CORE_TIMER_ENA BIT(16)
81 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
82 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
83 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
84 #define CORE_CDC_OFFSET_CFG 0x14C
85 #define CORE_CSR_CDC_DELAY_CFG 0x150
86 #define CORE_CDC_SLAVE_DDA_CFG 0x160
87 #define CORE_CSR_CDC_STATUS0 0x164
88 #define CORE_CALIBRATION_DONE BIT(0)
90 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
92 #define CORE_CSR_CDC_GEN_CFG 0x178
93 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
94 #define CORE_CDC_SWITCH_RC_EN BIT(1)
96 #define CORE_CDC_T4_DLY_SEL BIT(0)
97 #define CORE_CMDIN_RCLK_EN BIT(1)
98 #define CORE_START_CDC_TRAFFIC BIT(6)
100 #define CORE_PWRSAVE_DLL BIT(3)
102 #define DDR_CONFIG_POR_VAL 0x80040853
105 #define INVALID_TUNING_PHASE -1
106 #define SDHCI_MSM_MIN_CLOCK 400000
107 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
109 #define CDR_SELEXT_SHIFT 20
110 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
111 #define CMUX_SHIFT_PHASE_SHIFT 24
112 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
114 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
116 /* Timeout value to avoid infinite waiting for pwr_irq */
117 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
119 #define msm_host_readl(msm_host, host, offset) \
120 msm_host->var_ops->msm_readl_relaxed(host, offset)
122 #define msm_host_writel(msm_host, val, host, offset) \
123 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
125 struct sdhci_msm_offset
{
127 u32 core_mci_data_cnt
;
129 u32 core_mci_fifo_cnt
;
130 u32 core_mci_version
;
132 u32 core_testbus_config
;
133 u32 core_testbus_sel2_bit
;
134 u32 core_testbus_ena
;
135 u32 core_testbus_sel2
;
136 u32 core_pwrctl_status
;
137 u32 core_pwrctl_mask
;
138 u32 core_pwrctl_clear
;
140 u32 core_sdcc_debug_reg
;
143 u32 core_vendor_spec
;
144 u32 core_vendor_spec_adma_err_addr0
;
145 u32 core_vendor_spec_adma_err_addr1
;
146 u32 core_vendor_spec_func2
;
147 u32 core_vendor_spec_capabilities0
;
148 u32 core_ddr_200_cfg
;
149 u32 core_vendor_spec3
;
150 u32 core_dll_config_2
;
152 u32 core_ddr_config_2
;
155 static const struct sdhci_msm_offset sdhci_msm_v5_offset
= {
156 .core_mci_data_cnt
= 0x35c,
157 .core_mci_status
= 0x324,
158 .core_mci_fifo_cnt
= 0x308,
159 .core_mci_version
= 0x318,
160 .core_generics
= 0x320,
161 .core_testbus_config
= 0x32c,
162 .core_testbus_sel2_bit
= 3,
163 .core_testbus_ena
= (1 << 31),
164 .core_testbus_sel2
= (1 << 3),
165 .core_pwrctl_status
= 0x240,
166 .core_pwrctl_mask
= 0x244,
167 .core_pwrctl_clear
= 0x248,
168 .core_pwrctl_ctl
= 0x24c,
169 .core_sdcc_debug_reg
= 0x358,
170 .core_dll_config
= 0x200,
171 .core_dll_status
= 0x208,
172 .core_vendor_spec
= 0x20c,
173 .core_vendor_spec_adma_err_addr0
= 0x214,
174 .core_vendor_spec_adma_err_addr1
= 0x218,
175 .core_vendor_spec_func2
= 0x210,
176 .core_vendor_spec_capabilities0
= 0x21c,
177 .core_ddr_200_cfg
= 0x224,
178 .core_vendor_spec3
= 0x250,
179 .core_dll_config_2
= 0x254,
180 .core_ddr_config
= 0x258,
181 .core_ddr_config_2
= 0x25c,
184 static const struct sdhci_msm_offset sdhci_msm_mci_offset
= {
185 .core_hc_mode
= 0x78,
186 .core_mci_data_cnt
= 0x30,
187 .core_mci_status
= 0x34,
188 .core_mci_fifo_cnt
= 0x44,
189 .core_mci_version
= 0x050,
190 .core_generics
= 0x70,
191 .core_testbus_config
= 0x0cc,
192 .core_testbus_sel2_bit
= 4,
193 .core_testbus_ena
= (1 << 3),
194 .core_testbus_sel2
= (1 << 4),
195 .core_pwrctl_status
= 0xdc,
196 .core_pwrctl_mask
= 0xe0,
197 .core_pwrctl_clear
= 0xe4,
198 .core_pwrctl_ctl
= 0xe8,
199 .core_sdcc_debug_reg
= 0x124,
200 .core_dll_config
= 0x100,
201 .core_dll_status
= 0x108,
202 .core_vendor_spec
= 0x10c,
203 .core_vendor_spec_adma_err_addr0
= 0x114,
204 .core_vendor_spec_adma_err_addr1
= 0x118,
205 .core_vendor_spec_func2
= 0x110,
206 .core_vendor_spec_capabilities0
= 0x11c,
207 .core_ddr_200_cfg
= 0x184,
208 .core_vendor_spec3
= 0x1b0,
209 .core_dll_config_2
= 0x1b4,
210 .core_ddr_config
= 0x1b8,
211 .core_ddr_config_2
= 0x1bc,
214 struct sdhci_msm_variant_ops
{
215 u32 (*msm_readl_relaxed
)(struct sdhci_host
*host
, u32 offset
);
216 void (*msm_writel_relaxed
)(u32 val
, struct sdhci_host
*host
,
221 * From V5, register spaces have changed. Wrap this info in a structure
222 * and choose the data_structure based on version info mentioned in DT.
224 struct sdhci_msm_variant_info
{
226 bool restore_dll_config
;
227 const struct sdhci_msm_variant_ops
*var_ops
;
228 const struct sdhci_msm_offset
*offset
;
231 struct sdhci_msm_host
{
232 struct platform_device
*pdev
;
233 void __iomem
*core_mem
; /* MSM SDCC mapped address */
234 int pwr_irq
; /* power irq */
235 struct clk
*bus_clk
; /* SDHC bus voter clock */
236 struct clk
*xo_clk
; /* TCXO clk needed for FLL feature of cm_dll*/
237 struct clk_bulk_data bulk_clks
[4]; /* core, iface, cal, sleep clocks */
238 unsigned long clk_rate
;
239 struct mmc_host
*mmc
;
240 bool use_14lpp_dll_reset
;
242 bool calibration_done
;
243 u8 saved_tuning_phase
;
247 wait_queue_head_t pwr_irq_wait
;
251 bool restore_dll_config
;
252 const struct sdhci_msm_variant_ops
*var_ops
;
253 const struct sdhci_msm_offset
*offset
;
258 static const struct sdhci_msm_offset
*sdhci_priv_msm_offset(struct sdhci_host
*host
)
260 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
261 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
263 return msm_host
->offset
;
267 * APIs to read/write to vendor specific registers which were there in the
268 * core_mem region before MCI was removed.
270 static u32
sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host
*host
,
273 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
274 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
276 return readl_relaxed(msm_host
->core_mem
+ offset
);
279 static u32
sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host
*host
,
282 return readl_relaxed(host
->ioaddr
+ offset
);
285 static void sdhci_msm_mci_variant_writel_relaxed(u32 val
,
286 struct sdhci_host
*host
, u32 offset
)
288 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
289 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
291 writel_relaxed(val
, msm_host
->core_mem
+ offset
);
294 static void sdhci_msm_v5_variant_writel_relaxed(u32 val
,
295 struct sdhci_host
*host
, u32 offset
)
297 writel_relaxed(val
, host
->ioaddr
+ offset
);
300 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host
*host
,
303 struct mmc_ios ios
= host
->mmc
->ios
;
305 * The SDHC requires internal clock frequency to be double the
306 * actual clock that will be set for DDR mode. The controller
307 * uses the faster clock(100/400MHz) for some of its parts and
308 * send the actual required clock (50/200MHz) to the card.
310 if (ios
.timing
== MMC_TIMING_UHS_DDR50
||
311 ios
.timing
== MMC_TIMING_MMC_DDR52
||
312 ios
.timing
== MMC_TIMING_MMC_HS400
||
313 host
->flags
& SDHCI_HS400_TUNING
)
318 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host
*host
,
321 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
322 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
323 struct mmc_ios curr_ios
= host
->mmc
->ios
;
324 struct clk
*core_clk
= msm_host
->bulk_clks
[0].clk
;
327 clock
= msm_get_clock_rate_for_bus_mode(host
, clock
);
328 rc
= clk_set_rate(core_clk
, clock
);
330 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
331 mmc_hostname(host
->mmc
), clock
,
335 msm_host
->clk_rate
= clock
;
336 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
337 mmc_hostname(host
->mmc
), clk_get_rate(core_clk
),
341 /* Platform specific tuning */
342 static inline int msm_dll_poll_ck_out_en(struct sdhci_host
*host
, u8 poll
)
346 struct mmc_host
*mmc
= host
->mmc
;
347 const struct sdhci_msm_offset
*msm_offset
=
348 sdhci_priv_msm_offset(host
);
350 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
351 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+
352 msm_offset
->core_dll_config
) & CORE_CK_OUT_EN
);
354 while (ck_out_en
!= poll
) {
355 if (--wait_cnt
== 0) {
356 dev_err(mmc_dev(mmc
), "%s: CK_OUT_EN bit is not %d\n",
357 mmc_hostname(mmc
), poll
);
362 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+
363 msm_offset
->core_dll_config
) & CORE_CK_OUT_EN
);
369 static int msm_config_cm_dll_phase(struct sdhci_host
*host
, u8 phase
)
372 static const u8 grey_coded_phase_table
[] = {
373 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
374 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
378 struct mmc_host
*mmc
= host
->mmc
;
379 const struct sdhci_msm_offset
*msm_offset
=
380 sdhci_priv_msm_offset(host
);
385 spin_lock_irqsave(&host
->lock
, flags
);
387 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
388 config
&= ~(CORE_CDR_EN
| CORE_CK_OUT_EN
);
389 config
|= (CORE_CDR_EXT_EN
| CORE_DLL_EN
);
390 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
392 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
393 rc
= msm_dll_poll_ck_out_en(host
, 0);
398 * Write the selected DLL clock output phase (0 ... 15)
399 * to CDR_SELEXT bit field of DLL_CONFIG register.
401 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
402 config
&= ~CDR_SELEXT_MASK
;
403 config
|= grey_coded_phase_table
[phase
] << CDR_SELEXT_SHIFT
;
404 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
406 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
407 config
|= CORE_CK_OUT_EN
;
408 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
410 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
411 rc
= msm_dll_poll_ck_out_en(host
, 1);
415 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
416 config
|= CORE_CDR_EN
;
417 config
&= ~CORE_CDR_EXT_EN
;
418 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
422 dev_err(mmc_dev(mmc
), "%s: Failed to set DLL phase: %d\n",
423 mmc_hostname(mmc
), phase
);
425 spin_unlock_irqrestore(&host
->lock
, flags
);
430 * Find out the greatest range of consecuitive selected
431 * DLL clock output phases that can be used as sampling
432 * setting for SD3.0 UHS-I card read operation (in SDR104
433 * timing mode) or for eMMC4.5 card read operation (in
434 * HS400/HS200 timing mode).
435 * Select the 3/4 of the range and configure the DLL with the
436 * selected DLL clock output phase.
439 static int msm_find_most_appropriate_phase(struct sdhci_host
*host
,
440 u8
*phase_table
, u8 total_phases
)
443 u8 ranges
[MAX_PHASES
][MAX_PHASES
] = { {0}, {0} };
444 u8 phases_per_row
[MAX_PHASES
] = { 0 };
445 int row_index
= 0, col_index
= 0, selected_row_index
= 0, curr_max
= 0;
446 int i
, cnt
, phase_0_raw_index
= 0, phase_15_raw_index
= 0;
447 bool phase_0_found
= false, phase_15_found
= false;
448 struct mmc_host
*mmc
= host
->mmc
;
450 if (!total_phases
|| (total_phases
> MAX_PHASES
)) {
451 dev_err(mmc_dev(mmc
), "%s: Invalid argument: total_phases=%d\n",
452 mmc_hostname(mmc
), total_phases
);
456 for (cnt
= 0; cnt
< total_phases
; cnt
++) {
457 ranges
[row_index
][col_index
] = phase_table
[cnt
];
458 phases_per_row
[row_index
] += 1;
461 if ((cnt
+ 1) == total_phases
) {
463 /* check if next phase in phase_table is consecutive or not */
464 } else if ((phase_table
[cnt
] + 1) != phase_table
[cnt
+ 1]) {
470 if (row_index
>= MAX_PHASES
)
473 /* Check if phase-0 is present in first valid window? */
475 phase_0_found
= true;
476 phase_0_raw_index
= 0;
477 /* Check if cycle exist between 2 valid windows */
478 for (cnt
= 1; cnt
<= row_index
; cnt
++) {
479 if (phases_per_row
[cnt
]) {
480 for (i
= 0; i
< phases_per_row
[cnt
]; i
++) {
481 if (ranges
[cnt
][i
] == 15) {
482 phase_15_found
= true;
483 phase_15_raw_index
= cnt
;
491 /* If 2 valid windows form cycle then merge them as single window */
492 if (phase_0_found
&& phase_15_found
) {
493 /* number of phases in raw where phase 0 is present */
494 u8 phases_0
= phases_per_row
[phase_0_raw_index
];
495 /* number of phases in raw where phase 15 is present */
496 u8 phases_15
= phases_per_row
[phase_15_raw_index
];
498 if (phases_0
+ phases_15
>= MAX_PHASES
)
500 * If there are more than 1 phase windows then total
501 * number of phases in both the windows should not be
502 * more than or equal to MAX_PHASES.
506 /* Merge 2 cyclic windows */
508 for (cnt
= 0; cnt
< phases_0
; cnt
++) {
509 ranges
[phase_15_raw_index
][i
] =
510 ranges
[phase_0_raw_index
][cnt
];
511 if (++i
>= MAX_PHASES
)
515 phases_per_row
[phase_0_raw_index
] = 0;
516 phases_per_row
[phase_15_raw_index
] = phases_15
+ phases_0
;
519 for (cnt
= 0; cnt
<= row_index
; cnt
++) {
520 if (phases_per_row
[cnt
] > curr_max
) {
521 curr_max
= phases_per_row
[cnt
];
522 selected_row_index
= cnt
;
526 i
= (curr_max
* 3) / 4;
530 ret
= ranges
[selected_row_index
][i
];
532 if (ret
>= MAX_PHASES
) {
534 dev_err(mmc_dev(mmc
), "%s: Invalid phase selected=%d\n",
535 mmc_hostname(mmc
), ret
);
541 static inline void msm_cm_dll_set_freq(struct sdhci_host
*host
)
543 u32 mclk_freq
= 0, config
;
544 const struct sdhci_msm_offset
*msm_offset
=
545 sdhci_priv_msm_offset(host
);
547 /* Program the MCLK value to MCLK_FREQ bit field */
548 if (host
->clock
<= 112000000)
550 else if (host
->clock
<= 125000000)
552 else if (host
->clock
<= 137000000)
554 else if (host
->clock
<= 150000000)
556 else if (host
->clock
<= 162000000)
558 else if (host
->clock
<= 175000000)
560 else if (host
->clock
<= 187000000)
562 else if (host
->clock
<= 200000000)
565 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
566 config
&= ~CMUX_SHIFT_PHASE_MASK
;
567 config
|= mclk_freq
<< CMUX_SHIFT_PHASE_SHIFT
;
568 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
571 /* Initialize the DLL (Programmable Delay Line) */
572 static int msm_init_cm_dll(struct sdhci_host
*host
)
574 struct mmc_host
*mmc
= host
->mmc
;
575 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
576 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
578 unsigned long flags
, xo_clk
= 0;
580 const struct sdhci_msm_offset
*msm_offset
=
583 if (msm_host
->use_14lpp_dll_reset
&& !IS_ERR_OR_NULL(msm_host
->xo_clk
))
584 xo_clk
= clk_get_rate(msm_host
->xo_clk
);
586 spin_lock_irqsave(&host
->lock
, flags
);
589 * Make sure that clock is always enabled when DLL
590 * tuning is in progress. Keeping PWRSAVE ON may
591 * turn off the clock.
593 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
594 config
&= ~CORE_CLK_PWRSAVE
;
595 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
597 if (msm_host
->use_14lpp_dll_reset
) {
598 config
= readl_relaxed(host
->ioaddr
+
599 msm_offset
->core_dll_config
);
600 config
&= ~CORE_CK_OUT_EN
;
601 writel_relaxed(config
, host
->ioaddr
+
602 msm_offset
->core_dll_config
);
604 config
= readl_relaxed(host
->ioaddr
+
605 msm_offset
->core_dll_config_2
);
606 config
|= CORE_DLL_CLOCK_DISABLE
;
607 writel_relaxed(config
, host
->ioaddr
+
608 msm_offset
->core_dll_config_2
);
611 config
= readl_relaxed(host
->ioaddr
+
612 msm_offset
->core_dll_config
);
613 config
|= CORE_DLL_RST
;
614 writel_relaxed(config
, host
->ioaddr
+
615 msm_offset
->core_dll_config
);
617 config
= readl_relaxed(host
->ioaddr
+
618 msm_offset
->core_dll_config
);
619 config
|= CORE_DLL_PDN
;
620 writel_relaxed(config
, host
->ioaddr
+
621 msm_offset
->core_dll_config
);
622 msm_cm_dll_set_freq(host
);
624 if (msm_host
->use_14lpp_dll_reset
&&
625 !IS_ERR_OR_NULL(msm_host
->xo_clk
)) {
628 config
= readl_relaxed(host
->ioaddr
+
629 msm_offset
->core_dll_config_2
);
630 config
&= CORE_FLL_CYCLE_CNT
;
632 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 8),
635 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 4),
638 config
= readl_relaxed(host
->ioaddr
+
639 msm_offset
->core_dll_config_2
);
640 config
&= ~(0xFF << 10);
641 config
|= mclk_freq
<< 10;
643 writel_relaxed(config
, host
->ioaddr
+
644 msm_offset
->core_dll_config_2
);
645 /* wait for 5us before enabling DLL clock */
649 config
= readl_relaxed(host
->ioaddr
+
650 msm_offset
->core_dll_config
);
651 config
&= ~CORE_DLL_RST
;
652 writel_relaxed(config
, host
->ioaddr
+
653 msm_offset
->core_dll_config
);
655 config
= readl_relaxed(host
->ioaddr
+
656 msm_offset
->core_dll_config
);
657 config
&= ~CORE_DLL_PDN
;
658 writel_relaxed(config
, host
->ioaddr
+
659 msm_offset
->core_dll_config
);
661 if (msm_host
->use_14lpp_dll_reset
) {
662 msm_cm_dll_set_freq(host
);
663 config
= readl_relaxed(host
->ioaddr
+
664 msm_offset
->core_dll_config_2
);
665 config
&= ~CORE_DLL_CLOCK_DISABLE
;
666 writel_relaxed(config
, host
->ioaddr
+
667 msm_offset
->core_dll_config_2
);
670 config
= readl_relaxed(host
->ioaddr
+
671 msm_offset
->core_dll_config
);
672 config
|= CORE_DLL_EN
;
673 writel_relaxed(config
, host
->ioaddr
+
674 msm_offset
->core_dll_config
);
676 config
= readl_relaxed(host
->ioaddr
+
677 msm_offset
->core_dll_config
);
678 config
|= CORE_CK_OUT_EN
;
679 writel_relaxed(config
, host
->ioaddr
+
680 msm_offset
->core_dll_config
);
682 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
683 while (!(readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_status
) &
685 /* max. wait for 50us sec for LOCK bit to be set */
686 if (--wait_cnt
== 0) {
687 dev_err(mmc_dev(mmc
), "%s: DLL failed to LOCK\n",
689 spin_unlock_irqrestore(&host
->lock
, flags
);
695 spin_unlock_irqrestore(&host
->lock
, flags
);
699 static void msm_hc_select_default(struct sdhci_host
*host
)
701 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
702 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
704 const struct sdhci_msm_offset
*msm_offset
=
707 if (!msm_host
->use_cdclp533
) {
708 config
= readl_relaxed(host
->ioaddr
+
709 msm_offset
->core_vendor_spec3
);
710 config
&= ~CORE_PWRSAVE_DLL
;
711 writel_relaxed(config
, host
->ioaddr
+
712 msm_offset
->core_vendor_spec3
);
715 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
716 config
&= ~CORE_HC_MCLK_SEL_MASK
;
717 config
|= CORE_HC_MCLK_SEL_DFLT
;
718 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
721 * Disable HC_SELECT_IN to be able to use the UHS mode select
722 * configuration from Host Control2 register for all other
724 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
725 * in VENDOR_SPEC_FUNC
727 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
728 config
&= ~CORE_HC_SELECT_IN_EN
;
729 config
&= ~CORE_HC_SELECT_IN_MASK
;
730 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
733 * Make sure above writes impacting free running MCLK are completed
734 * before changing the clk_rate at GCC.
739 static void msm_hc_select_hs400(struct sdhci_host
*host
)
741 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
742 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
743 struct mmc_ios ios
= host
->mmc
->ios
;
744 u32 config
, dll_lock
;
746 const struct sdhci_msm_offset
*msm_offset
=
749 /* Select the divided clock (free running MCLK/2) */
750 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
751 config
&= ~CORE_HC_MCLK_SEL_MASK
;
752 config
|= CORE_HC_MCLK_SEL_HS400
;
754 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
756 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
759 if ((msm_host
->tuning_done
|| ios
.enhanced_strobe
) &&
760 !msm_host
->calibration_done
) {
761 config
= readl_relaxed(host
->ioaddr
+
762 msm_offset
->core_vendor_spec
);
763 config
|= CORE_HC_SELECT_IN_HS400
;
764 config
|= CORE_HC_SELECT_IN_EN
;
765 writel_relaxed(config
, host
->ioaddr
+
766 msm_offset
->core_vendor_spec
);
768 if (!msm_host
->clk_rate
&& !msm_host
->use_cdclp533
) {
770 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
771 * core_dll_status to be set. This should get set
772 * within 15 us at 200 MHz.
774 rc
= readl_relaxed_poll_timeout(host
->ioaddr
+
775 msm_offset
->core_dll_status
,
779 CORE_DDR_DLL_LOCK
)), 10,
781 if (rc
== -ETIMEDOUT
)
782 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
783 mmc_hostname(host
->mmc
), dll_lock
);
786 * Make sure above writes impacting free running MCLK are completed
787 * before changing the clk_rate at GCC.
793 * sdhci_msm_hc_select_mode :- In general all timing modes are
794 * controlled via UHS mode select in Host Control2 register.
795 * eMMC specific HS200/HS400 doesn't have their respective modes
796 * defined here, hence we use these values.
798 * HS200 - SDR104 (Since they both are equivalent in functionality)
799 * HS400 - This involves multiple configurations
800 * Initially SDR104 - when tuning is required as HS200
801 * Then when switching to DDR @ 400MHz (HS400) we use
802 * the vendor specific HC_SELECT_IN to control the mode.
804 * In addition to controlling the modes we also need to select the
805 * correct input clock for DLL depending on the mode.
807 * HS400 - divided clock (free running MCLK/2)
808 * All other modes - default (free running MCLK)
810 static void sdhci_msm_hc_select_mode(struct sdhci_host
*host
)
812 struct mmc_ios ios
= host
->mmc
->ios
;
814 if (ios
.timing
== MMC_TIMING_MMC_HS400
||
815 host
->flags
& SDHCI_HS400_TUNING
)
816 msm_hc_select_hs400(host
);
818 msm_hc_select_default(host
);
821 static int sdhci_msm_cdclp533_calibration(struct sdhci_host
*host
)
823 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
824 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
825 u32 config
, calib_done
;
827 const struct sdhci_msm_offset
*msm_offset
=
830 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
833 * Retuning in HS400 (DDR mode) will fail, just reset the
834 * tuning block and restore the saved tuning phase.
836 ret
= msm_init_cm_dll(host
);
840 /* Set the selected phase in delay line hw block */
841 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
845 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
846 config
|= CORE_CMD_DAT_TRACK_SEL
;
847 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
849 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
850 config
&= ~CORE_CDC_T4_DLY_SEL
;
851 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
853 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
854 config
&= ~CORE_CDC_SWITCH_BYPASS_OFF
;
855 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
857 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
858 config
|= CORE_CDC_SWITCH_RC_EN
;
859 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
861 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
862 config
&= ~CORE_START_CDC_TRAFFIC
;
863 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
865 /* Perform CDC Register Initialization Sequence */
867 writel_relaxed(0x11800EC, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
868 writel_relaxed(0x3011111, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG1
);
869 writel_relaxed(0x1201000, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
870 writel_relaxed(0x4, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG1
);
871 writel_relaxed(0xCB732020, host
->ioaddr
+ CORE_CSR_CDC_REFCOUNT_CFG
);
872 writel_relaxed(0xB19, host
->ioaddr
+ CORE_CSR_CDC_COARSE_CAL_CFG
);
873 writel_relaxed(0x4E2, host
->ioaddr
+ CORE_CSR_CDC_DELAY_CFG
);
874 writel_relaxed(0x0, host
->ioaddr
+ CORE_CDC_OFFSET_CFG
);
875 writel_relaxed(0x16334, host
->ioaddr
+ CORE_CDC_SLAVE_DDA_CFG
);
877 /* CDC HW Calibration */
879 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
880 config
|= CORE_SW_TRIG_FULL_CALIB
;
881 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
883 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
884 config
&= ~CORE_SW_TRIG_FULL_CALIB
;
885 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
887 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
888 config
|= CORE_HW_AUTOCAL_ENA
;
889 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
891 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
892 config
|= CORE_TIMER_ENA
;
893 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
895 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
,
897 (calib_done
& CORE_CALIBRATION_DONE
),
900 if (ret
== -ETIMEDOUT
) {
901 pr_err("%s: %s: CDC calibration was not completed\n",
902 mmc_hostname(host
->mmc
), __func__
);
906 ret
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
)
907 & CORE_CDC_ERROR_CODE_MASK
;
909 pr_err("%s: %s: CDC error code %d\n",
910 mmc_hostname(host
->mmc
), __func__
, ret
);
915 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
916 config
|= CORE_START_CDC_TRAFFIC
;
917 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
919 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
924 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host
*host
)
926 struct mmc_host
*mmc
= host
->mmc
;
927 u32 dll_status
, config
;
929 const struct sdhci_msm_offset
*msm_offset
=
930 sdhci_priv_msm_offset(host
);
932 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
935 * Currently the core_ddr_config register defaults to desired
936 * configuration on reset. Currently reprogramming the power on
937 * reset (POR) value in case it might have been modified by
938 * bootloaders. In the future, if this changes, then the desired
939 * values will need to be programmed appropriately.
941 writel_relaxed(DDR_CONFIG_POR_VAL
, host
->ioaddr
+
942 msm_offset
->core_ddr_config
);
944 if (mmc
->ios
.enhanced_strobe
) {
945 config
= readl_relaxed(host
->ioaddr
+
946 msm_offset
->core_ddr_200_cfg
);
947 config
|= CORE_CMDIN_RCLK_EN
;
948 writel_relaxed(config
, host
->ioaddr
+
949 msm_offset
->core_ddr_200_cfg
);
952 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config_2
);
953 config
|= CORE_DDR_CAL_EN
;
954 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config_2
);
956 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+
957 msm_offset
->core_dll_status
,
959 (dll_status
& CORE_DDR_DLL_LOCK
),
962 if (ret
== -ETIMEDOUT
) {
963 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
964 mmc_hostname(host
->mmc
), __func__
);
968 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec3
);
969 config
|= CORE_PWRSAVE_DLL
;
970 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec3
);
973 * Drain writebuffer to ensure above DLL calibration
974 * and PWRSAVE DLL is enabled.
978 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
983 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host
*host
)
985 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
986 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
987 struct mmc_host
*mmc
= host
->mmc
;
990 const struct sdhci_msm_offset
*msm_offset
=
993 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
996 * Retuning in HS400 (DDR mode) will fail, just reset the
997 * tuning block and restore the saved tuning phase.
999 ret
= msm_init_cm_dll(host
);
1003 if (!mmc
->ios
.enhanced_strobe
) {
1004 /* Set the selected phase in delay line hw block */
1005 ret
= msm_config_cm_dll_phase(host
,
1006 msm_host
->saved_tuning_phase
);
1009 config
= readl_relaxed(host
->ioaddr
+
1010 msm_offset
->core_dll_config
);
1011 config
|= CORE_CMD_DAT_TRACK_SEL
;
1012 writel_relaxed(config
, host
->ioaddr
+
1013 msm_offset
->core_dll_config
);
1016 if (msm_host
->use_cdclp533
)
1017 ret
= sdhci_msm_cdclp533_calibration(host
);
1019 ret
= sdhci_msm_cm_dll_sdc4_calibration(host
);
1021 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
1026 static bool sdhci_msm_is_tuning_needed(struct sdhci_host
*host
)
1028 struct mmc_ios
*ios
= &host
->mmc
->ios
;
1031 * Tuning is required for SDR104, HS200 and HS400 cards and
1032 * if clock frequency is greater than 100MHz in these modes.
1034 if (host
->clock
<= CORE_FREQ_100MHZ
||
1035 !(ios
->timing
== MMC_TIMING_MMC_HS400
||
1036 ios
->timing
== MMC_TIMING_MMC_HS200
||
1037 ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1038 ios
->enhanced_strobe
)
1044 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host
*host
)
1046 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1047 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1051 * SDR DLL comes into picture only for timing modes which needs
1054 if (!sdhci_msm_is_tuning_needed(host
))
1057 /* Reset the tuning block */
1058 ret
= msm_init_cm_dll(host
);
1062 /* Restore the tuning block */
1063 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
1068 static void sdhci_msm_set_cdr(struct sdhci_host
*host
, bool enable
)
1070 const struct sdhci_msm_offset
*msm_offset
= sdhci_priv_msm_offset(host
);
1071 u32 config
, oldconfig
= readl_relaxed(host
->ioaddr
+
1072 msm_offset
->core_dll_config
);
1076 config
|= CORE_CDR_EN
;
1077 config
&= ~CORE_CDR_EXT_EN
;
1079 config
&= ~CORE_CDR_EN
;
1080 config
|= CORE_CDR_EXT_EN
;
1083 if (config
!= oldconfig
) {
1084 writel_relaxed(config
, host
->ioaddr
+
1085 msm_offset
->core_dll_config
);
1089 static int sdhci_msm_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1091 struct sdhci_host
*host
= mmc_priv(mmc
);
1092 int tuning_seq_cnt
= 3;
1093 u8 phase
, tuned_phases
[16], tuned_phase_cnt
= 0;
1095 struct mmc_ios ios
= host
->mmc
->ios
;
1096 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1097 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1099 if (!sdhci_msm_is_tuning_needed(host
)) {
1100 msm_host
->use_cdr
= false;
1101 sdhci_msm_set_cdr(host
, false);
1105 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1106 msm_host
->use_cdr
= true;
1109 * For HS400 tuning in HS200 timing requires:
1110 * - select MCLK/2 in VENDOR_SPEC
1111 * - program MCLK to 400MHz (or nearest supported) in GCC
1113 if (host
->flags
& SDHCI_HS400_TUNING
) {
1114 sdhci_msm_hc_select_mode(host
);
1115 msm_set_clock_rate_for_bus_mode(host
, ios
.clock
);
1116 host
->flags
&= ~SDHCI_HS400_TUNING
;
1120 /* First of all reset the tuning block */
1121 rc
= msm_init_cm_dll(host
);
1127 /* Set the phase in delay line hw block */
1128 rc
= msm_config_cm_dll_phase(host
, phase
);
1132 rc
= mmc_send_tuning(mmc
, opcode
, NULL
);
1134 /* Tuning is successful at this tuning point */
1135 tuned_phases
[tuned_phase_cnt
++] = phase
;
1136 dev_dbg(mmc_dev(mmc
), "%s: Found good phase = %d\n",
1137 mmc_hostname(mmc
), phase
);
1139 } while (++phase
< ARRAY_SIZE(tuned_phases
));
1141 if (tuned_phase_cnt
) {
1142 rc
= msm_find_most_appropriate_phase(host
, tuned_phases
,
1150 * Finally set the selected phase in delay
1153 rc
= msm_config_cm_dll_phase(host
, phase
);
1156 msm_host
->saved_tuning_phase
= phase
;
1157 dev_dbg(mmc_dev(mmc
), "%s: Setting the tuning phase to %d\n",
1158 mmc_hostname(mmc
), phase
);
1160 if (--tuning_seq_cnt
)
1163 dev_dbg(mmc_dev(mmc
), "%s: No tuning point found\n",
1169 msm_host
->tuning_done
= true;
1174 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1175 * This needs to be done for both tuning and enhanced_strobe mode.
1176 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1177 * fixed feedback clock is used.
1179 static void sdhci_msm_hs400(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1181 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1182 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1185 if (host
->clock
> CORE_FREQ_100MHZ
&&
1186 (msm_host
->tuning_done
|| ios
->enhanced_strobe
) &&
1187 !msm_host
->calibration_done
) {
1188 ret
= sdhci_msm_hs400_dll_calibration(host
);
1190 msm_host
->calibration_done
= true;
1192 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1193 mmc_hostname(host
->mmc
), ret
);
1197 static void sdhci_msm_set_uhs_signaling(struct sdhci_host
*host
,
1200 struct mmc_host
*mmc
= host
->mmc
;
1201 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1202 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1205 const struct sdhci_msm_offset
*msm_offset
=
1208 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1209 /* Select Bus Speed Mode for host */
1210 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1212 case MMC_TIMING_UHS_SDR12
:
1213 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1215 case MMC_TIMING_UHS_SDR25
:
1216 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1218 case MMC_TIMING_UHS_SDR50
:
1219 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1221 case MMC_TIMING_MMC_HS400
:
1222 case MMC_TIMING_MMC_HS200
:
1223 case MMC_TIMING_UHS_SDR104
:
1224 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1226 case MMC_TIMING_UHS_DDR50
:
1227 case MMC_TIMING_MMC_DDR52
:
1228 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1233 * When clock frequency is less than 100MHz, the feedback clock must be
1234 * provided and DLL must not be used so that tuning can be skipped. To
1235 * provide feedback clock, the mode selection can be any value less
1236 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1238 if (host
->clock
<= CORE_FREQ_100MHZ
) {
1239 if (uhs
== MMC_TIMING_MMC_HS400
||
1240 uhs
== MMC_TIMING_MMC_HS200
||
1241 uhs
== MMC_TIMING_UHS_SDR104
)
1242 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1244 * DLL is not required for clock <= 100MHz
1245 * Thus, make sure DLL it is disabled when not required
1247 config
= readl_relaxed(host
->ioaddr
+
1248 msm_offset
->core_dll_config
);
1249 config
|= CORE_DLL_RST
;
1250 writel_relaxed(config
, host
->ioaddr
+
1251 msm_offset
->core_dll_config
);
1253 config
= readl_relaxed(host
->ioaddr
+
1254 msm_offset
->core_dll_config
);
1255 config
|= CORE_DLL_PDN
;
1256 writel_relaxed(config
, host
->ioaddr
+
1257 msm_offset
->core_dll_config
);
1260 * The DLL needs to be restored and CDCLP533 recalibrated
1261 * when the clock frequency is set back to 400MHz.
1263 msm_host
->calibration_done
= false;
1266 dev_dbg(mmc_dev(mmc
), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1267 mmc_hostname(host
->mmc
), host
->clock
, uhs
, ctrl_2
);
1268 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1270 if (mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
)
1271 sdhci_msm_hs400(host
, &mmc
->ios
);
1274 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host
*msm_host
)
1276 init_waitqueue_head(&msm_host
->pwr_irq_wait
);
1279 static inline void sdhci_msm_complete_pwr_irq_wait(
1280 struct sdhci_msm_host
*msm_host
)
1282 wake_up(&msm_host
->pwr_irq_wait
);
1286 * sdhci_msm_check_power_status API should be called when registers writes
1287 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1288 * To what state the register writes will change the IO lines should be passed
1289 * as the argument req_type. This API will check whether the IO line's state
1290 * is already the expected state and will wait for power irq only if
1291 * power irq is expected to be trigerred based on the current IO line state
1292 * and expected IO line state.
1294 static void sdhci_msm_check_power_status(struct sdhci_host
*host
, u32 req_type
)
1296 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1297 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1299 u32 val
= SWITCHABLE_SIGNALING_VOLTAGE
;
1300 const struct sdhci_msm_offset
*msm_offset
=
1303 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1304 mmc_hostname(host
->mmc
), __func__
, req_type
,
1305 msm_host
->curr_pwr_state
, msm_host
->curr_io_level
);
1308 * The power interrupt will not be generated for signal voltage
1309 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1310 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1313 if (!msm_host
->mci_removed
)
1314 val
= msm_host_readl(msm_host
, host
,
1315 msm_offset
->core_generics
);
1316 if ((req_type
& REQ_IO_HIGH
|| req_type
& REQ_IO_LOW
) &&
1317 !(val
& SWITCHABLE_SIGNALING_VOLTAGE
)) {
1322 * The IRQ for request type IO High/LOW will be generated when -
1323 * there is a state change in 1.8V enable bit (bit 3) of
1324 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1325 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1326 * to set it to 3.3V before card detection happens, the
1327 * IRQ doesn't get triggered as there is no state change in this bit.
1328 * The driver already handles this case by changing the IO voltage
1329 * level to high as part of controller power up sequence. Hence, check
1330 * for host->pwr to handle a case where IO voltage high request is
1331 * issued even before controller power up.
1333 if ((req_type
& REQ_IO_HIGH
) && !host
->pwr
) {
1334 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1335 mmc_hostname(host
->mmc
), req_type
);
1338 if ((req_type
& msm_host
->curr_pwr_state
) ||
1339 (req_type
& msm_host
->curr_io_level
))
1342 * This is needed here to handle cases where register writes will
1343 * not change the current bus state or io level of the controller.
1344 * In this case, no power irq will be triggerred and we should
1348 if (!wait_event_timeout(msm_host
->pwr_irq_wait
,
1349 msm_host
->pwr_irq_flag
,
1350 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS
)))
1351 dev_warn(&msm_host
->pdev
->dev
,
1352 "%s: pwr_irq for req: (%d) timed out\n",
1353 mmc_hostname(host
->mmc
), req_type
);
1355 pr_debug("%s: %s: request %d done\n", mmc_hostname(host
->mmc
),
1356 __func__
, req_type
);
1359 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host
*host
)
1361 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1362 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1363 const struct sdhci_msm_offset
*msm_offset
=
1366 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1367 mmc_hostname(host
->mmc
),
1368 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_status
),
1369 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_mask
),
1370 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_ctl
));
1373 static void sdhci_msm_handle_pwr_irq(struct sdhci_host
*host
, int irq
)
1375 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1376 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1377 u32 irq_status
, irq_ack
= 0;
1379 u32 pwr_state
= 0, io_level
= 0;
1381 const struct sdhci_msm_offset
*msm_offset
= msm_host
->offset
;
1383 irq_status
= msm_host_readl(msm_host
, host
,
1384 msm_offset
->core_pwrctl_status
);
1385 irq_status
&= INT_MASK
;
1387 msm_host_writel(msm_host
, irq_status
, host
,
1388 msm_offset
->core_pwrctl_clear
);
1391 * There is a rare HW scenario where the first clear pulse could be
1392 * lost when actual reset and clear/read of status register is
1393 * happening at a time. Hence, retry for at least 10 times to make
1394 * sure status register is cleared. Otherwise, this will result in
1395 * a spurious power IRQ resulting in system instability.
1397 while (irq_status
& msm_host_readl(msm_host
, host
,
1398 msm_offset
->core_pwrctl_status
)) {
1400 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1401 mmc_hostname(host
->mmc
), irq_status
);
1402 sdhci_msm_dump_pwr_ctrl_regs(host
);
1406 msm_host_writel(msm_host
, irq_status
, host
,
1407 msm_offset
->core_pwrctl_clear
);
1412 /* Handle BUS ON/OFF*/
1413 if (irq_status
& CORE_PWRCTL_BUS_ON
) {
1414 pwr_state
= REQ_BUS_ON
;
1415 io_level
= REQ_IO_HIGH
;
1416 irq_ack
|= CORE_PWRCTL_BUS_SUCCESS
;
1418 if (irq_status
& CORE_PWRCTL_BUS_OFF
) {
1419 pwr_state
= REQ_BUS_OFF
;
1420 io_level
= REQ_IO_LOW
;
1421 irq_ack
|= CORE_PWRCTL_BUS_SUCCESS
;
1423 /* Handle IO LOW/HIGH */
1424 if (irq_status
& CORE_PWRCTL_IO_LOW
) {
1425 io_level
= REQ_IO_LOW
;
1426 irq_ack
|= CORE_PWRCTL_IO_SUCCESS
;
1428 if (irq_status
& CORE_PWRCTL_IO_HIGH
) {
1429 io_level
= REQ_IO_HIGH
;
1430 irq_ack
|= CORE_PWRCTL_IO_SUCCESS
;
1434 * The driver has to acknowledge the interrupt, switch voltages and
1435 * report back if it succeded or not to this register. The voltage
1436 * switches are handled by the sdhci core, so just report success.
1438 msm_host_writel(msm_host
, irq_ack
, host
,
1439 msm_offset
->core_pwrctl_ctl
);
1442 * If we don't have info regarding the voltage levels supported by
1443 * regulators, don't change the IO PAD PWR SWITCH.
1445 if (msm_host
->caps_0
& CORE_VOLT_SUPPORT
) {
1448 * We should unset IO PAD PWR switch only if the register write
1449 * can set IO lines high and the regulator also switches to 3 V.
1450 * Else, we should keep the IO PAD PWR switch set.
1451 * This is applicable to certain targets where eMMC vccq supply
1452 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1453 * IO PAD PWR switch must be kept set to reflect actual
1454 * regulator voltage. This way, during initialization of
1455 * controllers with only 1.8V, we will set the IO PAD bit
1456 * without waiting for a REQ_IO_LOW.
1458 config
= readl_relaxed(host
->ioaddr
+
1459 msm_offset
->core_vendor_spec
);
1460 new_config
= config
;
1462 if ((io_level
& REQ_IO_HIGH
) &&
1463 (msm_host
->caps_0
& CORE_3_0V_SUPPORT
))
1464 new_config
&= ~CORE_IO_PAD_PWR_SWITCH
;
1465 else if ((io_level
& REQ_IO_LOW
) ||
1466 (msm_host
->caps_0
& CORE_1_8V_SUPPORT
))
1467 new_config
|= CORE_IO_PAD_PWR_SWITCH
;
1469 if (config
^ new_config
)
1470 writel_relaxed(new_config
, host
->ioaddr
+
1471 msm_offset
->core_vendor_spec
);
1475 msm_host
->curr_pwr_state
= pwr_state
;
1477 msm_host
->curr_io_level
= io_level
;
1479 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1480 mmc_hostname(msm_host
->mmc
), __func__
, irq
, irq_status
,
1484 static irqreturn_t
sdhci_msm_pwr_irq(int irq
, void *data
)
1486 struct sdhci_host
*host
= (struct sdhci_host
*)data
;
1487 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1488 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1490 sdhci_msm_handle_pwr_irq(host
, irq
);
1491 msm_host
->pwr_irq_flag
= 1;
1492 sdhci_msm_complete_pwr_irq_wait(msm_host
);
1498 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host
*host
)
1500 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1501 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1502 struct clk
*core_clk
= msm_host
->bulk_clks
[0].clk
;
1504 return clk_round_rate(core_clk
, ULONG_MAX
);
1507 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host
*host
)
1509 return SDHCI_MSM_MIN_CLOCK
;
1513 * __sdhci_msm_set_clock - sdhci_msm clock control.
1516 * MSM controller does not use internal divider and
1517 * instead directly control the GCC clock as per
1518 * HW recommendation.
1520 static void __sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1524 * Keep actual_clock as zero -
1525 * - since there is no divider used so no need of having actual_clock.
1526 * - MSM controller uses SDCLK for data timeout calculation. If
1527 * actual_clock is zero, host->clock is taken for calculation.
1529 host
->mmc
->actual_clock
= 0;
1531 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1537 * MSM controller do not use clock divider.
1538 * Thus read SDHCI_CLOCK_CONTROL and only enable
1539 * clock with no divider value programmed.
1541 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1542 sdhci_enable_clk(host
, clk
);
1545 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1546 static void sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1548 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1549 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1552 msm_host
->clk_rate
= clock
;
1556 sdhci_msm_hc_select_mode(host
);
1558 msm_set_clock_rate_for_bus_mode(host
, clock
);
1560 __sdhci_msm_set_clock(host
, clock
);
1564 * Platform specific register write functions. This is so that, if any
1565 * register write needs to be followed up by platform specific actions,
1566 * they can be added here. These functions can go to sleep when writes
1567 * to certain registers are done.
1568 * These functions are relying on sdhci_set_ios not using spinlock.
1570 static int __sdhci_msm_check_write(struct sdhci_host
*host
, u16 val
, int reg
)
1572 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1573 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1577 case SDHCI_HOST_CONTROL2
:
1578 req_type
= (val
& SDHCI_CTRL_VDD_180
) ? REQ_IO_LOW
:
1581 case SDHCI_SOFTWARE_RESET
:
1582 if (host
->pwr
&& (val
& SDHCI_RESET_ALL
))
1583 req_type
= REQ_BUS_OFF
;
1585 case SDHCI_POWER_CONTROL
:
1586 req_type
= !val
? REQ_BUS_OFF
: REQ_BUS_ON
;
1588 case SDHCI_TRANSFER_MODE
:
1589 msm_host
->transfer_mode
= val
;
1592 if (!msm_host
->use_cdr
)
1594 if ((msm_host
->transfer_mode
& SDHCI_TRNS_READ
) &&
1595 SDHCI_GET_CMD(val
) != MMC_SEND_TUNING_BLOCK_HS200
&&
1596 SDHCI_GET_CMD(val
) != MMC_SEND_TUNING_BLOCK
)
1597 sdhci_msm_set_cdr(host
, true);
1599 sdhci_msm_set_cdr(host
, false);
1604 msm_host
->pwr_irq_flag
= 0;
1606 * Since this register write may trigger a power irq, ensure
1607 * all previous register writes are complete by this point.
1614 /* This function may sleep*/
1615 static void sdhci_msm_writew(struct sdhci_host
*host
, u16 val
, int reg
)
1619 req_type
= __sdhci_msm_check_write(host
, val
, reg
);
1620 writew_relaxed(val
, host
->ioaddr
+ reg
);
1623 sdhci_msm_check_power_status(host
, req_type
);
1626 /* This function may sleep*/
1627 static void sdhci_msm_writeb(struct sdhci_host
*host
, u8 val
, int reg
)
1631 req_type
= __sdhci_msm_check_write(host
, val
, reg
);
1633 writeb_relaxed(val
, host
->ioaddr
+ reg
);
1636 sdhci_msm_check_power_status(host
, req_type
);
1639 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host
*msm_host
)
1641 struct mmc_host
*mmc
= msm_host
->mmc
;
1642 struct regulator
*supply
= mmc
->supply
.vqmmc
;
1643 u32 caps
= 0, config
;
1644 struct sdhci_host
*host
= mmc_priv(mmc
);
1645 const struct sdhci_msm_offset
*msm_offset
= msm_host
->offset
;
1647 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1648 if (regulator_is_supported_voltage(supply
, 1700000, 1950000))
1649 caps
|= CORE_1_8V_SUPPORT
;
1650 if (regulator_is_supported_voltage(supply
, 2700000, 3600000))
1651 caps
|= CORE_3_0V_SUPPORT
;
1654 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1660 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1661 * bit can be used as required later on.
1663 u32 io_level
= msm_host
->curr_io_level
;
1665 config
= readl_relaxed(host
->ioaddr
+
1666 msm_offset
->core_vendor_spec
);
1667 config
|= CORE_IO_PAD_PWR_SWITCH_EN
;
1669 if ((io_level
& REQ_IO_HIGH
) && (caps
& CORE_3_0V_SUPPORT
))
1670 config
&= ~CORE_IO_PAD_PWR_SWITCH
;
1671 else if ((io_level
& REQ_IO_LOW
) || (caps
& CORE_1_8V_SUPPORT
))
1672 config
|= CORE_IO_PAD_PWR_SWITCH
;
1674 writel_relaxed(config
,
1675 host
->ioaddr
+ msm_offset
->core_vendor_spec
);
1677 msm_host
->caps_0
|= caps
;
1678 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc
), caps
);
1681 static const struct sdhci_msm_variant_ops mci_var_ops
= {
1682 .msm_readl_relaxed
= sdhci_msm_mci_variant_readl_relaxed
,
1683 .msm_writel_relaxed
= sdhci_msm_mci_variant_writel_relaxed
,
1686 static const struct sdhci_msm_variant_ops v5_var_ops
= {
1687 .msm_readl_relaxed
= sdhci_msm_v5_variant_readl_relaxed
,
1688 .msm_writel_relaxed
= sdhci_msm_v5_variant_writel_relaxed
,
1691 static const struct sdhci_msm_variant_info sdhci_msm_mci_var
= {
1692 .var_ops
= &mci_var_ops
,
1693 .offset
= &sdhci_msm_mci_offset
,
1696 static const struct sdhci_msm_variant_info sdhci_msm_v5_var
= {
1697 .mci_removed
= true,
1698 .var_ops
= &v5_var_ops
,
1699 .offset
= &sdhci_msm_v5_offset
,
1702 static const struct sdhci_msm_variant_info sdm845_sdhci_var
= {
1703 .mci_removed
= true,
1704 .restore_dll_config
= true,
1705 .var_ops
= &v5_var_ops
,
1706 .offset
= &sdhci_msm_v5_offset
,
1709 static const struct of_device_id sdhci_msm_dt_match
[] = {
1710 {.compatible
= "qcom,sdhci-msm-v4", .data
= &sdhci_msm_mci_var
},
1711 {.compatible
= "qcom,sdhci-msm-v5", .data
= &sdhci_msm_v5_var
},
1712 {.compatible
= "qcom,sdm845-sdhci", .data
= &sdm845_sdhci_var
},
1716 MODULE_DEVICE_TABLE(of
, sdhci_msm_dt_match
);
1718 static const struct sdhci_ops sdhci_msm_ops
= {
1719 .reset
= sdhci_reset
,
1720 .set_clock
= sdhci_msm_set_clock
,
1721 .get_min_clock
= sdhci_msm_get_min_clock
,
1722 .get_max_clock
= sdhci_msm_get_max_clock
,
1723 .set_bus_width
= sdhci_set_bus_width
,
1724 .set_uhs_signaling
= sdhci_msm_set_uhs_signaling
,
1725 .write_w
= sdhci_msm_writew
,
1726 .write_b
= sdhci_msm_writeb
,
1729 static const struct sdhci_pltfm_data sdhci_msm_pdata
= {
1730 .quirks
= SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
1731 SDHCI_QUIRK_SINGLE_POWER_WRITE
|
1732 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1733 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1734 .ops
= &sdhci_msm_ops
,
1737 static int sdhci_msm_probe(struct platform_device
*pdev
)
1739 struct sdhci_host
*host
;
1740 struct sdhci_pltfm_host
*pltfm_host
;
1741 struct sdhci_msm_host
*msm_host
;
1742 struct resource
*core_memres
;
1745 u16 host_version
, core_minor
;
1746 u32 core_version
, config
;
1748 const struct sdhci_msm_offset
*msm_offset
;
1749 const struct sdhci_msm_variant_info
*var_info
;
1751 host
= sdhci_pltfm_init(pdev
, &sdhci_msm_pdata
, sizeof(*msm_host
));
1753 return PTR_ERR(host
);
1755 host
->sdma_boundary
= 0;
1756 pltfm_host
= sdhci_priv(host
);
1757 msm_host
= sdhci_pltfm_priv(pltfm_host
);
1758 msm_host
->mmc
= host
->mmc
;
1759 msm_host
->pdev
= pdev
;
1761 ret
= mmc_of_parse(host
->mmc
);
1766 * Based on the compatible string, load the required msm host info from
1767 * the data associated with the version info.
1769 var_info
= of_device_get_match_data(&pdev
->dev
);
1771 msm_host
->mci_removed
= var_info
->mci_removed
;
1772 msm_host
->restore_dll_config
= var_info
->restore_dll_config
;
1773 msm_host
->var_ops
= var_info
->var_ops
;
1774 msm_host
->offset
= var_info
->offset
;
1776 msm_offset
= msm_host
->offset
;
1778 sdhci_get_of_property(pdev
);
1780 msm_host
->saved_tuning_phase
= INVALID_TUNING_PHASE
;
1782 /* Setup SDCC bus voter clock. */
1783 msm_host
->bus_clk
= devm_clk_get(&pdev
->dev
, "bus");
1784 if (!IS_ERR(msm_host
->bus_clk
)) {
1785 /* Vote for max. clk rate for max. performance */
1786 ret
= clk_set_rate(msm_host
->bus_clk
, INT_MAX
);
1789 ret
= clk_prepare_enable(msm_host
->bus_clk
);
1794 /* Setup main peripheral bus clock */
1795 clk
= devm_clk_get(&pdev
->dev
, "iface");
1798 dev_err(&pdev
->dev
, "Peripheral clk setup failed (%d)\n", ret
);
1799 goto bus_clk_disable
;
1801 msm_host
->bulk_clks
[1].clk
= clk
;
1803 /* Setup SDC MMC clock */
1804 clk
= devm_clk_get(&pdev
->dev
, "core");
1807 dev_err(&pdev
->dev
, "SDC MMC clk setup failed (%d)\n", ret
);
1808 goto bus_clk_disable
;
1810 msm_host
->bulk_clks
[0].clk
= clk
;
1812 /* Vote for maximum clock rate for maximum performance */
1813 ret
= clk_set_rate(clk
, INT_MAX
);
1815 dev_warn(&pdev
->dev
, "core clock boost failed\n");
1817 clk
= devm_clk_get(&pdev
->dev
, "cal");
1820 msm_host
->bulk_clks
[2].clk
= clk
;
1822 clk
= devm_clk_get(&pdev
->dev
, "sleep");
1825 msm_host
->bulk_clks
[3].clk
= clk
;
1827 ret
= clk_bulk_prepare_enable(ARRAY_SIZE(msm_host
->bulk_clks
),
1828 msm_host
->bulk_clks
);
1830 goto bus_clk_disable
;
1833 * xo clock is needed for FLL feature of cm_dll.
1834 * In case if xo clock is not mentioned in DT, warn and proceed.
1836 msm_host
->xo_clk
= devm_clk_get(&pdev
->dev
, "xo");
1837 if (IS_ERR(msm_host
->xo_clk
)) {
1838 ret
= PTR_ERR(msm_host
->xo_clk
);
1839 dev_warn(&pdev
->dev
, "TCXO clk not present (%d)\n", ret
);
1842 if (!msm_host
->mci_removed
) {
1843 core_memres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1844 msm_host
->core_mem
= devm_ioremap_resource(&pdev
->dev
,
1847 if (IS_ERR(msm_host
->core_mem
)) {
1848 ret
= PTR_ERR(msm_host
->core_mem
);
1853 /* Reset the vendor spec register to power on reset state */
1854 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL
,
1855 host
->ioaddr
+ msm_offset
->core_vendor_spec
);
1857 if (!msm_host
->mci_removed
) {
1858 /* Set HC_MODE_EN bit in HC_MODE register */
1859 msm_host_writel(msm_host
, HC_MODE_EN
, host
,
1860 msm_offset
->core_hc_mode
);
1861 config
= msm_host_readl(msm_host
, host
,
1862 msm_offset
->core_hc_mode
);
1863 config
|= FF_CLK_SW_RST_DIS
;
1864 msm_host_writel(msm_host
, config
, host
,
1865 msm_offset
->core_hc_mode
);
1868 host_version
= readw_relaxed((host
->ioaddr
+ SDHCI_HOST_VERSION
));
1869 dev_dbg(&pdev
->dev
, "Host Version: 0x%x Vendor Version 0x%x\n",
1870 host_version
, ((host_version
& SDHCI_VENDOR_VER_MASK
) >>
1871 SDHCI_VENDOR_VER_SHIFT
));
1873 core_version
= msm_host_readl(msm_host
, host
,
1874 msm_offset
->core_mci_version
);
1875 core_major
= (core_version
& CORE_VERSION_MAJOR_MASK
) >>
1876 CORE_VERSION_MAJOR_SHIFT
;
1877 core_minor
= core_version
& CORE_VERSION_MINOR_MASK
;
1878 dev_dbg(&pdev
->dev
, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1879 core_version
, core_major
, core_minor
);
1881 if (core_major
== 1 && core_minor
>= 0x42)
1882 msm_host
->use_14lpp_dll_reset
= true;
1885 * SDCC 5 controller with major version 1, minor version 0x34 and later
1886 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1888 if (core_major
== 1 && core_minor
< 0x34)
1889 msm_host
->use_cdclp533
= true;
1892 * Support for some capabilities is not advertised by newer
1893 * controller versions and must be explicitly enabled.
1895 if (core_major
>= 1 && core_minor
!= 0x11 && core_minor
!= 0x12) {
1896 config
= readl_relaxed(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1897 config
|= SDHCI_CAN_VDD_300
| SDHCI_CAN_DO_8BIT
;
1898 writel_relaxed(config
, host
->ioaddr
+
1899 msm_offset
->core_vendor_spec_capabilities0
);
1903 * Power on reset state may trigger power irq if previous status of
1904 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1905 * interrupt in GIC, any pending power irq interrupt should be
1906 * acknowledged. Otherwise power irq interrupt handler would be
1907 * fired prematurely.
1909 sdhci_msm_handle_pwr_irq(host
, 0);
1912 * Ensure that above writes are propogated before interrupt enablement
1917 /* Setup IRQ for handling power/voltage tasks with PMIC */
1918 msm_host
->pwr_irq
= platform_get_irq_byname(pdev
, "pwr_irq");
1919 if (msm_host
->pwr_irq
< 0) {
1920 ret
= msm_host
->pwr_irq
;
1924 sdhci_msm_init_pwr_irq_wait(msm_host
);
1925 /* Enable pwr irq interrupts */
1926 msm_host_writel(msm_host
, INT_MASK
, host
,
1927 msm_offset
->core_pwrctl_mask
);
1929 ret
= devm_request_threaded_irq(&pdev
->dev
, msm_host
->pwr_irq
, NULL
,
1930 sdhci_msm_pwr_irq
, IRQF_ONESHOT
,
1931 dev_name(&pdev
->dev
), host
);
1933 dev_err(&pdev
->dev
, "Request IRQ failed (%d)\n", ret
);
1937 pm_runtime_get_noresume(&pdev
->dev
);
1938 pm_runtime_set_active(&pdev
->dev
);
1939 pm_runtime_enable(&pdev
->dev
);
1940 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1941 MSM_MMC_AUTOSUSPEND_DELAY_MS
);
1942 pm_runtime_use_autosuspend(&pdev
->dev
);
1944 host
->mmc_host_ops
.execute_tuning
= sdhci_msm_execute_tuning
;
1945 ret
= sdhci_add_host(host
);
1947 goto pm_runtime_disable
;
1948 sdhci_msm_set_regulator_caps(msm_host
);
1950 pm_runtime_mark_last_busy(&pdev
->dev
);
1951 pm_runtime_put_autosuspend(&pdev
->dev
);
1956 pm_runtime_disable(&pdev
->dev
);
1957 pm_runtime_set_suspended(&pdev
->dev
);
1958 pm_runtime_put_noidle(&pdev
->dev
);
1960 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
1961 msm_host
->bulk_clks
);
1963 if (!IS_ERR(msm_host
->bus_clk
))
1964 clk_disable_unprepare(msm_host
->bus_clk
);
1966 sdhci_pltfm_free(pdev
);
1970 static int sdhci_msm_remove(struct platform_device
*pdev
)
1972 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
1973 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1974 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1975 int dead
= (readl_relaxed(host
->ioaddr
+ SDHCI_INT_STATUS
) ==
1978 sdhci_remove_host(host
, dead
);
1980 pm_runtime_get_sync(&pdev
->dev
);
1981 pm_runtime_disable(&pdev
->dev
);
1982 pm_runtime_put_noidle(&pdev
->dev
);
1984 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
1985 msm_host
->bulk_clks
);
1986 if (!IS_ERR(msm_host
->bus_clk
))
1987 clk_disable_unprepare(msm_host
->bus_clk
);
1988 sdhci_pltfm_free(pdev
);
1992 static __maybe_unused
int sdhci_msm_runtime_suspend(struct device
*dev
)
1994 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1995 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1996 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1998 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
1999 msm_host
->bulk_clks
);
2004 static __maybe_unused
int sdhci_msm_runtime_resume(struct device
*dev
)
2006 struct sdhci_host
*host
= dev_get_drvdata(dev
);
2007 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2008 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2011 ret
= clk_bulk_prepare_enable(ARRAY_SIZE(msm_host
->bulk_clks
),
2012 msm_host
->bulk_clks
);
2016 * Whenever core-clock is gated dynamically, it's needed to
2017 * restore the SDR DLL settings when the clock is ungated.
2019 if (msm_host
->restore_dll_config
&& msm_host
->clk_rate
)
2020 return sdhci_msm_restore_sdr_dll_config(host
);
2025 static const struct dev_pm_ops sdhci_msm_pm_ops
= {
2026 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
2027 pm_runtime_force_resume
)
2028 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend
,
2029 sdhci_msm_runtime_resume
,
2033 static struct platform_driver sdhci_msm_driver
= {
2034 .probe
= sdhci_msm_probe
,
2035 .remove
= sdhci_msm_remove
,
2037 .name
= "sdhci_msm",
2038 .of_match_table
= sdhci_msm_dt_match
,
2039 .pm
= &sdhci_msm_pm_ops
,
2043 module_platform_driver(sdhci_msm_driver
);
2045 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2046 MODULE_LICENSE("GPL v2");