2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
25 #include "sdhci-pltfm.h"
27 #define CORE_MCI_VERSION 0x50
28 #define CORE_VERSION_MAJOR_SHIFT 28
29 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK 0xff
32 #define CORE_HC_MODE 0x78
33 #define HC_MODE_EN 0x1
34 #define CORE_POWER 0x0
35 #define CORE_SW_RST BIT(7)
36 #define FF_CLK_SW_RST_DIS BIT(13)
38 #define CORE_PWRCTL_STATUS 0xdc
39 #define CORE_PWRCTL_MASK 0xe0
40 #define CORE_PWRCTL_CLEAR 0xe4
41 #define CORE_PWRCTL_CTL 0xe8
42 #define CORE_PWRCTL_BUS_OFF BIT(0)
43 #define CORE_PWRCTL_BUS_ON BIT(1)
44 #define CORE_PWRCTL_IO_LOW BIT(2)
45 #define CORE_PWRCTL_IO_HIGH BIT(3)
46 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
47 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
48 #define REQ_BUS_OFF BIT(0)
49 #define REQ_BUS_ON BIT(1)
50 #define REQ_IO_LOW BIT(2)
51 #define REQ_IO_HIGH BIT(3)
54 #define CORE_DLL_LOCK BIT(7)
55 #define CORE_DDR_DLL_LOCK BIT(11)
56 #define CORE_DLL_EN BIT(16)
57 #define CORE_CDR_EN BIT(17)
58 #define CORE_CK_OUT_EN BIT(18)
59 #define CORE_CDR_EXT_EN BIT(19)
60 #define CORE_DLL_PDN BIT(29)
61 #define CORE_DLL_RST BIT(30)
62 #define CORE_DLL_CONFIG 0x100
63 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
64 #define CORE_DLL_STATUS 0x108
66 #define CORE_DLL_CONFIG_2 0x1b4
67 #define CORE_DDR_CAL_EN BIT(0)
68 #define CORE_FLL_CYCLE_CNT BIT(18)
69 #define CORE_DLL_CLOCK_DISABLE BIT(21)
71 #define CORE_VENDOR_SPEC 0x10c
72 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
73 #define CORE_CLK_PWRSAVE BIT(1)
74 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
75 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
76 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
77 #define CORE_HC_SELECT_IN_EN BIT(18)
78 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
79 #define CORE_HC_SELECT_IN_MASK (7 << 19)
81 #define CORE_CSR_CDC_CTLR_CFG0 0x130
82 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
83 #define CORE_HW_AUTOCAL_ENA BIT(17)
85 #define CORE_CSR_CDC_CTLR_CFG1 0x134
86 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
87 #define CORE_TIMER_ENA BIT(16)
89 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
90 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
91 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
92 #define CORE_CDC_OFFSET_CFG 0x14C
93 #define CORE_CSR_CDC_DELAY_CFG 0x150
94 #define CORE_CDC_SLAVE_DDA_CFG 0x160
95 #define CORE_CSR_CDC_STATUS0 0x164
96 #define CORE_CALIBRATION_DONE BIT(0)
98 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
100 #define CORE_CSR_CDC_GEN_CFG 0x178
101 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
102 #define CORE_CDC_SWITCH_RC_EN BIT(1)
104 #define CORE_DDR_200_CFG 0x184
105 #define CORE_CDC_T4_DLY_SEL BIT(0)
106 #define CORE_START_CDC_TRAFFIC BIT(6)
107 #define CORE_VENDOR_SPEC3 0x1b0
108 #define CORE_PWRSAVE_DLL BIT(3)
110 #define CORE_DDR_CONFIG 0x1b8
111 #define DDR_CONFIG_POR_VAL 0x80040853
113 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
115 #define INVALID_TUNING_PHASE -1
116 #define SDHCI_MSM_MIN_CLOCK 400000
117 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
119 #define CDR_SELEXT_SHIFT 20
120 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
121 #define CMUX_SHIFT_PHASE_SHIFT 24
122 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
124 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
125 struct sdhci_msm_host
{
126 struct platform_device
*pdev
;
127 void __iomem
*core_mem
; /* MSM SDCC mapped address */
128 int pwr_irq
; /* power irq */
129 struct clk
*clk
; /* main SD/MMC bus clock */
130 struct clk
*pclk
; /* SDHC peripheral bus clock */
131 struct clk
*bus_clk
; /* SDHC bus voter clock */
132 struct clk
*xo_clk
; /* TCXO clk needed for FLL feature of cm_dll*/
133 unsigned long clk_rate
;
134 struct mmc_host
*mmc
;
135 bool use_14lpp_dll_reset
;
137 bool calibration_done
;
138 u8 saved_tuning_phase
;
142 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host
*host
,
145 struct mmc_ios ios
= host
->mmc
->ios
;
147 * The SDHC requires internal clock frequency to be double the
148 * actual clock that will be set for DDR mode. The controller
149 * uses the faster clock(100/400MHz) for some of its parts and
150 * send the actual required clock (50/200MHz) to the card.
152 if (ios
.timing
== MMC_TIMING_UHS_DDR50
||
153 ios
.timing
== MMC_TIMING_MMC_DDR52
||
154 ios
.timing
== MMC_TIMING_MMC_HS400
)
159 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host
*host
,
162 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
163 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
164 struct mmc_ios curr_ios
= host
->mmc
->ios
;
167 clock
= msm_get_clock_rate_for_bus_mode(host
, clock
);
168 rc
= clk_set_rate(msm_host
->clk
, clock
);
170 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
171 mmc_hostname(host
->mmc
), clock
,
175 msm_host
->clk_rate
= clock
;
176 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
177 mmc_hostname(host
->mmc
), clk_get_rate(msm_host
->clk
),
181 /* Platform specific tuning */
182 static inline int msm_dll_poll_ck_out_en(struct sdhci_host
*host
, u8 poll
)
186 struct mmc_host
*mmc
= host
->mmc
;
188 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
189 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
192 while (ck_out_en
!= poll
) {
193 if (--wait_cnt
== 0) {
194 dev_err(mmc_dev(mmc
), "%s: CK_OUT_EN bit is not %d\n",
195 mmc_hostname(mmc
), poll
);
200 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
207 static int msm_config_cm_dll_phase(struct sdhci_host
*host
, u8 phase
)
210 static const u8 grey_coded_phase_table
[] = {
211 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
212 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
216 struct mmc_host
*mmc
= host
->mmc
;
221 spin_lock_irqsave(&host
->lock
, flags
);
223 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
224 config
&= ~(CORE_CDR_EN
| CORE_CK_OUT_EN
);
225 config
|= (CORE_CDR_EXT_EN
| CORE_DLL_EN
);
226 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
228 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
229 rc
= msm_dll_poll_ck_out_en(host
, 0);
234 * Write the selected DLL clock output phase (0 ... 15)
235 * to CDR_SELEXT bit field of DLL_CONFIG register.
237 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
238 config
&= ~CDR_SELEXT_MASK
;
239 config
|= grey_coded_phase_table
[phase
] << CDR_SELEXT_SHIFT
;
240 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
242 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
243 config
|= CORE_CK_OUT_EN
;
244 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
246 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
247 rc
= msm_dll_poll_ck_out_en(host
, 1);
251 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
252 config
|= CORE_CDR_EN
;
253 config
&= ~CORE_CDR_EXT_EN
;
254 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
258 dev_err(mmc_dev(mmc
), "%s: Failed to set DLL phase: %d\n",
259 mmc_hostname(mmc
), phase
);
261 spin_unlock_irqrestore(&host
->lock
, flags
);
266 * Find out the greatest range of consecuitive selected
267 * DLL clock output phases that can be used as sampling
268 * setting for SD3.0 UHS-I card read operation (in SDR104
269 * timing mode) or for eMMC4.5 card read operation (in
270 * HS400/HS200 timing mode).
271 * Select the 3/4 of the range and configure the DLL with the
272 * selected DLL clock output phase.
275 static int msm_find_most_appropriate_phase(struct sdhci_host
*host
,
276 u8
*phase_table
, u8 total_phases
)
279 u8 ranges
[MAX_PHASES
][MAX_PHASES
] = { {0}, {0} };
280 u8 phases_per_row
[MAX_PHASES
] = { 0 };
281 int row_index
= 0, col_index
= 0, selected_row_index
= 0, curr_max
= 0;
282 int i
, cnt
, phase_0_raw_index
= 0, phase_15_raw_index
= 0;
283 bool phase_0_found
= false, phase_15_found
= false;
284 struct mmc_host
*mmc
= host
->mmc
;
286 if (!total_phases
|| (total_phases
> MAX_PHASES
)) {
287 dev_err(mmc_dev(mmc
), "%s: Invalid argument: total_phases=%d\n",
288 mmc_hostname(mmc
), total_phases
);
292 for (cnt
= 0; cnt
< total_phases
; cnt
++) {
293 ranges
[row_index
][col_index
] = phase_table
[cnt
];
294 phases_per_row
[row_index
] += 1;
297 if ((cnt
+ 1) == total_phases
) {
299 /* check if next phase in phase_table is consecutive or not */
300 } else if ((phase_table
[cnt
] + 1) != phase_table
[cnt
+ 1]) {
306 if (row_index
>= MAX_PHASES
)
309 /* Check if phase-0 is present in first valid window? */
311 phase_0_found
= true;
312 phase_0_raw_index
= 0;
313 /* Check if cycle exist between 2 valid windows */
314 for (cnt
= 1; cnt
<= row_index
; cnt
++) {
315 if (phases_per_row
[cnt
]) {
316 for (i
= 0; i
< phases_per_row
[cnt
]; i
++) {
317 if (ranges
[cnt
][i
] == 15) {
318 phase_15_found
= true;
319 phase_15_raw_index
= cnt
;
327 /* If 2 valid windows form cycle then merge them as single window */
328 if (phase_0_found
&& phase_15_found
) {
329 /* number of phases in raw where phase 0 is present */
330 u8 phases_0
= phases_per_row
[phase_0_raw_index
];
331 /* number of phases in raw where phase 15 is present */
332 u8 phases_15
= phases_per_row
[phase_15_raw_index
];
334 if (phases_0
+ phases_15
>= MAX_PHASES
)
336 * If there are more than 1 phase windows then total
337 * number of phases in both the windows should not be
338 * more than or equal to MAX_PHASES.
342 /* Merge 2 cyclic windows */
344 for (cnt
= 0; cnt
< phases_0
; cnt
++) {
345 ranges
[phase_15_raw_index
][i
] =
346 ranges
[phase_0_raw_index
][cnt
];
347 if (++i
>= MAX_PHASES
)
351 phases_per_row
[phase_0_raw_index
] = 0;
352 phases_per_row
[phase_15_raw_index
] = phases_15
+ phases_0
;
355 for (cnt
= 0; cnt
<= row_index
; cnt
++) {
356 if (phases_per_row
[cnt
] > curr_max
) {
357 curr_max
= phases_per_row
[cnt
];
358 selected_row_index
= cnt
;
362 i
= (curr_max
* 3) / 4;
366 ret
= ranges
[selected_row_index
][i
];
368 if (ret
>= MAX_PHASES
) {
370 dev_err(mmc_dev(mmc
), "%s: Invalid phase selected=%d\n",
371 mmc_hostname(mmc
), ret
);
377 static inline void msm_cm_dll_set_freq(struct sdhci_host
*host
)
379 u32 mclk_freq
= 0, config
;
381 /* Program the MCLK value to MCLK_FREQ bit field */
382 if (host
->clock
<= 112000000)
384 else if (host
->clock
<= 125000000)
386 else if (host
->clock
<= 137000000)
388 else if (host
->clock
<= 150000000)
390 else if (host
->clock
<= 162000000)
392 else if (host
->clock
<= 175000000)
394 else if (host
->clock
<= 187000000)
396 else if (host
->clock
<= 200000000)
399 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
400 config
&= ~CMUX_SHIFT_PHASE_MASK
;
401 config
|= mclk_freq
<< CMUX_SHIFT_PHASE_SHIFT
;
402 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
405 /* Initialize the DLL (Programmable Delay Line) */
406 static int msm_init_cm_dll(struct sdhci_host
*host
)
408 struct mmc_host
*mmc
= host
->mmc
;
409 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
410 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
415 spin_lock_irqsave(&host
->lock
, flags
);
418 * Make sure that clock is always enabled when DLL
419 * tuning is in progress. Keeping PWRSAVE ON may
420 * turn off the clock.
422 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
423 config
&= ~CORE_CLK_PWRSAVE
;
424 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
426 if (msm_host
->use_14lpp_dll_reset
) {
427 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
428 config
&= ~CORE_CK_OUT_EN
;
429 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
431 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
432 config
|= CORE_DLL_CLOCK_DISABLE
;
433 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
436 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
437 config
|= CORE_DLL_RST
;
438 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
440 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
441 config
|= CORE_DLL_PDN
;
442 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
443 msm_cm_dll_set_freq(host
);
445 if (msm_host
->use_14lpp_dll_reset
&&
446 !IS_ERR_OR_NULL(msm_host
->xo_clk
)) {
449 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
450 config
&= CORE_FLL_CYCLE_CNT
;
452 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 8),
453 clk_get_rate(msm_host
->xo_clk
));
455 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 4),
456 clk_get_rate(msm_host
->xo_clk
));
458 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
459 config
&= ~(0xFF << 10);
460 config
|= mclk_freq
<< 10;
462 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
463 /* wait for 5us before enabling DLL clock */
467 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
468 config
&= ~CORE_DLL_RST
;
469 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
471 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
472 config
&= ~CORE_DLL_PDN
;
473 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
475 if (msm_host
->use_14lpp_dll_reset
) {
476 msm_cm_dll_set_freq(host
);
477 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
478 config
&= ~CORE_DLL_CLOCK_DISABLE
;
479 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
482 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
483 config
|= CORE_DLL_EN
;
484 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
486 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
487 config
|= CORE_CK_OUT_EN
;
488 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
490 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
491 while (!(readl_relaxed(host
->ioaddr
+ CORE_DLL_STATUS
) &
493 /* max. wait for 50us sec for LOCK bit to be set */
494 if (--wait_cnt
== 0) {
495 dev_err(mmc_dev(mmc
), "%s: DLL failed to LOCK\n",
497 spin_unlock_irqrestore(&host
->lock
, flags
);
503 spin_unlock_irqrestore(&host
->lock
, flags
);
507 static void msm_hc_select_default(struct sdhci_host
*host
)
509 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
510 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
513 if (!msm_host
->use_cdclp533
) {
514 config
= readl_relaxed(host
->ioaddr
+
516 config
&= ~CORE_PWRSAVE_DLL
;
517 writel_relaxed(config
, host
->ioaddr
+
521 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
522 config
&= ~CORE_HC_MCLK_SEL_MASK
;
523 config
|= CORE_HC_MCLK_SEL_DFLT
;
524 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
527 * Disable HC_SELECT_IN to be able to use the UHS mode select
528 * configuration from Host Control2 register for all other
530 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
531 * in VENDOR_SPEC_FUNC
533 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
534 config
&= ~CORE_HC_SELECT_IN_EN
;
535 config
&= ~CORE_HC_SELECT_IN_MASK
;
536 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
539 * Make sure above writes impacting free running MCLK are completed
540 * before changing the clk_rate at GCC.
545 static void msm_hc_select_hs400(struct sdhci_host
*host
)
547 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
548 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
549 u32 config
, dll_lock
;
552 /* Select the divided clock (free running MCLK/2) */
553 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
554 config
&= ~CORE_HC_MCLK_SEL_MASK
;
555 config
|= CORE_HC_MCLK_SEL_HS400
;
557 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
559 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
562 if (msm_host
->tuning_done
&& !msm_host
->calibration_done
) {
563 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
564 config
|= CORE_HC_SELECT_IN_HS400
;
565 config
|= CORE_HC_SELECT_IN_EN
;
566 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
568 if (!msm_host
->clk_rate
&& !msm_host
->use_cdclp533
) {
570 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
571 * CORE_DLL_STATUS to be set. This should get set
572 * within 15 us at 200 MHz.
574 rc
= readl_relaxed_poll_timeout(host
->ioaddr
+
579 CORE_DDR_DLL_LOCK
)), 10,
581 if (rc
== -ETIMEDOUT
)
582 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
583 mmc_hostname(host
->mmc
), dll_lock
);
586 * Make sure above writes impacting free running MCLK are completed
587 * before changing the clk_rate at GCC.
593 * sdhci_msm_hc_select_mode :- In general all timing modes are
594 * controlled via UHS mode select in Host Control2 register.
595 * eMMC specific HS200/HS400 doesn't have their respective modes
596 * defined here, hence we use these values.
598 * HS200 - SDR104 (Since they both are equivalent in functionality)
599 * HS400 - This involves multiple configurations
600 * Initially SDR104 - when tuning is required as HS200
601 * Then when switching to DDR @ 400MHz (HS400) we use
602 * the vendor specific HC_SELECT_IN to control the mode.
604 * In addition to controlling the modes we also need to select the
605 * correct input clock for DLL depending on the mode.
607 * HS400 - divided clock (free running MCLK/2)
608 * All other modes - default (free running MCLK)
610 void sdhci_msm_hc_select_mode(struct sdhci_host
*host
)
612 struct mmc_ios ios
= host
->mmc
->ios
;
614 if (ios
.timing
== MMC_TIMING_MMC_HS400
)
615 msm_hc_select_hs400(host
);
617 msm_hc_select_default(host
);
620 static int sdhci_msm_cdclp533_calibration(struct sdhci_host
*host
)
622 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
623 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
624 u32 config
, calib_done
;
627 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
630 * Retuning in HS400 (DDR mode) will fail, just reset the
631 * tuning block and restore the saved tuning phase.
633 ret
= msm_init_cm_dll(host
);
637 /* Set the selected phase in delay line hw block */
638 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
642 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
643 config
|= CORE_CMD_DAT_TRACK_SEL
;
644 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
646 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
647 config
&= ~CORE_CDC_T4_DLY_SEL
;
648 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
650 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
651 config
&= ~CORE_CDC_SWITCH_BYPASS_OFF
;
652 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
654 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
655 config
|= CORE_CDC_SWITCH_RC_EN
;
656 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
658 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
659 config
&= ~CORE_START_CDC_TRAFFIC
;
660 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
663 * Perform CDC Register Initialization Sequence
665 * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
666 * CORE_CSR_CDC_CTLR_CFG1 0x3011111
667 * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
668 * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
669 * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
670 * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
671 * CORE_CSR_CDC_DELAY_CFG 0x3AC
672 * CORE_CDC_OFFSET_CFG 0x0
673 * CORE_CDC_SLAVE_DDA_CFG 0x16334
676 writel_relaxed(0x11800EC, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
677 writel_relaxed(0x3011111, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG1
);
678 writel_relaxed(0x1201000, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
679 writel_relaxed(0x4, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG1
);
680 writel_relaxed(0xCB732020, host
->ioaddr
+ CORE_CSR_CDC_REFCOUNT_CFG
);
681 writel_relaxed(0xB19, host
->ioaddr
+ CORE_CSR_CDC_COARSE_CAL_CFG
);
682 writel_relaxed(0x4E2, host
->ioaddr
+ CORE_CSR_CDC_DELAY_CFG
);
683 writel_relaxed(0x0, host
->ioaddr
+ CORE_CDC_OFFSET_CFG
);
684 writel_relaxed(0x16334, host
->ioaddr
+ CORE_CDC_SLAVE_DDA_CFG
);
686 /* CDC HW Calibration */
688 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
689 config
|= CORE_SW_TRIG_FULL_CALIB
;
690 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
692 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
693 config
&= ~CORE_SW_TRIG_FULL_CALIB
;
694 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
696 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
697 config
|= CORE_HW_AUTOCAL_ENA
;
698 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
700 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
701 config
|= CORE_TIMER_ENA
;
702 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
704 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
,
706 (calib_done
& CORE_CALIBRATION_DONE
),
709 if (ret
== -ETIMEDOUT
) {
710 pr_err("%s: %s: CDC calibration was not completed\n",
711 mmc_hostname(host
->mmc
), __func__
);
715 ret
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
)
716 & CORE_CDC_ERROR_CODE_MASK
;
718 pr_err("%s: %s: CDC error code %d\n",
719 mmc_hostname(host
->mmc
), __func__
, ret
);
724 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
725 config
|= CORE_START_CDC_TRAFFIC
;
726 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
728 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
733 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host
*host
)
735 u32 dll_status
, config
;
738 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
741 * Currently the CORE_DDR_CONFIG register defaults to desired
742 * configuration on reset. Currently reprogramming the power on
743 * reset (POR) value in case it might have been modified by
744 * bootloaders. In the future, if this changes, then the desired
745 * values will need to be programmed appropriately.
747 writel_relaxed(DDR_CONFIG_POR_VAL
, host
->ioaddr
+ CORE_DDR_CONFIG
);
749 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
750 config
|= CORE_DDR_CAL_EN
;
751 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
753 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_DLL_STATUS
,
755 (dll_status
& CORE_DDR_DLL_LOCK
),
758 if (ret
== -ETIMEDOUT
) {
759 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
760 mmc_hostname(host
->mmc
), __func__
);
764 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC3
);
765 config
|= CORE_PWRSAVE_DLL
;
766 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC3
);
769 * Drain writebuffer to ensure above DLL calibration
770 * and PWRSAVE DLL is enabled.
774 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
779 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host
*host
)
781 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
782 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
786 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
789 * Retuning in HS400 (DDR mode) will fail, just reset the
790 * tuning block and restore the saved tuning phase.
792 ret
= msm_init_cm_dll(host
);
796 /* Set the selected phase in delay line hw block */
797 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
801 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
802 config
|= CORE_CMD_DAT_TRACK_SEL
;
803 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
804 if (msm_host
->use_cdclp533
)
805 ret
= sdhci_msm_cdclp533_calibration(host
);
807 ret
= sdhci_msm_cm_dll_sdc4_calibration(host
);
809 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
814 static int sdhci_msm_execute_tuning(struct sdhci_host
*host
, u32 opcode
)
816 int tuning_seq_cnt
= 3;
817 u8 phase
, tuned_phases
[16], tuned_phase_cnt
= 0;
819 struct mmc_host
*mmc
= host
->mmc
;
820 struct mmc_ios ios
= host
->mmc
->ios
;
821 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
822 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
825 * Tuning is required for SDR104, HS200 and HS400 cards and
826 * if clock frequency is greater than 100MHz in these modes.
828 if (host
->clock
<= CORE_FREQ_100MHZ
||
829 !(ios
.timing
== MMC_TIMING_MMC_HS400
||
830 ios
.timing
== MMC_TIMING_MMC_HS200
||
831 ios
.timing
== MMC_TIMING_UHS_SDR104
))
835 /* First of all reset the tuning block */
836 rc
= msm_init_cm_dll(host
);
842 /* Set the phase in delay line hw block */
843 rc
= msm_config_cm_dll_phase(host
, phase
);
847 msm_host
->saved_tuning_phase
= phase
;
848 rc
= mmc_send_tuning(mmc
, opcode
, NULL
);
850 /* Tuning is successful at this tuning point */
851 tuned_phases
[tuned_phase_cnt
++] = phase
;
852 dev_dbg(mmc_dev(mmc
), "%s: Found good phase = %d\n",
853 mmc_hostname(mmc
), phase
);
855 } while (++phase
< ARRAY_SIZE(tuned_phases
));
857 if (tuned_phase_cnt
) {
858 rc
= msm_find_most_appropriate_phase(host
, tuned_phases
,
866 * Finally set the selected phase in delay
869 rc
= msm_config_cm_dll_phase(host
, phase
);
872 dev_dbg(mmc_dev(mmc
), "%s: Setting the tuning phase to %d\n",
873 mmc_hostname(mmc
), phase
);
875 if (--tuning_seq_cnt
)
878 dev_dbg(mmc_dev(mmc
), "%s: No tuning point found\n",
884 msm_host
->tuning_done
= true;
889 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
890 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
891 * fixed feedback clock is used.
893 static void sdhci_msm_hs400(struct sdhci_host
*host
, struct mmc_ios
*ios
)
895 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
896 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
899 if (host
->clock
> CORE_FREQ_100MHZ
&&
900 msm_host
->tuning_done
&& !msm_host
->calibration_done
) {
901 ret
= sdhci_msm_hs400_dll_calibration(host
);
903 msm_host
->calibration_done
= true;
905 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
906 mmc_hostname(host
->mmc
), ret
);
910 static void sdhci_msm_set_uhs_signaling(struct sdhci_host
*host
,
913 struct mmc_host
*mmc
= host
->mmc
;
914 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
915 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
919 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
920 /* Select Bus Speed Mode for host */
921 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
923 case MMC_TIMING_UHS_SDR12
:
924 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
926 case MMC_TIMING_UHS_SDR25
:
927 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
929 case MMC_TIMING_UHS_SDR50
:
930 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
932 case MMC_TIMING_MMC_HS400
:
933 case MMC_TIMING_MMC_HS200
:
934 case MMC_TIMING_UHS_SDR104
:
935 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
937 case MMC_TIMING_UHS_DDR50
:
938 case MMC_TIMING_MMC_DDR52
:
939 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
944 * When clock frequency is less than 100MHz, the feedback clock must be
945 * provided and DLL must not be used so that tuning can be skipped. To
946 * provide feedback clock, the mode selection can be any value less
947 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
949 if (host
->clock
<= CORE_FREQ_100MHZ
) {
950 if (uhs
== MMC_TIMING_MMC_HS400
||
951 uhs
== MMC_TIMING_MMC_HS200
||
952 uhs
== MMC_TIMING_UHS_SDR104
)
953 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
955 * DLL is not required for clock <= 100MHz
956 * Thus, make sure DLL it is disabled when not required
958 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
959 config
|= CORE_DLL_RST
;
960 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
962 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
963 config
|= CORE_DLL_PDN
;
964 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
967 * The DLL needs to be restored and CDCLP533 recalibrated
968 * when the clock frequency is set back to 400MHz.
970 msm_host
->calibration_done
= false;
973 dev_dbg(mmc_dev(mmc
), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
974 mmc_hostname(host
->mmc
), host
->clock
, uhs
, ctrl_2
);
975 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
977 spin_unlock_irq(&host
->lock
);
979 if (mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
)
980 sdhci_msm_hs400(host
, &mmc
->ios
);
982 spin_lock_irq(&host
->lock
);
985 static void sdhci_msm_voltage_switch(struct sdhci_host
*host
)
987 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
988 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
989 u32 irq_status
, irq_ack
= 0;
991 irq_status
= readl_relaxed(msm_host
->core_mem
+ CORE_PWRCTL_STATUS
);
992 irq_status
&= INT_MASK
;
994 writel_relaxed(irq_status
, msm_host
->core_mem
+ CORE_PWRCTL_CLEAR
);
996 if (irq_status
& (CORE_PWRCTL_BUS_ON
| CORE_PWRCTL_BUS_OFF
))
997 irq_ack
|= CORE_PWRCTL_BUS_SUCCESS
;
998 if (irq_status
& (CORE_PWRCTL_IO_LOW
| CORE_PWRCTL_IO_HIGH
))
999 irq_ack
|= CORE_PWRCTL_IO_SUCCESS
;
1002 * The driver has to acknowledge the interrupt, switch voltages and
1003 * report back if it succeded or not to this register. The voltage
1004 * switches are handled by the sdhci core, so just report success.
1006 writel_relaxed(irq_ack
, msm_host
->core_mem
+ CORE_PWRCTL_CTL
);
1009 static irqreturn_t
sdhci_msm_pwr_irq(int irq
, void *data
)
1011 struct sdhci_host
*host
= (struct sdhci_host
*)data
;
1013 sdhci_msm_voltage_switch(host
);
1018 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host
*host
)
1020 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1021 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1023 return clk_round_rate(msm_host
->clk
, ULONG_MAX
);
1026 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host
*host
)
1028 return SDHCI_MSM_MIN_CLOCK
;
1032 * __sdhci_msm_set_clock - sdhci_msm clock control.
1035 * MSM controller does not use internal divider and
1036 * instead directly control the GCC clock as per
1037 * HW recommendation.
1039 void __sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1043 * Keep actual_clock as zero -
1044 * - since there is no divider used so no need of having actual_clock.
1045 * - MSM controller uses SDCLK for data timeout calculation. If
1046 * actual_clock is zero, host->clock is taken for calculation.
1048 host
->mmc
->actual_clock
= 0;
1050 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1056 * MSM controller do not use clock divider.
1057 * Thus read SDHCI_CLOCK_CONTROL and only enable
1058 * clock with no divider value programmed.
1060 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1061 sdhci_enable_clk(host
, clk
);
1064 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1065 static void sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1067 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1068 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1071 msm_host
->clk_rate
= clock
;
1075 spin_unlock_irq(&host
->lock
);
1077 sdhci_msm_hc_select_mode(host
);
1079 msm_set_clock_rate_for_bus_mode(host
, clock
);
1081 spin_lock_irq(&host
->lock
);
1083 __sdhci_msm_set_clock(host
, clock
);
1086 static const struct of_device_id sdhci_msm_dt_match
[] = {
1087 { .compatible
= "qcom,sdhci-msm-v4" },
1091 MODULE_DEVICE_TABLE(of
, sdhci_msm_dt_match
);
1093 static const struct sdhci_ops sdhci_msm_ops
= {
1094 .platform_execute_tuning
= sdhci_msm_execute_tuning
,
1095 .reset
= sdhci_reset
,
1096 .set_clock
= sdhci_msm_set_clock
,
1097 .get_min_clock
= sdhci_msm_get_min_clock
,
1098 .get_max_clock
= sdhci_msm_get_max_clock
,
1099 .set_bus_width
= sdhci_set_bus_width
,
1100 .set_uhs_signaling
= sdhci_msm_set_uhs_signaling
,
1101 .voltage_switch
= sdhci_msm_voltage_switch
,
1104 static const struct sdhci_pltfm_data sdhci_msm_pdata
= {
1105 .quirks
= SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
1106 SDHCI_QUIRK_NO_CARD_NO_RESET
|
1107 SDHCI_QUIRK_SINGLE_POWER_WRITE
|
1108 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1109 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1110 .ops
= &sdhci_msm_ops
,
1113 static int sdhci_msm_probe(struct platform_device
*pdev
)
1115 struct sdhci_host
*host
;
1116 struct sdhci_pltfm_host
*pltfm_host
;
1117 struct sdhci_msm_host
*msm_host
;
1118 struct resource
*core_memres
;
1120 u16 host_version
, core_minor
;
1121 u32 core_version
, config
;
1124 host
= sdhci_pltfm_init(pdev
, &sdhci_msm_pdata
, sizeof(*msm_host
));
1126 return PTR_ERR(host
);
1128 pltfm_host
= sdhci_priv(host
);
1129 msm_host
= sdhci_pltfm_priv(pltfm_host
);
1130 msm_host
->mmc
= host
->mmc
;
1131 msm_host
->pdev
= pdev
;
1133 ret
= mmc_of_parse(host
->mmc
);
1137 sdhci_get_of_property(pdev
);
1139 msm_host
->saved_tuning_phase
= INVALID_TUNING_PHASE
;
1141 /* Setup SDCC bus voter clock. */
1142 msm_host
->bus_clk
= devm_clk_get(&pdev
->dev
, "bus");
1143 if (!IS_ERR(msm_host
->bus_clk
)) {
1144 /* Vote for max. clk rate for max. performance */
1145 ret
= clk_set_rate(msm_host
->bus_clk
, INT_MAX
);
1148 ret
= clk_prepare_enable(msm_host
->bus_clk
);
1153 /* Setup main peripheral bus clock */
1154 msm_host
->pclk
= devm_clk_get(&pdev
->dev
, "iface");
1155 if (IS_ERR(msm_host
->pclk
)) {
1156 ret
= PTR_ERR(msm_host
->pclk
);
1157 dev_err(&pdev
->dev
, "Peripheral clk setup failed (%d)\n", ret
);
1158 goto bus_clk_disable
;
1161 ret
= clk_prepare_enable(msm_host
->pclk
);
1163 goto bus_clk_disable
;
1165 /* Setup SDC MMC clock */
1166 msm_host
->clk
= devm_clk_get(&pdev
->dev
, "core");
1167 if (IS_ERR(msm_host
->clk
)) {
1168 ret
= PTR_ERR(msm_host
->clk
);
1169 dev_err(&pdev
->dev
, "SDC MMC clk setup failed (%d)\n", ret
);
1174 * xo clock is needed for FLL feature of cm_dll.
1175 * In case if xo clock is not mentioned in DT, warn and proceed.
1177 msm_host
->xo_clk
= devm_clk_get(&pdev
->dev
, "xo");
1178 if (IS_ERR(msm_host
->xo_clk
)) {
1179 ret
= PTR_ERR(msm_host
->xo_clk
);
1180 dev_warn(&pdev
->dev
, "TCXO clk not present (%d)\n", ret
);
1183 /* Vote for maximum clock rate for maximum performance */
1184 ret
= clk_set_rate(msm_host
->clk
, INT_MAX
);
1186 dev_warn(&pdev
->dev
, "core clock boost failed\n");
1188 ret
= clk_prepare_enable(msm_host
->clk
);
1192 core_memres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1193 msm_host
->core_mem
= devm_ioremap_resource(&pdev
->dev
, core_memres
);
1195 if (IS_ERR(msm_host
->core_mem
)) {
1196 dev_err(&pdev
->dev
, "Failed to remap registers\n");
1197 ret
= PTR_ERR(msm_host
->core_mem
);
1201 /* Reset the vendor spec register to power on reset state */
1202 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL
,
1203 host
->ioaddr
+ CORE_VENDOR_SPEC
);
1205 /* Set HC_MODE_EN bit in HC_MODE register */
1206 writel_relaxed(HC_MODE_EN
, (msm_host
->core_mem
+ CORE_HC_MODE
));
1208 config
= readl_relaxed(msm_host
->core_mem
+ CORE_HC_MODE
);
1209 config
|= FF_CLK_SW_RST_DIS
;
1210 writel_relaxed(config
, msm_host
->core_mem
+ CORE_HC_MODE
);
1212 host_version
= readw_relaxed((host
->ioaddr
+ SDHCI_HOST_VERSION
));
1213 dev_dbg(&pdev
->dev
, "Host Version: 0x%x Vendor Version 0x%x\n",
1214 host_version
, ((host_version
& SDHCI_VENDOR_VER_MASK
) >>
1215 SDHCI_VENDOR_VER_SHIFT
));
1217 core_version
= readl_relaxed(msm_host
->core_mem
+ CORE_MCI_VERSION
);
1218 core_major
= (core_version
& CORE_VERSION_MAJOR_MASK
) >>
1219 CORE_VERSION_MAJOR_SHIFT
;
1220 core_minor
= core_version
& CORE_VERSION_MINOR_MASK
;
1221 dev_dbg(&pdev
->dev
, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1222 core_version
, core_major
, core_minor
);
1224 if (core_major
== 1 && core_minor
>= 0x42)
1225 msm_host
->use_14lpp_dll_reset
= true;
1228 * SDCC 5 controller with major version 1, minor version 0x34 and later
1229 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1231 if (core_major
== 1 && core_minor
< 0x34)
1232 msm_host
->use_cdclp533
= true;
1235 * Support for some capabilities is not advertised by newer
1236 * controller versions and must be explicitly enabled.
1238 if (core_major
>= 1 && core_minor
!= 0x11 && core_minor
!= 0x12) {
1239 config
= readl_relaxed(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1240 config
|= SDHCI_CAN_VDD_300
| SDHCI_CAN_DO_8BIT
;
1241 writel_relaxed(config
, host
->ioaddr
+
1242 CORE_VENDOR_SPEC_CAPABILITIES0
);
1245 /* Setup IRQ for handling power/voltage tasks with PMIC */
1246 msm_host
->pwr_irq
= platform_get_irq_byname(pdev
, "pwr_irq");
1247 if (msm_host
->pwr_irq
< 0) {
1248 dev_err(&pdev
->dev
, "Get pwr_irq failed (%d)\n",
1250 ret
= msm_host
->pwr_irq
;
1254 ret
= devm_request_threaded_irq(&pdev
->dev
, msm_host
->pwr_irq
, NULL
,
1255 sdhci_msm_pwr_irq
, IRQF_ONESHOT
,
1256 dev_name(&pdev
->dev
), host
);
1258 dev_err(&pdev
->dev
, "Request IRQ failed (%d)\n", ret
);
1262 pm_runtime_get_noresume(&pdev
->dev
);
1263 pm_runtime_set_active(&pdev
->dev
);
1264 pm_runtime_enable(&pdev
->dev
);
1265 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1266 MSM_MMC_AUTOSUSPEND_DELAY_MS
);
1267 pm_runtime_use_autosuspend(&pdev
->dev
);
1269 ret
= sdhci_add_host(host
);
1271 goto pm_runtime_disable
;
1273 pm_runtime_mark_last_busy(&pdev
->dev
);
1274 pm_runtime_put_autosuspend(&pdev
->dev
);
1279 pm_runtime_disable(&pdev
->dev
);
1280 pm_runtime_set_suspended(&pdev
->dev
);
1281 pm_runtime_put_noidle(&pdev
->dev
);
1283 clk_disable_unprepare(msm_host
->clk
);
1285 clk_disable_unprepare(msm_host
->pclk
);
1287 if (!IS_ERR(msm_host
->bus_clk
))
1288 clk_disable_unprepare(msm_host
->bus_clk
);
1290 sdhci_pltfm_free(pdev
);
1294 static int sdhci_msm_remove(struct platform_device
*pdev
)
1296 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
1297 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1298 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1299 int dead
= (readl_relaxed(host
->ioaddr
+ SDHCI_INT_STATUS
) ==
1302 sdhci_remove_host(host
, dead
);
1304 pm_runtime_get_sync(&pdev
->dev
);
1305 pm_runtime_disable(&pdev
->dev
);
1306 pm_runtime_put_noidle(&pdev
->dev
);
1308 clk_disable_unprepare(msm_host
->clk
);
1309 clk_disable_unprepare(msm_host
->pclk
);
1310 if (!IS_ERR(msm_host
->bus_clk
))
1311 clk_disable_unprepare(msm_host
->bus_clk
);
1312 sdhci_pltfm_free(pdev
);
1317 static int sdhci_msm_runtime_suspend(struct device
*dev
)
1319 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1320 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1321 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1323 clk_disable_unprepare(msm_host
->clk
);
1324 clk_disable_unprepare(msm_host
->pclk
);
1329 static int sdhci_msm_runtime_resume(struct device
*dev
)
1331 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1332 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1333 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1336 ret
= clk_prepare_enable(msm_host
->clk
);
1338 dev_err(dev
, "clk_enable failed for core_clk: %d\n", ret
);
1341 ret
= clk_prepare_enable(msm_host
->pclk
);
1343 dev_err(dev
, "clk_enable failed for iface_clk: %d\n", ret
);
1344 clk_disable_unprepare(msm_host
->clk
);
1352 static const struct dev_pm_ops sdhci_msm_pm_ops
= {
1353 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
1354 pm_runtime_force_resume
)
1355 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend
,
1356 sdhci_msm_runtime_resume
,
1360 static struct platform_driver sdhci_msm_driver
= {
1361 .probe
= sdhci_msm_probe
,
1362 .remove
= sdhci_msm_remove
,
1364 .name
= "sdhci_msm",
1365 .of_match_table
= sdhci_msm_dt_match
,
1366 .pm
= &sdhci_msm_pm_ops
,
1370 module_platform_driver(sdhci_msm_driver
);
1372 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1373 MODULE_LICENSE("GPL v2");