2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
8 * Based on sdhci-of-esdhc.c
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/regmap.h>
27 #include "sdhci-pltfm.h"
29 #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
30 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
32 #define VENDOR_ENHANCED_STROBE BIT(0)
33 #define CLK_CTRL_TIMEOUT_SHIFT 16
34 #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
35 #define CLK_CTRL_TIMEOUT_MIN_EXP 13
38 * On some SoCs the syscon area has a feature where the upper 16-bits of
39 * each 32-bit register act as a write mask for the lower 16-bits. This allows
40 * atomic updates of the register without locking. This macro is used on SoCs
41 * that have that feature.
43 #define HIWORD_UPDATE(val, mask, shift) \
44 ((val) << (shift) | (mask) << ((shift) + 16))
47 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
49 * @reg: Offset within the syscon of the register containing this field
50 * @width: Number of bits for this field
51 * @shift: Bit offset within @reg of this field (or -1 if not avail)
53 struct sdhci_arasan_soc_ctl_field
{
60 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
62 * It's up to the licensee of the Arsan IP block to make these available
63 * somewhere if needed. Presumably these will be scattered somewhere that's
64 * accessible via the syscon API.
66 * @baseclkfreq: Where to find corecfg_baseclkfreq
67 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
69 struct sdhci_arasan_soc_ctl_map
{
70 struct sdhci_arasan_soc_ctl_field baseclkfreq
;
75 * struct sdhci_arasan_data
76 * @clk_ahb: Pointer to the AHB clock
77 * @phy: Pointer to the generic phy
78 * @phy_on: True if the PHY is turned on.
79 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
80 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
82 struct sdhci_arasan_data
{
87 struct regmap
*soc_ctl_base
;
88 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
;
91 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map
= {
92 .baseclkfreq
= { .reg
= 0xf000, .width
= 8, .shift
= 8 },
93 .hiword_update
= true,
97 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
99 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
100 * Note that if a field is specified as not available (shift < 0) then
101 * this function will silently return an error code. It will be noisy
102 * and print errors for any other (unexpected) errors.
104 * @host: The sdhci_host
105 * @fld: The field to write to
106 * @val: The value to write
108 static int sdhci_arasan_syscon_write(struct sdhci_host
*host
,
109 const struct sdhci_arasan_soc_ctl_field
*fld
,
112 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
113 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
114 struct regmap
*soc_ctl_base
= sdhci_arasan
->soc_ctl_base
;
116 u16 width
= fld
->width
;
117 s16 shift
= fld
->shift
;
121 * Silently return errors for shift < 0 so caller doesn't have
122 * to check for fields which are optional. For fields that
123 * are required then caller needs to do something special
129 if (sdhci_arasan
->soc_ctl_map
->hiword_update
)
130 ret
= regmap_write(soc_ctl_base
, reg
,
131 HIWORD_UPDATE(val
, GENMASK(width
, 0),
134 ret
= regmap_update_bits(soc_ctl_base
, reg
,
135 GENMASK(shift
+ width
, shift
),
138 /* Yell about (unexpected) regmap errors */
140 pr_warn("%s: Regmap write fail: %d\n",
141 mmc_hostname(host
->mmc
), ret
);
146 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host
*host
)
150 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
152 div
= readl(host
->ioaddr
+ SDHCI_ARASAN_CLK_CTRL_OFFSET
);
153 div
= (div
& CLK_CTRL_TIMEOUT_MASK
) >> CLK_CTRL_TIMEOUT_SHIFT
;
155 freq
= clk_get_rate(pltfm_host
->clk
);
156 freq
/= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP
+ div
);
161 static void sdhci_arasan_set_clock(struct sdhci_host
*host
, unsigned int clock
)
163 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
164 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
166 if (sdhci_arasan
->phy_on
&& !IS_ERR(sdhci_arasan
->phy
)) {
167 sdhci_arasan
->phy_on
= false;
169 spin_unlock_irq(&host
->lock
);
170 phy_power_off(sdhci_arasan
->phy
);
171 spin_lock_irq(&host
->lock
);
174 sdhci_set_clock(host
, clock
);
176 if (host
->mmc
->actual_clock
&& !IS_ERR(sdhci_arasan
->phy
)) {
177 sdhci_arasan
->phy_on
= true;
179 spin_unlock_irq(&host
->lock
);
180 phy_power_on(sdhci_arasan
->phy
);
181 spin_lock_irq(&host
->lock
);
185 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host
*mmc
,
189 struct sdhci_host
*host
= mmc_priv(mmc
);
191 vendor
= readl(host
->ioaddr
+ SDHCI_ARASAN_VENDOR_REGISTER
);
192 if (ios
->enhanced_strobe
)
193 vendor
|= VENDOR_ENHANCED_STROBE
;
195 vendor
&= ~VENDOR_ENHANCED_STROBE
;
197 writel(vendor
, host
->ioaddr
+ SDHCI_ARASAN_VENDOR_REGISTER
);
200 static struct sdhci_ops sdhci_arasan_ops
= {
201 .set_clock
= sdhci_arasan_set_clock
,
202 .get_max_clock
= sdhci_pltfm_clk_get_max_clock
,
203 .get_timeout_clock
= sdhci_arasan_get_timeout_clock
,
204 .set_bus_width
= sdhci_set_bus_width
,
205 .reset
= sdhci_reset
,
206 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
209 static struct sdhci_pltfm_data sdhci_arasan_pdata
= {
210 .ops
= &sdhci_arasan_ops
,
211 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
212 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
|
213 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
,
216 #ifdef CONFIG_PM_SLEEP
218 * sdhci_arasan_suspend - Suspend method for the driver
219 * @dev: Address of the device structure
220 * Returns 0 on success and error value on error
222 * Put the device in a low power state.
224 static int sdhci_arasan_suspend(struct device
*dev
)
226 struct platform_device
*pdev
= to_platform_device(dev
);
227 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
228 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
229 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
232 ret
= sdhci_suspend_host(host
);
236 if (!IS_ERR(sdhci_arasan
->phy
)) {
237 ret
= phy_power_off(sdhci_arasan
->phy
);
239 dev_err(dev
, "Cannot power off phy.\n");
240 sdhci_resume_host(host
);
245 clk_disable(pltfm_host
->clk
);
246 clk_disable(sdhci_arasan
->clk_ahb
);
252 * sdhci_arasan_resume - Resume method for the driver
253 * @dev: Address of the device structure
254 * Returns 0 on success and error value on error
256 * Resume operation after suspend
258 static int sdhci_arasan_resume(struct device
*dev
)
260 struct platform_device
*pdev
= to_platform_device(dev
);
261 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
262 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
263 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
266 ret
= clk_enable(sdhci_arasan
->clk_ahb
);
268 dev_err(dev
, "Cannot enable AHB clock.\n");
272 ret
= clk_enable(pltfm_host
->clk
);
274 dev_err(dev
, "Cannot enable SD clock.\n");
278 if (!IS_ERR(sdhci_arasan
->phy
)) {
279 ret
= phy_power_on(sdhci_arasan
->phy
);
281 dev_err(dev
, "Cannot power on phy.\n");
286 return sdhci_resume_host(host
);
288 #endif /* ! CONFIG_PM_SLEEP */
290 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops
, sdhci_arasan_suspend
,
291 sdhci_arasan_resume
);
293 static const struct of_device_id sdhci_arasan_of_match
[] = {
294 /* SoC-specific compatible strings w/ soc_ctl_map */
296 .compatible
= "rockchip,rk3399-sdhci-5.1",
297 .data
= &rk3399_soc_ctl_map
,
300 /* Generic compatible below here */
301 { .compatible
= "arasan,sdhci-8.9a" },
302 { .compatible
= "arasan,sdhci-5.1" },
303 { .compatible
= "arasan,sdhci-4.9a" },
307 MODULE_DEVICE_TABLE(of
, sdhci_arasan_of_match
);
310 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
312 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
313 * function can be used to make that happen.
316 * - Many existing devices don't seem to do this and work fine. To keep
317 * compatibility for old hardware where the device tree doesn't provide a
318 * register map, this function is a noop if a soc_ctl_map hasn't been provided
320 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
321 * to achieve lower clock rates. That means that this function is called once
322 * at probe time and never called again.
324 * @host: The sdhci_host
326 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host
*host
)
328 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
329 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
330 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
=
331 sdhci_arasan
->soc_ctl_map
;
332 u32 mhz
= DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host
->clk
), 1000000);
334 /* Having a map is optional */
338 /* If we have a map, we expect to have a syscon */
339 if (!sdhci_arasan
->soc_ctl_base
) {
340 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
341 mmc_hostname(host
->mmc
));
345 sdhci_arasan_syscon_write(host
, &soc_ctl_map
->baseclkfreq
, mhz
);
348 static int sdhci_arasan_probe(struct platform_device
*pdev
)
351 const struct of_device_id
*match
;
352 struct device_node
*node
;
354 struct sdhci_host
*host
;
355 struct sdhci_pltfm_host
*pltfm_host
;
356 struct sdhci_arasan_data
*sdhci_arasan
;
358 host
= sdhci_pltfm_init(pdev
, &sdhci_arasan_pdata
,
359 sizeof(*sdhci_arasan
));
361 return PTR_ERR(host
);
363 pltfm_host
= sdhci_priv(host
);
364 sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
366 match
= of_match_node(sdhci_arasan_of_match
, pdev
->dev
.of_node
);
367 sdhci_arasan
->soc_ctl_map
= match
->data
;
369 node
= of_parse_phandle(pdev
->dev
.of_node
, "arasan,soc-ctl-syscon", 0);
371 sdhci_arasan
->soc_ctl_base
= syscon_node_to_regmap(node
);
374 if (IS_ERR(sdhci_arasan
->soc_ctl_base
)) {
375 ret
= PTR_ERR(sdhci_arasan
->soc_ctl_base
);
376 if (ret
!= -EPROBE_DEFER
)
377 dev_err(&pdev
->dev
, "Can't get syscon: %d\n",
383 sdhci_arasan
->clk_ahb
= devm_clk_get(&pdev
->dev
, "clk_ahb");
384 if (IS_ERR(sdhci_arasan
->clk_ahb
)) {
385 dev_err(&pdev
->dev
, "clk_ahb clock not found.\n");
386 ret
= PTR_ERR(sdhci_arasan
->clk_ahb
);
390 clk_xin
= devm_clk_get(&pdev
->dev
, "clk_xin");
391 if (IS_ERR(clk_xin
)) {
392 dev_err(&pdev
->dev
, "clk_xin clock not found.\n");
393 ret
= PTR_ERR(clk_xin
);
397 ret
= clk_prepare_enable(sdhci_arasan
->clk_ahb
);
399 dev_err(&pdev
->dev
, "Unable to enable AHB clock.\n");
403 ret
= clk_prepare_enable(clk_xin
);
405 dev_err(&pdev
->dev
, "Unable to enable SD clock.\n");
409 sdhci_get_of_property(pdev
);
410 pltfm_host
->clk
= clk_xin
;
412 sdhci_arasan_update_baseclkfreq(host
);
414 ret
= mmc_of_parse(host
->mmc
);
416 dev_err(&pdev
->dev
, "parsing dt failed (%u)\n", ret
);
417 goto clk_disable_all
;
420 sdhci_arasan
->phy
= ERR_PTR(-ENODEV
);
421 if (of_device_is_compatible(pdev
->dev
.of_node
,
422 "arasan,sdhci-5.1")) {
423 sdhci_arasan
->phy
= devm_phy_get(&pdev
->dev
,
425 if (IS_ERR(sdhci_arasan
->phy
)) {
426 ret
= PTR_ERR(sdhci_arasan
->phy
);
427 dev_err(&pdev
->dev
, "No phy for arasan,sdhci-5.1.\n");
428 goto clk_disable_all
;
431 ret
= phy_init(sdhci_arasan
->phy
);
433 dev_err(&pdev
->dev
, "phy_init err.\n");
434 goto clk_disable_all
;
437 host
->mmc_host_ops
.hs400_enhanced_strobe
=
438 sdhci_arasan_hs400_enhanced_strobe
;
441 ret
= sdhci_add_host(host
);
448 if (!IS_ERR(sdhci_arasan
->phy
))
449 phy_exit(sdhci_arasan
->phy
);
451 clk_disable_unprepare(clk_xin
);
453 clk_disable_unprepare(sdhci_arasan
->clk_ahb
);
455 sdhci_pltfm_free(pdev
);
459 static int sdhci_arasan_remove(struct platform_device
*pdev
)
462 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
463 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
464 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
465 struct clk
*clk_ahb
= sdhci_arasan
->clk_ahb
;
467 if (!IS_ERR(sdhci_arasan
->phy
)) {
468 phy_power_off(sdhci_arasan
->phy
);
469 phy_exit(sdhci_arasan
->phy
);
472 ret
= sdhci_pltfm_unregister(pdev
);
474 clk_disable_unprepare(clk_ahb
);
479 static struct platform_driver sdhci_arasan_driver
= {
481 .name
= "sdhci-arasan",
482 .of_match_table
= sdhci_arasan_of_match
,
483 .pm
= &sdhci_arasan_dev_pm_ops
,
485 .probe
= sdhci_arasan_probe
,
486 .remove
= sdhci_arasan_remove
,
489 module_platform_driver(sdhci_arasan_driver
);
491 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
492 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
493 MODULE_LICENSE("GPL");