1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
9 * Based on sdhci-of-esdhc.c
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
27 #include "sdhci-pltfm.h"
29 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
30 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
31 #define VENDOR_ENHANCED_STROBE BIT(0)
33 #define PHY_CLK_TOO_SLOW_HZ 400000
36 * On some SoCs the syscon area has a feature where the upper 16-bits of
37 * each 32-bit register act as a write mask for the lower 16-bits. This allows
38 * atomic updates of the register without locking. This macro is used on SoCs
39 * that have that feature.
41 #define HIWORD_UPDATE(val, mask, shift) \
42 ((val) << (shift) | (mask) << ((shift) + 16))
45 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
47 * @reg: Offset within the syscon of the register containing this field
48 * @width: Number of bits for this field
49 * @shift: Bit offset within @reg of this field (or -1 if not avail)
51 struct sdhci_arasan_soc_ctl_field
{
58 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
60 * It's up to the licensee of the Arsan IP block to make these available
61 * somewhere if needed. Presumably these will be scattered somewhere that's
62 * accessible via the syscon API.
64 * @baseclkfreq: Where to find corecfg_baseclkfreq
65 * @clockmultiplier: Where to find corecfg_clockmultiplier
66 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
68 struct sdhci_arasan_soc_ctl_map
{
69 struct sdhci_arasan_soc_ctl_field baseclkfreq
;
70 struct sdhci_arasan_soc_ctl_field clockmultiplier
;
75 * struct sdhci_arasan_data
76 * @host: Pointer to the main SDHCI host structure.
77 * @clk_ahb: Pointer to the AHB clock
78 * @phy: Pointer to the generic phy
79 * @is_phy_on: True if the PHY is on; false if not.
80 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
81 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
82 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
83 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
85 struct sdhci_arasan_data
{
86 struct sdhci_host
*host
;
92 struct clk_hw sdcardclk_hw
;
93 struct clk
*sdcardclk
;
95 struct regmap
*soc_ctl_base
;
96 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
;
97 unsigned int quirks
; /* Arasan deviations from spec */
99 /* Controller does not have CD wired and will not function normally without */
100 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
101 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
102 * internal clock even when the clock isn't stable */
103 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
106 struct sdhci_arasan_of_data
{
107 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
;
108 const struct sdhci_pltfm_data
*pdata
;
111 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map
= {
112 .baseclkfreq
= { .reg
= 0xf000, .width
= 8, .shift
= 8 },
113 .clockmultiplier
= { .reg
= 0xf02c, .width
= 8, .shift
= 0},
114 .hiword_update
= true,
118 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
120 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
121 * Note that if a field is specified as not available (shift < 0) then
122 * this function will silently return an error code. It will be noisy
123 * and print errors for any other (unexpected) errors.
125 * @host: The sdhci_host
126 * @fld: The field to write to
127 * @val: The value to write
129 static int sdhci_arasan_syscon_write(struct sdhci_host
*host
,
130 const struct sdhci_arasan_soc_ctl_field
*fld
,
133 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
134 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
135 struct regmap
*soc_ctl_base
= sdhci_arasan
->soc_ctl_base
;
137 u16 width
= fld
->width
;
138 s16 shift
= fld
->shift
;
142 * Silently return errors for shift < 0 so caller doesn't have
143 * to check for fields which are optional. For fields that
144 * are required then caller needs to do something special
150 if (sdhci_arasan
->soc_ctl_map
->hiword_update
)
151 ret
= regmap_write(soc_ctl_base
, reg
,
152 HIWORD_UPDATE(val
, GENMASK(width
, 0),
155 ret
= regmap_update_bits(soc_ctl_base
, reg
,
156 GENMASK(shift
+ width
, shift
),
159 /* Yell about (unexpected) regmap errors */
161 pr_warn("%s: Regmap write fail: %d\n",
162 mmc_hostname(host
->mmc
), ret
);
167 static void sdhci_arasan_set_clock(struct sdhci_host
*host
, unsigned int clock
)
169 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
170 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
171 bool ctrl_phy
= false;
173 if (!IS_ERR(sdhci_arasan
->phy
)) {
174 if (!sdhci_arasan
->is_phy_on
&& clock
<= PHY_CLK_TOO_SLOW_HZ
) {
176 * If PHY off, set clock to max speed and power PHY on.
178 * Although PHY docs apparently suggest power cycling
179 * when changing the clock the PHY doesn't like to be
180 * powered on while at low speeds like those used in ID
181 * mode. Even worse is powering the PHY on while the
184 * To workaround the PHY limitations, the best we can
185 * do is to power it on at a faster speed and then slam
186 * through low speeds without power cycling.
188 sdhci_set_clock(host
, host
->max_clk
);
189 phy_power_on(sdhci_arasan
->phy
);
190 sdhci_arasan
->is_phy_on
= true;
193 * We'll now fall through to the below case with
194 * ctrl_phy = false (so we won't turn off/on). The
195 * sdhci_set_clock() will set the real clock.
197 } else if (clock
> PHY_CLK_TOO_SLOW_HZ
) {
199 * At higher clock speeds the PHY is fine being power
200 * cycled and docs say you _should_ power cycle when
201 * changing clock speeds.
207 if (ctrl_phy
&& sdhci_arasan
->is_phy_on
) {
208 phy_power_off(sdhci_arasan
->phy
);
209 sdhci_arasan
->is_phy_on
= false;
212 sdhci_set_clock(host
, clock
);
214 if (sdhci_arasan
->quirks
& SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE
)
216 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
217 * after enabling the clock even though the clock is not
218 * stable. Trying to use a clock without waiting here results
219 * in EILSEQ while detecting some older/slower cards. The
220 * chosen delay is the maximum delay from sdhci_set_clock.
225 phy_power_on(sdhci_arasan
->phy
);
226 sdhci_arasan
->is_phy_on
= true;
230 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host
*mmc
,
234 struct sdhci_host
*host
= mmc_priv(mmc
);
236 vendor
= sdhci_readl(host
, SDHCI_ARASAN_VENDOR_REGISTER
);
237 if (ios
->enhanced_strobe
)
238 vendor
|= VENDOR_ENHANCED_STROBE
;
240 vendor
&= ~VENDOR_ENHANCED_STROBE
;
242 sdhci_writel(host
, vendor
, SDHCI_ARASAN_VENDOR_REGISTER
);
245 static void sdhci_arasan_reset(struct sdhci_host
*host
, u8 mask
)
248 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
249 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
251 sdhci_reset(host
, mask
);
253 if (sdhci_arasan
->quirks
& SDHCI_ARASAN_QUIRK_FORCE_CDTEST
) {
254 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
255 ctrl
|= SDHCI_CTRL_CDTEST_INS
| SDHCI_CTRL_CDTEST_EN
;
256 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
260 static int sdhci_arasan_voltage_switch(struct mmc_host
*mmc
,
263 switch (ios
->signal_voltage
) {
264 case MMC_SIGNAL_VOLTAGE_180
:
266 * Plese don't switch to 1V8 as arasan,5.1 doesn't
267 * actually refer to this setting to indicate the
268 * signal voltage and the state machine will be broken
269 * actually if we force to enable 1V8. That's something
270 * like broken quirk but we could work around here.
273 case MMC_SIGNAL_VOLTAGE_330
:
274 case MMC_SIGNAL_VOLTAGE_120
:
275 /* We don't support 3V3 and 1V2 */
282 static void sdhci_arasan_set_power(struct sdhci_host
*host
, unsigned char mode
,
285 if (!IS_ERR(host
->mmc
->supply
.vmmc
)) {
286 struct mmc_host
*mmc
= host
->mmc
;
288 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
290 sdhci_set_power_noreg(host
, mode
, vdd
);
293 static const struct sdhci_ops sdhci_arasan_ops
= {
294 .set_clock
= sdhci_arasan_set_clock
,
295 .get_max_clock
= sdhci_pltfm_clk_get_max_clock
,
296 .get_timeout_clock
= sdhci_pltfm_clk_get_max_clock
,
297 .set_bus_width
= sdhci_set_bus_width
,
298 .reset
= sdhci_arasan_reset
,
299 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
300 .set_power
= sdhci_arasan_set_power
,
303 static const struct sdhci_pltfm_data sdhci_arasan_pdata
= {
304 .ops
= &sdhci_arasan_ops
,
305 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
306 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
|
307 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
|
308 SDHCI_QUIRK2_STOP_WITH_TC
,
311 static struct sdhci_arasan_of_data sdhci_arasan_data
= {
312 .pdata
= &sdhci_arasan_pdata
,
315 static u32
sdhci_arasan_cqhci_irq(struct sdhci_host
*host
, u32 intmask
)
320 if (!sdhci_cqe_irq(host
, intmask
, &cmd_error
, &data_error
))
323 cqhci_irq(host
->mmc
, intmask
, cmd_error
, data_error
);
328 static void sdhci_arasan_dumpregs(struct mmc_host
*mmc
)
330 sdhci_dumpregs(mmc_priv(mmc
));
333 static void sdhci_arasan_cqe_enable(struct mmc_host
*mmc
)
335 struct sdhci_host
*host
= mmc_priv(mmc
);
338 reg
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
339 while (reg
& SDHCI_DATA_AVAILABLE
) {
340 sdhci_readl(host
, SDHCI_BUFFER
);
341 reg
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
344 sdhci_cqe_enable(mmc
);
347 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops
= {
348 .enable
= sdhci_arasan_cqe_enable
,
349 .disable
= sdhci_cqe_disable
,
350 .dumpregs
= sdhci_arasan_dumpregs
,
353 static const struct sdhci_ops sdhci_arasan_cqe_ops
= {
354 .set_clock
= sdhci_arasan_set_clock
,
355 .get_max_clock
= sdhci_pltfm_clk_get_max_clock
,
356 .get_timeout_clock
= sdhci_pltfm_clk_get_max_clock
,
357 .set_bus_width
= sdhci_set_bus_width
,
358 .reset
= sdhci_arasan_reset
,
359 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
360 .set_power
= sdhci_arasan_set_power
,
361 .irq
= sdhci_arasan_cqhci_irq
,
364 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata
= {
365 .ops
= &sdhci_arasan_cqe_ops
,
366 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
367 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
|
368 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
,
371 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data
= {
372 .soc_ctl_map
= &rk3399_soc_ctl_map
,
373 .pdata
= &sdhci_arasan_cqe_pdata
,
376 #ifdef CONFIG_PM_SLEEP
378 * sdhci_arasan_suspend - Suspend method for the driver
379 * @dev: Address of the device structure
380 * Returns 0 on success and error value on error
382 * Put the device in a low power state.
384 static int sdhci_arasan_suspend(struct device
*dev
)
386 struct sdhci_host
*host
= dev_get_drvdata(dev
);
387 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
388 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
391 if (host
->tuning_mode
!= SDHCI_TUNING_MODE_3
)
392 mmc_retune_needed(host
->mmc
);
394 if (sdhci_arasan
->has_cqe
) {
395 ret
= cqhci_suspend(host
->mmc
);
400 ret
= sdhci_suspend_host(host
);
404 if (!IS_ERR(sdhci_arasan
->phy
) && sdhci_arasan
->is_phy_on
) {
405 ret
= phy_power_off(sdhci_arasan
->phy
);
407 dev_err(dev
, "Cannot power off phy.\n");
408 sdhci_resume_host(host
);
411 sdhci_arasan
->is_phy_on
= false;
414 clk_disable(pltfm_host
->clk
);
415 clk_disable(sdhci_arasan
->clk_ahb
);
421 * sdhci_arasan_resume - Resume method for the driver
422 * @dev: Address of the device structure
423 * Returns 0 on success and error value on error
425 * Resume operation after suspend
427 static int sdhci_arasan_resume(struct device
*dev
)
429 struct sdhci_host
*host
= dev_get_drvdata(dev
);
430 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
431 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
434 ret
= clk_enable(sdhci_arasan
->clk_ahb
);
436 dev_err(dev
, "Cannot enable AHB clock.\n");
440 ret
= clk_enable(pltfm_host
->clk
);
442 dev_err(dev
, "Cannot enable SD clock.\n");
446 if (!IS_ERR(sdhci_arasan
->phy
) && host
->mmc
->actual_clock
) {
447 ret
= phy_power_on(sdhci_arasan
->phy
);
449 dev_err(dev
, "Cannot power on phy.\n");
452 sdhci_arasan
->is_phy_on
= true;
455 ret
= sdhci_resume_host(host
);
457 dev_err(dev
, "Cannot resume host.\n");
461 if (sdhci_arasan
->has_cqe
)
462 return cqhci_resume(host
->mmc
);
466 #endif /* ! CONFIG_PM_SLEEP */
468 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops
, sdhci_arasan_suspend
,
469 sdhci_arasan_resume
);
471 static const struct of_device_id sdhci_arasan_of_match
[] = {
472 /* SoC-specific compatible strings w/ soc_ctl_map */
474 .compatible
= "rockchip,rk3399-sdhci-5.1",
475 .data
= &sdhci_arasan_rk3399_data
,
477 /* Generic compatible below here */
479 .compatible
= "arasan,sdhci-8.9a",
480 .data
= &sdhci_arasan_data
,
483 .compatible
= "arasan,sdhci-5.1",
484 .data
= &sdhci_arasan_data
,
487 .compatible
= "arasan,sdhci-4.9a",
488 .data
= &sdhci_arasan_data
,
492 MODULE_DEVICE_TABLE(of
, sdhci_arasan_of_match
);
495 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
497 * Return the current actual rate of the SD card clock. This can be used
498 * to communicate with out PHY.
500 * @hw: Pointer to the hardware clock structure.
501 * @parent_rate The parent rate (should be rate of clk_xin).
502 * Returns the card clock rate.
504 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw
*hw
,
505 unsigned long parent_rate
)
508 struct sdhci_arasan_data
*sdhci_arasan
=
509 container_of(hw
, struct sdhci_arasan_data
, sdcardclk_hw
);
510 struct sdhci_host
*host
= sdhci_arasan
->host
;
512 return host
->mmc
->actual_clock
;
515 static const struct clk_ops arasan_sdcardclk_ops
= {
516 .recalc_rate
= sdhci_arasan_sdcardclk_recalc_rate
,
520 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
522 * The corecfg_clockmultiplier is supposed to contain clock multiplier
523 * value of programmable clock generator.
526 * - Many existing devices don't seem to do this and work fine. To keep
527 * compatibility for old hardware where the device tree doesn't provide a
528 * register map, this function is a noop if a soc_ctl_map hasn't been provided
530 * - The value of corecfg_clockmultiplier should sync with that of corresponding
531 * value reading from sdhci_capability_register. So this function is called
532 * once at probe time and never called again.
534 * @host: The sdhci_host
536 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host
*host
,
539 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
540 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
541 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
=
542 sdhci_arasan
->soc_ctl_map
;
544 /* Having a map is optional */
548 /* If we have a map, we expect to have a syscon */
549 if (!sdhci_arasan
->soc_ctl_base
) {
550 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
551 mmc_hostname(host
->mmc
));
555 sdhci_arasan_syscon_write(host
, &soc_ctl_map
->clockmultiplier
, value
);
559 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
561 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
562 * function can be used to make that happen.
565 * - Many existing devices don't seem to do this and work fine. To keep
566 * compatibility for old hardware where the device tree doesn't provide a
567 * register map, this function is a noop if a soc_ctl_map hasn't been provided
569 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
570 * to achieve lower clock rates. That means that this function is called once
571 * at probe time and never called again.
573 * @host: The sdhci_host
575 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host
*host
)
577 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
578 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
579 const struct sdhci_arasan_soc_ctl_map
*soc_ctl_map
=
580 sdhci_arasan
->soc_ctl_map
;
581 u32 mhz
= DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host
->clk
), 1000000);
583 /* Having a map is optional */
587 /* If we have a map, we expect to have a syscon */
588 if (!sdhci_arasan
->soc_ctl_base
) {
589 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
590 mmc_hostname(host
->mmc
));
594 sdhci_arasan_syscon_write(host
, &soc_ctl_map
->baseclkfreq
, mhz
);
598 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
600 * Some PHY devices need to know what the actual card clock is. In order for
601 * them to find out, we'll provide a clock through the common clock framework
604 * Note: without seriously re-architecting SDHCI's clock code and testing on
605 * all platforms, there's no way to create a totally beautiful clock here
606 * with all clock ops implemented. Instead, we'll just create a clock that can
607 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
608 * framework that we're doing things behind its back. This should be sufficient
609 * to create nice clean device tree bindings and later (if needed) we can try
610 * re-architecting SDHCI if we see some benefit to it.
612 * @sdhci_arasan: Our private data structure.
613 * @clk_xin: Pointer to the functional clock
614 * @dev: Pointer to our struct device.
615 * Returns 0 on success and error value on error
617 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data
*sdhci_arasan
,
621 struct device_node
*np
= dev
->of_node
;
622 struct clk_init_data sdcardclk_init
;
623 const char *parent_clk_name
;
626 /* Providing a clock to the PHY is optional; no error if missing */
627 if (!of_find_property(np
, "#clock-cells", NULL
))
630 ret
= of_property_read_string_index(np
, "clock-output-names", 0,
631 &sdcardclk_init
.name
);
633 dev_err(dev
, "DT has #clock-cells but no clock-output-names\n");
637 parent_clk_name
= __clk_get_name(clk_xin
);
638 sdcardclk_init
.parent_names
= &parent_clk_name
;
639 sdcardclk_init
.num_parents
= 1;
640 sdcardclk_init
.flags
= CLK_GET_RATE_NOCACHE
;
641 sdcardclk_init
.ops
= &arasan_sdcardclk_ops
;
643 sdhci_arasan
->sdcardclk_hw
.init
= &sdcardclk_init
;
644 sdhci_arasan
->sdcardclk
=
645 devm_clk_register(dev
, &sdhci_arasan
->sdcardclk_hw
);
646 sdhci_arasan
->sdcardclk_hw
.init
= NULL
;
648 ret
= of_clk_add_provider(np
, of_clk_src_simple_get
,
649 sdhci_arasan
->sdcardclk
);
651 dev_err(dev
, "Failed to add clock provider\n");
657 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
659 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
662 * @dev: Pointer to our struct device.
664 static void sdhci_arasan_unregister_sdclk(struct device
*dev
)
666 struct device_node
*np
= dev
->of_node
;
668 if (!of_find_property(np
, "#clock-cells", NULL
))
671 of_clk_del_provider(dev
->of_node
);
674 static int sdhci_arasan_add_host(struct sdhci_arasan_data
*sdhci_arasan
)
676 struct sdhci_host
*host
= sdhci_arasan
->host
;
677 struct cqhci_host
*cq_host
;
681 if (!sdhci_arasan
->has_cqe
)
682 return sdhci_add_host(host
);
684 ret
= sdhci_setup_host(host
);
688 cq_host
= devm_kzalloc(host
->mmc
->parent
,
689 sizeof(*cq_host
), GFP_KERNEL
);
695 cq_host
->mmio
= host
->ioaddr
+ SDHCI_ARASAN_CQE_BASE_ADDR
;
696 cq_host
->ops
= &sdhci_arasan_cqhci_ops
;
698 dma64
= host
->flags
& SDHCI_USE_64_BIT_DMA
;
700 cq_host
->caps
|= CQHCI_TASK_DESC_SZ_128
;
702 ret
= cqhci_init(cq_host
, host
->mmc
, dma64
);
706 ret
= __sdhci_add_host(host
);
713 sdhci_cleanup_host(host
);
717 static int sdhci_arasan_probe(struct platform_device
*pdev
)
720 const struct of_device_id
*match
;
721 struct device_node
*node
;
723 struct sdhci_host
*host
;
724 struct sdhci_pltfm_host
*pltfm_host
;
725 struct sdhci_arasan_data
*sdhci_arasan
;
726 struct device_node
*np
= pdev
->dev
.of_node
;
727 const struct sdhci_arasan_of_data
*data
;
729 match
= of_match_node(sdhci_arasan_of_match
, pdev
->dev
.of_node
);
731 host
= sdhci_pltfm_init(pdev
, data
->pdata
, sizeof(*sdhci_arasan
));
734 return PTR_ERR(host
);
736 pltfm_host
= sdhci_priv(host
);
737 sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
738 sdhci_arasan
->host
= host
;
740 sdhci_arasan
->soc_ctl_map
= data
->soc_ctl_map
;
742 node
= of_parse_phandle(pdev
->dev
.of_node
, "arasan,soc-ctl-syscon", 0);
744 sdhci_arasan
->soc_ctl_base
= syscon_node_to_regmap(node
);
747 if (IS_ERR(sdhci_arasan
->soc_ctl_base
)) {
748 ret
= PTR_ERR(sdhci_arasan
->soc_ctl_base
);
749 if (ret
!= -EPROBE_DEFER
)
750 dev_err(&pdev
->dev
, "Can't get syscon: %d\n",
756 sdhci_arasan
->clk_ahb
= devm_clk_get(&pdev
->dev
, "clk_ahb");
757 if (IS_ERR(sdhci_arasan
->clk_ahb
)) {
758 dev_err(&pdev
->dev
, "clk_ahb clock not found.\n");
759 ret
= PTR_ERR(sdhci_arasan
->clk_ahb
);
763 clk_xin
= devm_clk_get(&pdev
->dev
, "clk_xin");
764 if (IS_ERR(clk_xin
)) {
765 dev_err(&pdev
->dev
, "clk_xin clock not found.\n");
766 ret
= PTR_ERR(clk_xin
);
770 ret
= clk_prepare_enable(sdhci_arasan
->clk_ahb
);
772 dev_err(&pdev
->dev
, "Unable to enable AHB clock.\n");
776 ret
= clk_prepare_enable(clk_xin
);
778 dev_err(&pdev
->dev
, "Unable to enable SD clock.\n");
782 sdhci_get_of_property(pdev
);
784 if (of_property_read_bool(np
, "xlnx,fails-without-test-cd"))
785 sdhci_arasan
->quirks
|= SDHCI_ARASAN_QUIRK_FORCE_CDTEST
;
787 if (of_property_read_bool(np
, "xlnx,int-clock-stable-broken"))
788 sdhci_arasan
->quirks
|= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE
;
790 pltfm_host
->clk
= clk_xin
;
792 if (of_device_is_compatible(pdev
->dev
.of_node
,
793 "rockchip,rk3399-sdhci-5.1"))
794 sdhci_arasan_update_clockmultiplier(host
, 0x0);
796 sdhci_arasan_update_baseclkfreq(host
);
798 ret
= sdhci_arasan_register_sdclk(sdhci_arasan
, clk_xin
, &pdev
->dev
);
800 goto clk_disable_all
;
802 ret
= mmc_of_parse(host
->mmc
);
804 if (ret
!= -EPROBE_DEFER
)
805 dev_err(&pdev
->dev
, "parsing dt failed (%d)\n", ret
);
809 sdhci_arasan
->phy
= ERR_PTR(-ENODEV
);
810 if (of_device_is_compatible(pdev
->dev
.of_node
,
811 "arasan,sdhci-5.1")) {
812 sdhci_arasan
->phy
= devm_phy_get(&pdev
->dev
,
814 if (IS_ERR(sdhci_arasan
->phy
)) {
815 ret
= PTR_ERR(sdhci_arasan
->phy
);
816 dev_err(&pdev
->dev
, "No phy for arasan,sdhci-5.1.\n");
820 ret
= phy_init(sdhci_arasan
->phy
);
822 dev_err(&pdev
->dev
, "phy_init err.\n");
826 host
->mmc_host_ops
.hs400_enhanced_strobe
=
827 sdhci_arasan_hs400_enhanced_strobe
;
828 host
->mmc_host_ops
.start_signal_voltage_switch
=
829 sdhci_arasan_voltage_switch
;
830 sdhci_arasan
->has_cqe
= true;
831 host
->mmc
->caps2
|= MMC_CAP2_CQE
;
833 if (!of_property_read_bool(np
, "disable-cqe-dcmd"))
834 host
->mmc
->caps2
|= MMC_CAP2_CQE_DCMD
;
837 ret
= sdhci_arasan_add_host(sdhci_arasan
);
844 if (!IS_ERR(sdhci_arasan
->phy
))
845 phy_exit(sdhci_arasan
->phy
);
847 sdhci_arasan_unregister_sdclk(&pdev
->dev
);
849 clk_disable_unprepare(clk_xin
);
851 clk_disable_unprepare(sdhci_arasan
->clk_ahb
);
853 sdhci_pltfm_free(pdev
);
857 static int sdhci_arasan_remove(struct platform_device
*pdev
)
860 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
861 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
862 struct sdhci_arasan_data
*sdhci_arasan
= sdhci_pltfm_priv(pltfm_host
);
863 struct clk
*clk_ahb
= sdhci_arasan
->clk_ahb
;
865 if (!IS_ERR(sdhci_arasan
->phy
)) {
866 if (sdhci_arasan
->is_phy_on
)
867 phy_power_off(sdhci_arasan
->phy
);
868 phy_exit(sdhci_arasan
->phy
);
871 sdhci_arasan_unregister_sdclk(&pdev
->dev
);
873 ret
= sdhci_pltfm_unregister(pdev
);
875 clk_disable_unprepare(clk_ahb
);
880 static struct platform_driver sdhci_arasan_driver
= {
882 .name
= "sdhci-arasan",
883 .of_match_table
= sdhci_arasan_of_match
,
884 .pm
= &sdhci_arasan_dev_pm_ops
,
886 .probe
= sdhci_arasan_probe
,
887 .remove
= sdhci_arasan_remove
,
890 module_platform_driver(sdhci_arasan_driver
);
892 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
893 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
894 MODULE_LICENSE("GPL");