drivers/mmc/host/sdhci-of-at91.c

   1 /*
   2  * Atmel SDMMC controller driver.
   3  *
   4  * Copyright (C) 2015 Atmel,
   5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pm.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include "sdhci-pltfm.h"
  31
  32 #define SDMMC_CACR      0x230
  33 #define         SDMMC_CACR_CAPWREN      BIT(0)
  34 #define         SDMMC_CACR_KEY          (0x46 << 8)
  35
  36 #define SDHCI_AT91_PRESET_COMMON_CONF   0x400 /* drv type B, programmable clock mode */
  37
  38 struct sdhci_at91_priv {
  39         struct clk *hclock;
  40         struct clk *gck;
  41         struct clk *mainck;
  42 };
  43
  44 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
  45 {
  46         u16 clk;
  47         unsigned long timeout;
  48
  49         host->mmc->actual_clock = 0;
  50
  51         /*
  52          * There is no requirement to disable the internal clock before
  53          * changing the SD clock configuration. Moreover, disabling the
  54          * internal clock, changing the configuration and re-enabling the
  55          * internal clock causes some bugs. It can prevent to get the internal
  56          * clock stable flag ready and an unexpected switch to the base clock
  57          * when using presets.
  58          */
  59         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  60         clk &= SDHCI_CLOCK_INT_EN;
  61         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  62
  63         if (clock == 0)
  64                 return;
  65
  66         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  67
  68         clk |= SDHCI_CLOCK_INT_EN;
  69         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  70
  71         /* Wait max 20 ms */
  72         timeout = 20;
  73         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  74                 & SDHCI_CLOCK_INT_STABLE)) {
  75                 if (timeout == 0) {
  76                         pr_err("%s: Internal clock never stabilised.\n",
  77                                mmc_hostname(host->mmc));
  78                         return;
  79                 }
  80                 timeout--;
  81                 mdelay(1);
  82         }
  83
  84         clk |= SDHCI_CLOCK_CARD_EN;
  85         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  86 }
  87
  88 /*
  89  * In this specific implementation of the SDHCI controller, the power register
  90  * needs to have a valid voltage set even when the power supply is managed by
  91  * an external regulator.
  92  */
  93 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
  94                      unsigned short vdd)
  95 {
  96         if (!IS_ERR(host->mmc->supply.vmmc)) {
  97                 struct mmc_host *mmc = host->mmc;
  98
  99                 spin_unlock_irq(&host->lock);
 100                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 101                 spin_lock_irq(&host->lock);
 102         }
 103         sdhci_set_power_noreg(host, mode, vdd);
 104 }
 105
 106 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
 107         .set_clock              = sdhci_at91_set_clock,
 108         .set_bus_width          = sdhci_set_bus_width,
 109         .reset                  = sdhci_reset,
 110         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 111         .set_power              = sdhci_at91_set_power,
 112 };
 113
 114 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
 115         .ops = &sdhci_at91_sama5d2_ops,
 116 };
 117
 118 static const struct of_device_id sdhci_at91_dt_match[] = {
 119         { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
 120         {}
 121 };
 122 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
 123
 124 #ifdef CONFIG_PM
 125 static int sdhci_at91_runtime_suspend(struct device *dev)
 126 {
 127         struct sdhci_host *host = dev_get_drvdata(dev);
 128         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 129         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 130         int ret;
 131
 132         ret = sdhci_runtime_suspend_host(host);
 133
 134         clk_disable_unprepare(priv->gck);
 135         clk_disable_unprepare(priv->hclock);
 136         clk_disable_unprepare(priv->mainck);
 137
 138         return ret;
 139 }
 140
 141 static int sdhci_at91_runtime_resume(struct device *dev)
 142 {
 143         struct sdhci_host *host = dev_get_drvdata(dev);
 144         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 145         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 146         int ret;
 147
 148         ret = clk_prepare_enable(priv->mainck);
 149         if (ret) {
 150                 dev_err(dev, "can't enable mainck\n");
 151                 return ret;
 152         }
 153
 154         ret = clk_prepare_enable(priv->hclock);
 155         if (ret) {
 156                 dev_err(dev, "can't enable hclock\n");
 157                 return ret;
 158         }
 159
 160         ret = clk_prepare_enable(priv->gck);
 161         if (ret) {
 162                 dev_err(dev, "can't enable gck\n");
 163                 return ret;
 164         }
 165
 166         return sdhci_runtime_resume_host(host);
 167 }
 168 #endif /* CONFIG_PM */
 169
 170 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
 171         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 172                                 pm_runtime_force_resume)
 173         SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
 174                            sdhci_at91_runtime_resume,
 175                            NULL)
 176 };
 177
 178 static int sdhci_at91_probe(struct platform_device *pdev)
 179 {
 180         const struct of_device_id       *match;
 181         const struct sdhci_pltfm_data   *soc_data;
 182         struct sdhci_host               *host;
 183         struct sdhci_pltfm_host         *pltfm_host;
 184         struct sdhci_at91_priv          *priv;
 185         unsigned int                    caps0, caps1;
 186         unsigned int                    clk_base, clk_mul;
 187         unsigned int                    gck_rate, real_gck_rate;
 188         int                             ret;
 189         unsigned int                    preset_div;
 190
 191         match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
 192         if (!match)
 193                 return -EINVAL;
 194         soc_data = match->data;
 195
 196         host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
 197         if (IS_ERR(host))
 198                 return PTR_ERR(host);
 199
 200         pltfm_host = sdhci_priv(host);
 201         priv = sdhci_pltfm_priv(pltfm_host);
 202
 203         priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
 204         if (IS_ERR(priv->mainck)) {
 205                 dev_err(&pdev->dev, "failed to get baseclk\n");
 206                 return PTR_ERR(priv->mainck);
 207         }
 208
 209         priv->hclock = devm_clk_get(&pdev->dev, "hclock");
 210         if (IS_ERR(priv->hclock)) {
 211                 dev_err(&pdev->dev, "failed to get hclock\n");
 212                 return PTR_ERR(priv->hclock);
 213         }
 214
 215         priv->gck = devm_clk_get(&pdev->dev, "multclk");
 216         if (IS_ERR(priv->gck)) {
 217                 dev_err(&pdev->dev, "failed to get multclk\n");
 218                 return PTR_ERR(priv->gck);
 219         }
 220
 221         /*
 222          * The mult clock is provided by as a generated clock by the PMC
 223          * controller. In order to set the rate of gck, we have to get the
 224          * base clock rate and the clock mult from capabilities.
 225          */
 226         clk_prepare_enable(priv->hclock);
 227         caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
 228         caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
 229         clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
 230         clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
 231         gck_rate = clk_base * 1000000 * (clk_mul + 1);
 232         ret = clk_set_rate(priv->gck, gck_rate);
 233         if (ret < 0) {
 234                 dev_err(&pdev->dev, "failed to set gck");
 235                 goto hclock_disable_unprepare;
 236         }
 237         /*
 238          * We need to check if we have the requested rate for gck because in
 239          * some cases this rate could be not supported. If it happens, the rate
 240          * is the closest one gck can provide. We have to update the value
 241          * of clk mul.
 242          */
 243         real_gck_rate = clk_get_rate(priv->gck);
 244         if (real_gck_rate != gck_rate) {
 245                 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
 246                 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
 247                 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
 248                 /* Set capabilities in r/w mode. */
 249                 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
 250                 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
 251                 /* Set capabilities in ro mode. */
 252                 writel(0, host->ioaddr + SDMMC_CACR);
 253                 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
 254                          clk_mul, real_gck_rate);
 255         }
 256
 257         /*
 258          * We have to set preset values because it depends on the clk_mul
 259          * value. Moreover, SDR104 is supported in a degraded mode since the
 260          * maximum sd clock value is 120 MHz instead of 208 MHz. For that
 261          * reason, we need to use presets to support SDR104.
 262          */
 263         preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
 264         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 265                host->ioaddr + SDHCI_PRESET_FOR_SDR12);
 266         preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
 267         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 268                host->ioaddr + SDHCI_PRESET_FOR_SDR25);
 269         preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
 270         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 271                host->ioaddr + SDHCI_PRESET_FOR_SDR50);
 272         preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
 273         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 274                host->ioaddr + SDHCI_PRESET_FOR_SDR104);
 275         preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
 276         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 277                host->ioaddr + SDHCI_PRESET_FOR_DDR50);
 278
 279         clk_prepare_enable(priv->mainck);
 280         clk_prepare_enable(priv->gck);
 281
 282         ret = mmc_of_parse(host->mmc);
 283         if (ret)
 284                 goto clocks_disable_unprepare;
 285
 286         sdhci_get_of_property(pdev);
 287
 288         pm_runtime_get_noresume(&pdev->dev);
 289         pm_runtime_set_active(&pdev->dev);
 290         pm_runtime_enable(&pdev->dev);
 291         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 292         pm_runtime_use_autosuspend(&pdev->dev);
 293
 294         ret = sdhci_add_host(host);
 295         if (ret)
 296                 goto pm_runtime_disable;
 297
 298         /*
 299          * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
 300          * the assumption that all the clocks of the controller are disabled.
 301          * It means we can't get irq from it when it is runtime suspended.
 302          * For that reason, it is not planned to wake-up on a card detect irq
 303          * from the controller.
 304          * If we want to use runtime PM and to be able to wake-up on card
 305          * insertion, we have to use a GPIO for the card detection or we can
 306          * use polling. Be aware that using polling will resume/suspend the
 307          * controller between each attempt.
 308          * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
 309          * to enable polling via device tree with broken-cd property.
 310          */
 311         if (mmc_card_is_removable(host->mmc) &&
 312             mmc_gpio_get_cd(host->mmc) < 0) {
 313                 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
 314                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 315         }
 316
 317         pm_runtime_put_autosuspend(&pdev->dev);
 318
 319         return 0;
 320
 321 pm_runtime_disable:
 322         pm_runtime_disable(&pdev->dev);
 323         pm_runtime_set_suspended(&pdev->dev);
 324         pm_runtime_put_noidle(&pdev->dev);
 325 clocks_disable_unprepare:
 326         clk_disable_unprepare(priv->gck);
 327         clk_disable_unprepare(priv->mainck);
 328 hclock_disable_unprepare:
 329         clk_disable_unprepare(priv->hclock);
 330         sdhci_pltfm_free(pdev);
 331         return ret;
 332 }
 333
 334 static int sdhci_at91_remove(struct platform_device *pdev)
 335 {
 336         struct sdhci_host       *host = platform_get_drvdata(pdev);
 337         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 338         struct sdhci_at91_priv  *priv = sdhci_pltfm_priv(pltfm_host);
 339         struct clk *gck = priv->gck;
 340         struct clk *hclock = priv->hclock;
 341         struct clk *mainck = priv->mainck;
 342
 343         pm_runtime_get_sync(&pdev->dev);
 344         pm_runtime_disable(&pdev->dev);
 345         pm_runtime_put_noidle(&pdev->dev);
 346
 347         sdhci_pltfm_unregister(pdev);
 348
 349         clk_disable_unprepare(gck);
 350         clk_disable_unprepare(hclock);
 351         clk_disable_unprepare(mainck);
 352
 353         return 0;
 354 }
 355
 356 static struct platform_driver sdhci_at91_driver = {
 357         .driver         = {
 358                 .name   = "sdhci-at91",
 359                 .of_match_table = sdhci_at91_dt_match,
 360                 .pm     = &sdhci_at91_dev_pm_ops,
 361         },
 362         .probe          = sdhci_at91_probe,
 363         .remove         = sdhci_at91_remove,
 364 };
 365
 366 module_platform_driver(sdhci_at91_driver);
 367
 368 MODULE_DESCRIPTION("SDHCI driver for at91");
 369 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 370 MODULE_LICENSE("GPL v2");