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[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "sdhci.h"
34 #include "sdhci-pci.h"
35 #include "sdhci-pci-o2micro.h"
36
37 static int sdhci_pci_enable_dma(struct sdhci_host *host);
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
39
40 #ifdef CONFIG_PM_SLEEP
41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
42 {
43 int i, ret;
44
45 for (i = 0; i < chip->num_slots; i++) {
46 struct sdhci_pci_slot *slot = chip->slots[i];
47 struct sdhci_host *host;
48
49 if (!slot)
50 continue;
51
52 host = slot->host;
53
54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
55 mmc_retune_needed(host->mmc);
56
57 ret = sdhci_suspend_host(host);
58 if (ret)
59 goto err_pci_suspend;
60
61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
62 sdhci_enable_irq_wakeups(host);
63 }
64
65 return 0;
66
67 err_pci_suspend:
68 while (--i >= 0)
69 sdhci_resume_host(chip->slots[i]->host);
70 return ret;
71 }
72
73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
74 {
75 mmc_pm_flag_t pm_flags = 0;
76 int i;
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80
81 if (slot)
82 pm_flags |= slot->host->mmc->pm_flags;
83 }
84
85 return device_init_wakeup(&chip->pdev->dev,
86 (pm_flags & MMC_PM_KEEP_POWER) &&
87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
88 }
89
90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
91 {
92 int ret;
93
94 ret = __sdhci_pci_suspend_host(chip);
95 if (ret)
96 return ret;
97
98 sdhci_pci_init_wakeup(chip);
99
100 return 0;
101 }
102
103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
104 {
105 struct sdhci_pci_slot *slot;
106 int i, ret;
107
108 for (i = 0; i < chip->num_slots; i++) {
109 slot = chip->slots[i];
110 if (!slot)
111 continue;
112
113 ret = sdhci_resume_host(slot->host);
114 if (ret)
115 return ret;
116 }
117
118 return 0;
119 }
120 #endif
121
122 #ifdef CONFIG_PM
123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
124 {
125 struct sdhci_pci_slot *slot;
126 struct sdhci_host *host;
127 int i, ret;
128
129 for (i = 0; i < chip->num_slots; i++) {
130 slot = chip->slots[i];
131 if (!slot)
132 continue;
133
134 host = slot->host;
135
136 ret = sdhci_runtime_suspend_host(host);
137 if (ret)
138 goto err_pci_runtime_suspend;
139
140 if (chip->rpm_retune &&
141 host->tuning_mode != SDHCI_TUNING_MODE_3)
142 mmc_retune_needed(host->mmc);
143 }
144
145 return 0;
146
147 err_pci_runtime_suspend:
148 while (--i >= 0)
149 sdhci_runtime_resume_host(chip->slots[i]->host);
150 return ret;
151 }
152
153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
154 {
155 struct sdhci_pci_slot *slot;
156 int i, ret;
157
158 for (i = 0; i < chip->num_slots; i++) {
159 slot = chip->slots[i];
160 if (!slot)
161 continue;
162
163 ret = sdhci_runtime_resume_host(slot->host);
164 if (ret)
165 return ret;
166 }
167
168 return 0;
169 }
170 #endif
171
172 /*****************************************************************************\
173 * *
174 * Hardware specific quirk handling *
175 * *
176 \*****************************************************************************/
177
178 static int ricoh_probe(struct sdhci_pci_chip *chip)
179 {
180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
183 return 0;
184 }
185
186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
187 {
188 slot->host->caps =
189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
190 & SDHCI_TIMEOUT_CLK_MASK) |
191
192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
193 & SDHCI_CLOCK_BASE_MASK) |
194
195 SDHCI_TIMEOUT_CLK_UNIT |
196 SDHCI_CAN_VDD_330 |
197 SDHCI_CAN_DO_HISPD |
198 SDHCI_CAN_DO_SDMA;
199 return 0;
200 }
201
202 #ifdef CONFIG_PM_SLEEP
203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
204 {
205 /* Apply a delay to allow controller to settle */
206 /* Otherwise it becomes confused if card state changed
207 during suspend */
208 msleep(500);
209 return sdhci_pci_resume_host(chip);
210 }
211 #endif
212
213 static const struct sdhci_pci_fixes sdhci_ricoh = {
214 .probe = ricoh_probe,
215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
216 SDHCI_QUIRK_FORCE_DMA |
217 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
218 };
219
220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
221 .probe_slot = ricoh_mmc_probe_slot,
222 #ifdef CONFIG_PM_SLEEP
223 .resume = ricoh_mmc_resume,
224 #endif
225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
226 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
227 SDHCI_QUIRK_NO_CARD_NO_RESET |
228 SDHCI_QUIRK_MISSING_CAPS
229 };
230
231 static const struct sdhci_pci_fixes sdhci_ene_712 = {
232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
233 SDHCI_QUIRK_BROKEN_DMA,
234 };
235
236 static const struct sdhci_pci_fixes sdhci_ene_714 = {
237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
239 SDHCI_QUIRK_BROKEN_DMA,
240 };
241
242 static const struct sdhci_pci_fixes sdhci_cafe = {
243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
244 SDHCI_QUIRK_NO_BUSY_IRQ |
245 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
247 };
248
249 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
251 };
252
253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
254 {
255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
256 return 0;
257 }
258
259 /*
260 * ADMA operation is disabled for Moorestown platform due to
261 * hardware bugs.
262 */
263 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
264 {
265 /*
266 * slots number is fixed here for MRST as SDIO3/5 are never used and
267 * have hardware bugs.
268 */
269 chip->num_slots = 1;
270 return 0;
271 }
272
273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
274 {
275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
276 return 0;
277 }
278
279 #ifdef CONFIG_PM
280
281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
282 {
283 struct sdhci_pci_slot *slot = dev_id;
284 struct sdhci_host *host = slot->host;
285
286 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
287 return IRQ_HANDLED;
288 }
289
290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
291 {
292 int err, irq, gpio = slot->cd_gpio;
293
294 slot->cd_gpio = -EINVAL;
295 slot->cd_irq = -EINVAL;
296
297 if (!gpio_is_valid(gpio))
298 return;
299
300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
301 if (err < 0)
302 goto out;
303
304 err = gpio_direction_input(gpio);
305 if (err < 0)
306 goto out_free;
307
308 irq = gpio_to_irq(gpio);
309 if (irq < 0)
310 goto out_free;
311
312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
313 IRQF_TRIGGER_FALLING, "sd_cd", slot);
314 if (err)
315 goto out_free;
316
317 slot->cd_gpio = gpio;
318 slot->cd_irq = irq;
319
320 return;
321
322 out_free:
323 devm_gpio_free(&slot->chip->pdev->dev, gpio);
324 out:
325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
326 }
327
328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
329 {
330 if (slot->cd_irq >= 0)
331 free_irq(slot->cd_irq, slot);
332 }
333
334 #else
335
336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
337 {
338 }
339
340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
341 {
342 }
343
344 #endif
345
346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
347 {
348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
350 return 0;
351 }
352
353 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
354 {
355 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
356 return 0;
357 }
358
359 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
360 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
361 .probe_slot = mrst_hc_probe_slot,
362 };
363
364 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
365 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
366 .probe = mrst_hc_probe,
367 };
368
369 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
370 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
371 .allow_runtime_pm = true,
372 .own_cd_for_runtime_pm = true,
373 };
374
375 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
376 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
377 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
378 .allow_runtime_pm = true,
379 .probe_slot = mfd_sdio_probe_slot,
380 };
381
382 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
383 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
384 .allow_runtime_pm = true,
385 .probe_slot = mfd_emmc_probe_slot,
386 };
387
388 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
389 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
390 .probe_slot = pch_hc_probe_slot,
391 };
392
393 enum {
394 INTEL_DSM_FNS = 0,
395 INTEL_DSM_V18_SWITCH = 3,
396 INTEL_DSM_DRV_STRENGTH = 9,
397 INTEL_DSM_D3_RETUNE = 10,
398 };
399
400 struct intel_host {
401 u32 dsm_fns;
402 int drv_strength;
403 bool d3_retune;
404 };
405
406 static const guid_t intel_dsm_guid =
407 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
409
410 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
411 unsigned int fn, u32 *result)
412 {
413 union acpi_object *obj;
414 int err = 0;
415 size_t len;
416
417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
418 if (!obj)
419 return -EOPNOTSUPP;
420
421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
422 err = -EINVAL;
423 goto out;
424 }
425
426 len = min_t(size_t, obj->buffer.length, 4);
427
428 *result = 0;
429 memcpy(result, obj->buffer.pointer, len);
430 out:
431 ACPI_FREE(obj);
432
433 return err;
434 }
435
436 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
437 unsigned int fn, u32 *result)
438 {
439 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
440 return -EOPNOTSUPP;
441
442 return __intel_dsm(intel_host, dev, fn, result);
443 }
444
445 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
446 struct mmc_host *mmc)
447 {
448 int err;
449 u32 val;
450
451 intel_host->d3_retune = true;
452
453 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
454 if (err) {
455 pr_debug("%s: DSM not supported, error %d\n",
456 mmc_hostname(mmc), err);
457 return;
458 }
459
460 pr_debug("%s: DSM function mask %#x\n",
461 mmc_hostname(mmc), intel_host->dsm_fns);
462
463 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
464 intel_host->drv_strength = err ? 0 : val;
465
466 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
467 intel_host->d3_retune = err ? true : !!val;
468 }
469
470 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
471 {
472 u8 reg;
473
474 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
475 reg |= 0x10;
476 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
477 /* For eMMC, minimum is 1us but give it 9us for good measure */
478 udelay(9);
479 reg &= ~0x10;
480 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
481 /* For eMMC, minimum is 200us but give it 300us for good measure */
482 usleep_range(300, 1000);
483 }
484
485 static int intel_select_drive_strength(struct mmc_card *card,
486 unsigned int max_dtr, int host_drv,
487 int card_drv, int *drv_type)
488 {
489 struct sdhci_host *host = mmc_priv(card->host);
490 struct sdhci_pci_slot *slot = sdhci_priv(host);
491 struct intel_host *intel_host = sdhci_pci_priv(slot);
492
493 return intel_host->drv_strength;
494 }
495
496 static int bxt_get_cd(struct mmc_host *mmc)
497 {
498 int gpio_cd = mmc_gpio_get_cd(mmc);
499 struct sdhci_host *host = mmc_priv(mmc);
500 unsigned long flags;
501 int ret = 0;
502
503 if (!gpio_cd)
504 return 0;
505
506 spin_lock_irqsave(&host->lock, flags);
507
508 if (host->flags & SDHCI_DEVICE_DEAD)
509 goto out;
510
511 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
512 out:
513 spin_unlock_irqrestore(&host->lock, flags);
514
515 return ret;
516 }
517
518 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
519 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
520
521 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
522 unsigned short vdd)
523 {
524 int cntr;
525 u8 reg;
526
527 sdhci_set_power(host, mode, vdd);
528
529 if (mode == MMC_POWER_OFF)
530 return;
531
532 /*
533 * Bus power might not enable after D3 -> D0 transition due to the
534 * present state not yet having propagated. Retry for up to 2ms.
535 */
536 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
537 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
538 if (reg & SDHCI_POWER_ON)
539 break;
540 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
541 reg |= SDHCI_POWER_ON;
542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
543 }
544 }
545
546 #define INTEL_HS400_ES_REG 0x78
547 #define INTEL_HS400_ES_BIT BIT(0)
548
549 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
550 struct mmc_ios *ios)
551 {
552 struct sdhci_host *host = mmc_priv(mmc);
553 u32 val;
554
555 val = sdhci_readl(host, INTEL_HS400_ES_REG);
556 if (ios->enhanced_strobe)
557 val |= INTEL_HS400_ES_BIT;
558 else
559 val &= ~INTEL_HS400_ES_BIT;
560 sdhci_writel(host, val, INTEL_HS400_ES_REG);
561 }
562
563 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
564 {
565 struct sdhci_pci_slot *slot = sdhci_priv(host);
566 struct intel_host *intel_host = sdhci_pci_priv(slot);
567 struct device *dev = &slot->chip->pdev->dev;
568 u32 result = 0;
569 int err;
570
571 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
572 pr_debug("%s: %s DSM error %d result %u\n",
573 mmc_hostname(host->mmc), __func__, err, result);
574 }
575
576 static const struct sdhci_ops sdhci_intel_byt_ops = {
577 .set_clock = sdhci_set_clock,
578 .set_power = sdhci_intel_set_power,
579 .enable_dma = sdhci_pci_enable_dma,
580 .set_bus_width = sdhci_set_bus_width,
581 .reset = sdhci_reset,
582 .set_uhs_signaling = sdhci_set_uhs_signaling,
583 .hw_reset = sdhci_pci_hw_reset,
584 .voltage_switch = sdhci_intel_voltage_switch,
585 };
586
587 static void byt_read_dsm(struct sdhci_pci_slot *slot)
588 {
589 struct intel_host *intel_host = sdhci_pci_priv(slot);
590 struct device *dev = &slot->chip->pdev->dev;
591 struct mmc_host *mmc = slot->host->mmc;
592
593 intel_dsm_init(intel_host, dev, mmc);
594 slot->chip->rpm_retune = intel_host->d3_retune;
595 }
596
597 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
598 {
599 byt_read_dsm(slot);
600 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
601 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
602 MMC_CAP_CMD_DURING_TFR |
603 MMC_CAP_WAIT_WHILE_BUSY;
604 slot->hw_reset = sdhci_pci_int_hw_reset;
605 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
606 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
607 slot->host->mmc_host_ops.select_drive_strength =
608 intel_select_drive_strength;
609 return 0;
610 }
611
612 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
613 {
614 int ret = byt_emmc_probe_slot(slot);
615
616 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
617 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
618 slot->host->mmc_host_ops.hs400_enhanced_strobe =
619 intel_hs400_enhanced_strobe;
620 }
621
622 return ret;
623 }
624
625 #ifdef CONFIG_ACPI
626 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
627 {
628 acpi_status status;
629 unsigned long long max_freq;
630
631 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
632 "MXFQ", NULL, &max_freq);
633 if (ACPI_FAILURE(status)) {
634 dev_err(&slot->chip->pdev->dev,
635 "MXFQ not found in acpi table\n");
636 return -EINVAL;
637 }
638
639 slot->host->mmc->f_max = max_freq * 1000000;
640
641 return 0;
642 }
643 #else
644 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
645 {
646 return 0;
647 }
648 #endif
649
650 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
651 {
652 int err;
653
654 byt_read_dsm(slot);
655
656 err = ni_set_max_freq(slot);
657 if (err)
658 return err;
659
660 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
661 MMC_CAP_WAIT_WHILE_BUSY;
662 return 0;
663 }
664
665 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
666 {
667 byt_read_dsm(slot);
668 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
669 MMC_CAP_WAIT_WHILE_BUSY;
670 return 0;
671 }
672
673 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
674 {
675 byt_read_dsm(slot);
676 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
677 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
678 slot->cd_idx = 0;
679 slot->cd_override_level = true;
680 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
681 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
682 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
683 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
684 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
685
686 return 0;
687 }
688
689 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
690 .allow_runtime_pm = true,
691 .probe_slot = byt_emmc_probe_slot,
692 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
693 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
694 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
695 SDHCI_QUIRK2_STOP_WITH_TC,
696 .ops = &sdhci_intel_byt_ops,
697 .priv_size = sizeof(struct intel_host),
698 };
699
700 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
701 .allow_runtime_pm = true,
702 .probe_slot = glk_emmc_probe_slot,
703 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
704 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
705 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
706 SDHCI_QUIRK2_STOP_WITH_TC,
707 .ops = &sdhci_intel_byt_ops,
708 .priv_size = sizeof(struct intel_host),
709 };
710
711 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
712 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
713 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
714 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
715 .allow_runtime_pm = true,
716 .probe_slot = ni_byt_sdio_probe_slot,
717 .ops = &sdhci_intel_byt_ops,
718 .priv_size = sizeof(struct intel_host),
719 };
720
721 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
722 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
723 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
724 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
725 .allow_runtime_pm = true,
726 .probe_slot = byt_sdio_probe_slot,
727 .ops = &sdhci_intel_byt_ops,
728 .priv_size = sizeof(struct intel_host),
729 };
730
731 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
732 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
733 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
734 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
735 SDHCI_QUIRK2_STOP_WITH_TC,
736 .allow_runtime_pm = true,
737 .own_cd_for_runtime_pm = true,
738 .probe_slot = byt_sd_probe_slot,
739 .ops = &sdhci_intel_byt_ops,
740 .priv_size = sizeof(struct intel_host),
741 };
742
743 /* Define Host controllers for Intel Merrifield platform */
744 #define INTEL_MRFLD_EMMC_0 0
745 #define INTEL_MRFLD_EMMC_1 1
746 #define INTEL_MRFLD_SD 2
747 #define INTEL_MRFLD_SDIO 3
748
749 #ifdef CONFIG_ACPI
750 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
751 {
752 struct acpi_device *device, *child;
753
754 device = ACPI_COMPANION(&slot->chip->pdev->dev);
755 if (!device)
756 return;
757
758 acpi_device_fix_up_power(device);
759 list_for_each_entry(child, &device->children, node)
760 if (child->status.present && child->status.enabled)
761 acpi_device_fix_up_power(child);
762 }
763 #else
764 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
765 #endif
766
767 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
768 {
769 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
770
771 switch (func) {
772 case INTEL_MRFLD_EMMC_0:
773 case INTEL_MRFLD_EMMC_1:
774 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
775 MMC_CAP_8_BIT_DATA |
776 MMC_CAP_1_8V_DDR;
777 break;
778 case INTEL_MRFLD_SD:
779 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
780 break;
781 case INTEL_MRFLD_SDIO:
782 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
783 MMC_CAP_POWER_OFF_CARD;
784 break;
785 default:
786 return -ENODEV;
787 }
788
789 intel_mrfld_mmc_fix_up_power_slot(slot);
790 return 0;
791 }
792
793 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
794 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
795 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
796 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
797 .allow_runtime_pm = true,
798 .probe_slot = intel_mrfld_mmc_probe_slot,
799 };
800
801 /* O2Micro extra registers */
802 #define O2_SD_LOCK_WP 0xD3
803 #define O2_SD_MULTI_VCC3V 0xEE
804 #define O2_SD_CLKREQ 0xEC
805 #define O2_SD_CAPS 0xE0
806 #define O2_SD_ADMA1 0xE2
807 #define O2_SD_ADMA2 0xE7
808 #define O2_SD_INF_MOD 0xF1
809
810 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
811 {
812 u8 scratch;
813 int ret;
814
815 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
816 if (ret)
817 return ret;
818
819 /*
820 * Turn PMOS on [bit 0], set over current detection to 2.4 V
821 * [bit 1:2] and enable over current debouncing [bit 6].
822 */
823 if (on)
824 scratch |= 0x47;
825 else
826 scratch &= ~0x47;
827
828 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
829 }
830
831 static int jmicron_probe(struct sdhci_pci_chip *chip)
832 {
833 int ret;
834 u16 mmcdev = 0;
835
836 if (chip->pdev->revision == 0) {
837 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
838 SDHCI_QUIRK_32BIT_DMA_SIZE |
839 SDHCI_QUIRK_32BIT_ADMA_SIZE |
840 SDHCI_QUIRK_RESET_AFTER_REQUEST |
841 SDHCI_QUIRK_BROKEN_SMALL_PIO;
842 }
843
844 /*
845 * JMicron chips can have two interfaces to the same hardware
846 * in order to work around limitations in Microsoft's driver.
847 * We need to make sure we only bind to one of them.
848 *
849 * This code assumes two things:
850 *
851 * 1. The PCI code adds subfunctions in order.
852 *
853 * 2. The MMC interface has a lower subfunction number
854 * than the SD interface.
855 */
856 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
857 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
858 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
859 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
860
861 if (mmcdev) {
862 struct pci_dev *sd_dev;
863
864 sd_dev = NULL;
865 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
866 mmcdev, sd_dev)) != NULL) {
867 if ((PCI_SLOT(chip->pdev->devfn) ==
868 PCI_SLOT(sd_dev->devfn)) &&
869 (chip->pdev->bus == sd_dev->bus))
870 break;
871 }
872
873 if (sd_dev) {
874 pci_dev_put(sd_dev);
875 dev_info(&chip->pdev->dev, "Refusing to bind to "
876 "secondary interface.\n");
877 return -ENODEV;
878 }
879 }
880
881 /*
882 * JMicron chips need a bit of a nudge to enable the power
883 * output pins.
884 */
885 ret = jmicron_pmos(chip, 1);
886 if (ret) {
887 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
888 return ret;
889 }
890
891 /* quirk for unsable RO-detection on JM388 chips */
892 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
893 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
894 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
895
896 return 0;
897 }
898
899 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
900 {
901 u8 scratch;
902
903 scratch = readb(host->ioaddr + 0xC0);
904
905 if (on)
906 scratch |= 0x01;
907 else
908 scratch &= ~0x01;
909
910 writeb(scratch, host->ioaddr + 0xC0);
911 }
912
913 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
914 {
915 if (slot->chip->pdev->revision == 0) {
916 u16 version;
917
918 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
919 version = (version & SDHCI_VENDOR_VER_MASK) >>
920 SDHCI_VENDOR_VER_SHIFT;
921
922 /*
923 * Older versions of the chip have lots of nasty glitches
924 * in the ADMA engine. It's best just to avoid it
925 * completely.
926 */
927 if (version < 0xAC)
928 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
929 }
930
931 /* JM388 MMC doesn't support 1.8V while SD supports it */
932 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
933 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
934 MMC_VDD_29_30 | MMC_VDD_30_31 |
935 MMC_VDD_165_195; /* allow 1.8V */
936 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
937 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
938 }
939
940 /*
941 * The secondary interface requires a bit set to get the
942 * interrupts.
943 */
944 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
945 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
946 jmicron_enable_mmc(slot->host, 1);
947
948 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
949
950 return 0;
951 }
952
953 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
954 {
955 if (dead)
956 return;
957
958 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
959 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
960 jmicron_enable_mmc(slot->host, 0);
961 }
962
963 #ifdef CONFIG_PM_SLEEP
964 static int jmicron_suspend(struct sdhci_pci_chip *chip)
965 {
966 int i, ret;
967
968 ret = __sdhci_pci_suspend_host(chip);
969 if (ret)
970 return ret;
971
972 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
973 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
974 for (i = 0; i < chip->num_slots; i++)
975 jmicron_enable_mmc(chip->slots[i]->host, 0);
976 }
977
978 sdhci_pci_init_wakeup(chip);
979
980 return 0;
981 }
982
983 static int jmicron_resume(struct sdhci_pci_chip *chip)
984 {
985 int ret, i;
986
987 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
988 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
989 for (i = 0; i < chip->num_slots; i++)
990 jmicron_enable_mmc(chip->slots[i]->host, 1);
991 }
992
993 ret = jmicron_pmos(chip, 1);
994 if (ret) {
995 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
996 return ret;
997 }
998
999 return sdhci_pci_resume_host(chip);
1000 }
1001 #endif
1002
1003 static const struct sdhci_pci_fixes sdhci_o2 = {
1004 .probe = sdhci_pci_o2_probe,
1005 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1006 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1007 .probe_slot = sdhci_pci_o2_probe_slot,
1008 #ifdef CONFIG_PM_SLEEP
1009 .resume = sdhci_pci_o2_resume,
1010 #endif
1011 };
1012
1013 static const struct sdhci_pci_fixes sdhci_jmicron = {
1014 .probe = jmicron_probe,
1015
1016 .probe_slot = jmicron_probe_slot,
1017 .remove_slot = jmicron_remove_slot,
1018
1019 #ifdef CONFIG_PM_SLEEP
1020 .suspend = jmicron_suspend,
1021 .resume = jmicron_resume,
1022 #endif
1023 };
1024
1025 /* SysKonnect CardBus2SDIO extra registers */
1026 #define SYSKT_CTRL 0x200
1027 #define SYSKT_RDFIFO_STAT 0x204
1028 #define SYSKT_WRFIFO_STAT 0x208
1029 #define SYSKT_POWER_DATA 0x20c
1030 #define SYSKT_POWER_330 0xef
1031 #define SYSKT_POWER_300 0xf8
1032 #define SYSKT_POWER_184 0xcc
1033 #define SYSKT_POWER_CMD 0x20d
1034 #define SYSKT_POWER_START (1 << 7)
1035 #define SYSKT_POWER_STATUS 0x20e
1036 #define SYSKT_POWER_STATUS_OK (1 << 0)
1037 #define SYSKT_BOARD_REV 0x210
1038 #define SYSKT_CHIP_REV 0x211
1039 #define SYSKT_CONF_DATA 0x212
1040 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1041 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1042 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1043
1044 static int syskt_probe(struct sdhci_pci_chip *chip)
1045 {
1046 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1047 chip->pdev->class &= ~0x0000FF;
1048 chip->pdev->class |= PCI_SDHCI_IFDMA;
1049 }
1050 return 0;
1051 }
1052
1053 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1054 {
1055 int tm, ps;
1056
1057 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1058 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1059 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1060 "board rev %d.%d, chip rev %d.%d\n",
1061 board_rev >> 4, board_rev & 0xf,
1062 chip_rev >> 4, chip_rev & 0xf);
1063 if (chip_rev >= 0x20)
1064 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1065
1066 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1067 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1068 udelay(50);
1069 tm = 10; /* Wait max 1 ms */
1070 do {
1071 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1072 if (ps & SYSKT_POWER_STATUS_OK)
1073 break;
1074 udelay(100);
1075 } while (--tm);
1076 if (!tm) {
1077 dev_err(&slot->chip->pdev->dev,
1078 "power regulator never stabilized");
1079 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1080 return -ENODEV;
1081 }
1082
1083 return 0;
1084 }
1085
1086 static const struct sdhci_pci_fixes sdhci_syskt = {
1087 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1088 .probe = syskt_probe,
1089 .probe_slot = syskt_probe_slot,
1090 };
1091
1092 static int via_probe(struct sdhci_pci_chip *chip)
1093 {
1094 if (chip->pdev->revision == 0x10)
1095 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1096
1097 return 0;
1098 }
1099
1100 static const struct sdhci_pci_fixes sdhci_via = {
1101 .probe = via_probe,
1102 };
1103
1104 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1105 {
1106 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1107 return 0;
1108 }
1109
1110 static const struct sdhci_pci_fixes sdhci_rtsx = {
1111 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1112 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1113 SDHCI_QUIRK2_BROKEN_DDR50,
1114 .probe_slot = rtsx_probe_slot,
1115 };
1116
1117 /*AMD chipset generation*/
1118 enum amd_chipset_gen {
1119 AMD_CHIPSET_BEFORE_ML,
1120 AMD_CHIPSET_CZ,
1121 AMD_CHIPSET_NL,
1122 AMD_CHIPSET_UNKNOWN,
1123 };
1124
1125 /* AMD registers */
1126 #define AMD_SD_AUTO_PATTERN 0xB8
1127 #define AMD_MSLEEP_DURATION 4
1128 #define AMD_SD_MISC_CONTROL 0xD0
1129 #define AMD_MAX_TUNE_VALUE 0x0B
1130 #define AMD_AUTO_TUNE_SEL 0x10800
1131 #define AMD_FIFO_PTR 0x30
1132 #define AMD_BIT_MASK 0x1F
1133
1134 static void amd_tuning_reset(struct sdhci_host *host)
1135 {
1136 unsigned int val;
1137
1138 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1139 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1140 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1141
1142 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1143 val &= ~SDHCI_CTRL_EXEC_TUNING;
1144 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1145 }
1146
1147 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1148 {
1149 unsigned int val;
1150
1151 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1152 val &= ~AMD_BIT_MASK;
1153 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1154 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1155 }
1156
1157 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1158 {
1159 unsigned int val;
1160
1161 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1162 val |= AMD_FIFO_PTR;
1163 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1164 }
1165
1166 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1167 {
1168 struct sdhci_pci_slot *slot = sdhci_priv(host);
1169 struct pci_dev *pdev = slot->chip->pdev;
1170 u8 valid_win = 0;
1171 u8 valid_win_max = 0;
1172 u8 valid_win_end = 0;
1173 u8 ctrl, tune_around;
1174
1175 amd_tuning_reset(host);
1176
1177 for (tune_around = 0; tune_around < 12; tune_around++) {
1178 amd_config_tuning_phase(pdev, tune_around);
1179
1180 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1181 valid_win = 0;
1182 msleep(AMD_MSLEEP_DURATION);
1183 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1184 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1185 } else if (++valid_win > valid_win_max) {
1186 valid_win_max = valid_win;
1187 valid_win_end = tune_around;
1188 }
1189 }
1190
1191 if (!valid_win_max) {
1192 dev_err(&pdev->dev, "no tuning point found\n");
1193 return -EIO;
1194 }
1195
1196 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1197
1198 amd_enable_manual_tuning(pdev);
1199
1200 host->mmc->retune_period = 0;
1201
1202 return 0;
1203 }
1204
1205 static int amd_probe(struct sdhci_pci_chip *chip)
1206 {
1207 struct pci_dev *smbus_dev;
1208 enum amd_chipset_gen gen;
1209
1210 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1211 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1212 if (smbus_dev) {
1213 gen = AMD_CHIPSET_BEFORE_ML;
1214 } else {
1215 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1216 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1217 if (smbus_dev) {
1218 if (smbus_dev->revision < 0x51)
1219 gen = AMD_CHIPSET_CZ;
1220 else
1221 gen = AMD_CHIPSET_NL;
1222 } else {
1223 gen = AMD_CHIPSET_UNKNOWN;
1224 }
1225 }
1226
1227 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1228 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1229
1230 return 0;
1231 }
1232
1233 static const struct sdhci_ops amd_sdhci_pci_ops = {
1234 .set_clock = sdhci_set_clock,
1235 .enable_dma = sdhci_pci_enable_dma,
1236 .set_bus_width = sdhci_set_bus_width,
1237 .reset = sdhci_reset,
1238 .set_uhs_signaling = sdhci_set_uhs_signaling,
1239 .platform_execute_tuning = amd_execute_tuning,
1240 };
1241
1242 static const struct sdhci_pci_fixes sdhci_amd = {
1243 .probe = amd_probe,
1244 .ops = &amd_sdhci_pci_ops,
1245 };
1246
1247 static const struct pci_device_id pci_ids[] = {
1248 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1249 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1250 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1251 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1252 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1253 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1254 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1255 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1256 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1257 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1258 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1259 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1260 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1261 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1262 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1263 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1264 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1265 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1266 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1267 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1268 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1269 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1270 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1271 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1272 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1273 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1274 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1275 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1276 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1277 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1278 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1279 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1280 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1281 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1282 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1283 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1284 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1285 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1286 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1287 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1288 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1289 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1290 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1291 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1292 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1293 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1294 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1295 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1296 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1297 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1298 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1299 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1300 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1301 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1302 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1303 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1304 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1305 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1306 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1307 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1308 SDHCI_PCI_DEVICE(O2, 8120, o2),
1309 SDHCI_PCI_DEVICE(O2, 8220, o2),
1310 SDHCI_PCI_DEVICE(O2, 8221, o2),
1311 SDHCI_PCI_DEVICE(O2, 8320, o2),
1312 SDHCI_PCI_DEVICE(O2, 8321, o2),
1313 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1314 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1315 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1316 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1317 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1318 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1319 /* Generic SD host controller */
1320 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1321 { /* end: all zeroes */ },
1322 };
1323
1324 MODULE_DEVICE_TABLE(pci, pci_ids);
1325
1326 /*****************************************************************************\
1327 * *
1328 * SDHCI core callbacks *
1329 * *
1330 \*****************************************************************************/
1331
1332 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1333 {
1334 struct sdhci_pci_slot *slot;
1335 struct pci_dev *pdev;
1336
1337 slot = sdhci_priv(host);
1338 pdev = slot->chip->pdev;
1339
1340 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1341 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1342 (host->flags & SDHCI_USE_SDMA)) {
1343 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1344 "doesn't fully claim to support it.\n");
1345 }
1346
1347 pci_set_master(pdev);
1348
1349 return 0;
1350 }
1351
1352 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1353 {
1354 struct sdhci_pci_slot *slot = sdhci_priv(host);
1355 int rst_n_gpio = slot->rst_n_gpio;
1356
1357 if (!gpio_is_valid(rst_n_gpio))
1358 return;
1359 gpio_set_value_cansleep(rst_n_gpio, 0);
1360 /* For eMMC, minimum is 1us but give it 10us for good measure */
1361 udelay(10);
1362 gpio_set_value_cansleep(rst_n_gpio, 1);
1363 /* For eMMC, minimum is 200us but give it 300us for good measure */
1364 usleep_range(300, 1000);
1365 }
1366
1367 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1368 {
1369 struct sdhci_pci_slot *slot = sdhci_priv(host);
1370
1371 if (slot->hw_reset)
1372 slot->hw_reset(host);
1373 }
1374
1375 static const struct sdhci_ops sdhci_pci_ops = {
1376 .set_clock = sdhci_set_clock,
1377 .enable_dma = sdhci_pci_enable_dma,
1378 .set_bus_width = sdhci_set_bus_width,
1379 .reset = sdhci_reset,
1380 .set_uhs_signaling = sdhci_set_uhs_signaling,
1381 .hw_reset = sdhci_pci_hw_reset,
1382 };
1383
1384 /*****************************************************************************\
1385 * *
1386 * Suspend/resume *
1387 * *
1388 \*****************************************************************************/
1389
1390 #ifdef CONFIG_PM_SLEEP
1391 static int sdhci_pci_suspend(struct device *dev)
1392 {
1393 struct pci_dev *pdev = to_pci_dev(dev);
1394 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1395
1396 if (!chip)
1397 return 0;
1398
1399 if (chip->fixes && chip->fixes->suspend)
1400 return chip->fixes->suspend(chip);
1401
1402 return sdhci_pci_suspend_host(chip);
1403 }
1404
1405 static int sdhci_pci_resume(struct device *dev)
1406 {
1407 struct pci_dev *pdev = to_pci_dev(dev);
1408 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1409
1410 if (!chip)
1411 return 0;
1412
1413 if (chip->fixes && chip->fixes->resume)
1414 return chip->fixes->resume(chip);
1415
1416 return sdhci_pci_resume_host(chip);
1417 }
1418 #endif
1419
1420 #ifdef CONFIG_PM
1421 static int sdhci_pci_runtime_suspend(struct device *dev)
1422 {
1423 struct pci_dev *pdev = to_pci_dev(dev);
1424 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1425
1426 if (!chip)
1427 return 0;
1428
1429 if (chip->fixes && chip->fixes->runtime_suspend)
1430 return chip->fixes->runtime_suspend(chip);
1431
1432 return sdhci_pci_runtime_suspend_host(chip);
1433 }
1434
1435 static int sdhci_pci_runtime_resume(struct device *dev)
1436 {
1437 struct pci_dev *pdev = to_pci_dev(dev);
1438 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1439
1440 if (!chip)
1441 return 0;
1442
1443 if (chip->fixes && chip->fixes->runtime_resume)
1444 return chip->fixes->runtime_resume(chip);
1445
1446 return sdhci_pci_runtime_resume_host(chip);
1447 }
1448 #endif
1449
1450 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1451 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1452 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1453 sdhci_pci_runtime_resume, NULL)
1454 };
1455
1456 /*****************************************************************************\
1457 * *
1458 * Device probing/removal *
1459 * *
1460 \*****************************************************************************/
1461
1462 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1463 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1464 int slotno)
1465 {
1466 struct sdhci_pci_slot *slot;
1467 struct sdhci_host *host;
1468 int ret, bar = first_bar + slotno;
1469 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1470
1471 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1472 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1473 return ERR_PTR(-ENODEV);
1474 }
1475
1476 if (pci_resource_len(pdev, bar) < 0x100) {
1477 dev_err(&pdev->dev, "Invalid iomem size. You may "
1478 "experience problems.\n");
1479 }
1480
1481 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1482 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1483 return ERR_PTR(-ENODEV);
1484 }
1485
1486 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1487 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1488 return ERR_PTR(-ENODEV);
1489 }
1490
1491 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1492 if (IS_ERR(host)) {
1493 dev_err(&pdev->dev, "cannot allocate host\n");
1494 return ERR_CAST(host);
1495 }
1496
1497 slot = sdhci_priv(host);
1498
1499 slot->chip = chip;
1500 slot->host = host;
1501 slot->rst_n_gpio = -EINVAL;
1502 slot->cd_gpio = -EINVAL;
1503 slot->cd_idx = -1;
1504
1505 /* Retrieve platform data if there is any */
1506 if (*sdhci_pci_get_data)
1507 slot->data = sdhci_pci_get_data(pdev, slotno);
1508
1509 if (slot->data) {
1510 if (slot->data->setup) {
1511 ret = slot->data->setup(slot->data);
1512 if (ret) {
1513 dev_err(&pdev->dev, "platform setup failed\n");
1514 goto free;
1515 }
1516 }
1517 slot->rst_n_gpio = slot->data->rst_n_gpio;
1518 slot->cd_gpio = slot->data->cd_gpio;
1519 }
1520
1521 host->hw_name = "PCI";
1522 host->ops = chip->fixes && chip->fixes->ops ?
1523 chip->fixes->ops :
1524 &sdhci_pci_ops;
1525 host->quirks = chip->quirks;
1526 host->quirks2 = chip->quirks2;
1527
1528 host->irq = pdev->irq;
1529
1530 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1531 if (ret) {
1532 dev_err(&pdev->dev, "cannot request region\n");
1533 goto cleanup;
1534 }
1535
1536 host->ioaddr = pcim_iomap_table(pdev)[bar];
1537
1538 if (chip->fixes && chip->fixes->probe_slot) {
1539 ret = chip->fixes->probe_slot(slot);
1540 if (ret)
1541 goto cleanup;
1542 }
1543
1544 if (gpio_is_valid(slot->rst_n_gpio)) {
1545 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1546 gpio_direction_output(slot->rst_n_gpio, 1);
1547 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1548 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1549 } else {
1550 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1551 slot->rst_n_gpio = -EINVAL;
1552 }
1553 }
1554
1555 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1556 host->mmc->slotno = slotno;
1557 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1558
1559 if (slot->cd_idx >= 0) {
1560 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1561 slot->cd_override_level, 0, NULL);
1562 if (ret == -EPROBE_DEFER)
1563 goto remove;
1564
1565 if (ret) {
1566 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1567 slot->cd_idx = -1;
1568 }
1569 }
1570
1571 if (chip->fixes && chip->fixes->add_host)
1572 ret = chip->fixes->add_host(slot);
1573 else
1574 ret = sdhci_add_host(host);
1575 if (ret)
1576 goto remove;
1577
1578 sdhci_pci_add_own_cd(slot);
1579
1580 /*
1581 * Check if the chip needs a separate GPIO for card detect to wake up
1582 * from runtime suspend. If it is not there, don't allow runtime PM.
1583 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1584 */
1585 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1586 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1587 chip->allow_runtime_pm = false;
1588
1589 return slot;
1590
1591 remove:
1592 if (chip->fixes && chip->fixes->remove_slot)
1593 chip->fixes->remove_slot(slot, 0);
1594
1595 cleanup:
1596 if (slot->data && slot->data->cleanup)
1597 slot->data->cleanup(slot->data);
1598
1599 free:
1600 sdhci_free_host(host);
1601
1602 return ERR_PTR(ret);
1603 }
1604
1605 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1606 {
1607 int dead;
1608 u32 scratch;
1609
1610 sdhci_pci_remove_own_cd(slot);
1611
1612 dead = 0;
1613 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1614 if (scratch == (u32)-1)
1615 dead = 1;
1616
1617 sdhci_remove_host(slot->host, dead);
1618
1619 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1620 slot->chip->fixes->remove_slot(slot, dead);
1621
1622 if (slot->data && slot->data->cleanup)
1623 slot->data->cleanup(slot->data);
1624
1625 sdhci_free_host(slot->host);
1626 }
1627
1628 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1629 {
1630 pm_suspend_ignore_children(dev, 1);
1631 pm_runtime_set_autosuspend_delay(dev, 50);
1632 pm_runtime_use_autosuspend(dev);
1633 pm_runtime_allow(dev);
1634 /* Stay active until mmc core scans for a card */
1635 pm_runtime_put_noidle(dev);
1636 }
1637
1638 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1639 {
1640 pm_runtime_forbid(dev);
1641 pm_runtime_get_noresume(dev);
1642 }
1643
1644 static int sdhci_pci_probe(struct pci_dev *pdev,
1645 const struct pci_device_id *ent)
1646 {
1647 struct sdhci_pci_chip *chip;
1648 struct sdhci_pci_slot *slot;
1649
1650 u8 slots, first_bar;
1651 int ret, i;
1652
1653 BUG_ON(pdev == NULL);
1654 BUG_ON(ent == NULL);
1655
1656 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1657 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1658
1659 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1660 if (ret)
1661 return ret;
1662
1663 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1664 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1665 if (slots == 0)
1666 return -ENODEV;
1667
1668 BUG_ON(slots > MAX_SLOTS);
1669
1670 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1671 if (ret)
1672 return ret;
1673
1674 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1675
1676 if (first_bar > 5) {
1677 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1678 return -ENODEV;
1679 }
1680
1681 ret = pcim_enable_device(pdev);
1682 if (ret)
1683 return ret;
1684
1685 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1686 if (!chip)
1687 return -ENOMEM;
1688
1689 chip->pdev = pdev;
1690 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1691 if (chip->fixes) {
1692 chip->quirks = chip->fixes->quirks;
1693 chip->quirks2 = chip->fixes->quirks2;
1694 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1695 }
1696 chip->num_slots = slots;
1697 chip->pm_retune = true;
1698 chip->rpm_retune = true;
1699
1700 pci_set_drvdata(pdev, chip);
1701
1702 if (chip->fixes && chip->fixes->probe) {
1703 ret = chip->fixes->probe(chip);
1704 if (ret)
1705 return ret;
1706 }
1707
1708 slots = chip->num_slots; /* Quirk may have changed this */
1709
1710 for (i = 0; i < slots; i++) {
1711 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1712 if (IS_ERR(slot)) {
1713 for (i--; i >= 0; i--)
1714 sdhci_pci_remove_slot(chip->slots[i]);
1715 return PTR_ERR(slot);
1716 }
1717
1718 chip->slots[i] = slot;
1719 }
1720
1721 if (chip->allow_runtime_pm)
1722 sdhci_pci_runtime_pm_allow(&pdev->dev);
1723
1724 return 0;
1725 }
1726
1727 static void sdhci_pci_remove(struct pci_dev *pdev)
1728 {
1729 int i;
1730 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1731
1732 if (chip->allow_runtime_pm)
1733 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1734
1735 for (i = 0; i < chip->num_slots; i++)
1736 sdhci_pci_remove_slot(chip->slots[i]);
1737 }
1738
1739 static struct pci_driver sdhci_driver = {
1740 .name = "sdhci-pci",
1741 .id_table = pci_ids,
1742 .probe = sdhci_pci_probe,
1743 .remove = sdhci_pci_remove,
1744 .driver = {
1745 .pm = &sdhci_pci_pm_ops
1746 },
1747 };
1748
1749 module_pci_driver(sdhci_driver);
1750
1751 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1752 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1753 MODULE_LICENSE("GPL");
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