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sdhci: Advertise 2.0v supply on SDIO host controller
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "sdhci.h"
34 #include "sdhci-pci.h"
35
36 static int sdhci_pci_enable_dma(struct sdhci_host *host);
37 static void sdhci_pci_hw_reset(struct sdhci_host *host);
38
39 #ifdef CONFIG_PM_SLEEP
40 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
41 {
42 int i, ret;
43
44 for (i = 0; i < chip->num_slots; i++) {
45 struct sdhci_pci_slot *slot = chip->slots[i];
46 struct sdhci_host *host;
47
48 if (!slot)
49 continue;
50
51 host = slot->host;
52
53 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
54 mmc_retune_needed(host->mmc);
55
56 ret = sdhci_suspend_host(host);
57 if (ret)
58 goto err_pci_suspend;
59
60 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
61 sdhci_enable_irq_wakeups(host);
62 }
63
64 return 0;
65
66 err_pci_suspend:
67 while (--i >= 0)
68 sdhci_resume_host(chip->slots[i]->host);
69 return ret;
70 }
71
72 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
73 {
74 mmc_pm_flag_t pm_flags = 0;
75 int i;
76
77 for (i = 0; i < chip->num_slots; i++) {
78 struct sdhci_pci_slot *slot = chip->slots[i];
79
80 if (slot)
81 pm_flags |= slot->host->mmc->pm_flags;
82 }
83
84 return device_init_wakeup(&chip->pdev->dev,
85 (pm_flags & MMC_PM_KEEP_POWER) &&
86 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
87 }
88
89 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
90 {
91 int ret;
92
93 ret = __sdhci_pci_suspend_host(chip);
94 if (ret)
95 return ret;
96
97 sdhci_pci_init_wakeup(chip);
98
99 return 0;
100 }
101
102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
103 {
104 struct sdhci_pci_slot *slot;
105 int i, ret;
106
107 for (i = 0; i < chip->num_slots; i++) {
108 slot = chip->slots[i];
109 if (!slot)
110 continue;
111
112 ret = sdhci_resume_host(slot->host);
113 if (ret)
114 return ret;
115 }
116
117 return 0;
118 }
119 #endif
120
121 #ifdef CONFIG_PM
122 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
123 {
124 struct sdhci_pci_slot *slot;
125 struct sdhci_host *host;
126 int i, ret;
127
128 for (i = 0; i < chip->num_slots; i++) {
129 slot = chip->slots[i];
130 if (!slot)
131 continue;
132
133 host = slot->host;
134
135 ret = sdhci_runtime_suspend_host(host);
136 if (ret)
137 goto err_pci_runtime_suspend;
138
139 if (chip->rpm_retune &&
140 host->tuning_mode != SDHCI_TUNING_MODE_3)
141 mmc_retune_needed(host->mmc);
142 }
143
144 return 0;
145
146 err_pci_runtime_suspend:
147 while (--i >= 0)
148 sdhci_runtime_resume_host(chip->slots[i]->host);
149 return ret;
150 }
151
152 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
153 {
154 struct sdhci_pci_slot *slot;
155 int i, ret;
156
157 for (i = 0; i < chip->num_slots; i++) {
158 slot = chip->slots[i];
159 if (!slot)
160 continue;
161
162 ret = sdhci_runtime_resume_host(slot->host);
163 if (ret)
164 return ret;
165 }
166
167 return 0;
168 }
169 #endif
170
171 /*****************************************************************************\
172 * *
173 * Hardware specific quirk handling *
174 * *
175 \*****************************************************************************/
176
177 static int ricoh_probe(struct sdhci_pci_chip *chip)
178 {
179 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
180 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
181 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
182 return 0;
183 }
184
185 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
186 {
187 slot->host->caps =
188 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
189 & SDHCI_TIMEOUT_CLK_MASK) |
190
191 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
192 & SDHCI_CLOCK_BASE_MASK) |
193
194 SDHCI_TIMEOUT_CLK_UNIT |
195 SDHCI_CAN_VDD_330 |
196 SDHCI_CAN_DO_HISPD |
197 SDHCI_CAN_DO_SDMA;
198 return 0;
199 }
200
201 #ifdef CONFIG_PM_SLEEP
202 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
203 {
204 /* Apply a delay to allow controller to settle */
205 /* Otherwise it becomes confused if card state changed
206 during suspend */
207 msleep(500);
208 return sdhci_pci_resume_host(chip);
209 }
210 #endif
211
212 static const struct sdhci_pci_fixes sdhci_ricoh = {
213 .probe = ricoh_probe,
214 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
215 SDHCI_QUIRK_FORCE_DMA |
216 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
217 };
218
219 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
220 .probe_slot = ricoh_mmc_probe_slot,
221 #ifdef CONFIG_PM_SLEEP
222 .resume = ricoh_mmc_resume,
223 #endif
224 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
225 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
226 SDHCI_QUIRK_NO_CARD_NO_RESET |
227 SDHCI_QUIRK_MISSING_CAPS
228 };
229
230 static const struct sdhci_pci_fixes sdhci_ene_712 = {
231 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
232 SDHCI_QUIRK_BROKEN_DMA,
233 };
234
235 static const struct sdhci_pci_fixes sdhci_ene_714 = {
236 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
237 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
238 SDHCI_QUIRK_BROKEN_DMA,
239 };
240
241 static const struct sdhci_pci_fixes sdhci_cafe = {
242 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
243 SDHCI_QUIRK_NO_BUSY_IRQ |
244 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
245 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
246 };
247
248 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
249 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
250 };
251
252 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
253 {
254 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
255 return 0;
256 }
257
258 /*
259 * ADMA operation is disabled for Moorestown platform due to
260 * hardware bugs.
261 */
262 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
263 {
264 /*
265 * slots number is fixed here for MRST as SDIO3/5 are never used and
266 * have hardware bugs.
267 */
268 chip->num_slots = 1;
269 return 0;
270 }
271
272 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
273 {
274 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
275 return 0;
276 }
277
278 #ifdef CONFIG_PM
279
280 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
281 {
282 struct sdhci_pci_slot *slot = dev_id;
283 struct sdhci_host *host = slot->host;
284
285 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
286 return IRQ_HANDLED;
287 }
288
289 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
290 {
291 int err, irq, gpio = slot->cd_gpio;
292
293 slot->cd_gpio = -EINVAL;
294 slot->cd_irq = -EINVAL;
295
296 if (!gpio_is_valid(gpio))
297 return;
298
299 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
300 if (err < 0)
301 goto out;
302
303 err = gpio_direction_input(gpio);
304 if (err < 0)
305 goto out_free;
306
307 irq = gpio_to_irq(gpio);
308 if (irq < 0)
309 goto out_free;
310
311 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
312 IRQF_TRIGGER_FALLING, "sd_cd", slot);
313 if (err)
314 goto out_free;
315
316 slot->cd_gpio = gpio;
317 slot->cd_irq = irq;
318
319 return;
320
321 out_free:
322 devm_gpio_free(&slot->chip->pdev->dev, gpio);
323 out:
324 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
325 }
326
327 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
328 {
329 if (slot->cd_irq >= 0)
330 free_irq(slot->cd_irq, slot);
331 }
332
333 #else
334
335 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
336 {
337 }
338
339 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
340 {
341 }
342
343 #endif
344
345 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
346 {
347 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
348 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
349 return 0;
350 }
351
352 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
353 {
354 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
355 return 0;
356 }
357
358 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
359 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
360 .probe_slot = mrst_hc_probe_slot,
361 };
362
363 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
364 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
365 .probe = mrst_hc_probe,
366 };
367
368 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
369 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
370 .allow_runtime_pm = true,
371 .own_cd_for_runtime_pm = true,
372 };
373
374 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
375 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
376 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
377 .allow_runtime_pm = true,
378 .probe_slot = mfd_sdio_probe_slot,
379 };
380
381 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
382 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
383 .allow_runtime_pm = true,
384 .probe_slot = mfd_emmc_probe_slot,
385 };
386
387 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
388 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
389 .probe_slot = pch_hc_probe_slot,
390 };
391
392 enum {
393 INTEL_DSM_FNS = 0,
394 INTEL_DSM_V18_SWITCH = 3,
395 INTEL_DSM_DRV_STRENGTH = 9,
396 INTEL_DSM_D3_RETUNE = 10,
397 };
398
399 struct intel_host {
400 u32 dsm_fns;
401 int drv_strength;
402 bool d3_retune;
403 };
404
405 static const guid_t intel_dsm_guid =
406 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
407 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
408
409 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
410 unsigned int fn, u32 *result)
411 {
412 union acpi_object *obj;
413 int err = 0;
414 size_t len;
415
416 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
417 if (!obj)
418 return -EOPNOTSUPP;
419
420 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
421 err = -EINVAL;
422 goto out;
423 }
424
425 len = min_t(size_t, obj->buffer.length, 4);
426
427 *result = 0;
428 memcpy(result, obj->buffer.pointer, len);
429 out:
430 ACPI_FREE(obj);
431
432 return err;
433 }
434
435 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
436 unsigned int fn, u32 *result)
437 {
438 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
439 return -EOPNOTSUPP;
440
441 return __intel_dsm(intel_host, dev, fn, result);
442 }
443
444 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
445 struct mmc_host *mmc)
446 {
447 int err;
448 u32 val;
449
450 intel_host->d3_retune = true;
451
452 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
453 if (err) {
454 pr_debug("%s: DSM not supported, error %d\n",
455 mmc_hostname(mmc), err);
456 return;
457 }
458
459 pr_debug("%s: DSM function mask %#x\n",
460 mmc_hostname(mmc), intel_host->dsm_fns);
461
462 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
463 intel_host->drv_strength = err ? 0 : val;
464
465 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
466 intel_host->d3_retune = err ? true : !!val;
467 }
468
469 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
470 {
471 u8 reg;
472
473 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
474 reg |= 0x10;
475 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
476 /* For eMMC, minimum is 1us but give it 9us for good measure */
477 udelay(9);
478 reg &= ~0x10;
479 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
480 /* For eMMC, minimum is 200us but give it 300us for good measure */
481 usleep_range(300, 1000);
482 }
483
484 static int intel_select_drive_strength(struct mmc_card *card,
485 unsigned int max_dtr, int host_drv,
486 int card_drv, int *drv_type)
487 {
488 struct sdhci_host *host = mmc_priv(card->host);
489 struct sdhci_pci_slot *slot = sdhci_priv(host);
490 struct intel_host *intel_host = sdhci_pci_priv(slot);
491
492 return intel_host->drv_strength;
493 }
494
495 static int bxt_get_cd(struct mmc_host *mmc)
496 {
497 int gpio_cd = mmc_gpio_get_cd(mmc);
498 struct sdhci_host *host = mmc_priv(mmc);
499 unsigned long flags;
500 int ret = 0;
501
502 if (!gpio_cd)
503 return 0;
504
505 spin_lock_irqsave(&host->lock, flags);
506
507 if (host->flags & SDHCI_DEVICE_DEAD)
508 goto out;
509
510 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
511 out:
512 spin_unlock_irqrestore(&host->lock, flags);
513
514 return ret;
515 }
516
517 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
518 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
519
520 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
521 unsigned short vdd)
522 {
523 int cntr;
524 u8 reg;
525
526 sdhci_set_power(host, mode, vdd);
527
528 if (mode == MMC_POWER_OFF)
529 return;
530
531 /*
532 * Bus power might not enable after D3 -> D0 transition due to the
533 * present state not yet having propagated. Retry for up to 2ms.
534 */
535 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
536 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
537 if (reg & SDHCI_POWER_ON)
538 break;
539 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
540 reg |= SDHCI_POWER_ON;
541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
542 }
543 }
544
545 #define INTEL_HS400_ES_REG 0x78
546 #define INTEL_HS400_ES_BIT BIT(0)
547
548 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
549 struct mmc_ios *ios)
550 {
551 struct sdhci_host *host = mmc_priv(mmc);
552 u32 val;
553
554 val = sdhci_readl(host, INTEL_HS400_ES_REG);
555 if (ios->enhanced_strobe)
556 val |= INTEL_HS400_ES_BIT;
557 else
558 val &= ~INTEL_HS400_ES_BIT;
559 sdhci_writel(host, val, INTEL_HS400_ES_REG);
560 }
561
562 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
563 {
564 struct sdhci_pci_slot *slot = sdhci_priv(host);
565 struct intel_host *intel_host = sdhci_pci_priv(slot);
566 struct device *dev = &slot->chip->pdev->dev;
567 u32 result = 0;
568 int err;
569
570 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
571 pr_debug("%s: %s DSM error %d result %u\n",
572 mmc_hostname(host->mmc), __func__, err, result);
573 }
574
575 static const struct sdhci_ops sdhci_intel_byt_ops = {
576 .set_clock = sdhci_set_clock,
577 .set_power = sdhci_intel_set_power,
578 .enable_dma = sdhci_pci_enable_dma,
579 .set_bus_width = sdhci_set_bus_width,
580 .reset = sdhci_reset,
581 .set_uhs_signaling = sdhci_set_uhs_signaling,
582 .hw_reset = sdhci_pci_hw_reset,
583 .voltage_switch = sdhci_intel_voltage_switch,
584 };
585
586 static void byt_read_dsm(struct sdhci_pci_slot *slot)
587 {
588 struct intel_host *intel_host = sdhci_pci_priv(slot);
589 struct device *dev = &slot->chip->pdev->dev;
590 struct mmc_host *mmc = slot->host->mmc;
591
592 intel_dsm_init(intel_host, dev, mmc);
593 slot->chip->rpm_retune = intel_host->d3_retune;
594 }
595
596 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
597 {
598 int err = sdhci_execute_tuning(mmc, opcode);
599 struct sdhci_host *host = mmc_priv(mmc);
600
601 if (err)
602 return err;
603
604 /*
605 * Tuning can leave the IP in an active state (Buffer Read Enable bit
606 * set) which prevents the entry to low power states (i.e. S0i3). Data
607 * reset will clear it.
608 */
609 sdhci_reset(host, SDHCI_RESET_DATA);
610
611 return 0;
612 }
613
614 static void byt_probe_slot(struct sdhci_pci_slot *slot)
615 {
616 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
617
618 byt_read_dsm(slot);
619
620 ops->execute_tuning = intel_execute_tuning;
621 }
622
623 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
624 {
625 byt_probe_slot(slot);
626 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
627 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
628 MMC_CAP_CMD_DURING_TFR |
629 MMC_CAP_WAIT_WHILE_BUSY;
630 slot->hw_reset = sdhci_pci_int_hw_reset;
631 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
632 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
633 slot->host->mmc_host_ops.select_drive_strength =
634 intel_select_drive_strength;
635 return 0;
636 }
637
638 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
639 {
640 int ret = byt_emmc_probe_slot(slot);
641
642 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
643 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
644 slot->host->mmc_host_ops.hs400_enhanced_strobe =
645 intel_hs400_enhanced_strobe;
646 }
647
648 return ret;
649 }
650
651 #ifdef CONFIG_ACPI
652 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
653 {
654 acpi_status status;
655 unsigned long long max_freq;
656
657 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
658 "MXFQ", NULL, &max_freq);
659 if (ACPI_FAILURE(status)) {
660 dev_err(&slot->chip->pdev->dev,
661 "MXFQ not found in acpi table\n");
662 return -EINVAL;
663 }
664
665 slot->host->mmc->f_max = max_freq * 1000000;
666
667 return 0;
668 }
669 #else
670 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
671 {
672 return 0;
673 }
674 #endif
675
676 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
677 {
678 int err;
679
680 byt_probe_slot(slot);
681
682 err = ni_set_max_freq(slot);
683 if (err)
684 return err;
685
686 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
687 MMC_CAP_WAIT_WHILE_BUSY;
688 return 0;
689 }
690
691 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
692 {
693 byt_probe_slot(slot);
694 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
695 MMC_CAP_WAIT_WHILE_BUSY;
696 return 0;
697 }
698
699 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
700 {
701 byt_probe_slot(slot);
702 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
703 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
704 slot->cd_idx = 0;
705 slot->cd_override_level = true;
706 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
707 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
708 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
709 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
710 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
711
712 return 0;
713 }
714
715 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
716 .allow_runtime_pm = true,
717 .probe_slot = byt_emmc_probe_slot,
718 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
719 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
720 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
721 SDHCI_QUIRK2_STOP_WITH_TC,
722 .ops = &sdhci_intel_byt_ops,
723 .priv_size = sizeof(struct intel_host),
724 };
725
726 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
727 .allow_runtime_pm = true,
728 .probe_slot = glk_emmc_probe_slot,
729 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
730 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
731 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
732 SDHCI_QUIRK2_STOP_WITH_TC,
733 .ops = &sdhci_intel_byt_ops,
734 .priv_size = sizeof(struct intel_host),
735 };
736
737 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
738 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
739 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
740 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
741 .allow_runtime_pm = true,
742 .probe_slot = ni_byt_sdio_probe_slot,
743 .ops = &sdhci_intel_byt_ops,
744 .priv_size = sizeof(struct intel_host),
745 };
746
747 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
748 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
749 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
750 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
751 .allow_runtime_pm = true,
752 .probe_slot = byt_sdio_probe_slot,
753 .ops = &sdhci_intel_byt_ops,
754 .priv_size = sizeof(struct intel_host),
755 };
756
757 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
758 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
759 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
760 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
761 SDHCI_QUIRK2_STOP_WITH_TC,
762 .allow_runtime_pm = true,
763 .own_cd_for_runtime_pm = true,
764 .probe_slot = byt_sd_probe_slot,
765 .ops = &sdhci_intel_byt_ops,
766 .priv_size = sizeof(struct intel_host),
767 };
768
769 /* Define Host controllers for Intel Merrifield platform */
770 #define INTEL_MRFLD_EMMC_0 0
771 #define INTEL_MRFLD_EMMC_1 1
772 #define INTEL_MRFLD_SD 2
773 #define INTEL_MRFLD_SDIO 3
774
775 #ifdef CONFIG_ACPI
776 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
777 {
778 struct acpi_device *device, *child;
779
780 device = ACPI_COMPANION(&slot->chip->pdev->dev);
781 if (!device)
782 return;
783
784 acpi_device_fix_up_power(device);
785 list_for_each_entry(child, &device->children, node)
786 if (child->status.present && child->status.enabled)
787 acpi_device_fix_up_power(child);
788 }
789 #else
790 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
791 #endif
792
793 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
794 {
795 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
796
797 switch (func) {
798 case INTEL_MRFLD_EMMC_0:
799 case INTEL_MRFLD_EMMC_1:
800 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
801 MMC_CAP_8_BIT_DATA |
802 MMC_CAP_1_8V_DDR;
803 break;
804 case INTEL_MRFLD_SD:
805 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
806 break;
807 case INTEL_MRFLD_SDIO:
808 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
809 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
810 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
811 MMC_CAP_POWER_OFF_CARD;
812 break;
813 default:
814 return -ENODEV;
815 }
816
817 intel_mrfld_mmc_fix_up_power_slot(slot);
818 return 0;
819 }
820
821 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
822 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
823 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
824 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
825 .allow_runtime_pm = true,
826 .probe_slot = intel_mrfld_mmc_probe_slot,
827 };
828
829 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
830 {
831 u8 scratch;
832 int ret;
833
834 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
835 if (ret)
836 return ret;
837
838 /*
839 * Turn PMOS on [bit 0], set over current detection to 2.4 V
840 * [bit 1:2] and enable over current debouncing [bit 6].
841 */
842 if (on)
843 scratch |= 0x47;
844 else
845 scratch &= ~0x47;
846
847 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
848 }
849
850 static int jmicron_probe(struct sdhci_pci_chip *chip)
851 {
852 int ret;
853 u16 mmcdev = 0;
854
855 if (chip->pdev->revision == 0) {
856 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
857 SDHCI_QUIRK_32BIT_DMA_SIZE |
858 SDHCI_QUIRK_32BIT_ADMA_SIZE |
859 SDHCI_QUIRK_RESET_AFTER_REQUEST |
860 SDHCI_QUIRK_BROKEN_SMALL_PIO;
861 }
862
863 /*
864 * JMicron chips can have two interfaces to the same hardware
865 * in order to work around limitations in Microsoft's driver.
866 * We need to make sure we only bind to one of them.
867 *
868 * This code assumes two things:
869 *
870 * 1. The PCI code adds subfunctions in order.
871 *
872 * 2. The MMC interface has a lower subfunction number
873 * than the SD interface.
874 */
875 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
876 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
877 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
878 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
879
880 if (mmcdev) {
881 struct pci_dev *sd_dev;
882
883 sd_dev = NULL;
884 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
885 mmcdev, sd_dev)) != NULL) {
886 if ((PCI_SLOT(chip->pdev->devfn) ==
887 PCI_SLOT(sd_dev->devfn)) &&
888 (chip->pdev->bus == sd_dev->bus))
889 break;
890 }
891
892 if (sd_dev) {
893 pci_dev_put(sd_dev);
894 dev_info(&chip->pdev->dev, "Refusing to bind to "
895 "secondary interface.\n");
896 return -ENODEV;
897 }
898 }
899
900 /*
901 * JMicron chips need a bit of a nudge to enable the power
902 * output pins.
903 */
904 ret = jmicron_pmos(chip, 1);
905 if (ret) {
906 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
907 return ret;
908 }
909
910 /* quirk for unsable RO-detection on JM388 chips */
911 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
912 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
913 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
914
915 return 0;
916 }
917
918 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
919 {
920 u8 scratch;
921
922 scratch = readb(host->ioaddr + 0xC0);
923
924 if (on)
925 scratch |= 0x01;
926 else
927 scratch &= ~0x01;
928
929 writeb(scratch, host->ioaddr + 0xC0);
930 }
931
932 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
933 {
934 if (slot->chip->pdev->revision == 0) {
935 u16 version;
936
937 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
938 version = (version & SDHCI_VENDOR_VER_MASK) >>
939 SDHCI_VENDOR_VER_SHIFT;
940
941 /*
942 * Older versions of the chip have lots of nasty glitches
943 * in the ADMA engine. It's best just to avoid it
944 * completely.
945 */
946 if (version < 0xAC)
947 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
948 }
949
950 /* JM388 MMC doesn't support 1.8V while SD supports it */
951 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
952 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
953 MMC_VDD_29_30 | MMC_VDD_30_31 |
954 MMC_VDD_165_195; /* allow 1.8V */
955 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
956 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
957 }
958
959 /*
960 * The secondary interface requires a bit set to get the
961 * interrupts.
962 */
963 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
964 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
965 jmicron_enable_mmc(slot->host, 1);
966
967 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
968
969 return 0;
970 }
971
972 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
973 {
974 if (dead)
975 return;
976
977 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
978 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
979 jmicron_enable_mmc(slot->host, 0);
980 }
981
982 #ifdef CONFIG_PM_SLEEP
983 static int jmicron_suspend(struct sdhci_pci_chip *chip)
984 {
985 int i, ret;
986
987 ret = __sdhci_pci_suspend_host(chip);
988 if (ret)
989 return ret;
990
991 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
992 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
993 for (i = 0; i < chip->num_slots; i++)
994 jmicron_enable_mmc(chip->slots[i]->host, 0);
995 }
996
997 sdhci_pci_init_wakeup(chip);
998
999 return 0;
1000 }
1001
1002 static int jmicron_resume(struct sdhci_pci_chip *chip)
1003 {
1004 int ret, i;
1005
1006 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1007 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1008 for (i = 0; i < chip->num_slots; i++)
1009 jmicron_enable_mmc(chip->slots[i]->host, 1);
1010 }
1011
1012 ret = jmicron_pmos(chip, 1);
1013 if (ret) {
1014 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1015 return ret;
1016 }
1017
1018 return sdhci_pci_resume_host(chip);
1019 }
1020 #endif
1021
1022 static const struct sdhci_pci_fixes sdhci_o2 = {
1023 .probe = sdhci_pci_o2_probe,
1024 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1025 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1026 .probe_slot = sdhci_pci_o2_probe_slot,
1027 #ifdef CONFIG_PM_SLEEP
1028 .resume = sdhci_pci_o2_resume,
1029 #endif
1030 };
1031
1032 static const struct sdhci_pci_fixes sdhci_jmicron = {
1033 .probe = jmicron_probe,
1034
1035 .probe_slot = jmicron_probe_slot,
1036 .remove_slot = jmicron_remove_slot,
1037
1038 #ifdef CONFIG_PM_SLEEP
1039 .suspend = jmicron_suspend,
1040 .resume = jmicron_resume,
1041 #endif
1042 };
1043
1044 /* SysKonnect CardBus2SDIO extra registers */
1045 #define SYSKT_CTRL 0x200
1046 #define SYSKT_RDFIFO_STAT 0x204
1047 #define SYSKT_WRFIFO_STAT 0x208
1048 #define SYSKT_POWER_DATA 0x20c
1049 #define SYSKT_POWER_330 0xef
1050 #define SYSKT_POWER_300 0xf8
1051 #define SYSKT_POWER_184 0xcc
1052 #define SYSKT_POWER_CMD 0x20d
1053 #define SYSKT_POWER_START (1 << 7)
1054 #define SYSKT_POWER_STATUS 0x20e
1055 #define SYSKT_POWER_STATUS_OK (1 << 0)
1056 #define SYSKT_BOARD_REV 0x210
1057 #define SYSKT_CHIP_REV 0x211
1058 #define SYSKT_CONF_DATA 0x212
1059 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1060 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1061 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1062
1063 static int syskt_probe(struct sdhci_pci_chip *chip)
1064 {
1065 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1066 chip->pdev->class &= ~0x0000FF;
1067 chip->pdev->class |= PCI_SDHCI_IFDMA;
1068 }
1069 return 0;
1070 }
1071
1072 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1073 {
1074 int tm, ps;
1075
1076 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1077 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1078 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1079 "board rev %d.%d, chip rev %d.%d\n",
1080 board_rev >> 4, board_rev & 0xf,
1081 chip_rev >> 4, chip_rev & 0xf);
1082 if (chip_rev >= 0x20)
1083 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1084
1085 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1086 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1087 udelay(50);
1088 tm = 10; /* Wait max 1 ms */
1089 do {
1090 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1091 if (ps & SYSKT_POWER_STATUS_OK)
1092 break;
1093 udelay(100);
1094 } while (--tm);
1095 if (!tm) {
1096 dev_err(&slot->chip->pdev->dev,
1097 "power regulator never stabilized");
1098 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1099 return -ENODEV;
1100 }
1101
1102 return 0;
1103 }
1104
1105 static const struct sdhci_pci_fixes sdhci_syskt = {
1106 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1107 .probe = syskt_probe,
1108 .probe_slot = syskt_probe_slot,
1109 };
1110
1111 static int via_probe(struct sdhci_pci_chip *chip)
1112 {
1113 if (chip->pdev->revision == 0x10)
1114 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1115
1116 return 0;
1117 }
1118
1119 static const struct sdhci_pci_fixes sdhci_via = {
1120 .probe = via_probe,
1121 };
1122
1123 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1124 {
1125 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1126 return 0;
1127 }
1128
1129 static const struct sdhci_pci_fixes sdhci_rtsx = {
1130 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1131 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1132 SDHCI_QUIRK2_BROKEN_DDR50,
1133 .probe_slot = rtsx_probe_slot,
1134 };
1135
1136 /*AMD chipset generation*/
1137 enum amd_chipset_gen {
1138 AMD_CHIPSET_BEFORE_ML,
1139 AMD_CHIPSET_CZ,
1140 AMD_CHIPSET_NL,
1141 AMD_CHIPSET_UNKNOWN,
1142 };
1143
1144 /* AMD registers */
1145 #define AMD_SD_AUTO_PATTERN 0xB8
1146 #define AMD_MSLEEP_DURATION 4
1147 #define AMD_SD_MISC_CONTROL 0xD0
1148 #define AMD_MAX_TUNE_VALUE 0x0B
1149 #define AMD_AUTO_TUNE_SEL 0x10800
1150 #define AMD_FIFO_PTR 0x30
1151 #define AMD_BIT_MASK 0x1F
1152
1153 static void amd_tuning_reset(struct sdhci_host *host)
1154 {
1155 unsigned int val;
1156
1157 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1158 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1159 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1160
1161 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1162 val &= ~SDHCI_CTRL_EXEC_TUNING;
1163 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1164 }
1165
1166 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1167 {
1168 unsigned int val;
1169
1170 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1171 val &= ~AMD_BIT_MASK;
1172 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1173 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1174 }
1175
1176 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1177 {
1178 unsigned int val;
1179
1180 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1181 val |= AMD_FIFO_PTR;
1182 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1183 }
1184
1185 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1186 {
1187 struct sdhci_pci_slot *slot = sdhci_priv(host);
1188 struct pci_dev *pdev = slot->chip->pdev;
1189 u8 valid_win = 0;
1190 u8 valid_win_max = 0;
1191 u8 valid_win_end = 0;
1192 u8 ctrl, tune_around;
1193
1194 amd_tuning_reset(host);
1195
1196 for (tune_around = 0; tune_around < 12; tune_around++) {
1197 amd_config_tuning_phase(pdev, tune_around);
1198
1199 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1200 valid_win = 0;
1201 msleep(AMD_MSLEEP_DURATION);
1202 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1203 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1204 } else if (++valid_win > valid_win_max) {
1205 valid_win_max = valid_win;
1206 valid_win_end = tune_around;
1207 }
1208 }
1209
1210 if (!valid_win_max) {
1211 dev_err(&pdev->dev, "no tuning point found\n");
1212 return -EIO;
1213 }
1214
1215 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1216
1217 amd_enable_manual_tuning(pdev);
1218
1219 host->mmc->retune_period = 0;
1220
1221 return 0;
1222 }
1223
1224 static int amd_probe(struct sdhci_pci_chip *chip)
1225 {
1226 struct pci_dev *smbus_dev;
1227 enum amd_chipset_gen gen;
1228
1229 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1230 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1231 if (smbus_dev) {
1232 gen = AMD_CHIPSET_BEFORE_ML;
1233 } else {
1234 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1235 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1236 if (smbus_dev) {
1237 if (smbus_dev->revision < 0x51)
1238 gen = AMD_CHIPSET_CZ;
1239 else
1240 gen = AMD_CHIPSET_NL;
1241 } else {
1242 gen = AMD_CHIPSET_UNKNOWN;
1243 }
1244 }
1245
1246 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1247 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1248
1249 return 0;
1250 }
1251
1252 static const struct sdhci_ops amd_sdhci_pci_ops = {
1253 .set_clock = sdhci_set_clock,
1254 .enable_dma = sdhci_pci_enable_dma,
1255 .set_bus_width = sdhci_set_bus_width,
1256 .reset = sdhci_reset,
1257 .set_uhs_signaling = sdhci_set_uhs_signaling,
1258 .platform_execute_tuning = amd_execute_tuning,
1259 };
1260
1261 static const struct sdhci_pci_fixes sdhci_amd = {
1262 .probe = amd_probe,
1263 .ops = &amd_sdhci_pci_ops,
1264 };
1265
1266 static const struct pci_device_id pci_ids[] = {
1267 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1268 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1269 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1270 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1271 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1272 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1273 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1274 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1275 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1276 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1277 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1278 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1279 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1280 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1281 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1282 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1283 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1284 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1285 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1286 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1287 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1288 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1289 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1290 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1291 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1292 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1293 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1294 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1295 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1296 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1297 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1298 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1299 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1300 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1301 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1302 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1303 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1304 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1305 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1306 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1307 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1308 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1309 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1310 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1311 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1312 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1313 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1314 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1315 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1316 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1317 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1318 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1319 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1320 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1321 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1322 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1323 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1324 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1325 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1326 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1327 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1328 SDHCI_PCI_DEVICE(O2, 8120, o2),
1329 SDHCI_PCI_DEVICE(O2, 8220, o2),
1330 SDHCI_PCI_DEVICE(O2, 8221, o2),
1331 SDHCI_PCI_DEVICE(O2, 8320, o2),
1332 SDHCI_PCI_DEVICE(O2, 8321, o2),
1333 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1334 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1335 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1336 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1337 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1338 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1339 /* Generic SD host controller */
1340 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1341 { /* end: all zeroes */ },
1342 };
1343
1344 MODULE_DEVICE_TABLE(pci, pci_ids);
1345
1346 /*****************************************************************************\
1347 * *
1348 * SDHCI core callbacks *
1349 * *
1350 \*****************************************************************************/
1351
1352 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1353 {
1354 struct sdhci_pci_slot *slot;
1355 struct pci_dev *pdev;
1356
1357 slot = sdhci_priv(host);
1358 pdev = slot->chip->pdev;
1359
1360 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1361 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1362 (host->flags & SDHCI_USE_SDMA)) {
1363 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1364 "doesn't fully claim to support it.\n");
1365 }
1366
1367 pci_set_master(pdev);
1368
1369 return 0;
1370 }
1371
1372 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1373 {
1374 struct sdhci_pci_slot *slot = sdhci_priv(host);
1375 int rst_n_gpio = slot->rst_n_gpio;
1376
1377 if (!gpio_is_valid(rst_n_gpio))
1378 return;
1379 gpio_set_value_cansleep(rst_n_gpio, 0);
1380 /* For eMMC, minimum is 1us but give it 10us for good measure */
1381 udelay(10);
1382 gpio_set_value_cansleep(rst_n_gpio, 1);
1383 /* For eMMC, minimum is 200us but give it 300us for good measure */
1384 usleep_range(300, 1000);
1385 }
1386
1387 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1388 {
1389 struct sdhci_pci_slot *slot = sdhci_priv(host);
1390
1391 if (slot->hw_reset)
1392 slot->hw_reset(host);
1393 }
1394
1395 static const struct sdhci_ops sdhci_pci_ops = {
1396 .set_clock = sdhci_set_clock,
1397 .enable_dma = sdhci_pci_enable_dma,
1398 .set_bus_width = sdhci_set_bus_width,
1399 .reset = sdhci_reset,
1400 .set_uhs_signaling = sdhci_set_uhs_signaling,
1401 .hw_reset = sdhci_pci_hw_reset,
1402 };
1403
1404 /*****************************************************************************\
1405 * *
1406 * Suspend/resume *
1407 * *
1408 \*****************************************************************************/
1409
1410 #ifdef CONFIG_PM_SLEEP
1411 static int sdhci_pci_suspend(struct device *dev)
1412 {
1413 struct pci_dev *pdev = to_pci_dev(dev);
1414 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1415
1416 if (!chip)
1417 return 0;
1418
1419 if (chip->fixes && chip->fixes->suspend)
1420 return chip->fixes->suspend(chip);
1421
1422 return sdhci_pci_suspend_host(chip);
1423 }
1424
1425 static int sdhci_pci_resume(struct device *dev)
1426 {
1427 struct pci_dev *pdev = to_pci_dev(dev);
1428 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1429
1430 if (!chip)
1431 return 0;
1432
1433 if (chip->fixes && chip->fixes->resume)
1434 return chip->fixes->resume(chip);
1435
1436 return sdhci_pci_resume_host(chip);
1437 }
1438 #endif
1439
1440 #ifdef CONFIG_PM
1441 static int sdhci_pci_runtime_suspend(struct device *dev)
1442 {
1443 struct pci_dev *pdev = to_pci_dev(dev);
1444 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1445
1446 if (!chip)
1447 return 0;
1448
1449 if (chip->fixes && chip->fixes->runtime_suspend)
1450 return chip->fixes->runtime_suspend(chip);
1451
1452 return sdhci_pci_runtime_suspend_host(chip);
1453 }
1454
1455 static int sdhci_pci_runtime_resume(struct device *dev)
1456 {
1457 struct pci_dev *pdev = to_pci_dev(dev);
1458 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1459
1460 if (!chip)
1461 return 0;
1462
1463 if (chip->fixes && chip->fixes->runtime_resume)
1464 return chip->fixes->runtime_resume(chip);
1465
1466 return sdhci_pci_runtime_resume_host(chip);
1467 }
1468 #endif
1469
1470 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1471 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1472 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1473 sdhci_pci_runtime_resume, NULL)
1474 };
1475
1476 /*****************************************************************************\
1477 * *
1478 * Device probing/removal *
1479 * *
1480 \*****************************************************************************/
1481
1482 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1483 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1484 int slotno)
1485 {
1486 struct sdhci_pci_slot *slot;
1487 struct sdhci_host *host;
1488 int ret, bar = first_bar + slotno;
1489 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1490
1491 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1492 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1493 return ERR_PTR(-ENODEV);
1494 }
1495
1496 if (pci_resource_len(pdev, bar) < 0x100) {
1497 dev_err(&pdev->dev, "Invalid iomem size. You may "
1498 "experience problems.\n");
1499 }
1500
1501 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1502 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1503 return ERR_PTR(-ENODEV);
1504 }
1505
1506 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1507 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1508 return ERR_PTR(-ENODEV);
1509 }
1510
1511 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1512 if (IS_ERR(host)) {
1513 dev_err(&pdev->dev, "cannot allocate host\n");
1514 return ERR_CAST(host);
1515 }
1516
1517 slot = sdhci_priv(host);
1518
1519 slot->chip = chip;
1520 slot->host = host;
1521 slot->rst_n_gpio = -EINVAL;
1522 slot->cd_gpio = -EINVAL;
1523 slot->cd_idx = -1;
1524
1525 /* Retrieve platform data if there is any */
1526 if (*sdhci_pci_get_data)
1527 slot->data = sdhci_pci_get_data(pdev, slotno);
1528
1529 if (slot->data) {
1530 if (slot->data->setup) {
1531 ret = slot->data->setup(slot->data);
1532 if (ret) {
1533 dev_err(&pdev->dev, "platform setup failed\n");
1534 goto free;
1535 }
1536 }
1537 slot->rst_n_gpio = slot->data->rst_n_gpio;
1538 slot->cd_gpio = slot->data->cd_gpio;
1539 }
1540
1541 host->hw_name = "PCI";
1542 host->ops = chip->fixes && chip->fixes->ops ?
1543 chip->fixes->ops :
1544 &sdhci_pci_ops;
1545 host->quirks = chip->quirks;
1546 host->quirks2 = chip->quirks2;
1547
1548 host->irq = pdev->irq;
1549
1550 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1551 if (ret) {
1552 dev_err(&pdev->dev, "cannot request region\n");
1553 goto cleanup;
1554 }
1555
1556 host->ioaddr = pcim_iomap_table(pdev)[bar];
1557
1558 if (chip->fixes && chip->fixes->probe_slot) {
1559 ret = chip->fixes->probe_slot(slot);
1560 if (ret)
1561 goto cleanup;
1562 }
1563
1564 if (gpio_is_valid(slot->rst_n_gpio)) {
1565 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1566 gpio_direction_output(slot->rst_n_gpio, 1);
1567 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1568 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1569 } else {
1570 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1571 slot->rst_n_gpio = -EINVAL;
1572 }
1573 }
1574
1575 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1576 host->mmc->slotno = slotno;
1577 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1578
1579 if (slot->cd_idx >= 0) {
1580 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1581 slot->cd_override_level, 0, NULL);
1582 if (ret == -EPROBE_DEFER)
1583 goto remove;
1584
1585 if (ret) {
1586 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1587 slot->cd_idx = -1;
1588 }
1589 }
1590
1591 if (chip->fixes && chip->fixes->add_host)
1592 ret = chip->fixes->add_host(slot);
1593 else
1594 ret = sdhci_add_host(host);
1595 if (ret)
1596 goto remove;
1597
1598 sdhci_pci_add_own_cd(slot);
1599
1600 /*
1601 * Check if the chip needs a separate GPIO for card detect to wake up
1602 * from runtime suspend. If it is not there, don't allow runtime PM.
1603 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1604 */
1605 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1606 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1607 chip->allow_runtime_pm = false;
1608
1609 return slot;
1610
1611 remove:
1612 if (chip->fixes && chip->fixes->remove_slot)
1613 chip->fixes->remove_slot(slot, 0);
1614
1615 cleanup:
1616 if (slot->data && slot->data->cleanup)
1617 slot->data->cleanup(slot->data);
1618
1619 free:
1620 sdhci_free_host(host);
1621
1622 return ERR_PTR(ret);
1623 }
1624
1625 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1626 {
1627 int dead;
1628 u32 scratch;
1629
1630 sdhci_pci_remove_own_cd(slot);
1631
1632 dead = 0;
1633 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1634 if (scratch == (u32)-1)
1635 dead = 1;
1636
1637 sdhci_remove_host(slot->host, dead);
1638
1639 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1640 slot->chip->fixes->remove_slot(slot, dead);
1641
1642 if (slot->data && slot->data->cleanup)
1643 slot->data->cleanup(slot->data);
1644
1645 sdhci_free_host(slot->host);
1646 }
1647
1648 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1649 {
1650 pm_suspend_ignore_children(dev, 1);
1651 pm_runtime_set_autosuspend_delay(dev, 50);
1652 pm_runtime_use_autosuspend(dev);
1653 pm_runtime_allow(dev);
1654 /* Stay active until mmc core scans for a card */
1655 pm_runtime_put_noidle(dev);
1656 }
1657
1658 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1659 {
1660 pm_runtime_forbid(dev);
1661 pm_runtime_get_noresume(dev);
1662 }
1663
1664 static int sdhci_pci_probe(struct pci_dev *pdev,
1665 const struct pci_device_id *ent)
1666 {
1667 struct sdhci_pci_chip *chip;
1668 struct sdhci_pci_slot *slot;
1669
1670 u8 slots, first_bar;
1671 int ret, i;
1672
1673 BUG_ON(pdev == NULL);
1674 BUG_ON(ent == NULL);
1675
1676 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1677 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1678
1679 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1680 if (ret)
1681 return ret;
1682
1683 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1684 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1685 if (slots == 0)
1686 return -ENODEV;
1687
1688 BUG_ON(slots > MAX_SLOTS);
1689
1690 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1691 if (ret)
1692 return ret;
1693
1694 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1695
1696 if (first_bar > 5) {
1697 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1698 return -ENODEV;
1699 }
1700
1701 ret = pcim_enable_device(pdev);
1702 if (ret)
1703 return ret;
1704
1705 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1706 if (!chip)
1707 return -ENOMEM;
1708
1709 chip->pdev = pdev;
1710 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1711 if (chip->fixes) {
1712 chip->quirks = chip->fixes->quirks;
1713 chip->quirks2 = chip->fixes->quirks2;
1714 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1715 }
1716 chip->num_slots = slots;
1717 chip->pm_retune = true;
1718 chip->rpm_retune = true;
1719
1720 pci_set_drvdata(pdev, chip);
1721
1722 if (chip->fixes && chip->fixes->probe) {
1723 ret = chip->fixes->probe(chip);
1724 if (ret)
1725 return ret;
1726 }
1727
1728 slots = chip->num_slots; /* Quirk may have changed this */
1729
1730 for (i = 0; i < slots; i++) {
1731 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1732 if (IS_ERR(slot)) {
1733 for (i--; i >= 0; i--)
1734 sdhci_pci_remove_slot(chip->slots[i]);
1735 return PTR_ERR(slot);
1736 }
1737
1738 chip->slots[i] = slot;
1739 }
1740
1741 if (chip->allow_runtime_pm)
1742 sdhci_pci_runtime_pm_allow(&pdev->dev);
1743
1744 return 0;
1745 }
1746
1747 static void sdhci_pci_remove(struct pci_dev *pdev)
1748 {
1749 int i;
1750 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1751
1752 if (chip->allow_runtime_pm)
1753 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1754
1755 for (i = 0; i < chip->num_slots; i++)
1756 sdhci_pci_remove_slot(chip->slots[i]);
1757 }
1758
1759 static struct pci_driver sdhci_driver = {
1760 .name = "sdhci-pci",
1761 .id_table = pci_ids,
1762 .probe = sdhci_pci_probe,
1763 .remove = sdhci_pci_remove,
1764 .driver = {
1765 .pm = &sdhci_pci_pm_ops
1766 },
1767 };
1768
1769 module_pci_driver(sdhci_driver);
1770
1771 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1772 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1773 MODULE_LICENSE("GPL");
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