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UBUNTU: Ubuntu-4.13.0-45.50
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "sdhci.h"
34 #include "sdhci-pci.h"
35 #include "sdhci-pci-o2micro.h"
36
37 static int sdhci_pci_enable_dma(struct sdhci_host *host);
38 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width);
39 static void sdhci_pci_hw_reset(struct sdhci_host *host);
40
41 #ifdef CONFIG_PM_SLEEP
42 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
43 {
44 int i, ret;
45
46 for (i = 0; i < chip->num_slots; i++) {
47 struct sdhci_pci_slot *slot = chip->slots[i];
48 struct sdhci_host *host;
49
50 if (!slot)
51 continue;
52
53 host = slot->host;
54
55 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
56 mmc_retune_needed(host->mmc);
57
58 ret = sdhci_suspend_host(host);
59 if (ret)
60 goto err_pci_suspend;
61
62 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
63 sdhci_enable_irq_wakeups(host);
64 }
65
66 return 0;
67
68 err_pci_suspend:
69 while (--i >= 0)
70 sdhci_resume_host(chip->slots[i]->host);
71 return ret;
72 }
73
74 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
75 {
76 mmc_pm_flag_t pm_flags = 0;
77 int i;
78
79 for (i = 0; i < chip->num_slots; i++) {
80 struct sdhci_pci_slot *slot = chip->slots[i];
81
82 if (slot)
83 pm_flags |= slot->host->mmc->pm_flags;
84 }
85
86 return device_init_wakeup(&chip->pdev->dev,
87 (pm_flags & MMC_PM_KEEP_POWER) &&
88 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
89 }
90
91 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
92 {
93 int ret;
94
95 ret = __sdhci_pci_suspend_host(chip);
96 if (ret)
97 return ret;
98
99 sdhci_pci_init_wakeup(chip);
100
101 return 0;
102 }
103
104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
105 {
106 struct sdhci_pci_slot *slot;
107 int i, ret;
108
109 for (i = 0; i < chip->num_slots; i++) {
110 slot = chip->slots[i];
111 if (!slot)
112 continue;
113
114 ret = sdhci_resume_host(slot->host);
115 if (ret)
116 return ret;
117 }
118
119 return 0;
120 }
121 #endif
122
123 #ifdef CONFIG_PM
124 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
125 {
126 struct sdhci_pci_slot *slot;
127 struct sdhci_host *host;
128 int i, ret;
129
130 for (i = 0; i < chip->num_slots; i++) {
131 slot = chip->slots[i];
132 if (!slot)
133 continue;
134
135 host = slot->host;
136
137 ret = sdhci_runtime_suspend_host(host);
138 if (ret)
139 goto err_pci_runtime_suspend;
140
141 if (chip->rpm_retune &&
142 host->tuning_mode != SDHCI_TUNING_MODE_3)
143 mmc_retune_needed(host->mmc);
144 }
145
146 return 0;
147
148 err_pci_runtime_suspend:
149 while (--i >= 0)
150 sdhci_runtime_resume_host(chip->slots[i]->host);
151 return ret;
152 }
153
154 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
155 {
156 struct sdhci_pci_slot *slot;
157 int i, ret;
158
159 for (i = 0; i < chip->num_slots; i++) {
160 slot = chip->slots[i];
161 if (!slot)
162 continue;
163
164 ret = sdhci_runtime_resume_host(slot->host);
165 if (ret)
166 return ret;
167 }
168
169 return 0;
170 }
171 #endif
172
173 /*****************************************************************************\
174 * *
175 * Hardware specific quirk handling *
176 * *
177 \*****************************************************************************/
178
179 static int ricoh_probe(struct sdhci_pci_chip *chip)
180 {
181 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
182 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
183 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
184 return 0;
185 }
186
187 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
188 {
189 slot->host->caps =
190 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
191 & SDHCI_TIMEOUT_CLK_MASK) |
192
193 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
194 & SDHCI_CLOCK_BASE_MASK) |
195
196 SDHCI_TIMEOUT_CLK_UNIT |
197 SDHCI_CAN_VDD_330 |
198 SDHCI_CAN_DO_HISPD |
199 SDHCI_CAN_DO_SDMA;
200 return 0;
201 }
202
203 #ifdef CONFIG_PM_SLEEP
204 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
205 {
206 /* Apply a delay to allow controller to settle */
207 /* Otherwise it becomes confused if card state changed
208 during suspend */
209 msleep(500);
210 return sdhci_pci_resume_host(chip);
211 }
212 #endif
213
214 static const struct sdhci_pci_fixes sdhci_ricoh = {
215 .probe = ricoh_probe,
216 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
217 SDHCI_QUIRK_FORCE_DMA |
218 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
219 };
220
221 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
222 .probe_slot = ricoh_mmc_probe_slot,
223 #ifdef CONFIG_PM_SLEEP
224 .resume = ricoh_mmc_resume,
225 #endif
226 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
227 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
228 SDHCI_QUIRK_NO_CARD_NO_RESET |
229 SDHCI_QUIRK_MISSING_CAPS
230 };
231
232 static const struct sdhci_pci_fixes sdhci_ene_712 = {
233 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
234 SDHCI_QUIRK_BROKEN_DMA,
235 };
236
237 static const struct sdhci_pci_fixes sdhci_ene_714 = {
238 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
239 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
240 SDHCI_QUIRK_BROKEN_DMA,
241 };
242
243 static const struct sdhci_pci_fixes sdhci_cafe = {
244 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
245 SDHCI_QUIRK_NO_BUSY_IRQ |
246 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
247 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
248 };
249
250 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
251 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
252 };
253
254 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
255 {
256 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
257 return 0;
258 }
259
260 /*
261 * ADMA operation is disabled for Moorestown platform due to
262 * hardware bugs.
263 */
264 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
265 {
266 /*
267 * slots number is fixed here for MRST as SDIO3/5 are never used and
268 * have hardware bugs.
269 */
270 chip->num_slots = 1;
271 return 0;
272 }
273
274 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
275 {
276 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
277 return 0;
278 }
279
280 #ifdef CONFIG_PM
281
282 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
283 {
284 struct sdhci_pci_slot *slot = dev_id;
285 struct sdhci_host *host = slot->host;
286
287 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
288 return IRQ_HANDLED;
289 }
290
291 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
292 {
293 int err, irq, gpio = slot->cd_gpio;
294
295 slot->cd_gpio = -EINVAL;
296 slot->cd_irq = -EINVAL;
297
298 if (!gpio_is_valid(gpio))
299 return;
300
301 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
302 if (err < 0)
303 goto out;
304
305 err = gpio_direction_input(gpio);
306 if (err < 0)
307 goto out_free;
308
309 irq = gpio_to_irq(gpio);
310 if (irq < 0)
311 goto out_free;
312
313 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
314 IRQF_TRIGGER_FALLING, "sd_cd", slot);
315 if (err)
316 goto out_free;
317
318 slot->cd_gpio = gpio;
319 slot->cd_irq = irq;
320
321 return;
322
323 out_free:
324 devm_gpio_free(&slot->chip->pdev->dev, gpio);
325 out:
326 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
327 }
328
329 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
330 {
331 if (slot->cd_irq >= 0)
332 free_irq(slot->cd_irq, slot);
333 }
334
335 #else
336
337 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
338 {
339 }
340
341 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
342 {
343 }
344
345 #endif
346
347 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
348 {
349 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
350 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
351 return 0;
352 }
353
354 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
355 {
356 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
357 return 0;
358 }
359
360 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
361 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
362 .probe_slot = mrst_hc_probe_slot,
363 };
364
365 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
366 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
367 .probe = mrst_hc_probe,
368 };
369
370 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 .allow_runtime_pm = true,
373 .own_cd_for_runtime_pm = true,
374 };
375
376 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
377 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
378 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
379 .allow_runtime_pm = true,
380 .probe_slot = mfd_sdio_probe_slot,
381 };
382
383 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
384 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
385 .allow_runtime_pm = true,
386 .probe_slot = mfd_emmc_probe_slot,
387 };
388
389 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
390 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
391 .probe_slot = pch_hc_probe_slot,
392 };
393
394 enum {
395 INTEL_DSM_FNS = 0,
396 INTEL_DSM_V18_SWITCH = 3,
397 INTEL_DSM_DRV_STRENGTH = 9,
398 INTEL_DSM_D3_RETUNE = 10,
399 };
400
401 struct intel_host {
402 u32 dsm_fns;
403 int drv_strength;
404 bool d3_retune;
405 };
406
407 static const guid_t intel_dsm_guid =
408 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
409 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
410
411 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
412 unsigned int fn, u32 *result)
413 {
414 union acpi_object *obj;
415 int err = 0;
416 size_t len;
417
418 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
419 if (!obj)
420 return -EOPNOTSUPP;
421
422 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
423 err = -EINVAL;
424 goto out;
425 }
426
427 len = min_t(size_t, obj->buffer.length, 4);
428
429 *result = 0;
430 memcpy(result, obj->buffer.pointer, len);
431 out:
432 ACPI_FREE(obj);
433
434 return err;
435 }
436
437 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
438 unsigned int fn, u32 *result)
439 {
440 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
441 return -EOPNOTSUPP;
442
443 return __intel_dsm(intel_host, dev, fn, result);
444 }
445
446 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
447 struct mmc_host *mmc)
448 {
449 int err;
450 u32 val;
451
452 intel_host->d3_retune = true;
453
454 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
455 if (err) {
456 pr_debug("%s: DSM not supported, error %d\n",
457 mmc_hostname(mmc), err);
458 return;
459 }
460
461 pr_debug("%s: DSM function mask %#x\n",
462 mmc_hostname(mmc), intel_host->dsm_fns);
463
464 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
465 intel_host->drv_strength = err ? 0 : val;
466
467 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
468 intel_host->d3_retune = err ? true : !!val;
469 }
470
471 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
472 {
473 u8 reg;
474
475 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
476 reg |= 0x10;
477 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
478 /* For eMMC, minimum is 1us but give it 9us for good measure */
479 udelay(9);
480 reg &= ~0x10;
481 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
482 /* For eMMC, minimum is 200us but give it 300us for good measure */
483 usleep_range(300, 1000);
484 }
485
486 static int intel_select_drive_strength(struct mmc_card *card,
487 unsigned int max_dtr, int host_drv,
488 int card_drv, int *drv_type)
489 {
490 struct sdhci_host *host = mmc_priv(card->host);
491 struct sdhci_pci_slot *slot = sdhci_priv(host);
492 struct intel_host *intel_host = sdhci_pci_priv(slot);
493
494 return intel_host->drv_strength;
495 }
496
497 static int bxt_get_cd(struct mmc_host *mmc)
498 {
499 int gpio_cd = mmc_gpio_get_cd(mmc);
500 struct sdhci_host *host = mmc_priv(mmc);
501 unsigned long flags;
502 int ret = 0;
503
504 if (!gpio_cd)
505 return 0;
506
507 spin_lock_irqsave(&host->lock, flags);
508
509 if (host->flags & SDHCI_DEVICE_DEAD)
510 goto out;
511
512 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
513 out:
514 spin_unlock_irqrestore(&host->lock, flags);
515
516 return ret;
517 }
518
519 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
520 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
521
522 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
523 unsigned short vdd)
524 {
525 int cntr;
526 u8 reg;
527
528 sdhci_set_power(host, mode, vdd);
529
530 if (mode == MMC_POWER_OFF)
531 return;
532
533 /*
534 * Bus power might not enable after D3 -> D0 transition due to the
535 * present state not yet having propagated. Retry for up to 2ms.
536 */
537 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
538 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
539 if (reg & SDHCI_POWER_ON)
540 break;
541 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
542 reg |= SDHCI_POWER_ON;
543 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
544 }
545 }
546
547 #define INTEL_HS400_ES_REG 0x78
548 #define INTEL_HS400_ES_BIT BIT(0)
549
550 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
551 struct mmc_ios *ios)
552 {
553 struct sdhci_host *host = mmc_priv(mmc);
554 u32 val;
555
556 val = sdhci_readl(host, INTEL_HS400_ES_REG);
557 if (ios->enhanced_strobe)
558 val |= INTEL_HS400_ES_BIT;
559 else
560 val &= ~INTEL_HS400_ES_BIT;
561 sdhci_writel(host, val, INTEL_HS400_ES_REG);
562 }
563
564 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
565 {
566 struct sdhci_pci_slot *slot = sdhci_priv(host);
567 struct intel_host *intel_host = sdhci_pci_priv(slot);
568 struct device *dev = &slot->chip->pdev->dev;
569 u32 result = 0;
570 int err;
571
572 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
573 pr_debug("%s: %s DSM error %d result %u\n",
574 mmc_hostname(host->mmc), __func__, err, result);
575 }
576
577 static const struct sdhci_ops sdhci_intel_byt_ops = {
578 .set_clock = sdhci_set_clock,
579 .set_power = sdhci_intel_set_power,
580 .enable_dma = sdhci_pci_enable_dma,
581 .set_bus_width = sdhci_pci_set_bus_width,
582 .reset = sdhci_reset,
583 .set_uhs_signaling = sdhci_set_uhs_signaling,
584 .hw_reset = sdhci_pci_hw_reset,
585 .voltage_switch = sdhci_intel_voltage_switch,
586 };
587
588 static void byt_read_dsm(struct sdhci_pci_slot *slot)
589 {
590 struct intel_host *intel_host = sdhci_pci_priv(slot);
591 struct device *dev = &slot->chip->pdev->dev;
592 struct mmc_host *mmc = slot->host->mmc;
593
594 intel_dsm_init(intel_host, dev, mmc);
595 slot->chip->rpm_retune = intel_host->d3_retune;
596 }
597
598 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
599 {
600 byt_read_dsm(slot);
601 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
602 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
603 MMC_CAP_CMD_DURING_TFR |
604 MMC_CAP_WAIT_WHILE_BUSY;
605 slot->hw_reset = sdhci_pci_int_hw_reset;
606 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
607 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
608 slot->host->mmc_host_ops.select_drive_strength =
609 intel_select_drive_strength;
610 return 0;
611 }
612
613 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
614 {
615 int ret = byt_emmc_probe_slot(slot);
616
617 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
618 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
619 slot->host->mmc_host_ops.hs400_enhanced_strobe =
620 intel_hs400_enhanced_strobe;
621 }
622
623 return ret;
624 }
625
626 #ifdef CONFIG_ACPI
627 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
628 {
629 acpi_status status;
630 unsigned long long max_freq;
631
632 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
633 "MXFQ", NULL, &max_freq);
634 if (ACPI_FAILURE(status)) {
635 dev_err(&slot->chip->pdev->dev,
636 "MXFQ not found in acpi table\n");
637 return -EINVAL;
638 }
639
640 slot->host->mmc->f_max = max_freq * 1000000;
641
642 return 0;
643 }
644 #else
645 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
646 {
647 return 0;
648 }
649 #endif
650
651 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
652 {
653 int err;
654
655 byt_read_dsm(slot);
656
657 err = ni_set_max_freq(slot);
658 if (err)
659 return err;
660
661 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
662 MMC_CAP_WAIT_WHILE_BUSY;
663 return 0;
664 }
665
666 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
667 {
668 byt_read_dsm(slot);
669 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
670 MMC_CAP_WAIT_WHILE_BUSY;
671 return 0;
672 }
673
674 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
675 {
676 byt_read_dsm(slot);
677 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
678 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
679 slot->cd_idx = 0;
680 slot->cd_override_level = true;
681 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
682 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
683 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
684 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
685 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
686
687 return 0;
688 }
689
690 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
691 .allow_runtime_pm = true,
692 .probe_slot = byt_emmc_probe_slot,
693 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
694 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
695 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
696 SDHCI_QUIRK2_STOP_WITH_TC,
697 .ops = &sdhci_intel_byt_ops,
698 .priv_size = sizeof(struct intel_host),
699 };
700
701 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
702 .allow_runtime_pm = true,
703 .probe_slot = glk_emmc_probe_slot,
704 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
705 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
706 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
707 SDHCI_QUIRK2_STOP_WITH_TC,
708 .ops = &sdhci_intel_byt_ops,
709 .priv_size = sizeof(struct intel_host),
710 };
711
712 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
713 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
714 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
715 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
716 .allow_runtime_pm = true,
717 .probe_slot = ni_byt_sdio_probe_slot,
718 .ops = &sdhci_intel_byt_ops,
719 .priv_size = sizeof(struct intel_host),
720 };
721
722 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
723 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
724 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
725 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
726 .allow_runtime_pm = true,
727 .probe_slot = byt_sdio_probe_slot,
728 .ops = &sdhci_intel_byt_ops,
729 .priv_size = sizeof(struct intel_host),
730 };
731
732 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
733 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
734 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
735 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
736 SDHCI_QUIRK2_STOP_WITH_TC,
737 .allow_runtime_pm = true,
738 .own_cd_for_runtime_pm = true,
739 .probe_slot = byt_sd_probe_slot,
740 .ops = &sdhci_intel_byt_ops,
741 .priv_size = sizeof(struct intel_host),
742 };
743
744 /* Define Host controllers for Intel Merrifield platform */
745 #define INTEL_MRFLD_EMMC_0 0
746 #define INTEL_MRFLD_EMMC_1 1
747 #define INTEL_MRFLD_SD 2
748 #define INTEL_MRFLD_SDIO 3
749
750 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
751 {
752 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
753
754 switch (func) {
755 case INTEL_MRFLD_EMMC_0:
756 case INTEL_MRFLD_EMMC_1:
757 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
758 MMC_CAP_8_BIT_DATA |
759 MMC_CAP_1_8V_DDR;
760 break;
761 case INTEL_MRFLD_SD:
762 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
763 break;
764 case INTEL_MRFLD_SDIO:
765 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
766 MMC_CAP_POWER_OFF_CARD;
767 break;
768 default:
769 return -ENODEV;
770 }
771 return 0;
772 }
773
774 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
775 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
776 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
777 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
778 .allow_runtime_pm = true,
779 .probe_slot = intel_mrfld_mmc_probe_slot,
780 };
781
782 /* O2Micro extra registers */
783 #define O2_SD_LOCK_WP 0xD3
784 #define O2_SD_MULTI_VCC3V 0xEE
785 #define O2_SD_CLKREQ 0xEC
786 #define O2_SD_CAPS 0xE0
787 #define O2_SD_ADMA1 0xE2
788 #define O2_SD_ADMA2 0xE7
789 #define O2_SD_INF_MOD 0xF1
790
791 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
792 {
793 u8 scratch;
794 int ret;
795
796 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
797 if (ret)
798 return ret;
799
800 /*
801 * Turn PMOS on [bit 0], set over current detection to 2.4 V
802 * [bit 1:2] and enable over current debouncing [bit 6].
803 */
804 if (on)
805 scratch |= 0x47;
806 else
807 scratch &= ~0x47;
808
809 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
810 }
811
812 static int jmicron_probe(struct sdhci_pci_chip *chip)
813 {
814 int ret;
815 u16 mmcdev = 0;
816
817 if (chip->pdev->revision == 0) {
818 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
819 SDHCI_QUIRK_32BIT_DMA_SIZE |
820 SDHCI_QUIRK_32BIT_ADMA_SIZE |
821 SDHCI_QUIRK_RESET_AFTER_REQUEST |
822 SDHCI_QUIRK_BROKEN_SMALL_PIO;
823 }
824
825 /*
826 * JMicron chips can have two interfaces to the same hardware
827 * in order to work around limitations in Microsoft's driver.
828 * We need to make sure we only bind to one of them.
829 *
830 * This code assumes two things:
831 *
832 * 1. The PCI code adds subfunctions in order.
833 *
834 * 2. The MMC interface has a lower subfunction number
835 * than the SD interface.
836 */
837 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
838 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
839 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
840 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
841
842 if (mmcdev) {
843 struct pci_dev *sd_dev;
844
845 sd_dev = NULL;
846 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
847 mmcdev, sd_dev)) != NULL) {
848 if ((PCI_SLOT(chip->pdev->devfn) ==
849 PCI_SLOT(sd_dev->devfn)) &&
850 (chip->pdev->bus == sd_dev->bus))
851 break;
852 }
853
854 if (sd_dev) {
855 pci_dev_put(sd_dev);
856 dev_info(&chip->pdev->dev, "Refusing to bind to "
857 "secondary interface.\n");
858 return -ENODEV;
859 }
860 }
861
862 /*
863 * JMicron chips need a bit of a nudge to enable the power
864 * output pins.
865 */
866 ret = jmicron_pmos(chip, 1);
867 if (ret) {
868 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
869 return ret;
870 }
871
872 /* quirk for unsable RO-detection on JM388 chips */
873 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
874 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
875 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
876
877 return 0;
878 }
879
880 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
881 {
882 u8 scratch;
883
884 scratch = readb(host->ioaddr + 0xC0);
885
886 if (on)
887 scratch |= 0x01;
888 else
889 scratch &= ~0x01;
890
891 writeb(scratch, host->ioaddr + 0xC0);
892 }
893
894 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
895 {
896 if (slot->chip->pdev->revision == 0) {
897 u16 version;
898
899 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
900 version = (version & SDHCI_VENDOR_VER_MASK) >>
901 SDHCI_VENDOR_VER_SHIFT;
902
903 /*
904 * Older versions of the chip have lots of nasty glitches
905 * in the ADMA engine. It's best just to avoid it
906 * completely.
907 */
908 if (version < 0xAC)
909 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
910 }
911
912 /* JM388 MMC doesn't support 1.8V while SD supports it */
913 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
914 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
915 MMC_VDD_29_30 | MMC_VDD_30_31 |
916 MMC_VDD_165_195; /* allow 1.8V */
917 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
918 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
919 }
920
921 /*
922 * The secondary interface requires a bit set to get the
923 * interrupts.
924 */
925 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
926 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
927 jmicron_enable_mmc(slot->host, 1);
928
929 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
930
931 return 0;
932 }
933
934 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
935 {
936 if (dead)
937 return;
938
939 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
940 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
941 jmicron_enable_mmc(slot->host, 0);
942 }
943
944 #ifdef CONFIG_PM_SLEEP
945 static int jmicron_suspend(struct sdhci_pci_chip *chip)
946 {
947 int i, ret;
948
949 ret = __sdhci_pci_suspend_host(chip);
950 if (ret)
951 return ret;
952
953 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
954 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
955 for (i = 0; i < chip->num_slots; i++)
956 jmicron_enable_mmc(chip->slots[i]->host, 0);
957 }
958
959 sdhci_pci_init_wakeup(chip);
960
961 return 0;
962 }
963
964 static int jmicron_resume(struct sdhci_pci_chip *chip)
965 {
966 int ret, i;
967
968 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
969 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
970 for (i = 0; i < chip->num_slots; i++)
971 jmicron_enable_mmc(chip->slots[i]->host, 1);
972 }
973
974 ret = jmicron_pmos(chip, 1);
975 if (ret) {
976 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
977 return ret;
978 }
979
980 return sdhci_pci_resume_host(chip);
981 }
982 #endif
983
984 static const struct sdhci_pci_fixes sdhci_o2 = {
985 .probe = sdhci_pci_o2_probe,
986 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
987 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
988 .probe_slot = sdhci_pci_o2_probe_slot,
989 #ifdef CONFIG_PM_SLEEP
990 .resume = sdhci_pci_o2_resume,
991 #endif
992 };
993
994 static const struct sdhci_pci_fixes sdhci_jmicron = {
995 .probe = jmicron_probe,
996
997 .probe_slot = jmicron_probe_slot,
998 .remove_slot = jmicron_remove_slot,
999
1000 #ifdef CONFIG_PM_SLEEP
1001 .suspend = jmicron_suspend,
1002 .resume = jmicron_resume,
1003 #endif
1004 };
1005
1006 /* SysKonnect CardBus2SDIO extra registers */
1007 #define SYSKT_CTRL 0x200
1008 #define SYSKT_RDFIFO_STAT 0x204
1009 #define SYSKT_WRFIFO_STAT 0x208
1010 #define SYSKT_POWER_DATA 0x20c
1011 #define SYSKT_POWER_330 0xef
1012 #define SYSKT_POWER_300 0xf8
1013 #define SYSKT_POWER_184 0xcc
1014 #define SYSKT_POWER_CMD 0x20d
1015 #define SYSKT_POWER_START (1 << 7)
1016 #define SYSKT_POWER_STATUS 0x20e
1017 #define SYSKT_POWER_STATUS_OK (1 << 0)
1018 #define SYSKT_BOARD_REV 0x210
1019 #define SYSKT_CHIP_REV 0x211
1020 #define SYSKT_CONF_DATA 0x212
1021 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1022 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1023 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1024
1025 static int syskt_probe(struct sdhci_pci_chip *chip)
1026 {
1027 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1028 chip->pdev->class &= ~0x0000FF;
1029 chip->pdev->class |= PCI_SDHCI_IFDMA;
1030 }
1031 return 0;
1032 }
1033
1034 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1035 {
1036 int tm, ps;
1037
1038 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1039 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1040 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1041 "board rev %d.%d, chip rev %d.%d\n",
1042 board_rev >> 4, board_rev & 0xf,
1043 chip_rev >> 4, chip_rev & 0xf);
1044 if (chip_rev >= 0x20)
1045 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1046
1047 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1048 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1049 udelay(50);
1050 tm = 10; /* Wait max 1 ms */
1051 do {
1052 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1053 if (ps & SYSKT_POWER_STATUS_OK)
1054 break;
1055 udelay(100);
1056 } while (--tm);
1057 if (!tm) {
1058 dev_err(&slot->chip->pdev->dev,
1059 "power regulator never stabilized");
1060 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1061 return -ENODEV;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static const struct sdhci_pci_fixes sdhci_syskt = {
1068 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1069 .probe = syskt_probe,
1070 .probe_slot = syskt_probe_slot,
1071 };
1072
1073 static int via_probe(struct sdhci_pci_chip *chip)
1074 {
1075 if (chip->pdev->revision == 0x10)
1076 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1077
1078 return 0;
1079 }
1080
1081 static const struct sdhci_pci_fixes sdhci_via = {
1082 .probe = via_probe,
1083 };
1084
1085 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1086 {
1087 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1088 return 0;
1089 }
1090
1091 static const struct sdhci_pci_fixes sdhci_rtsx = {
1092 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1093 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1094 SDHCI_QUIRK2_BROKEN_DDR50,
1095 .probe_slot = rtsx_probe_slot,
1096 };
1097
1098 /*AMD chipset generation*/
1099 enum amd_chipset_gen {
1100 AMD_CHIPSET_BEFORE_ML,
1101 AMD_CHIPSET_CZ,
1102 AMD_CHIPSET_NL,
1103 AMD_CHIPSET_UNKNOWN,
1104 };
1105
1106 /* AMD registers */
1107 #define AMD_SD_AUTO_PATTERN 0xB8
1108 #define AMD_MSLEEP_DURATION 4
1109 #define AMD_SD_MISC_CONTROL 0xD0
1110 #define AMD_MAX_TUNE_VALUE 0x0B
1111 #define AMD_AUTO_TUNE_SEL 0x10800
1112 #define AMD_FIFO_PTR 0x30
1113 #define AMD_BIT_MASK 0x1F
1114
1115 static void amd_tuning_reset(struct sdhci_host *host)
1116 {
1117 unsigned int val;
1118
1119 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1120 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1121 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1122
1123 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1124 val &= ~SDHCI_CTRL_EXEC_TUNING;
1125 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1126 }
1127
1128 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1129 {
1130 unsigned int val;
1131
1132 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1133 val &= ~AMD_BIT_MASK;
1134 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1135 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1136 }
1137
1138 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1139 {
1140 unsigned int val;
1141
1142 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1143 val |= AMD_FIFO_PTR;
1144 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1145 }
1146
1147 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1148 {
1149 struct sdhci_pci_slot *slot = sdhci_priv(host);
1150 struct pci_dev *pdev = slot->chip->pdev;
1151 u8 valid_win = 0;
1152 u8 valid_win_max = 0;
1153 u8 valid_win_end = 0;
1154 u8 ctrl, tune_around;
1155
1156 amd_tuning_reset(host);
1157
1158 for (tune_around = 0; tune_around < 12; tune_around++) {
1159 amd_config_tuning_phase(pdev, tune_around);
1160
1161 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1162 valid_win = 0;
1163 msleep(AMD_MSLEEP_DURATION);
1164 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1165 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1166 } else if (++valid_win > valid_win_max) {
1167 valid_win_max = valid_win;
1168 valid_win_end = tune_around;
1169 }
1170 }
1171
1172 if (!valid_win_max) {
1173 dev_err(&pdev->dev, "no tuning point found\n");
1174 return -EIO;
1175 }
1176
1177 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1178
1179 amd_enable_manual_tuning(pdev);
1180
1181 host->mmc->retune_period = 0;
1182
1183 return 0;
1184 }
1185
1186 static int amd_probe(struct sdhci_pci_chip *chip)
1187 {
1188 struct pci_dev *smbus_dev;
1189 enum amd_chipset_gen gen;
1190
1191 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1192 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1193 if (smbus_dev) {
1194 gen = AMD_CHIPSET_BEFORE_ML;
1195 } else {
1196 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1197 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1198 if (smbus_dev) {
1199 if (smbus_dev->revision < 0x51)
1200 gen = AMD_CHIPSET_CZ;
1201 else
1202 gen = AMD_CHIPSET_NL;
1203 } else {
1204 gen = AMD_CHIPSET_UNKNOWN;
1205 }
1206 }
1207
1208 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1209 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1210
1211 return 0;
1212 }
1213
1214 static const struct sdhci_ops amd_sdhci_pci_ops = {
1215 .set_clock = sdhci_set_clock,
1216 .enable_dma = sdhci_pci_enable_dma,
1217 .set_bus_width = sdhci_pci_set_bus_width,
1218 .reset = sdhci_reset,
1219 .set_uhs_signaling = sdhci_set_uhs_signaling,
1220 .platform_execute_tuning = amd_execute_tuning,
1221 };
1222
1223 static const struct sdhci_pci_fixes sdhci_amd = {
1224 .probe = amd_probe,
1225 .ops = &amd_sdhci_pci_ops,
1226 };
1227
1228 static const struct pci_device_id pci_ids[] = {
1229 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1230 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1231 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1232 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1233 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1234 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1235 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1236 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1237 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1238 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1239 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1240 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1241 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1242 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1243 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1244 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1245 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1246 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1247 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1248 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1249 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1250 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1251 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1252 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1253 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1254 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1255 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1256 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1257 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1258 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1259 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1260 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1261 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1262 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1263 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1264 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1265 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1266 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1267 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1268 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1269 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1270 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1271 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1272 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1273 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1274 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1275 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1276 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1277 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1278 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1279 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1280 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1281 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1282 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1283 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1284 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1285 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1286 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1287 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1288 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1289 SDHCI_PCI_DEVICE(O2, 8120, o2),
1290 SDHCI_PCI_DEVICE(O2, 8220, o2),
1291 SDHCI_PCI_DEVICE(O2, 8221, o2),
1292 SDHCI_PCI_DEVICE(O2, 8320, o2),
1293 SDHCI_PCI_DEVICE(O2, 8321, o2),
1294 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1295 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1296 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1297 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1298 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1299 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1300 /* Generic SD host controller */
1301 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1302 { /* end: all zeroes */ },
1303 };
1304
1305 MODULE_DEVICE_TABLE(pci, pci_ids);
1306
1307 /*****************************************************************************\
1308 * *
1309 * SDHCI core callbacks *
1310 * *
1311 \*****************************************************************************/
1312
1313 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1314 {
1315 struct sdhci_pci_slot *slot;
1316 struct pci_dev *pdev;
1317
1318 slot = sdhci_priv(host);
1319 pdev = slot->chip->pdev;
1320
1321 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1322 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1323 (host->flags & SDHCI_USE_SDMA)) {
1324 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1325 "doesn't fully claim to support it.\n");
1326 }
1327
1328 pci_set_master(pdev);
1329
1330 return 0;
1331 }
1332
1333 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1334 {
1335 u8 ctrl;
1336
1337 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1338
1339 switch (width) {
1340 case MMC_BUS_WIDTH_8:
1341 ctrl |= SDHCI_CTRL_8BITBUS;
1342 ctrl &= ~SDHCI_CTRL_4BITBUS;
1343 break;
1344 case MMC_BUS_WIDTH_4:
1345 ctrl |= SDHCI_CTRL_4BITBUS;
1346 ctrl &= ~SDHCI_CTRL_8BITBUS;
1347 break;
1348 default:
1349 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1350 break;
1351 }
1352
1353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1354 }
1355
1356 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1357 {
1358 struct sdhci_pci_slot *slot = sdhci_priv(host);
1359 int rst_n_gpio = slot->rst_n_gpio;
1360
1361 if (!gpio_is_valid(rst_n_gpio))
1362 return;
1363 gpio_set_value_cansleep(rst_n_gpio, 0);
1364 /* For eMMC, minimum is 1us but give it 10us for good measure */
1365 udelay(10);
1366 gpio_set_value_cansleep(rst_n_gpio, 1);
1367 /* For eMMC, minimum is 200us but give it 300us for good measure */
1368 usleep_range(300, 1000);
1369 }
1370
1371 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1372 {
1373 struct sdhci_pci_slot *slot = sdhci_priv(host);
1374
1375 if (slot->hw_reset)
1376 slot->hw_reset(host);
1377 }
1378
1379 static const struct sdhci_ops sdhci_pci_ops = {
1380 .set_clock = sdhci_set_clock,
1381 .enable_dma = sdhci_pci_enable_dma,
1382 .set_bus_width = sdhci_pci_set_bus_width,
1383 .reset = sdhci_reset,
1384 .set_uhs_signaling = sdhci_set_uhs_signaling,
1385 .hw_reset = sdhci_pci_hw_reset,
1386 };
1387
1388 /*****************************************************************************\
1389 * *
1390 * Suspend/resume *
1391 * *
1392 \*****************************************************************************/
1393
1394 #ifdef CONFIG_PM_SLEEP
1395 static int sdhci_pci_suspend(struct device *dev)
1396 {
1397 struct pci_dev *pdev = to_pci_dev(dev);
1398 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1399
1400 if (!chip)
1401 return 0;
1402
1403 if (chip->fixes && chip->fixes->suspend)
1404 return chip->fixes->suspend(chip);
1405
1406 return sdhci_pci_suspend_host(chip);
1407 }
1408
1409 static int sdhci_pci_resume(struct device *dev)
1410 {
1411 struct pci_dev *pdev = to_pci_dev(dev);
1412 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1413
1414 if (!chip)
1415 return 0;
1416
1417 if (chip->fixes && chip->fixes->resume)
1418 return chip->fixes->resume(chip);
1419
1420 return sdhci_pci_resume_host(chip);
1421 }
1422 #endif
1423
1424 #ifdef CONFIG_PM
1425 static int sdhci_pci_runtime_suspend(struct device *dev)
1426 {
1427 struct pci_dev *pdev = to_pci_dev(dev);
1428 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1429
1430 if (!chip)
1431 return 0;
1432
1433 if (chip->fixes && chip->fixes->runtime_suspend)
1434 return chip->fixes->runtime_suspend(chip);
1435
1436 return sdhci_pci_runtime_suspend_host(chip);
1437 }
1438
1439 static int sdhci_pci_runtime_resume(struct device *dev)
1440 {
1441 struct pci_dev *pdev = to_pci_dev(dev);
1442 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1443
1444 if (!chip)
1445 return 0;
1446
1447 if (chip->fixes && chip->fixes->runtime_resume)
1448 return chip->fixes->runtime_resume(chip);
1449
1450 return sdhci_pci_runtime_resume_host(chip);
1451 }
1452 #endif
1453
1454 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1455 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1456 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1457 sdhci_pci_runtime_resume, NULL)
1458 };
1459
1460 /*****************************************************************************\
1461 * *
1462 * Device probing/removal *
1463 * *
1464 \*****************************************************************************/
1465
1466 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1467 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1468 int slotno)
1469 {
1470 struct sdhci_pci_slot *slot;
1471 struct sdhci_host *host;
1472 int ret, bar = first_bar + slotno;
1473 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1474
1475 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1476 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1477 return ERR_PTR(-ENODEV);
1478 }
1479
1480 if (pci_resource_len(pdev, bar) < 0x100) {
1481 dev_err(&pdev->dev, "Invalid iomem size. You may "
1482 "experience problems.\n");
1483 }
1484
1485 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1486 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1487 return ERR_PTR(-ENODEV);
1488 }
1489
1490 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1491 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1492 return ERR_PTR(-ENODEV);
1493 }
1494
1495 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1496 if (IS_ERR(host)) {
1497 dev_err(&pdev->dev, "cannot allocate host\n");
1498 return ERR_CAST(host);
1499 }
1500
1501 slot = sdhci_priv(host);
1502
1503 slot->chip = chip;
1504 slot->host = host;
1505 slot->rst_n_gpio = -EINVAL;
1506 slot->cd_gpio = -EINVAL;
1507 slot->cd_idx = -1;
1508
1509 /* Retrieve platform data if there is any */
1510 if (*sdhci_pci_get_data)
1511 slot->data = sdhci_pci_get_data(pdev, slotno);
1512
1513 if (slot->data) {
1514 if (slot->data->setup) {
1515 ret = slot->data->setup(slot->data);
1516 if (ret) {
1517 dev_err(&pdev->dev, "platform setup failed\n");
1518 goto free;
1519 }
1520 }
1521 slot->rst_n_gpio = slot->data->rst_n_gpio;
1522 slot->cd_gpio = slot->data->cd_gpio;
1523 }
1524
1525 host->hw_name = "PCI";
1526 host->ops = chip->fixes && chip->fixes->ops ?
1527 chip->fixes->ops :
1528 &sdhci_pci_ops;
1529 host->quirks = chip->quirks;
1530 host->quirks2 = chip->quirks2;
1531
1532 host->irq = pdev->irq;
1533
1534 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1535 if (ret) {
1536 dev_err(&pdev->dev, "cannot request region\n");
1537 goto cleanup;
1538 }
1539
1540 host->ioaddr = pcim_iomap_table(pdev)[bar];
1541
1542 if (chip->fixes && chip->fixes->probe_slot) {
1543 ret = chip->fixes->probe_slot(slot);
1544 if (ret)
1545 goto cleanup;
1546 }
1547
1548 if (gpio_is_valid(slot->rst_n_gpio)) {
1549 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1550 gpio_direction_output(slot->rst_n_gpio, 1);
1551 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1552 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1553 } else {
1554 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1555 slot->rst_n_gpio = -EINVAL;
1556 }
1557 }
1558
1559 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1560 host->mmc->slotno = slotno;
1561 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1562
1563 if (slot->cd_idx >= 0) {
1564 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1565 slot->cd_override_level, 0, NULL);
1566 if (ret == -EPROBE_DEFER)
1567 goto remove;
1568
1569 if (ret) {
1570 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1571 slot->cd_idx = -1;
1572 }
1573 }
1574
1575 if (chip->fixes && chip->fixes->add_host)
1576 ret = chip->fixes->add_host(slot);
1577 else
1578 ret = sdhci_add_host(host);
1579 if (ret)
1580 goto remove;
1581
1582 sdhci_pci_add_own_cd(slot);
1583
1584 /*
1585 * Check if the chip needs a separate GPIO for card detect to wake up
1586 * from runtime suspend. If it is not there, don't allow runtime PM.
1587 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1588 */
1589 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1590 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1591 chip->allow_runtime_pm = false;
1592
1593 return slot;
1594
1595 remove:
1596 if (chip->fixes && chip->fixes->remove_slot)
1597 chip->fixes->remove_slot(slot, 0);
1598
1599 cleanup:
1600 if (slot->data && slot->data->cleanup)
1601 slot->data->cleanup(slot->data);
1602
1603 free:
1604 sdhci_free_host(host);
1605
1606 return ERR_PTR(ret);
1607 }
1608
1609 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1610 {
1611 int dead;
1612 u32 scratch;
1613
1614 sdhci_pci_remove_own_cd(slot);
1615
1616 dead = 0;
1617 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1618 if (scratch == (u32)-1)
1619 dead = 1;
1620
1621 sdhci_remove_host(slot->host, dead);
1622
1623 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1624 slot->chip->fixes->remove_slot(slot, dead);
1625
1626 if (slot->data && slot->data->cleanup)
1627 slot->data->cleanup(slot->data);
1628
1629 sdhci_free_host(slot->host);
1630 }
1631
1632 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1633 {
1634 pm_suspend_ignore_children(dev, 1);
1635 pm_runtime_set_autosuspend_delay(dev, 50);
1636 pm_runtime_use_autosuspend(dev);
1637 pm_runtime_allow(dev);
1638 /* Stay active until mmc core scans for a card */
1639 pm_runtime_put_noidle(dev);
1640 }
1641
1642 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1643 {
1644 pm_runtime_forbid(dev);
1645 pm_runtime_get_noresume(dev);
1646 }
1647
1648 static int sdhci_pci_probe(struct pci_dev *pdev,
1649 const struct pci_device_id *ent)
1650 {
1651 struct sdhci_pci_chip *chip;
1652 struct sdhci_pci_slot *slot;
1653
1654 u8 slots, first_bar;
1655 int ret, i;
1656
1657 BUG_ON(pdev == NULL);
1658 BUG_ON(ent == NULL);
1659
1660 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1661 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1662
1663 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1664 if (ret)
1665 return ret;
1666
1667 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1668 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1669 if (slots == 0)
1670 return -ENODEV;
1671
1672 BUG_ON(slots > MAX_SLOTS);
1673
1674 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1675 if (ret)
1676 return ret;
1677
1678 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1679
1680 if (first_bar > 5) {
1681 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1682 return -ENODEV;
1683 }
1684
1685 ret = pcim_enable_device(pdev);
1686 if (ret)
1687 return ret;
1688
1689 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1690 if (!chip)
1691 return -ENOMEM;
1692
1693 chip->pdev = pdev;
1694 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1695 if (chip->fixes) {
1696 chip->quirks = chip->fixes->quirks;
1697 chip->quirks2 = chip->fixes->quirks2;
1698 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1699 }
1700 chip->num_slots = slots;
1701 chip->pm_retune = true;
1702 chip->rpm_retune = true;
1703
1704 pci_set_drvdata(pdev, chip);
1705
1706 if (chip->fixes && chip->fixes->probe) {
1707 ret = chip->fixes->probe(chip);
1708 if (ret)
1709 return ret;
1710 }
1711
1712 slots = chip->num_slots; /* Quirk may have changed this */
1713
1714 for (i = 0; i < slots; i++) {
1715 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1716 if (IS_ERR(slot)) {
1717 for (i--; i >= 0; i--)
1718 sdhci_pci_remove_slot(chip->slots[i]);
1719 return PTR_ERR(slot);
1720 }
1721
1722 chip->slots[i] = slot;
1723 }
1724
1725 if (chip->allow_runtime_pm)
1726 sdhci_pci_runtime_pm_allow(&pdev->dev);
1727
1728 return 0;
1729 }
1730
1731 static void sdhci_pci_remove(struct pci_dev *pdev)
1732 {
1733 int i;
1734 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1735
1736 if (chip->allow_runtime_pm)
1737 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1738
1739 for (i = 0; i < chip->num_slots; i++)
1740 sdhci_pci_remove_slot(chip->slots[i]);
1741 }
1742
1743 static struct pci_driver sdhci_driver = {
1744 .name = "sdhci-pci",
1745 .id_table = pci_ids,
1746 .probe = sdhci_pci_probe,
1747 .remove = sdhci_pci_remove,
1748 .driver = {
1749 .pm = &sdhci_pci_pm_ops
1750 },
1751 };
1752
1753 module_pci_driver(sdhci_driver);
1754
1755 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1756 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1757 MODULE_LICENSE("GPL");
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