1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform_data/mmc-sdhci-s3c.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
25 #include <linux/of_gpio.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/mmc/host.h>
31 #include "sdhci-s3c-regs.h"
34 #define MAX_BUS_CLK (4)
37 * struct sdhci_s3c - S3C SDHCI instance
38 * @host: The SDHCI host created
39 * @pdev: The platform device we where created from.
40 * @ioarea: The resource created when we claimed the IO area.
41 * @pdata: The platform data for this controller.
42 * @cur_clk: The index of the current bus clock.
43 * @clk_io: The clock for the internal bus interface.
44 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
47 struct sdhci_host
*host
;
48 struct platform_device
*pdev
;
49 struct resource
*ioarea
;
50 struct s3c_sdhci_platdata
*pdata
;
56 struct clk
*clk_bus
[MAX_BUS_CLK
];
57 unsigned long clk_rates
[MAX_BUS_CLK
];
61 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
62 * @sdhci_quirks: sdhci host specific quirks.
64 * Specifies platform specific configuration of sdhci controller.
65 * Note: A structure for driver specific platform data is used for future
66 * expansion of its usage.
68 struct sdhci_s3c_drv_data
{
69 unsigned int sdhci_quirks
;
72 static inline struct sdhci_s3c
*to_s3c(struct sdhci_host
*host
)
74 return sdhci_priv(host
);
78 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
79 * @host: The SDHCI host instance.
81 * Callback to return the maximum clock rate acheivable by the controller.
83 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host
*host
)
85 struct sdhci_s3c
*ourhost
= to_s3c(host
);
86 unsigned long rate
, max
= 0;
89 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
90 rate
= ourhost
->clk_rates
[src
];
99 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
100 * @ourhost: Our SDHCI instance.
101 * @src: The source clock index.
102 * @wanted: The clock frequency wanted.
104 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c
*ourhost
,
109 struct clk
*clksrc
= ourhost
->clk_bus
[src
];
116 * If controller uses a non-standard clock division, find the best clock
117 * speed possible with selected clock source and skip the division.
119 if (ourhost
->host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
) {
120 rate
= clk_round_rate(clksrc
, wanted
);
121 return wanted
- rate
;
124 rate
= ourhost
->clk_rates
[src
];
126 for (shift
= 0; shift
<= 8; ++shift
) {
127 if ((rate
>> shift
) <= wanted
)
132 dev_dbg(&ourhost
->pdev
->dev
,
133 "clk %d: rate %ld, min rate %lu > wanted %u\n",
134 src
, rate
, rate
/ 256, wanted
);
138 dev_dbg(&ourhost
->pdev
->dev
, "clk %d: rate %ld, want %d, got %ld\n",
139 src
, rate
, wanted
, rate
>> shift
);
141 return wanted
- (rate
>> shift
);
145 * sdhci_s3c_set_clock - callback on clock change
146 * @host: The SDHCI host being changed
147 * @clock: The clock rate being requested.
149 * When the card's clock is going to be changed, look at the new frequency
150 * and find the best clock source to go with it.
152 static void sdhci_s3c_set_clock(struct sdhci_host
*host
, unsigned int clock
)
154 struct sdhci_s3c
*ourhost
= to_s3c(host
);
155 unsigned int best
= UINT_MAX
;
161 /* don't bother if the clock is going off. */
165 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
166 delta
= sdhci_s3c_consider_clock(ourhost
, src
, clock
);
173 dev_dbg(&ourhost
->pdev
->dev
,
174 "selected source %d, clock %d, delta %d\n",
175 best_src
, clock
, best
);
177 /* select the new clock source */
178 if (ourhost
->cur_clk
!= best_src
) {
179 struct clk
*clk
= ourhost
->clk_bus
[best_src
];
181 clk_prepare_enable(clk
);
182 if (ourhost
->cur_clk
>= 0)
183 clk_disable_unprepare(
184 ourhost
->clk_bus
[ourhost
->cur_clk
]);
186 ourhost
->cur_clk
= best_src
;
187 host
->max_clk
= ourhost
->clk_rates
[best_src
];
190 /* turn clock off to card before changing clock source */
191 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
193 ctrl
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
194 ctrl
&= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
195 ctrl
|= best_src
<< S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
196 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
198 /* reprogram default hardware configuration */
199 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA
,
200 host
->ioaddr
+ S3C64XX_SDHCI_CONTROL4
);
202 ctrl
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
203 ctrl
|= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR
|
204 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK
|
205 S3C_SDHCI_CTRL2_ENFBCLKRX
|
206 S3C_SDHCI_CTRL2_DFCNT_NONE
|
207 S3C_SDHCI_CTRL2_ENCLKOUTHOLD
);
208 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
210 /* reconfigure the controller for new clock rate */
211 ctrl
= (S3C_SDHCI_CTRL3_FCSEL1
| S3C_SDHCI_CTRL3_FCSEL0
);
212 if (clock
< 25 * 1000000)
213 ctrl
|= (S3C_SDHCI_CTRL3_FCSEL3
| S3C_SDHCI_CTRL3_FCSEL2
);
214 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL3
);
218 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
219 * @host: The SDHCI host being queried
221 * To init mmc host properly a minimal clock value is needed. For high system
222 * bus clock's values the standard formula gives values out of allowed range.
223 * The clock still can be set to lower values, if clock source other then
224 * system bus is selected.
226 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host
*host
)
228 struct sdhci_s3c
*ourhost
= to_s3c(host
);
229 unsigned long rate
, min
= ULONG_MAX
;
232 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
233 rate
= ourhost
->clk_rates
[src
] / 256;
243 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
244 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host
*host
)
246 struct sdhci_s3c
*ourhost
= to_s3c(host
);
247 unsigned long rate
, max
= 0;
250 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
253 clk
= ourhost
->clk_bus
[src
];
257 rate
= clk_round_rate(clk
, ULONG_MAX
);
265 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
266 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host
*host
)
268 struct sdhci_s3c
*ourhost
= to_s3c(host
);
269 unsigned long rate
, min
= ULONG_MAX
;
272 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
275 clk
= ourhost
->clk_bus
[src
];
279 rate
= clk_round_rate(clk
, 0);
287 /* sdhci_cmu_set_clock - callback on clock change.*/
288 static void sdhci_cmu_set_clock(struct sdhci_host
*host
, unsigned int clock
)
290 struct sdhci_s3c
*ourhost
= to_s3c(host
);
291 struct device
*dev
= &ourhost
->pdev
->dev
;
292 unsigned long timeout
;
295 /* If the clock is going off, set to 0 at clock control register */
297 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
301 sdhci_s3c_set_clock(host
, clock
);
303 clk_set_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], clock
);
305 clk
= SDHCI_CLOCK_INT_EN
;
306 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
310 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
311 & SDHCI_CLOCK_INT_STABLE
)) {
313 dev_err(dev
, "%s: Internal clock never stabilised.\n",
314 mmc_hostname(host
->mmc
));
321 clk
|= SDHCI_CLOCK_CARD_EN
;
322 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
326 * sdhci_s3c_set_bus_width - support 8bit buswidth
327 * @host: The SDHCI host being queried
328 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
330 * We have 8-bit width support but is not a v3 controller.
331 * So we add platform_bus_width() and support 8bit width.
333 static void sdhci_s3c_set_bus_width(struct sdhci_host
*host
, int width
)
337 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
340 case MMC_BUS_WIDTH_8
:
341 ctrl
|= SDHCI_CTRL_8BITBUS
;
342 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
344 case MMC_BUS_WIDTH_4
:
345 ctrl
|= SDHCI_CTRL_4BITBUS
;
346 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
349 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
350 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
354 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
357 static struct sdhci_ops sdhci_s3c_ops
= {
358 .get_max_clock
= sdhci_s3c_get_max_clk
,
359 .set_clock
= sdhci_s3c_set_clock
,
360 .get_min_clock
= sdhci_s3c_get_min_clock
,
361 .set_bus_width
= sdhci_s3c_set_bus_width
,
362 .reset
= sdhci_reset
,
365 static void sdhci_s3c_notify_change(struct platform_device
*dev
, int state
)
367 struct sdhci_host
*host
= platform_get_drvdata(dev
);
368 #ifdef CONFIG_PM_RUNTIME
369 struct sdhci_s3c
*sc
= sdhci_priv(host
);
374 spin_lock_irqsave(&host
->lock
, flags
);
376 dev_dbg(&dev
->dev
, "card inserted.\n");
377 #ifdef CONFIG_PM_RUNTIME
378 clk_prepare_enable(sc
->clk_io
);
380 host
->flags
&= ~SDHCI_DEVICE_DEAD
;
381 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
383 dev_dbg(&dev
->dev
, "card removed.\n");
384 host
->flags
|= SDHCI_DEVICE_DEAD
;
385 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
386 #ifdef CONFIG_PM_RUNTIME
387 clk_disable_unprepare(sc
->clk_io
);
390 tasklet_schedule(&host
->card_tasklet
);
391 spin_unlock_irqrestore(&host
->lock
, flags
);
395 static irqreturn_t
sdhci_s3c_gpio_card_detect_thread(int irq
, void *dev_id
)
397 struct sdhci_s3c
*sc
= dev_id
;
398 int status
= gpio_get_value(sc
->ext_cd_gpio
);
399 if (sc
->pdata
->ext_cd_gpio_invert
)
401 sdhci_s3c_notify_change(sc
->pdev
, status
);
405 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c
*sc
)
407 struct s3c_sdhci_platdata
*pdata
= sc
->pdata
;
408 struct device
*dev
= &sc
->pdev
->dev
;
410 if (devm_gpio_request(dev
, pdata
->ext_cd_gpio
, "SDHCI EXT CD") == 0) {
411 sc
->ext_cd_gpio
= pdata
->ext_cd_gpio
;
412 sc
->ext_cd_irq
= gpio_to_irq(pdata
->ext_cd_gpio
);
413 if (sc
->ext_cd_irq
&&
414 request_threaded_irq(sc
->ext_cd_irq
, NULL
,
415 sdhci_s3c_gpio_card_detect_thread
,
416 IRQF_TRIGGER_RISING
|
417 IRQF_TRIGGER_FALLING
|
419 dev_name(dev
), sc
) == 0) {
420 int status
= gpio_get_value(sc
->ext_cd_gpio
);
421 if (pdata
->ext_cd_gpio_invert
)
423 sdhci_s3c_notify_change(sc
->pdev
, status
);
425 dev_warn(dev
, "cannot request irq for card detect\n");
429 dev_err(dev
, "cannot request gpio for card detect\n");
434 static int sdhci_s3c_parse_dt(struct device
*dev
,
435 struct sdhci_host
*host
, struct s3c_sdhci_platdata
*pdata
)
437 struct device_node
*node
= dev
->of_node
;
438 struct sdhci_s3c
*ourhost
= to_s3c(host
);
442 /* if the bus-width property is not specified, assume width as 1 */
443 if (of_property_read_u32(node
, "bus-width", &max_width
))
445 pdata
->max_width
= max_width
;
447 /* get the card detection method */
448 if (of_get_property(node
, "broken-cd", NULL
)) {
449 pdata
->cd_type
= S3C_SDHCI_CD_NONE
;
453 if (of_get_property(node
, "non-removable", NULL
)) {
454 pdata
->cd_type
= S3C_SDHCI_CD_PERMANENT
;
458 gpio
= of_get_named_gpio(node
, "cd-gpios", 0);
459 if (gpio_is_valid(gpio
)) {
460 pdata
->cd_type
= S3C_SDHCI_CD_GPIO
;
461 pdata
->ext_cd_gpio
= gpio
;
462 ourhost
->ext_cd_gpio
= -1;
463 if (of_get_property(node
, "cd-inverted", NULL
))
464 pdata
->ext_cd_gpio_invert
= 1;
466 } else if (gpio
!= -ENOENT
) {
467 dev_err(dev
, "invalid card detect gpio specified\n");
471 /* assuming internal card detect that will be configured by pinctrl */
472 pdata
->cd_type
= S3C_SDHCI_CD_INTERNAL
;
476 static int sdhci_s3c_parse_dt(struct device
*dev
,
477 struct sdhci_host
*host
, struct s3c_sdhci_platdata
*pdata
)
483 static const struct of_device_id sdhci_s3c_dt_match
[];
485 static inline struct sdhci_s3c_drv_data
*sdhci_s3c_get_driver_data(
486 struct platform_device
*pdev
)
489 if (pdev
->dev
.of_node
) {
490 const struct of_device_id
*match
;
491 match
= of_match_node(sdhci_s3c_dt_match
, pdev
->dev
.of_node
);
492 return (struct sdhci_s3c_drv_data
*)match
->data
;
495 return (struct sdhci_s3c_drv_data
*)
496 platform_get_device_id(pdev
)->driver_data
;
499 static int sdhci_s3c_probe(struct platform_device
*pdev
)
501 struct s3c_sdhci_platdata
*pdata
;
502 struct sdhci_s3c_drv_data
*drv_data
;
503 struct device
*dev
= &pdev
->dev
;
504 struct sdhci_host
*host
;
505 struct sdhci_s3c
*sc
;
506 struct resource
*res
;
507 int ret
, irq
, ptr
, clks
;
509 if (!pdev
->dev
.platform_data
&& !pdev
->dev
.of_node
) {
510 dev_err(dev
, "no device data specified\n");
514 irq
= platform_get_irq(pdev
, 0);
516 dev_err(dev
, "no irq specified\n");
520 host
= sdhci_alloc_host(dev
, sizeof(struct sdhci_s3c
));
522 dev_err(dev
, "sdhci_alloc_host() failed\n");
523 return PTR_ERR(host
);
525 sc
= sdhci_priv(host
);
527 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
530 goto err_pdata_io_clk
;
533 if (pdev
->dev
.of_node
) {
534 ret
= sdhci_s3c_parse_dt(&pdev
->dev
, host
, pdata
);
536 goto err_pdata_io_clk
;
538 memcpy(pdata
, pdev
->dev
.platform_data
, sizeof(*pdata
));
539 sc
->ext_cd_gpio
= -1; /* invalid gpio number */
542 drv_data
= sdhci_s3c_get_driver_data(pdev
);
549 platform_set_drvdata(pdev
, host
);
551 sc
->clk_io
= devm_clk_get(dev
, "hsmmc");
552 if (IS_ERR(sc
->clk_io
)) {
553 dev_err(dev
, "failed to get io clock\n");
554 ret
= PTR_ERR(sc
->clk_io
);
555 goto err_pdata_io_clk
;
558 /* enable the local io clock and keep it running for the moment. */
559 clk_prepare_enable(sc
->clk_io
);
561 for (clks
= 0, ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
564 snprintf(name
, 14, "mmc_busclk.%d", ptr
);
565 sc
->clk_bus
[ptr
] = devm_clk_get(dev
, name
);
566 if (IS_ERR(sc
->clk_bus
[ptr
]))
570 sc
->clk_rates
[ptr
] = clk_get_rate(sc
->clk_bus
[ptr
]);
572 dev_info(dev
, "clock source %d: %s (%ld Hz)\n",
573 ptr
, name
, sc
->clk_rates
[ptr
]);
577 dev_err(dev
, "failed to find any bus clocks\n");
582 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
583 host
->ioaddr
= devm_ioremap_resource(&pdev
->dev
, res
);
584 if (IS_ERR(host
->ioaddr
)) {
585 ret
= PTR_ERR(host
->ioaddr
);
589 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
591 pdata
->cfg_gpio(pdev
, pdata
->max_width
);
593 host
->hw_name
= "samsung-hsmmc";
594 host
->ops
= &sdhci_s3c_ops
;
599 /* Setup quirks for the controller */
600 host
->quirks
|= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
;
601 host
->quirks
|= SDHCI_QUIRK_NO_HISPD_BIT
;
603 host
->quirks
|= drv_data
->sdhci_quirks
;
605 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
607 /* we currently see overruns on errors, so disable the SDMA
608 * support as well. */
609 host
->quirks
|= SDHCI_QUIRK_BROKEN_DMA
;
611 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
613 /* It seems we do not get an DATA transfer complete on non-busy
614 * transfers, not sure if this is a problem with this specific
615 * SDHCI block, or a missing configuration that needs to be set. */
616 host
->quirks
|= SDHCI_QUIRK_NO_BUSY_IRQ
;
618 /* This host supports the Auto CMD12 */
619 host
->quirks
|= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
;
621 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
622 host
->quirks
|= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
;
624 if (pdata
->cd_type
== S3C_SDHCI_CD_NONE
||
625 pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
626 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
628 if (pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
629 host
->mmc
->caps
= MMC_CAP_NONREMOVABLE
;
631 switch (pdata
->max_width
) {
633 host
->mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
635 host
->mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
640 host
->mmc
->pm_caps
|= pdata
->pm_caps
;
642 host
->quirks
|= (SDHCI_QUIRK_32BIT_DMA_ADDR
|
643 SDHCI_QUIRK_32BIT_DMA_SIZE
);
645 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
646 host
->quirks
|= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
;
649 * If controller does not have internal clock divider,
650 * we can use overriding functions instead of default.
652 if (host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
) {
653 sdhci_s3c_ops
.set_clock
= sdhci_cmu_set_clock
;
654 sdhci_s3c_ops
.get_min_clock
= sdhci_cmu_get_min_clock
;
655 sdhci_s3c_ops
.get_max_clock
= sdhci_cmu_get_max_clock
;
658 /* It supports additional host capabilities if needed */
659 if (pdata
->host_caps
)
660 host
->mmc
->caps
|= pdata
->host_caps
;
662 if (pdata
->host_caps2
)
663 host
->mmc
->caps2
|= pdata
->host_caps2
;
665 pm_runtime_enable(&pdev
->dev
);
666 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
667 pm_runtime_use_autosuspend(&pdev
->dev
);
668 pm_suspend_ignore_children(&pdev
->dev
, 1);
670 ret
= sdhci_add_host(host
);
672 dev_err(dev
, "sdhci_add_host() failed\n");
673 pm_runtime_forbid(&pdev
->dev
);
674 pm_runtime_get_noresume(&pdev
->dev
);
678 /* The following two methods of card detection might call
679 sdhci_s3c_notify_change() immediately, so they can be called
680 only after sdhci_add_host(). Setup errors are ignored. */
681 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_init
)
682 pdata
->ext_cd_init(&sdhci_s3c_notify_change
);
683 if (pdata
->cd_type
== S3C_SDHCI_CD_GPIO
&&
684 gpio_is_valid(pdata
->ext_cd_gpio
))
685 sdhci_s3c_setup_card_detect_gpio(sc
);
687 #ifdef CONFIG_PM_RUNTIME
688 if (pdata
->cd_type
!= S3C_SDHCI_CD_INTERNAL
)
689 clk_disable_unprepare(sc
->clk_io
);
695 clk_disable_unprepare(sc
->clk_io
);
698 sdhci_free_host(host
);
703 static int sdhci_s3c_remove(struct platform_device
*pdev
)
705 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
706 struct sdhci_s3c
*sc
= sdhci_priv(host
);
707 struct s3c_sdhci_platdata
*pdata
= sc
->pdata
;
709 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_cleanup
)
710 pdata
->ext_cd_cleanup(&sdhci_s3c_notify_change
);
713 free_irq(sc
->ext_cd_irq
, sc
);
715 #ifdef CONFIG_PM_RUNTIME
716 if (pdata
->cd_type
!= S3C_SDHCI_CD_INTERNAL
)
717 clk_prepare_enable(sc
->clk_io
);
719 sdhci_remove_host(host
, 1);
721 pm_runtime_dont_use_autosuspend(&pdev
->dev
);
722 pm_runtime_disable(&pdev
->dev
);
724 clk_disable_unprepare(sc
->clk_io
);
726 sdhci_free_host(host
);
731 #ifdef CONFIG_PM_SLEEP
732 static int sdhci_s3c_suspend(struct device
*dev
)
734 struct sdhci_host
*host
= dev_get_drvdata(dev
);
736 return sdhci_suspend_host(host
);
739 static int sdhci_s3c_resume(struct device
*dev
)
741 struct sdhci_host
*host
= dev_get_drvdata(dev
);
743 return sdhci_resume_host(host
);
747 #ifdef CONFIG_PM_RUNTIME
748 static int sdhci_s3c_runtime_suspend(struct device
*dev
)
750 struct sdhci_host
*host
= dev_get_drvdata(dev
);
751 struct sdhci_s3c
*ourhost
= to_s3c(host
);
752 struct clk
*busclk
= ourhost
->clk_io
;
755 ret
= sdhci_runtime_suspend_host(host
);
757 if (ourhost
->cur_clk
>= 0)
758 clk_disable_unprepare(ourhost
->clk_bus
[ourhost
->cur_clk
]);
759 clk_disable_unprepare(busclk
);
763 static int sdhci_s3c_runtime_resume(struct device
*dev
)
765 struct sdhci_host
*host
= dev_get_drvdata(dev
);
766 struct sdhci_s3c
*ourhost
= to_s3c(host
);
767 struct clk
*busclk
= ourhost
->clk_io
;
770 clk_prepare_enable(busclk
);
771 if (ourhost
->cur_clk
>= 0)
772 clk_prepare_enable(ourhost
->clk_bus
[ourhost
->cur_clk
]);
773 ret
= sdhci_runtime_resume_host(host
);
779 static const struct dev_pm_ops sdhci_s3c_pmops
= {
780 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend
, sdhci_s3c_resume
)
781 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend
, sdhci_s3c_runtime_resume
,
785 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
788 #define SDHCI_S3C_PMOPS NULL
791 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
792 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data
= {
793 .sdhci_quirks
= SDHCI_QUIRK_NONSTANDARD_CLOCK
,
795 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
797 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
800 static struct platform_device_id sdhci_s3c_driver_ids
[] = {
803 .driver_data
= (kernel_ulong_t
)NULL
,
805 .name
= "exynos4-sdhci",
806 .driver_data
= EXYNOS4_SDHCI_DRV_DATA
,
810 MODULE_DEVICE_TABLE(platform
, sdhci_s3c_driver_ids
);
813 static const struct of_device_id sdhci_s3c_dt_match
[] = {
814 { .compatible
= "samsung,s3c6410-sdhci", },
815 { .compatible
= "samsung,exynos4210-sdhci",
816 .data
= (void *)EXYNOS4_SDHCI_DRV_DATA
},
819 MODULE_DEVICE_TABLE(of
, sdhci_s3c_dt_match
);
822 static struct platform_driver sdhci_s3c_driver
= {
823 .probe
= sdhci_s3c_probe
,
824 .remove
= sdhci_s3c_remove
,
825 .id_table
= sdhci_s3c_driver_ids
,
827 .owner
= THIS_MODULE
,
829 .of_match_table
= of_match_ptr(sdhci_s3c_dt_match
),
830 .pm
= SDHCI_S3C_PMOPS
,
834 module_platform_driver(sdhci_s3c_driver
);
836 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
837 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
838 MODULE_LICENSE("GPL v2");
839 MODULE_ALIAS("platform:s3c-sdhci");