drivers/mmc/host/sdhci-tegra.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/reset.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/mmc.h>
  28 #include <linux/mmc/slot-gpio.h>
  29 #include <linux/gpio/consumer.h>
  30
  31 #include "sdhci-pltfm.h"
  32
  33 /* Tegra SDHOST controller vendor register definitions */
  34 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL                   0x100
  35 #define SDHCI_CLOCK_CTRL_TAP_MASK                       0x00ff0000
  36 #define SDHCI_CLOCK_CTRL_TAP_SHIFT                      16
  37 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE          BIT(5)
  38 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE         BIT(3)
  39 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE        BIT(2)
  40
  41 #define SDHCI_TEGRA_VENDOR_MISC_CTRL            0x120
  42 #define SDHCI_MISC_CTRL_ENABLE_SDR104           0x8
  43 #define SDHCI_MISC_CTRL_ENABLE_SDR50            0x10
  44 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300   0x20
  45 #define SDHCI_MISC_CTRL_ENABLE_DDR50            0x200
  46
  47 #define SDHCI_TEGRA_AUTO_CAL_CONFIG             0x1e4
  48 #define SDHCI_AUTO_CAL_START                    BIT(31)
  49 #define SDHCI_AUTO_CAL_ENABLE                   BIT(29)
  50
  51 #define NVQUIRK_FORCE_SDHCI_SPEC_200    BIT(0)
  52 #define NVQUIRK_ENABLE_BLOCK_GAP_DET    BIT(1)
  53 #define NVQUIRK_ENABLE_SDHCI_SPEC_300   BIT(2)
  54 #define NVQUIRK_ENABLE_SDR50            BIT(3)
  55 #define NVQUIRK_ENABLE_SDR104           BIT(4)
  56 #define NVQUIRK_ENABLE_DDR50            BIT(5)
  57 #define NVQUIRK_HAS_PADCALIB            BIT(6)
  58
  59 struct sdhci_tegra_soc_data {
  60         const struct sdhci_pltfm_data *pdata;
  61         u32 nvquirks;
  62 };
  63
  64 struct sdhci_tegra {
  65         const struct sdhci_tegra_soc_data *soc_data;
  66         struct gpio_desc *power_gpio;
  67         bool ddr_signaling;
  68         bool pad_calib_required;
  69
  70         struct reset_control *rst;
  71 };
  72
  73 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  74 {
  75         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  76         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  77         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  78
  79         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  80                         (reg == SDHCI_HOST_VERSION))) {
  81                 /* Erratum: Version register is invalid in HW. */
  82                 return SDHCI_SPEC_200;
  83         }
  84
  85         return readw(host->ioaddr + reg);
  86 }
  87
  88 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  89 {
  90         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  91
  92         switch (reg) {
  93         case SDHCI_TRANSFER_MODE:
  94                 /*
  95                  * Postpone this write, we must do it together with a
  96                  * command write that is down below.
  97                  */
  98                 pltfm_host->xfer_mode_shadow = val;
  99                 return;
 100         case SDHCI_COMMAND:
 101                 writel((val << 16) | pltfm_host->xfer_mode_shadow,
 102                         host->ioaddr + SDHCI_TRANSFER_MODE);
 103                 return;
 104         }
 105
 106         writew(val, host->ioaddr + reg);
 107 }
 108
 109 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 110 {
 111         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 112         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 113         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 114
 115         /* Seems like we're getting spurious timeout and crc errors, so
 116          * disable signalling of them. In case of real errors software
 117          * timers should take care of eventually detecting them.
 118          */
 119         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
 120                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
 121
 122         writel(val, host->ioaddr + reg);
 123
 124         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
 125                         (reg == SDHCI_INT_ENABLE))) {
 126                 /* Erratum: Must enable block gap interrupt detection */
 127                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 128                 if (val & SDHCI_INT_CARD_INT)
 129                         gap_ctrl |= 0x8;
 130                 else
 131                         gap_ctrl &= ~0x8;
 132                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 133         }
 134 }
 135
 136 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
 137 {
 138         return mmc_gpio_get_ro(host->mmc);
 139 }
 140
 141 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 142 {
 143         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 144         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 145         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 146         u32 misc_ctrl, clk_ctrl;
 147
 148         sdhci_reset(host, mask);
 149
 150         if (!(mask & SDHCI_RESET_ALL))
 151                 return;
 152
 153         misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 154         clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 155
 156         misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
 157                        SDHCI_MISC_CTRL_ENABLE_SDR50 |
 158                        SDHCI_MISC_CTRL_ENABLE_DDR50 |
 159                        SDHCI_MISC_CTRL_ENABLE_SDR104);
 160
 161         clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
 162
 163         /*
 164          * If the board does not define a regulator for the SDHCI
 165          * IO voltage, then don't advertise support for UHS modes
 166          * even if the device supports it because the IO voltage
 167          * cannot be configured.
 168          */
 169         if (!IS_ERR(host->mmc->supply.vqmmc)) {
 170                 /* Erratum: Enable SDHCI spec v3.00 support */
 171                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
 172                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
 173                 /* Advertise UHS modes as supported by host */
 174                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
 175                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
 176                 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
 177                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
 178                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
 179                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
 180                 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
 181                         clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
 182         }
 183
 184         sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 185         sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 186
 187         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
 188                 tegra_host->pad_calib_required = true;
 189
 190         tegra_host->ddr_signaling = false;
 191 }
 192
 193 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
 194 {
 195         u32 val;
 196
 197         mdelay(1);
 198
 199         val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 200         val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
 201         sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 202 }
 203
 204 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 205 {
 206         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 207         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 208         unsigned long host_clk;
 209
 210         if (!clock)
 211                 return sdhci_set_clock(host, clock);
 212
 213         host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
 214         clk_set_rate(pltfm_host->clk, host_clk);
 215         host->max_clk = clk_get_rate(pltfm_host->clk);
 216
 217         sdhci_set_clock(host, clock);
 218
 219         if (tegra_host->pad_calib_required) {
 220                 tegra_sdhci_pad_autocalib(host);
 221                 tegra_host->pad_calib_required = false;
 222         }
 223 }
 224
 225 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 226                                           unsigned timing)
 227 {
 228         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 229         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 230
 231         if (timing == MMC_TIMING_UHS_DDR50)
 232                 tegra_host->ddr_signaling = true;
 233
 234         return sdhci_set_uhs_signaling(host, timing);
 235 }
 236
 237 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
 238 {
 239         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 240
 241         /*
 242          * DDR modes require the host to run at double the card frequency, so
 243          * the maximum rate we can support is half of the module input clock.
 244          */
 245         return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
 246 }
 247
 248 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
 249 {
 250         u32 reg;
 251
 252         reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 253         reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
 254         reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
 255         sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 256 }
 257
 258 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
 259 {
 260         unsigned int min, max;
 261
 262         /*
 263          * Start search for minimum tap value at 10, as smaller values are
 264          * may wrongly be reported as working but fail at higher speeds,
 265          * according to the TRM.
 266          */
 267         min = 10;
 268         while (min < 255) {
 269                 tegra_sdhci_set_tap(host, min);
 270                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
 271                         break;
 272                 min++;
 273         }
 274
 275         /* Find the maximum tap value that still passes. */
 276         max = min + 1;
 277         while (max < 255) {
 278                 tegra_sdhci_set_tap(host, max);
 279                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 280                         max--;
 281                         break;
 282                 }
 283                 max++;
 284         }
 285
 286         /* The TRM states the ideal tap value is at 75% in the passing range. */
 287         tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
 288
 289         return mmc_send_tuning(host->mmc, opcode, NULL);
 290 }
 291
 292 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
 293 {
 294         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 295         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 296         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 297
 298         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
 299                 tegra_host->pad_calib_required = true;
 300 }
 301
 302 static const struct sdhci_ops tegra_sdhci_ops = {
 303         .get_ro     = tegra_sdhci_get_ro,
 304         .read_w     = tegra_sdhci_readw,
 305         .write_l    = tegra_sdhci_writel,
 306         .set_clock  = tegra_sdhci_set_clock,
 307         .set_bus_width = sdhci_set_bus_width,
 308         .reset      = tegra_sdhci_reset,
 309         .platform_execute_tuning = tegra_sdhci_execute_tuning,
 310         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
 311         .voltage_switch = tegra_sdhci_voltage_switch,
 312         .get_max_clock = tegra_sdhci_get_max_clock,
 313 };
 314
 315 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
 316         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 317                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 318                   SDHCI_QUIRK_NO_HISPD_BIT |
 319                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 320                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 321         .ops  = &tegra_sdhci_ops,
 322 };
 323
 324 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
 325         .pdata = &sdhci_tegra20_pdata,
 326         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
 327                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
 328 };
 329
 330 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
 331         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 332                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 333                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 334                   SDHCI_QUIRK_NO_HISPD_BIT |
 335                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 336                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 337         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 338         .ops  = &tegra_sdhci_ops,
 339 };
 340
 341 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
 342         .pdata = &sdhci_tegra30_pdata,
 343         .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
 344                     NVQUIRK_ENABLE_SDR50 |
 345                     NVQUIRK_ENABLE_SDR104 |
 346                     NVQUIRK_HAS_PADCALIB,
 347 };
 348
 349 static const struct sdhci_ops tegra114_sdhci_ops = {
 350         .get_ro     = tegra_sdhci_get_ro,
 351         .read_w     = tegra_sdhci_readw,
 352         .write_w    = tegra_sdhci_writew,
 353         .write_l    = tegra_sdhci_writel,
 354         .set_clock  = tegra_sdhci_set_clock,
 355         .set_bus_width = sdhci_set_bus_width,
 356         .reset      = tegra_sdhci_reset,
 357         .platform_execute_tuning = tegra_sdhci_execute_tuning,
 358         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
 359         .voltage_switch = tegra_sdhci_voltage_switch,
 360         .get_max_clock = tegra_sdhci_get_max_clock,
 361 };
 362
 363 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
 364         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 365                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 366                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 367                   SDHCI_QUIRK_NO_HISPD_BIT |
 368                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 369                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 370         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 371         .ops  = &tegra114_sdhci_ops,
 372 };
 373
 374 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
 375         .pdata = &sdhci_tegra114_pdata,
 376 };
 377
 378 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
 379         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 380                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 381                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 382                   SDHCI_QUIRK_NO_HISPD_BIT |
 383                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 384                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 385         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 386                    /*
 387                     * The TRM states that the SD/MMC controller found on
 388                     * Tegra124 can address 34 bits (the maximum supported by
 389                     * the Tegra memory controller), but tests show that DMA
 390                     * to or from above 4 GiB doesn't work. This is possibly
 391                     * caused by missing programming, though it's not obvious
 392                     * what sequence is required. Mark 64-bit DMA broken for
 393                     * now to fix this for existing users (e.g. Nyan boards).
 394                     */
 395                    SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
 396         .ops  = &tegra114_sdhci_ops,
 397 };
 398
 399 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
 400         .pdata = &sdhci_tegra124_pdata,
 401 };
 402
 403 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
 404         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 405                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 406                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 407                   SDHCI_QUIRK_NO_HISPD_BIT |
 408                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 409                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 410         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 411         .ops  = &tegra114_sdhci_ops,
 412 };
 413
 414 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
 415         .pdata = &sdhci_tegra210_pdata,
 416 };
 417
 418 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
 419         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 420                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 421                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 422                   SDHCI_QUIRK_NO_HISPD_BIT |
 423                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 424                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 425         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 426                    /* SDHCI controllers on Tegra186 support 40-bit addressing.
 427                     * IOVA addresses are 48-bit wide on Tegra186.
 428                     * With 64-bit dma mask used for SDHCI, accesses can
 429                     * be broken. Disable 64-bit dma, which would fall back
 430                     * to 32-bit dma mask. Ideally 40-bit dma mask would work,
 431                     * But it is not supported as of now.
 432                     */
 433                    SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
 434         .ops  = &tegra114_sdhci_ops,
 435 };
 436
 437 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
 438         .pdata = &sdhci_tegra186_pdata,
 439 };
 440
 441 static const struct of_device_id sdhci_tegra_dt_match[] = {
 442         { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
 443         { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
 444         { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
 445         { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
 446         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
 447         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
 448         {}
 449 };
 450 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
 451
 452 static int sdhci_tegra_probe(struct platform_device *pdev)
 453 {
 454         const struct of_device_id *match;
 455         const struct sdhci_tegra_soc_data *soc_data;
 456         struct sdhci_host *host;
 457         struct sdhci_pltfm_host *pltfm_host;
 458         struct sdhci_tegra *tegra_host;
 459         struct clk *clk;
 460         int rc;
 461
 462         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
 463         if (!match)
 464                 return -EINVAL;
 465         soc_data = match->data;
 466
 467         host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
 468         if (IS_ERR(host))
 469                 return PTR_ERR(host);
 470         pltfm_host = sdhci_priv(host);
 471
 472         tegra_host = sdhci_pltfm_priv(pltfm_host);
 473         tegra_host->ddr_signaling = false;
 474         tegra_host->pad_calib_required = false;
 475         tegra_host->soc_data = soc_data;
 476
 477         rc = mmc_of_parse(host->mmc);
 478         if (rc)
 479                 goto err_parse_dt;
 480
 481         if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
 482                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
 483
 484         tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
 485                                                          GPIOD_OUT_HIGH);
 486         if (IS_ERR(tegra_host->power_gpio)) {
 487                 rc = PTR_ERR(tegra_host->power_gpio);
 488                 goto err_power_req;
 489         }
 490
 491         clk = devm_clk_get(mmc_dev(host->mmc), NULL);
 492         if (IS_ERR(clk)) {
 493                 dev_err(mmc_dev(host->mmc), "clk err\n");
 494                 rc = PTR_ERR(clk);
 495                 goto err_clk_get;
 496         }
 497         clk_prepare_enable(clk);
 498         pltfm_host->clk = clk;
 499
 500         tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
 501                                                            "sdhci");
 502         if (IS_ERR(tegra_host->rst)) {
 503                 rc = PTR_ERR(tegra_host->rst);
 504                 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
 505                 goto err_rst_get;
 506         }
 507
 508         rc = reset_control_assert(tegra_host->rst);
 509         if (rc)
 510                 goto err_rst_get;
 511
 512         usleep_range(2000, 4000);
 513
 514         rc = reset_control_deassert(tegra_host->rst);
 515         if (rc)
 516                 goto err_rst_get;
 517
 518         usleep_range(2000, 4000);
 519
 520         rc = sdhci_add_host(host);
 521         if (rc)
 522                 goto err_add_host;
 523
 524         return 0;
 525
 526 err_add_host:
 527         reset_control_assert(tegra_host->rst);
 528 err_rst_get:
 529         clk_disable_unprepare(pltfm_host->clk);
 530 err_clk_get:
 531 err_power_req:
 532 err_parse_dt:
 533         sdhci_pltfm_free(pdev);
 534         return rc;
 535 }
 536
 537 static int sdhci_tegra_remove(struct platform_device *pdev)
 538 {
 539         struct sdhci_host *host = platform_get_drvdata(pdev);
 540         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 541         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 542
 543         sdhci_remove_host(host, 0);
 544
 545         reset_control_assert(tegra_host->rst);
 546         usleep_range(2000, 4000);
 547         clk_disable_unprepare(pltfm_host->clk);
 548
 549         sdhci_pltfm_free(pdev);
 550
 551         return 0;
 552 }
 553
 554 static struct platform_driver sdhci_tegra_driver = {
 555         .driver         = {
 556                 .name   = "sdhci-tegra",
 557                 .of_match_table = sdhci_tegra_dt_match,
 558                 .pm     = &sdhci_pltfm_pmops,
 559         },
 560         .probe          = sdhci_tegra_probe,
 561         .remove         = sdhci_tegra_remove,
 562 };
 563
 564 module_platform_driver(sdhci_tegra_driver);
 565
 566 MODULE_DESCRIPTION("SDHCI driver for Tegra");
 567 MODULE_AUTHOR("Google, Inc.");
 568 MODULE_LICENSE("GPL v2");