drivers/mmc/host/sdhci-xenon.h

   1 /*
   2  * Copyright (C) 2016 Marvell, All Rights Reserved.
   3  *
   4  * Author:      Hu Ziji <huziji@marvell.com>
   5  * Date:        2016-8-24
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  */
  11 #ifndef SDHCI_XENON_H_
  12 #define SDHCI_XENON_H_
  13
  14 /* Register Offset of Xenon SDHC self-defined register */
  15 #define XENON_SYS_CFG_INFO                      0x0104
  16 #define XENON_SLOT_TYPE_SDIO_SHIFT              24
  17 #define XENON_NR_SUPPORTED_SLOT_MASK            0x7
  18
  19 #define XENON_SYS_OP_CTRL                       0x0108
  20 #define XENON_AUTO_CLKGATE_DISABLE_MASK         BIT(20)
  21 #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT        8
  22 #define XENON_SLOT_ENABLE_SHIFT                 0
  23
  24 #define XENON_SYS_EXT_OP_CTRL                   0x010C
  25 #define XENON_MASK_CMD_CONFLICT_ERR             BIT(8)
  26
  27 #define XENON_SLOT_OP_STATUS_CTRL               0x0128
  28 #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT       16
  29 #define XENON_TUN_CONSECUTIVE_TIMES_MASK        0x7
  30 #define XENON_TUN_CONSECUTIVE_TIMES             0x4
  31 #define XENON_TUNING_STEP_SHIFT                 12
  32 #define XENON_TUNING_STEP_MASK                  0xF
  33 #define XENON_TUNING_STEP_DIVIDER               BIT(6)
  34
  35 #define XENON_SLOT_EMMC_CTRL                    0x0130
  36 #define XENON_ENABLE_DATA_STROBE                BIT(24)
  37
  38 #define XENON_SLOT_RETUNING_REQ_CTRL            0x0144
  39 /* retuning compatible */
  40 #define XENON_RETUNING_COMPATIBLE               0x1
  41
  42 #define XENON_SLOT_EXT_PRESENT_STATE            0x014C
  43 #define XENON_DLL_LOCK_STATE                    0x1
  44
  45 #define XENON_SLOT_DLL_CUR_DLY_VAL              0x0150
  46
  47 /* Tuning Parameter */
  48 #define XENON_TMR_RETUN_NO_PRESENT              0xF
  49 #define XENON_DEF_TUNING_COUNT                  0x9
  50
  51 #define XENON_DEFAULT_SDCLK_FREQ                400000
  52 #define XENON_LOWEST_SDCLK_FREQ                 100000
  53
  54 /* Xenon specific Mode Select value */
  55 #define XENON_CTRL_HS200                        0x5
  56 #define XENON_CTRL_HS400                        0x6
  57
  58 struct xenon_priv {
  59         unsigned char   tuning_count;
  60         /* idx of SDHC */
  61         u8              sdhc_id;
  62
  63         /*
  64          * eMMC/SD/SDIO require different register settings.
  65          * Xenon driver has to recognize card type
  66          * before mmc_host->card is not available.
  67          * This field records the card type during init.
  68          * It is updated in xenon_init_card().
  69          *
  70          * It is only valid during initialization after it is updated.
  71          * Do not access this variable in normal transfers after
  72          * initialization completes.
  73          */
  74         unsigned int    init_card_type;
  75
  76         /*
  77          * The bus_width, timing, and clock fields in below
  78          * record the current ios setting of Xenon SDHC.
  79          * Driver will adjust PHY setting if any change to
  80          * ios affects PHY timing.
  81          */
  82         unsigned char   bus_width;
  83         unsigned char   timing;
  84         unsigned int    clock;
  85
  86         int             phy_type;
  87         /*
  88          * Contains board-specific PHY parameters
  89          * passed from device tree.
  90          */
  91         void            *phy_params;
  92         struct xenon_emmc_phy_regs *emmc_phy_regs;
  93 };
  94
  95 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
  96 int xenon_phy_parse_dt(struct device_node *np,
  97                        struct sdhci_host *host);
  98 void xenon_soc_pad_ctrl(struct sdhci_host *host,
  99                         unsigned char signal_voltage);
 100 #endif