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mmc: sdhci: Get rid of host->busy_handle
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #define MAX_TUNING_LOOP 40
42
43 static unsigned int debug_quirks = 0;
44 static unsigned int debug_quirks2;
45
46 static void sdhci_finish_data(struct sdhci_host *);
47
48 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
49
50 static void sdhci_dumpregs(struct sdhci_host *host)
51 {
52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
54
55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
90
91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97 else
98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
101 }
102
103 pr_err(DRIVER_NAME ": ===========================================\n");
104 }
105
106 /*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110 \*****************************************************************************/
111
112 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113 {
114 u32 present;
115
116 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
117 !mmc_card_is_removable(host->mmc))
118 return;
119
120 if (enable) {
121 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
122 SDHCI_CARD_PRESENT;
123
124 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
125 SDHCI_INT_CARD_INSERT;
126 } else {
127 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
128 }
129
130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
132 }
133
134 static void sdhci_enable_card_detection(struct sdhci_host *host)
135 {
136 sdhci_set_card_detection(host, true);
137 }
138
139 static void sdhci_disable_card_detection(struct sdhci_host *host)
140 {
141 sdhci_set_card_detection(host, false);
142 }
143
144 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
145 {
146 if (host->bus_on)
147 return;
148 host->bus_on = true;
149 pm_runtime_get_noresume(host->mmc->parent);
150 }
151
152 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
153 {
154 if (!host->bus_on)
155 return;
156 host->bus_on = false;
157 pm_runtime_put_noidle(host->mmc->parent);
158 }
159
160 void sdhci_reset(struct sdhci_host *host, u8 mask)
161 {
162 unsigned long timeout;
163
164 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
165
166 if (mask & SDHCI_RESET_ALL) {
167 host->clock = 0;
168 /* Reset-all turns off SD Bus Power */
169 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
170 sdhci_runtime_pm_bus_off(host);
171 }
172
173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
178 if (timeout == 0) {
179 pr_err("%s: Reset 0x%x never completed.\n",
180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
186 }
187 }
188 EXPORT_SYMBOL_GPL(sdhci_reset);
189
190 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
191 {
192 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
193 struct mmc_host *mmc = host->mmc;
194
195 if (!mmc->ops->get_cd(mmc))
196 return;
197 }
198
199 host->ops->reset(host, mask);
200
201 if (mask & SDHCI_RESET_ALL) {
202 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
203 if (host->ops->enable_dma)
204 host->ops->enable_dma(host);
205 }
206
207 /* Resetting the controller clears many */
208 host->preset_enabled = false;
209 }
210 }
211
212 static void sdhci_init(struct sdhci_host *host, int soft)
213 {
214 struct mmc_host *mmc = host->mmc;
215
216 if (soft)
217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
218 else
219 sdhci_do_reset(host, SDHCI_RESET_ALL);
220
221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
233 mmc->ops->set_ios(mmc, &mmc->ios);
234 }
235 }
236
237 static void sdhci_reinit(struct sdhci_host *host)
238 {
239 sdhci_init(host, 0);
240 sdhci_enable_card_detection(host);
241 }
242
243 static void __sdhci_led_activate(struct sdhci_host *host)
244 {
245 u8 ctrl;
246
247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
248 ctrl |= SDHCI_CTRL_LED;
249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
250 }
251
252 static void __sdhci_led_deactivate(struct sdhci_host *host)
253 {
254 u8 ctrl;
255
256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
257 ctrl &= ~SDHCI_CTRL_LED;
258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
259 }
260
261 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
262 static void sdhci_led_control(struct led_classdev *led,
263 enum led_brightness brightness)
264 {
265 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
266 unsigned long flags;
267
268 spin_lock_irqsave(&host->lock, flags);
269
270 if (host->runtime_suspended)
271 goto out;
272
273 if (brightness == LED_OFF)
274 __sdhci_led_deactivate(host);
275 else
276 __sdhci_led_activate(host);
277 out:
278 spin_unlock_irqrestore(&host->lock, flags);
279 }
280
281 static int sdhci_led_register(struct sdhci_host *host)
282 {
283 struct mmc_host *mmc = host->mmc;
284
285 snprintf(host->led_name, sizeof(host->led_name),
286 "%s::", mmc_hostname(mmc));
287
288 host->led.name = host->led_name;
289 host->led.brightness = LED_OFF;
290 host->led.default_trigger = mmc_hostname(mmc);
291 host->led.brightness_set = sdhci_led_control;
292
293 return led_classdev_register(mmc_dev(mmc), &host->led);
294 }
295
296 static void sdhci_led_unregister(struct sdhci_host *host)
297 {
298 led_classdev_unregister(&host->led);
299 }
300
301 static inline void sdhci_led_activate(struct sdhci_host *host)
302 {
303 }
304
305 static inline void sdhci_led_deactivate(struct sdhci_host *host)
306 {
307 }
308
309 #else
310
311 static inline int sdhci_led_register(struct sdhci_host *host)
312 {
313 return 0;
314 }
315
316 static inline void sdhci_led_unregister(struct sdhci_host *host)
317 {
318 }
319
320 static inline void sdhci_led_activate(struct sdhci_host *host)
321 {
322 __sdhci_led_activate(host);
323 }
324
325 static inline void sdhci_led_deactivate(struct sdhci_host *host)
326 {
327 __sdhci_led_deactivate(host);
328 }
329
330 #endif
331
332 /*****************************************************************************\
333 * *
334 * Core functions *
335 * *
336 \*****************************************************************************/
337
338 static void sdhci_read_block_pio(struct sdhci_host *host)
339 {
340 unsigned long flags;
341 size_t blksize, len, chunk;
342 u32 uninitialized_var(scratch);
343 u8 *buf;
344
345 DBG("PIO reading\n");
346
347 blksize = host->data->blksz;
348 chunk = 0;
349
350 local_irq_save(flags);
351
352 while (blksize) {
353 BUG_ON(!sg_miter_next(&host->sg_miter));
354
355 len = min(host->sg_miter.length, blksize);
356
357 blksize -= len;
358 host->sg_miter.consumed = len;
359
360 buf = host->sg_miter.addr;
361
362 while (len) {
363 if (chunk == 0) {
364 scratch = sdhci_readl(host, SDHCI_BUFFER);
365 chunk = 4;
366 }
367
368 *buf = scratch & 0xFF;
369
370 buf++;
371 scratch >>= 8;
372 chunk--;
373 len--;
374 }
375 }
376
377 sg_miter_stop(&host->sg_miter);
378
379 local_irq_restore(flags);
380 }
381
382 static void sdhci_write_block_pio(struct sdhci_host *host)
383 {
384 unsigned long flags;
385 size_t blksize, len, chunk;
386 u32 scratch;
387 u8 *buf;
388
389 DBG("PIO writing\n");
390
391 blksize = host->data->blksz;
392 chunk = 0;
393 scratch = 0;
394
395 local_irq_save(flags);
396
397 while (blksize) {
398 BUG_ON(!sg_miter_next(&host->sg_miter));
399
400 len = min(host->sg_miter.length, blksize);
401
402 blksize -= len;
403 host->sg_miter.consumed = len;
404
405 buf = host->sg_miter.addr;
406
407 while (len) {
408 scratch |= (u32)*buf << (chunk * 8);
409
410 buf++;
411 chunk++;
412 len--;
413
414 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
415 sdhci_writel(host, scratch, SDHCI_BUFFER);
416 chunk = 0;
417 scratch = 0;
418 }
419 }
420 }
421
422 sg_miter_stop(&host->sg_miter);
423
424 local_irq_restore(flags);
425 }
426
427 static void sdhci_transfer_pio(struct sdhci_host *host)
428 {
429 u32 mask;
430
431 if (host->blocks == 0)
432 return;
433
434 if (host->data->flags & MMC_DATA_READ)
435 mask = SDHCI_DATA_AVAILABLE;
436 else
437 mask = SDHCI_SPACE_AVAILABLE;
438
439 /*
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
443 */
444 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
445 (host->data->blocks == 1))
446 mask = ~0;
447
448 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
449 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 udelay(100);
451
452 if (host->data->flags & MMC_DATA_READ)
453 sdhci_read_block_pio(host);
454 else
455 sdhci_write_block_pio(host);
456
457 host->blocks--;
458 if (host->blocks == 0)
459 break;
460 }
461
462 DBG("PIO transfer complete.\n");
463 }
464
465 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
466 struct mmc_data *data, int cookie)
467 {
468 int sg_count;
469
470 /*
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
473 */
474 if (data->host_cookie == COOKIE_PRE_MAPPED)
475 return data->sg_count;
476
477 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
478 data->flags & MMC_DATA_WRITE ?
479 DMA_TO_DEVICE : DMA_FROM_DEVICE);
480
481 if (sg_count == 0)
482 return -ENOSPC;
483
484 data->sg_count = sg_count;
485 data->host_cookie = cookie;
486
487 return sg_count;
488 }
489
490 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
491 {
492 local_irq_save(*flags);
493 return kmap_atomic(sg_page(sg)) + sg->offset;
494 }
495
496 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
497 {
498 kunmap_atomic(buffer);
499 local_irq_restore(*flags);
500 }
501
502 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
503 dma_addr_t addr, int len, unsigned cmd)
504 {
505 struct sdhci_adma2_64_desc *dma_desc = desc;
506
507 /* 32-bit and 64-bit descriptors have these members in same position */
508 dma_desc->cmd = cpu_to_le16(cmd);
509 dma_desc->len = cpu_to_le16(len);
510 dma_desc->addr_lo = cpu_to_le32((u32)addr);
511
512 if (host->flags & SDHCI_USE_64_BIT_DMA)
513 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
514 }
515
516 static void sdhci_adma_mark_end(void *desc)
517 {
518 struct sdhci_adma2_64_desc *dma_desc = desc;
519
520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
521 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
522 }
523
524 static void sdhci_adma_table_pre(struct sdhci_host *host,
525 struct mmc_data *data, int sg_count)
526 {
527 struct scatterlist *sg;
528 unsigned long flags;
529 dma_addr_t addr, align_addr;
530 void *desc, *align;
531 char *buffer;
532 int len, offset, i;
533
534 /*
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
537 */
538
539 host->sg_count = sg_count;
540
541 desc = host->adma_table;
542 align = host->align_buffer;
543
544 align_addr = host->align_addr;
545
546 for_each_sg(data->sg, sg, host->sg_count, i) {
547 addr = sg_dma_address(sg);
548 len = sg_dma_len(sg);
549
550 /*
551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
554 * alignment.
555 */
556 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
557 SDHCI_ADMA2_MASK;
558 if (offset) {
559 if (data->flags & MMC_DATA_WRITE) {
560 buffer = sdhci_kmap_atomic(sg, &flags);
561 memcpy(align, buffer, offset);
562 sdhci_kunmap_atomic(buffer, &flags);
563 }
564
565 /* tran, valid */
566 sdhci_adma_write_desc(host, desc, align_addr, offset,
567 ADMA2_TRAN_VALID);
568
569 BUG_ON(offset > 65536);
570
571 align += SDHCI_ADMA2_ALIGN;
572 align_addr += SDHCI_ADMA2_ALIGN;
573
574 desc += host->desc_sz;
575
576 addr += offset;
577 len -= offset;
578 }
579
580 BUG_ON(len > 65536);
581
582 if (len) {
583 /* tran, valid */
584 sdhci_adma_write_desc(host, desc, addr, len,
585 ADMA2_TRAN_VALID);
586 desc += host->desc_sz;
587 }
588
589 /*
590 * If this triggers then we have a calculation bug
591 * somewhere. :/
592 */
593 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
594 }
595
596 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
597 /* Mark the last descriptor as the terminating descriptor */
598 if (desc != host->adma_table) {
599 desc -= host->desc_sz;
600 sdhci_adma_mark_end(desc);
601 }
602 } else {
603 /* Add a terminating entry - nop, end, valid */
604 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
605 }
606 }
607
608 static void sdhci_adma_table_post(struct sdhci_host *host,
609 struct mmc_data *data)
610 {
611 struct scatterlist *sg;
612 int i, size;
613 void *align;
614 char *buffer;
615 unsigned long flags;
616
617 if (data->flags & MMC_DATA_READ) {
618 bool has_unaligned = false;
619
620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data->sg, sg, host->sg_count, i)
622 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
623 has_unaligned = true;
624 break;
625 }
626
627 if (has_unaligned) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
629 data->sg_len, DMA_FROM_DEVICE);
630
631 align = host->align_buffer;
632
633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
635 size = SDHCI_ADMA2_ALIGN -
636 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
637
638 buffer = sdhci_kmap_atomic(sg, &flags);
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
641
642 align += SDHCI_ADMA2_ALIGN;
643 }
644 }
645 }
646 }
647 }
648
649 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
650 {
651 u8 count;
652 struct mmc_data *data = cmd->data;
653 unsigned target_timeout, current_timeout;
654
655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
662 return 0xE;
663
664 /* Unspecified timeout, assume max */
665 if (!data && !cmd->busy_timeout)
666 return 0xE;
667
668 /* timeout in us */
669 if (!data)
670 target_timeout = cmd->busy_timeout * 1000;
671 else {
672 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
673 if (host->clock && data->timeout_clks) {
674 unsigned long long val;
675
676 /*
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
680 */
681 val = 1000000 * data->timeout_clks;
682 if (do_div(val, host->clock))
683 target_timeout++;
684 target_timeout += val;
685 }
686 }
687
688 /*
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
695 * =>
696 * (1) / (2) > 2^6
697 */
698 count = 0;
699 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
700 while (current_timeout < target_timeout) {
701 count++;
702 current_timeout <<= 1;
703 if (count >= 0xF)
704 break;
705 }
706
707 if (count >= 0xF) {
708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host->mmc), count, cmd->opcode);
710 count = 0xE;
711 }
712
713 return count;
714 }
715
716 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
717 {
718 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
719 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
720
721 if (host->flags & SDHCI_REQ_USE_DMA)
722 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
723 else
724 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
725
726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
728 }
729
730 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
731 {
732 u8 count;
733
734 if (host->ops->set_timeout) {
735 host->ops->set_timeout(host, cmd);
736 } else {
737 count = sdhci_calc_timeout(host, cmd);
738 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 }
740 }
741
742 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
743 {
744 u8 ctrl;
745 struct mmc_data *data = cmd->data;
746
747 WARN_ON(host->data);
748
749 if (data || (cmd->flags & MMC_RSP_BUSY))
750 sdhci_set_timeout(host, cmd);
751
752 if (!data)
753 return;
754
755 /* Sanity checks */
756 BUG_ON(data->blksz * data->blocks > 524288);
757 BUG_ON(data->blksz > host->mmc->max_blk_size);
758 BUG_ON(data->blocks > 65535);
759
760 host->data = data;
761 host->data_early = 0;
762 host->data->bytes_xfered = 0;
763
764 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
765 struct scatterlist *sg;
766 unsigned int length_mask, offset_mask;
767 int i;
768
769 host->flags |= SDHCI_REQ_USE_DMA;
770
771 /*
772 * FIXME: This doesn't account for merging when mapping the
773 * scatterlist.
774 *
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
777 */
778 length_mask = 0;
779 offset_mask = 0;
780 if (host->flags & SDHCI_USE_ADMA) {
781 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
782 length_mask = 3;
783 /*
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
787 */
788 offset_mask = 3;
789 }
790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
792 length_mask = 3;
793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 offset_mask = 3;
795 }
796
797 if (unlikely(length_mask | offset_mask)) {
798 for_each_sg(data->sg, sg, data->sg_len, i) {
799 if (sg->length & length_mask) {
800 DBG("Reverting to PIO because of transfer size (%d)\n",
801 sg->length);
802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
805 if (sg->offset & offset_mask) {
806 DBG("Reverting to PIO because of bad alignment\n");
807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
814 if (host->flags & SDHCI_REQ_USE_DMA) {
815 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
816
817 if (sg_cnt <= 0) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 } else if (host->flags & SDHCI_USE_ADMA) {
825 sdhci_adma_table_pre(host, data, sg_cnt);
826
827 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
832 } else {
833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
836 }
837 }
838
839 /*
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
842 * is ADMA.
843 */
844 if (host->version >= SDHCI_SPEC_200) {
845 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
846 ctrl &= ~SDHCI_CTRL_DMA_MASK;
847 if ((host->flags & SDHCI_REQ_USE_DMA) &&
848 (host->flags & SDHCI_USE_ADMA)) {
849 if (host->flags & SDHCI_USE_64_BIT_DMA)
850 ctrl |= SDHCI_CTRL_ADMA64;
851 else
852 ctrl |= SDHCI_CTRL_ADMA32;
853 } else {
854 ctrl |= SDHCI_CTRL_SDMA;
855 }
856 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
857 }
858
859 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
860 int flags;
861
862 flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
868 host->blocks = data->blocks;
869 }
870
871 sdhci_set_transfer_irqs(host);
872
873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
875 data->blksz), SDHCI_BLOCK_SIZE);
876 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
877 }
878
879 static void sdhci_set_transfer_mode(struct sdhci_host *host,
880 struct mmc_command *cmd)
881 {
882 u16 mode = 0;
883 struct mmc_data *data = cmd->data;
884
885 if (data == NULL) {
886 if (host->quirks2 &
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
888 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
889 } else {
890 /* clear Auto CMD settings for no data CMDs */
891 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
892 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
893 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
894 }
895 return;
896 }
897
898 WARN_ON(!host->data);
899
900 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902
903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
904 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
909 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
910 (cmd->opcode != SD_IO_RW_EXTENDED))
911 mode |= SDHCI_TRNS_AUTO_CMD12;
912 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
913 mode |= SDHCI_TRNS_AUTO_CMD23;
914 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
915 }
916 }
917
918 if (data->flags & MMC_DATA_READ)
919 mode |= SDHCI_TRNS_READ;
920 if (host->flags & SDHCI_REQ_USE_DMA)
921 mode |= SDHCI_TRNS_DMA;
922
923 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
924 }
925
926 static void sdhci_finish_data(struct sdhci_host *host)
927 {
928 struct mmc_data *data;
929
930 data = host->data;
931 host->data = NULL;
932 host->data_cmd = NULL;
933
934 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
935 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
936 sdhci_adma_table_post(host, data);
937
938 /*
939 * The specification states that the block count register must
940 * be updated, but it does not specify at what point in the
941 * data flow. That makes the register entirely useless to read
942 * back so we have to assume that nothing made it to the card
943 * in the event of an error.
944 */
945 if (data->error)
946 data->bytes_xfered = 0;
947 else
948 data->bytes_xfered = data->blksz * data->blocks;
949
950 /*
951 * Need to send CMD12 if -
952 * a) open-ended multiblock transfer (no CMD23)
953 * b) error in multiblock transfer
954 */
955 if (data->stop &&
956 (data->error ||
957 !host->mrq->sbc)) {
958
959 /*
960 * The controller needs a reset of internal state machines
961 * upon error conditions.
962 */
963 if (data->error) {
964 sdhci_do_reset(host, SDHCI_RESET_CMD);
965 sdhci_do_reset(host, SDHCI_RESET_DATA);
966 }
967
968 sdhci_send_command(host, data->stop);
969 } else
970 tasklet_schedule(&host->finish_tasklet);
971 }
972
973 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
974 {
975 int flags;
976 u32 mask;
977 unsigned long timeout;
978
979 WARN_ON(host->cmd);
980
981 /* Initially, a command has no error */
982 cmd->error = 0;
983
984 /* Wait max 10 ms */
985 timeout = 10;
986
987 mask = SDHCI_CMD_INHIBIT;
988 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
989 mask |= SDHCI_DATA_INHIBIT;
990
991 /* We shouldn't wait for data inihibit for stop commands, even
992 though they might use busy signaling */
993 if (host->mrq->data && (cmd == host->mrq->data->stop))
994 mask &= ~SDHCI_DATA_INHIBIT;
995
996 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
997 if (timeout == 0) {
998 pr_err("%s: Controller never released inhibit bit(s).\n",
999 mmc_hostname(host->mmc));
1000 sdhci_dumpregs(host);
1001 cmd->error = -EIO;
1002 tasklet_schedule(&host->finish_tasklet);
1003 return;
1004 }
1005 timeout--;
1006 mdelay(1);
1007 }
1008
1009 timeout = jiffies;
1010 if (!cmd->data && cmd->busy_timeout > 9000)
1011 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1012 else
1013 timeout += 10 * HZ;
1014 mod_timer(&host->timer, timeout);
1015
1016 host->cmd = cmd;
1017 if (cmd->data || cmd->flags & MMC_RSP_BUSY) {
1018 WARN_ON(host->data_cmd);
1019 host->data_cmd = cmd;
1020 }
1021
1022 sdhci_prepare_data(host, cmd);
1023
1024 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1025
1026 sdhci_set_transfer_mode(host, cmd);
1027
1028 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1029 pr_err("%s: Unsupported response type!\n",
1030 mmc_hostname(host->mmc));
1031 cmd->error = -EINVAL;
1032 tasklet_schedule(&host->finish_tasklet);
1033 return;
1034 }
1035
1036 if (!(cmd->flags & MMC_RSP_PRESENT))
1037 flags = SDHCI_CMD_RESP_NONE;
1038 else if (cmd->flags & MMC_RSP_136)
1039 flags = SDHCI_CMD_RESP_LONG;
1040 else if (cmd->flags & MMC_RSP_BUSY)
1041 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1042 else
1043 flags = SDHCI_CMD_RESP_SHORT;
1044
1045 if (cmd->flags & MMC_RSP_CRC)
1046 flags |= SDHCI_CMD_CRC;
1047 if (cmd->flags & MMC_RSP_OPCODE)
1048 flags |= SDHCI_CMD_INDEX;
1049
1050 /* CMD19 is special in that the Data Present Select should be set */
1051 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1052 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1053 flags |= SDHCI_CMD_DATA;
1054
1055 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1056 }
1057 EXPORT_SYMBOL_GPL(sdhci_send_command);
1058
1059 static void sdhci_finish_command(struct sdhci_host *host)
1060 {
1061 struct mmc_command *cmd = host->cmd;
1062 int i;
1063
1064 host->cmd = NULL;
1065
1066 if (cmd->flags & MMC_RSP_PRESENT) {
1067 if (cmd->flags & MMC_RSP_136) {
1068 /* CRC is stripped so we need to do some shifting. */
1069 for (i = 0;i < 4;i++) {
1070 cmd->resp[i] = sdhci_readl(host,
1071 SDHCI_RESPONSE + (3-i)*4) << 8;
1072 if (i != 3)
1073 cmd->resp[i] |=
1074 sdhci_readb(host,
1075 SDHCI_RESPONSE + (3-i)*4-1);
1076 }
1077 } else {
1078 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1079 }
1080 }
1081
1082 /*
1083 * The host can send and interrupt when the busy state has
1084 * ended, allowing us to wait without wasting CPU cycles.
1085 * The busy signal uses DAT0 so this is similar to waiting
1086 * for data to complete.
1087 *
1088 * Note: The 1.0 specification is a bit ambiguous about this
1089 * feature so there might be some problems with older
1090 * controllers.
1091 */
1092 if (cmd->flags & MMC_RSP_BUSY) {
1093 if (cmd->data) {
1094 DBG("Cannot wait for busy signal when also doing a data transfer");
1095 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1096 cmd == host->data_cmd) {
1097 /* Command complete before busy is ended */
1098 return;
1099 }
1100 }
1101
1102 /* Finished CMD23, now send actual command. */
1103 if (cmd == host->mrq->sbc) {
1104 sdhci_send_command(host, host->mrq->cmd);
1105 } else {
1106
1107 /* Processed actual command. */
1108 if (host->data && host->data_early)
1109 sdhci_finish_data(host);
1110
1111 if (!cmd->data)
1112 tasklet_schedule(&host->finish_tasklet);
1113 }
1114 }
1115
1116 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1117 {
1118 u16 preset = 0;
1119
1120 switch (host->timing) {
1121 case MMC_TIMING_UHS_SDR12:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1123 break;
1124 case MMC_TIMING_UHS_SDR25:
1125 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1126 break;
1127 case MMC_TIMING_UHS_SDR50:
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1129 break;
1130 case MMC_TIMING_UHS_SDR104:
1131 case MMC_TIMING_MMC_HS200:
1132 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1133 break;
1134 case MMC_TIMING_UHS_DDR50:
1135 case MMC_TIMING_MMC_DDR52:
1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1137 break;
1138 case MMC_TIMING_MMC_HS400:
1139 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1140 break;
1141 default:
1142 pr_warn("%s: Invalid UHS-I mode selected\n",
1143 mmc_hostname(host->mmc));
1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1145 break;
1146 }
1147 return preset;
1148 }
1149
1150 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1151 unsigned int *actual_clock)
1152 {
1153 int div = 0; /* Initialized for compiler warning */
1154 int real_div = div, clk_mul = 1;
1155 u16 clk = 0;
1156 bool switch_base_clk = false;
1157
1158 if (host->version >= SDHCI_SPEC_300) {
1159 if (host->preset_enabled) {
1160 u16 pre_val;
1161
1162 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1163 pre_val = sdhci_get_preset_value(host);
1164 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1165 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1166 if (host->clk_mul &&
1167 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1168 clk = SDHCI_PROG_CLOCK_MODE;
1169 real_div = div + 1;
1170 clk_mul = host->clk_mul;
1171 } else {
1172 real_div = max_t(int, 1, div << 1);
1173 }
1174 goto clock_set;
1175 }
1176
1177 /*
1178 * Check if the Host Controller supports Programmable Clock
1179 * Mode.
1180 */
1181 if (host->clk_mul) {
1182 for (div = 1; div <= 1024; div++) {
1183 if ((host->max_clk * host->clk_mul / div)
1184 <= clock)
1185 break;
1186 }
1187 if ((host->max_clk * host->clk_mul / div) <= clock) {
1188 /*
1189 * Set Programmable Clock Mode in the Clock
1190 * Control register.
1191 */
1192 clk = SDHCI_PROG_CLOCK_MODE;
1193 real_div = div;
1194 clk_mul = host->clk_mul;
1195 div--;
1196 } else {
1197 /*
1198 * Divisor can be too small to reach clock
1199 * speed requirement. Then use the base clock.
1200 */
1201 switch_base_clk = true;
1202 }
1203 }
1204
1205 if (!host->clk_mul || switch_base_clk) {
1206 /* Version 3.00 divisors must be a multiple of 2. */
1207 if (host->max_clk <= clock)
1208 div = 1;
1209 else {
1210 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1211 div += 2) {
1212 if ((host->max_clk / div) <= clock)
1213 break;
1214 }
1215 }
1216 real_div = div;
1217 div >>= 1;
1218 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1219 && !div && host->max_clk <= 25000000)
1220 div = 1;
1221 }
1222 } else {
1223 /* Version 2.00 divisors must be a power of 2. */
1224 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1225 if ((host->max_clk / div) <= clock)
1226 break;
1227 }
1228 real_div = div;
1229 div >>= 1;
1230 }
1231
1232 clock_set:
1233 if (real_div)
1234 *actual_clock = (host->max_clk * clk_mul) / real_div;
1235 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1236 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1237 << SDHCI_DIVIDER_HI_SHIFT;
1238
1239 return clk;
1240 }
1241 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1242
1243 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1244 {
1245 u16 clk;
1246 unsigned long timeout;
1247
1248 host->mmc->actual_clock = 0;
1249
1250 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1251
1252 if (clock == 0)
1253 return;
1254
1255 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1256
1257 clk |= SDHCI_CLOCK_INT_EN;
1258 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1259
1260 /* Wait max 20 ms */
1261 timeout = 20;
1262 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1263 & SDHCI_CLOCK_INT_STABLE)) {
1264 if (timeout == 0) {
1265 pr_err("%s: Internal clock never stabilised.\n",
1266 mmc_hostname(host->mmc));
1267 sdhci_dumpregs(host);
1268 return;
1269 }
1270 timeout--;
1271 mdelay(1);
1272 }
1273
1274 clk |= SDHCI_CLOCK_CARD_EN;
1275 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1276 }
1277 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1278
1279 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1280 unsigned short vdd)
1281 {
1282 struct mmc_host *mmc = host->mmc;
1283
1284 spin_unlock_irq(&host->lock);
1285 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1286 spin_lock_irq(&host->lock);
1287
1288 if (mode != MMC_POWER_OFF)
1289 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1290 else
1291 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1292 }
1293
1294 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1295 unsigned short vdd)
1296 {
1297 u8 pwr = 0;
1298
1299 if (mode != MMC_POWER_OFF) {
1300 switch (1 << vdd) {
1301 case MMC_VDD_165_195:
1302 pwr = SDHCI_POWER_180;
1303 break;
1304 case MMC_VDD_29_30:
1305 case MMC_VDD_30_31:
1306 pwr = SDHCI_POWER_300;
1307 break;
1308 case MMC_VDD_32_33:
1309 case MMC_VDD_33_34:
1310 pwr = SDHCI_POWER_330;
1311 break;
1312 default:
1313 WARN(1, "%s: Invalid vdd %#x\n",
1314 mmc_hostname(host->mmc), vdd);
1315 break;
1316 }
1317 }
1318
1319 if (host->pwr == pwr)
1320 return;
1321
1322 host->pwr = pwr;
1323
1324 if (pwr == 0) {
1325 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1326 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1327 sdhci_runtime_pm_bus_off(host);
1328 } else {
1329 /*
1330 * Spec says that we should clear the power reg before setting
1331 * a new value. Some controllers don't seem to like this though.
1332 */
1333 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1334 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1335
1336 /*
1337 * At least the Marvell CaFe chip gets confused if we set the
1338 * voltage and set turn on power at the same time, so set the
1339 * voltage first.
1340 */
1341 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1342 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1343
1344 pwr |= SDHCI_POWER_ON;
1345
1346 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1347
1348 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1349 sdhci_runtime_pm_bus_on(host);
1350
1351 /*
1352 * Some controllers need an extra 10ms delay of 10ms before
1353 * they can apply clock after applying power
1354 */
1355 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1356 mdelay(10);
1357 }
1358 }
1359 EXPORT_SYMBOL_GPL(sdhci_set_power);
1360
1361 static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1362 unsigned short vdd)
1363 {
1364 struct mmc_host *mmc = host->mmc;
1365
1366 if (host->ops->set_power)
1367 host->ops->set_power(host, mode, vdd);
1368 else if (!IS_ERR(mmc->supply.vmmc))
1369 sdhci_set_power_reg(host, mode, vdd);
1370 else
1371 sdhci_set_power(host, mode, vdd);
1372 }
1373
1374 /*****************************************************************************\
1375 * *
1376 * MMC callbacks *
1377 * *
1378 \*****************************************************************************/
1379
1380 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1381 {
1382 struct sdhci_host *host;
1383 int present;
1384 unsigned long flags;
1385
1386 host = mmc_priv(mmc);
1387
1388 /* Firstly check card presence */
1389 present = mmc->ops->get_cd(mmc);
1390
1391 spin_lock_irqsave(&host->lock, flags);
1392
1393 WARN_ON(host->mrq != NULL);
1394
1395 sdhci_led_activate(host);
1396
1397 /*
1398 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1399 * requests if Auto-CMD12 is enabled.
1400 */
1401 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1402 if (mrq->stop) {
1403 mrq->data->stop = NULL;
1404 mrq->stop = NULL;
1405 }
1406 }
1407
1408 host->mrq = mrq;
1409
1410 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1411 host->mrq->cmd->error = -ENOMEDIUM;
1412 tasklet_schedule(&host->finish_tasklet);
1413 } else {
1414 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1415 sdhci_send_command(host, mrq->sbc);
1416 else
1417 sdhci_send_command(host, mrq->cmd);
1418 }
1419
1420 mmiowb();
1421 spin_unlock_irqrestore(&host->lock, flags);
1422 }
1423
1424 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1425 {
1426 u8 ctrl;
1427
1428 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1429 if (width == MMC_BUS_WIDTH_8) {
1430 ctrl &= ~SDHCI_CTRL_4BITBUS;
1431 if (host->version >= SDHCI_SPEC_300)
1432 ctrl |= SDHCI_CTRL_8BITBUS;
1433 } else {
1434 if (host->version >= SDHCI_SPEC_300)
1435 ctrl &= ~SDHCI_CTRL_8BITBUS;
1436 if (width == MMC_BUS_WIDTH_4)
1437 ctrl |= SDHCI_CTRL_4BITBUS;
1438 else
1439 ctrl &= ~SDHCI_CTRL_4BITBUS;
1440 }
1441 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1442 }
1443 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1444
1445 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1446 {
1447 u16 ctrl_2;
1448
1449 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1450 /* Select Bus Speed Mode for host */
1451 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1452 if ((timing == MMC_TIMING_MMC_HS200) ||
1453 (timing == MMC_TIMING_UHS_SDR104))
1454 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1455 else if (timing == MMC_TIMING_UHS_SDR12)
1456 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1457 else if (timing == MMC_TIMING_UHS_SDR25)
1458 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1459 else if (timing == MMC_TIMING_UHS_SDR50)
1460 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1461 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1462 (timing == MMC_TIMING_MMC_DDR52))
1463 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1464 else if (timing == MMC_TIMING_MMC_HS400)
1465 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1466 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1467 }
1468 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1469
1470 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1471 {
1472 struct sdhci_host *host = mmc_priv(mmc);
1473 unsigned long flags;
1474 u8 ctrl;
1475
1476 spin_lock_irqsave(&host->lock, flags);
1477
1478 if (host->flags & SDHCI_DEVICE_DEAD) {
1479 spin_unlock_irqrestore(&host->lock, flags);
1480 if (!IS_ERR(mmc->supply.vmmc) &&
1481 ios->power_mode == MMC_POWER_OFF)
1482 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1483 return;
1484 }
1485
1486 /*
1487 * Reset the chip on each power off.
1488 * Should clear out any weird states.
1489 */
1490 if (ios->power_mode == MMC_POWER_OFF) {
1491 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1492 sdhci_reinit(host);
1493 }
1494
1495 if (host->version >= SDHCI_SPEC_300 &&
1496 (ios->power_mode == MMC_POWER_UP) &&
1497 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1498 sdhci_enable_preset_value(host, false);
1499
1500 if (!ios->clock || ios->clock != host->clock) {
1501 host->ops->set_clock(host, ios->clock);
1502 host->clock = ios->clock;
1503
1504 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1505 host->clock) {
1506 host->timeout_clk = host->mmc->actual_clock ?
1507 host->mmc->actual_clock / 1000 :
1508 host->clock / 1000;
1509 host->mmc->max_busy_timeout =
1510 host->ops->get_max_timeout_count ?
1511 host->ops->get_max_timeout_count(host) :
1512 1 << 27;
1513 host->mmc->max_busy_timeout /= host->timeout_clk;
1514 }
1515 }
1516
1517 __sdhci_set_power(host, ios->power_mode, ios->vdd);
1518
1519 if (host->ops->platform_send_init_74_clocks)
1520 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1521
1522 host->ops->set_bus_width(host, ios->bus_width);
1523
1524 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1525
1526 if ((ios->timing == MMC_TIMING_SD_HS ||
1527 ios->timing == MMC_TIMING_MMC_HS)
1528 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1529 ctrl |= SDHCI_CTRL_HISPD;
1530 else
1531 ctrl &= ~SDHCI_CTRL_HISPD;
1532
1533 if (host->version >= SDHCI_SPEC_300) {
1534 u16 clk, ctrl_2;
1535
1536 /* In case of UHS-I modes, set High Speed Enable */
1537 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1538 (ios->timing == MMC_TIMING_MMC_HS200) ||
1539 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1540 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1541 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1542 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1543 (ios->timing == MMC_TIMING_UHS_SDR25))
1544 ctrl |= SDHCI_CTRL_HISPD;
1545
1546 if (!host->preset_enabled) {
1547 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1548 /*
1549 * We only need to set Driver Strength if the
1550 * preset value enable is not set.
1551 */
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1554 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1555 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1556 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1557 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1558 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1559 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1560 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1561 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1562 else {
1563 pr_warn("%s: invalid driver type, default to driver type B\n",
1564 mmc_hostname(mmc));
1565 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1566 }
1567
1568 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1569 } else {
1570 /*
1571 * According to SDHC Spec v3.00, if the Preset Value
1572 * Enable in the Host Control 2 register is set, we
1573 * need to reset SD Clock Enable before changing High
1574 * Speed Enable to avoid generating clock gliches.
1575 */
1576
1577 /* Reset SD Clock Enable */
1578 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1579 clk &= ~SDHCI_CLOCK_CARD_EN;
1580 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1581
1582 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1583
1584 /* Re-enable SD Clock */
1585 host->ops->set_clock(host, host->clock);
1586 }
1587
1588 /* Reset SD Clock Enable */
1589 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1590 clk &= ~SDHCI_CLOCK_CARD_EN;
1591 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1592
1593 host->ops->set_uhs_signaling(host, ios->timing);
1594 host->timing = ios->timing;
1595
1596 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1597 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1598 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1599 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1600 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1601 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1602 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1603 u16 preset;
1604
1605 sdhci_enable_preset_value(host, true);
1606 preset = sdhci_get_preset_value(host);
1607 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1608 >> SDHCI_PRESET_DRV_SHIFT;
1609 }
1610
1611 /* Re-enable SD Clock */
1612 host->ops->set_clock(host, host->clock);
1613 } else
1614 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1615
1616 /*
1617 * Some (ENE) controllers go apeshit on some ios operation,
1618 * signalling timeout and CRC errors even on CMD0. Resetting
1619 * it on each ios seems to solve the problem.
1620 */
1621 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1622 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1623
1624 mmiowb();
1625 spin_unlock_irqrestore(&host->lock, flags);
1626 }
1627
1628 static int sdhci_get_cd(struct mmc_host *mmc)
1629 {
1630 struct sdhci_host *host = mmc_priv(mmc);
1631 int gpio_cd = mmc_gpio_get_cd(mmc);
1632
1633 if (host->flags & SDHCI_DEVICE_DEAD)
1634 return 0;
1635
1636 /* If nonremovable, assume that the card is always present. */
1637 if (!mmc_card_is_removable(host->mmc))
1638 return 1;
1639
1640 /*
1641 * Try slot gpio detect, if defined it take precedence
1642 * over build in controller functionality
1643 */
1644 if (gpio_cd >= 0)
1645 return !!gpio_cd;
1646
1647 /* If polling, assume that the card is always present. */
1648 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1649 return 1;
1650
1651 /* Host native card detect */
1652 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1653 }
1654
1655 static int sdhci_check_ro(struct sdhci_host *host)
1656 {
1657 unsigned long flags;
1658 int is_readonly;
1659
1660 spin_lock_irqsave(&host->lock, flags);
1661
1662 if (host->flags & SDHCI_DEVICE_DEAD)
1663 is_readonly = 0;
1664 else if (host->ops->get_ro)
1665 is_readonly = host->ops->get_ro(host);
1666 else
1667 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1668 & SDHCI_WRITE_PROTECT);
1669
1670 spin_unlock_irqrestore(&host->lock, flags);
1671
1672 /* This quirk needs to be replaced by a callback-function later */
1673 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1674 !is_readonly : is_readonly;
1675 }
1676
1677 #define SAMPLE_COUNT 5
1678
1679 static int sdhci_get_ro(struct mmc_host *mmc)
1680 {
1681 struct sdhci_host *host = mmc_priv(mmc);
1682 int i, ro_count;
1683
1684 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1685 return sdhci_check_ro(host);
1686
1687 ro_count = 0;
1688 for (i = 0; i < SAMPLE_COUNT; i++) {
1689 if (sdhci_check_ro(host)) {
1690 if (++ro_count > SAMPLE_COUNT / 2)
1691 return 1;
1692 }
1693 msleep(30);
1694 }
1695 return 0;
1696 }
1697
1698 static void sdhci_hw_reset(struct mmc_host *mmc)
1699 {
1700 struct sdhci_host *host = mmc_priv(mmc);
1701
1702 if (host->ops && host->ops->hw_reset)
1703 host->ops->hw_reset(host);
1704 }
1705
1706 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1707 {
1708 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1709 if (enable)
1710 host->ier |= SDHCI_INT_CARD_INT;
1711 else
1712 host->ier &= ~SDHCI_INT_CARD_INT;
1713
1714 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1715 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1716 mmiowb();
1717 }
1718 }
1719
1720 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1721 {
1722 struct sdhci_host *host = mmc_priv(mmc);
1723 unsigned long flags;
1724
1725 spin_lock_irqsave(&host->lock, flags);
1726 if (enable)
1727 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1728 else
1729 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1730
1731 sdhci_enable_sdio_irq_nolock(host, enable);
1732 spin_unlock_irqrestore(&host->lock, flags);
1733 }
1734
1735 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1736 struct mmc_ios *ios)
1737 {
1738 struct sdhci_host *host = mmc_priv(mmc);
1739 u16 ctrl;
1740 int ret;
1741
1742 /*
1743 * Signal Voltage Switching is only applicable for Host Controllers
1744 * v3.00 and above.
1745 */
1746 if (host->version < SDHCI_SPEC_300)
1747 return 0;
1748
1749 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1750
1751 switch (ios->signal_voltage) {
1752 case MMC_SIGNAL_VOLTAGE_330:
1753 if (!(host->flags & SDHCI_SIGNALING_330))
1754 return -EINVAL;
1755 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1756 ctrl &= ~SDHCI_CTRL_VDD_180;
1757 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1758
1759 if (!IS_ERR(mmc->supply.vqmmc)) {
1760 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1761 3600000);
1762 if (ret) {
1763 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1764 mmc_hostname(mmc));
1765 return -EIO;
1766 }
1767 }
1768 /* Wait for 5ms */
1769 usleep_range(5000, 5500);
1770
1771 /* 3.3V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (!(ctrl & SDHCI_CTRL_VDD_180))
1774 return 0;
1775
1776 pr_warn("%s: 3.3V regulator output did not became stable\n",
1777 mmc_hostname(mmc));
1778
1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_180:
1781 if (!(host->flags & SDHCI_SIGNALING_180))
1782 return -EINVAL;
1783 if (!IS_ERR(mmc->supply.vqmmc)) {
1784 ret = regulator_set_voltage(mmc->supply.vqmmc,
1785 1700000, 1950000);
1786 if (ret) {
1787 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1788 mmc_hostname(mmc));
1789 return -EIO;
1790 }
1791 }
1792
1793 /*
1794 * Enable 1.8V Signal Enable in the Host Control2
1795 * register
1796 */
1797 ctrl |= SDHCI_CTRL_VDD_180;
1798 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1799
1800 /* Some controller need to do more when switching */
1801 if (host->ops->voltage_switch)
1802 host->ops->voltage_switch(host);
1803
1804 /* 1.8V regulator output should be stable within 5 ms */
1805 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1806 if (ctrl & SDHCI_CTRL_VDD_180)
1807 return 0;
1808
1809 pr_warn("%s: 1.8V regulator output did not became stable\n",
1810 mmc_hostname(mmc));
1811
1812 return -EAGAIN;
1813 case MMC_SIGNAL_VOLTAGE_120:
1814 if (!(host->flags & SDHCI_SIGNALING_120))
1815 return -EINVAL;
1816 if (!IS_ERR(mmc->supply.vqmmc)) {
1817 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1818 1300000);
1819 if (ret) {
1820 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1821 mmc_hostname(mmc));
1822 return -EIO;
1823 }
1824 }
1825 return 0;
1826 default:
1827 /* No signal voltage switch required */
1828 return 0;
1829 }
1830 }
1831
1832 static int sdhci_card_busy(struct mmc_host *mmc)
1833 {
1834 struct sdhci_host *host = mmc_priv(mmc);
1835 u32 present_state;
1836
1837 /* Check whether DAT[0] is 0 */
1838 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1839
1840 return !(present_state & SDHCI_DATA_0_LVL_MASK);
1841 }
1842
1843 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1844 {
1845 struct sdhci_host *host = mmc_priv(mmc);
1846 unsigned long flags;
1847
1848 spin_lock_irqsave(&host->lock, flags);
1849 host->flags |= SDHCI_HS400_TUNING;
1850 spin_unlock_irqrestore(&host->lock, flags);
1851
1852 return 0;
1853 }
1854
1855 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1856 {
1857 struct sdhci_host *host = mmc_priv(mmc);
1858 u16 ctrl;
1859 int tuning_loop_counter = MAX_TUNING_LOOP;
1860 int err = 0;
1861 unsigned long flags;
1862 unsigned int tuning_count = 0;
1863 bool hs400_tuning;
1864
1865 spin_lock_irqsave(&host->lock, flags);
1866
1867 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1868 host->flags &= ~SDHCI_HS400_TUNING;
1869
1870 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1871 tuning_count = host->tuning_count;
1872
1873 /*
1874 * The Host Controller needs tuning in case of SDR104 and DDR50
1875 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1876 * the Capabilities register.
1877 * If the Host Controller supports the HS200 mode then the
1878 * tuning function has to be executed.
1879 */
1880 switch (host->timing) {
1881 /* HS400 tuning is done in HS200 mode */
1882 case MMC_TIMING_MMC_HS400:
1883 err = -EINVAL;
1884 goto out_unlock;
1885
1886 case MMC_TIMING_MMC_HS200:
1887 /*
1888 * Periodic re-tuning for HS400 is not expected to be needed, so
1889 * disable it here.
1890 */
1891 if (hs400_tuning)
1892 tuning_count = 0;
1893 break;
1894
1895 case MMC_TIMING_UHS_SDR104:
1896 case MMC_TIMING_UHS_DDR50:
1897 break;
1898
1899 case MMC_TIMING_UHS_SDR50:
1900 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
1901 break;
1902 /* FALLTHROUGH */
1903
1904 default:
1905 goto out_unlock;
1906 }
1907
1908 if (host->ops->platform_execute_tuning) {
1909 spin_unlock_irqrestore(&host->lock, flags);
1910 err = host->ops->platform_execute_tuning(host, opcode);
1911 return err;
1912 }
1913
1914 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1915 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1916 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1917 ctrl |= SDHCI_CTRL_TUNED_CLK;
1918 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1919
1920 /*
1921 * As per the Host Controller spec v3.00, tuning command
1922 * generates Buffer Read Ready interrupt, so enable that.
1923 *
1924 * Note: The spec clearly says that when tuning sequence
1925 * is being performed, the controller does not generate
1926 * interrupts other than Buffer Read Ready interrupt. But
1927 * to make sure we don't hit a controller bug, we _only_
1928 * enable Buffer Read Ready interrupt here.
1929 */
1930 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1931 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1932
1933 /*
1934 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1935 * of loops reaches 40 times.
1936 */
1937 do {
1938 struct mmc_command cmd = {0};
1939 struct mmc_request mrq = {NULL};
1940
1941 cmd.opcode = opcode;
1942 cmd.arg = 0;
1943 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1944 cmd.retries = 0;
1945 cmd.data = NULL;
1946 cmd.error = 0;
1947
1948 if (tuning_loop_counter-- == 0)
1949 break;
1950
1951 mrq.cmd = &cmd;
1952 host->mrq = &mrq;
1953
1954 /*
1955 * In response to CMD19, the card sends 64 bytes of tuning
1956 * block to the Host Controller. So we set the block size
1957 * to 64 here.
1958 */
1959 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1960 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1961 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1962 SDHCI_BLOCK_SIZE);
1963 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1964 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1965 SDHCI_BLOCK_SIZE);
1966 } else {
1967 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1968 SDHCI_BLOCK_SIZE);
1969 }
1970
1971 /*
1972 * The tuning block is sent by the card to the host controller.
1973 * So we set the TRNS_READ bit in the Transfer Mode register.
1974 * This also takes care of setting DMA Enable and Multi Block
1975 * Select in the same register to 0.
1976 */
1977 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1978
1979 sdhci_send_command(host, &cmd);
1980
1981 host->cmd = NULL;
1982 host->mrq = NULL;
1983
1984 spin_unlock_irqrestore(&host->lock, flags);
1985 /* Wait for Buffer Read Ready interrupt */
1986 wait_event_interruptible_timeout(host->buf_ready_int,
1987 (host->tuning_done == 1),
1988 msecs_to_jiffies(50));
1989 spin_lock_irqsave(&host->lock, flags);
1990
1991 if (!host->tuning_done) {
1992 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
1993 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1994 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1995 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1996 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1997
1998 err = -EIO;
1999 goto out;
2000 }
2001
2002 host->tuning_done = 0;
2003
2004 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2005
2006 /* eMMC spec does not require a delay between tuning cycles */
2007 if (opcode == MMC_SEND_TUNING_BLOCK)
2008 mdelay(1);
2009 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2010
2011 /*
2012 * The Host Driver has exhausted the maximum number of loops allowed,
2013 * so use fixed sampling frequency.
2014 */
2015 if (tuning_loop_counter < 0) {
2016 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2017 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2018 }
2019 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2020 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2021 err = -EIO;
2022 }
2023
2024 out:
2025 if (tuning_count) {
2026 /*
2027 * In case tuning fails, host controllers which support
2028 * re-tuning can try tuning again at a later time, when the
2029 * re-tuning timer expires. So for these controllers, we
2030 * return 0. Since there might be other controllers who do not
2031 * have this capability, we return error for them.
2032 */
2033 err = 0;
2034 }
2035
2036 host->mmc->retune_period = err ? 0 : tuning_count;
2037
2038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2040 out_unlock:
2041 spin_unlock_irqrestore(&host->lock, flags);
2042 return err;
2043 }
2044
2045 static int sdhci_select_drive_strength(struct mmc_card *card,
2046 unsigned int max_dtr, int host_drv,
2047 int card_drv, int *drv_type)
2048 {
2049 struct sdhci_host *host = mmc_priv(card->host);
2050
2051 if (!host->ops->select_drive_strength)
2052 return 0;
2053
2054 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2055 card_drv, drv_type);
2056 }
2057
2058 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2059 {
2060 /* Host Controller v3.00 defines preset value registers */
2061 if (host->version < SDHCI_SPEC_300)
2062 return;
2063
2064 /*
2065 * We only enable or disable Preset Value if they are not already
2066 * enabled or disabled respectively. Otherwise, we bail out.
2067 */
2068 if (host->preset_enabled != enable) {
2069 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2070
2071 if (enable)
2072 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2073 else
2074 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2075
2076 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2077
2078 if (enable)
2079 host->flags |= SDHCI_PV_ENABLED;
2080 else
2081 host->flags &= ~SDHCI_PV_ENABLED;
2082
2083 host->preset_enabled = enable;
2084 }
2085 }
2086
2087 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2088 int err)
2089 {
2090 struct sdhci_host *host = mmc_priv(mmc);
2091 struct mmc_data *data = mrq->data;
2092
2093 if (data->host_cookie != COOKIE_UNMAPPED)
2094 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2095 data->flags & MMC_DATA_WRITE ?
2096 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2097
2098 data->host_cookie = COOKIE_UNMAPPED;
2099 }
2100
2101 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2102 bool is_first_req)
2103 {
2104 struct sdhci_host *host = mmc_priv(mmc);
2105
2106 mrq->data->host_cookie = COOKIE_UNMAPPED;
2107
2108 if (host->flags & SDHCI_REQ_USE_DMA)
2109 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2110 }
2111
2112 static void sdhci_card_event(struct mmc_host *mmc)
2113 {
2114 struct sdhci_host *host = mmc_priv(mmc);
2115 unsigned long flags;
2116 int present;
2117
2118 /* First check if client has provided their own card event */
2119 if (host->ops->card_event)
2120 host->ops->card_event(host);
2121
2122 present = mmc->ops->get_cd(mmc);
2123
2124 spin_lock_irqsave(&host->lock, flags);
2125
2126 /* Check host->mrq first in case we are runtime suspended */
2127 if (host->mrq && !present) {
2128 pr_err("%s: Card removed during transfer!\n",
2129 mmc_hostname(host->mmc));
2130 pr_err("%s: Resetting controller.\n",
2131 mmc_hostname(host->mmc));
2132
2133 sdhci_do_reset(host, SDHCI_RESET_CMD);
2134 sdhci_do_reset(host, SDHCI_RESET_DATA);
2135
2136 host->mrq->cmd->error = -ENOMEDIUM;
2137 tasklet_schedule(&host->finish_tasklet);
2138 }
2139
2140 spin_unlock_irqrestore(&host->lock, flags);
2141 }
2142
2143 static const struct mmc_host_ops sdhci_ops = {
2144 .request = sdhci_request,
2145 .post_req = sdhci_post_req,
2146 .pre_req = sdhci_pre_req,
2147 .set_ios = sdhci_set_ios,
2148 .get_cd = sdhci_get_cd,
2149 .get_ro = sdhci_get_ro,
2150 .hw_reset = sdhci_hw_reset,
2151 .enable_sdio_irq = sdhci_enable_sdio_irq,
2152 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2153 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2154 .execute_tuning = sdhci_execute_tuning,
2155 .select_drive_strength = sdhci_select_drive_strength,
2156 .card_event = sdhci_card_event,
2157 .card_busy = sdhci_card_busy,
2158 };
2159
2160 /*****************************************************************************\
2161 * *
2162 * Tasklets *
2163 * *
2164 \*****************************************************************************/
2165
2166 static void sdhci_tasklet_finish(unsigned long param)
2167 {
2168 struct sdhci_host *host;
2169 unsigned long flags;
2170 struct mmc_request *mrq;
2171
2172 host = (struct sdhci_host*)param;
2173
2174 spin_lock_irqsave(&host->lock, flags);
2175
2176 /*
2177 * If this tasklet gets rescheduled while running, it will
2178 * be run again afterwards but without any active request.
2179 */
2180 if (!host->mrq) {
2181 spin_unlock_irqrestore(&host->lock, flags);
2182 return;
2183 }
2184
2185 del_timer(&host->timer);
2186
2187 mrq = host->mrq;
2188
2189 /*
2190 * Always unmap the data buffers if they were mapped by
2191 * sdhci_prepare_data() whenever we finish with a request.
2192 * This avoids leaking DMA mappings on error.
2193 */
2194 if (host->flags & SDHCI_REQ_USE_DMA) {
2195 struct mmc_data *data = mrq->data;
2196
2197 if (data && data->host_cookie == COOKIE_MAPPED) {
2198 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2199 (data->flags & MMC_DATA_READ) ?
2200 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2201 data->host_cookie = COOKIE_UNMAPPED;
2202 }
2203 }
2204
2205 /*
2206 * The controller needs a reset of internal state machines
2207 * upon error conditions.
2208 */
2209 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2210 ((mrq->cmd && mrq->cmd->error) ||
2211 (mrq->sbc && mrq->sbc->error) ||
2212 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2213 (mrq->data->stop && mrq->data->stop->error))) ||
2214 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2215
2216 /* Some controllers need this kick or reset won't work here */
2217 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2218 /* This is to force an update */
2219 host->ops->set_clock(host, host->clock);
2220
2221 /* Spec says we should do both at the same time, but Ricoh
2222 controllers do not like that. */
2223 sdhci_do_reset(host, SDHCI_RESET_CMD);
2224 sdhci_do_reset(host, SDHCI_RESET_DATA);
2225 }
2226
2227 host->mrq = NULL;
2228 host->cmd = NULL;
2229 host->data = NULL;
2230 host->data_cmd = NULL;
2231
2232 sdhci_led_deactivate(host);
2233
2234 mmiowb();
2235 spin_unlock_irqrestore(&host->lock, flags);
2236
2237 mmc_request_done(host->mmc, mrq);
2238 }
2239
2240 static void sdhci_timeout_timer(unsigned long data)
2241 {
2242 struct sdhci_host *host;
2243 unsigned long flags;
2244
2245 host = (struct sdhci_host*)data;
2246
2247 spin_lock_irqsave(&host->lock, flags);
2248
2249 if (host->mrq) {
2250 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2251 mmc_hostname(host->mmc));
2252 sdhci_dumpregs(host);
2253
2254 if (host->data) {
2255 host->data->error = -ETIMEDOUT;
2256 sdhci_finish_data(host);
2257 } else {
2258 if (host->cmd)
2259 host->cmd->error = -ETIMEDOUT;
2260 else
2261 host->mrq->cmd->error = -ETIMEDOUT;
2262
2263 tasklet_schedule(&host->finish_tasklet);
2264 }
2265 }
2266
2267 mmiowb();
2268 spin_unlock_irqrestore(&host->lock, flags);
2269 }
2270
2271 /*****************************************************************************\
2272 * *
2273 * Interrupt handling *
2274 * *
2275 \*****************************************************************************/
2276
2277 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2278 {
2279 if (!host->cmd) {
2280 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2281 mmc_hostname(host->mmc), (unsigned)intmask);
2282 sdhci_dumpregs(host);
2283 return;
2284 }
2285
2286 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2287 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2288 if (intmask & SDHCI_INT_TIMEOUT)
2289 host->cmd->error = -ETIMEDOUT;
2290 else
2291 host->cmd->error = -EILSEQ;
2292
2293 /*
2294 * If this command initiates a data phase and a response
2295 * CRC error is signalled, the card can start transferring
2296 * data - the card may have received the command without
2297 * error. We must not terminate the mmc_request early.
2298 *
2299 * If the card did not receive the command or returned an
2300 * error which prevented it sending data, the data phase
2301 * will time out.
2302 */
2303 if (host->cmd->data &&
2304 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2305 SDHCI_INT_CRC) {
2306 host->cmd = NULL;
2307 return;
2308 }
2309
2310 tasklet_schedule(&host->finish_tasklet);
2311 return;
2312 }
2313
2314 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2315 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2316 host->cmd->opcode == MMC_STOP_TRANSMISSION)
2317 *mask &= ~SDHCI_INT_DATA_END;
2318
2319 if (intmask & SDHCI_INT_RESPONSE)
2320 sdhci_finish_command(host);
2321 }
2322
2323 #ifdef CONFIG_MMC_DEBUG
2324 static void sdhci_adma_show_error(struct sdhci_host *host)
2325 {
2326 const char *name = mmc_hostname(host->mmc);
2327 void *desc = host->adma_table;
2328
2329 sdhci_dumpregs(host);
2330
2331 while (true) {
2332 struct sdhci_adma2_64_desc *dma_desc = desc;
2333
2334 if (host->flags & SDHCI_USE_64_BIT_DMA)
2335 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2336 name, desc, le32_to_cpu(dma_desc->addr_hi),
2337 le32_to_cpu(dma_desc->addr_lo),
2338 le16_to_cpu(dma_desc->len),
2339 le16_to_cpu(dma_desc->cmd));
2340 else
2341 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2342 name, desc, le32_to_cpu(dma_desc->addr_lo),
2343 le16_to_cpu(dma_desc->len),
2344 le16_to_cpu(dma_desc->cmd));
2345
2346 desc += host->desc_sz;
2347
2348 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2349 break;
2350 }
2351 }
2352 #else
2353 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2354 #endif
2355
2356 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2357 {
2358 u32 command;
2359
2360 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2361 if (intmask & SDHCI_INT_DATA_AVAIL) {
2362 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2363 if (command == MMC_SEND_TUNING_BLOCK ||
2364 command == MMC_SEND_TUNING_BLOCK_HS200) {
2365 host->tuning_done = 1;
2366 wake_up(&host->buf_ready_int);
2367 return;
2368 }
2369 }
2370
2371 if (!host->data) {
2372 struct mmc_command *data_cmd = host->data_cmd;
2373
2374 if (data_cmd)
2375 host->data_cmd = NULL;
2376
2377 /*
2378 * The "data complete" interrupt is also used to
2379 * indicate that a busy state has ended. See comment
2380 * above in sdhci_cmd_irq().
2381 */
2382 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2383 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2384 data_cmd->error = -ETIMEDOUT;
2385 tasklet_schedule(&host->finish_tasklet);
2386 return;
2387 }
2388 if (intmask & SDHCI_INT_DATA_END) {
2389 /*
2390 * Some cards handle busy-end interrupt
2391 * before the command completed, so make
2392 * sure we do things in the proper order.
2393 */
2394 if (host->cmd == data_cmd)
2395 return;
2396
2397 tasklet_schedule(&host->finish_tasklet);
2398 return;
2399 }
2400 }
2401
2402 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2403 mmc_hostname(host->mmc), (unsigned)intmask);
2404 sdhci_dumpregs(host);
2405
2406 return;
2407 }
2408
2409 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2410 host->data->error = -ETIMEDOUT;
2411 else if (intmask & SDHCI_INT_DATA_END_BIT)
2412 host->data->error = -EILSEQ;
2413 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2414 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2415 != MMC_BUS_TEST_R)
2416 host->data->error = -EILSEQ;
2417 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2418 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2419 sdhci_adma_show_error(host);
2420 host->data->error = -EIO;
2421 if (host->ops->adma_workaround)
2422 host->ops->adma_workaround(host, intmask);
2423 }
2424
2425 if (host->data->error)
2426 sdhci_finish_data(host);
2427 else {
2428 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2429 sdhci_transfer_pio(host);
2430
2431 /*
2432 * We currently don't do anything fancy with DMA
2433 * boundaries, but as we can't disable the feature
2434 * we need to at least restart the transfer.
2435 *
2436 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2437 * should return a valid address to continue from, but as
2438 * some controllers are faulty, don't trust them.
2439 */
2440 if (intmask & SDHCI_INT_DMA_END) {
2441 u32 dmastart, dmanow;
2442 dmastart = sg_dma_address(host->data->sg);
2443 dmanow = dmastart + host->data->bytes_xfered;
2444 /*
2445 * Force update to the next DMA block boundary.
2446 */
2447 dmanow = (dmanow &
2448 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2449 SDHCI_DEFAULT_BOUNDARY_SIZE;
2450 host->data->bytes_xfered = dmanow - dmastart;
2451 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2452 " next 0x%08x\n",
2453 mmc_hostname(host->mmc), dmastart,
2454 host->data->bytes_xfered, dmanow);
2455 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2456 }
2457
2458 if (intmask & SDHCI_INT_DATA_END) {
2459 if (host->cmd == host->data_cmd) {
2460 /*
2461 * Data managed to finish before the
2462 * command completed. Make sure we do
2463 * things in the proper order.
2464 */
2465 host->data_early = 1;
2466 } else {
2467 sdhci_finish_data(host);
2468 }
2469 }
2470 }
2471 }
2472
2473 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2474 {
2475 irqreturn_t result = IRQ_NONE;
2476 struct sdhci_host *host = dev_id;
2477 u32 intmask, mask, unexpected = 0;
2478 int max_loops = 16;
2479
2480 spin_lock(&host->lock);
2481
2482 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2483 spin_unlock(&host->lock);
2484 return IRQ_NONE;
2485 }
2486
2487 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2488 if (!intmask || intmask == 0xffffffff) {
2489 result = IRQ_NONE;
2490 goto out;
2491 }
2492
2493 do {
2494 /* Clear selected interrupts. */
2495 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2496 SDHCI_INT_BUS_POWER);
2497 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2498
2499 DBG("*** %s got interrupt: 0x%08x\n",
2500 mmc_hostname(host->mmc), intmask);
2501
2502 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2503 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2504 SDHCI_CARD_PRESENT;
2505
2506 /*
2507 * There is a observation on i.mx esdhc. INSERT
2508 * bit will be immediately set again when it gets
2509 * cleared, if a card is inserted. We have to mask
2510 * the irq to prevent interrupt storm which will
2511 * freeze the system. And the REMOVE gets the
2512 * same situation.
2513 *
2514 * More testing are needed here to ensure it works
2515 * for other platforms though.
2516 */
2517 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2518 SDHCI_INT_CARD_REMOVE);
2519 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2520 SDHCI_INT_CARD_INSERT;
2521 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2522 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2523
2524 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2525 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2526
2527 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2528 SDHCI_INT_CARD_REMOVE);
2529 result = IRQ_WAKE_THREAD;
2530 }
2531
2532 if (intmask & SDHCI_INT_CMD_MASK)
2533 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2534 &intmask);
2535
2536 if (intmask & SDHCI_INT_DATA_MASK)
2537 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2538
2539 if (intmask & SDHCI_INT_BUS_POWER)
2540 pr_err("%s: Card is consuming too much power!\n",
2541 mmc_hostname(host->mmc));
2542
2543 if (intmask & SDHCI_INT_CARD_INT) {
2544 sdhci_enable_sdio_irq_nolock(host, false);
2545 host->thread_isr |= SDHCI_INT_CARD_INT;
2546 result = IRQ_WAKE_THREAD;
2547 }
2548
2549 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2550 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2551 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2552 SDHCI_INT_CARD_INT);
2553
2554 if (intmask) {
2555 unexpected |= intmask;
2556 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2557 }
2558
2559 if (result == IRQ_NONE)
2560 result = IRQ_HANDLED;
2561
2562 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2563 } while (intmask && --max_loops);
2564 out:
2565 spin_unlock(&host->lock);
2566
2567 if (unexpected) {
2568 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2569 mmc_hostname(host->mmc), unexpected);
2570 sdhci_dumpregs(host);
2571 }
2572
2573 return result;
2574 }
2575
2576 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2577 {
2578 struct sdhci_host *host = dev_id;
2579 unsigned long flags;
2580 u32 isr;
2581
2582 spin_lock_irqsave(&host->lock, flags);
2583 isr = host->thread_isr;
2584 host->thread_isr = 0;
2585 spin_unlock_irqrestore(&host->lock, flags);
2586
2587 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2588 struct mmc_host *mmc = host->mmc;
2589
2590 mmc->ops->card_event(mmc);
2591 mmc_detect_change(mmc, msecs_to_jiffies(200));
2592 }
2593
2594 if (isr & SDHCI_INT_CARD_INT) {
2595 sdio_run_irqs(host->mmc);
2596
2597 spin_lock_irqsave(&host->lock, flags);
2598 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2599 sdhci_enable_sdio_irq_nolock(host, true);
2600 spin_unlock_irqrestore(&host->lock, flags);
2601 }
2602
2603 return isr ? IRQ_HANDLED : IRQ_NONE;
2604 }
2605
2606 /*****************************************************************************\
2607 * *
2608 * Suspend/resume *
2609 * *
2610 \*****************************************************************************/
2611
2612 #ifdef CONFIG_PM
2613 /*
2614 * To enable wakeup events, the corresponding events have to be enabled in
2615 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2616 * Table' in the SD Host Controller Standard Specification.
2617 * It is useless to restore SDHCI_INT_ENABLE state in
2618 * sdhci_disable_irq_wakeups() since it will be set by
2619 * sdhci_enable_card_detection() or sdhci_init().
2620 */
2621 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2622 {
2623 u8 val;
2624 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2625 | SDHCI_WAKE_ON_INT;
2626 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2627 SDHCI_INT_CARD_INT;
2628
2629 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2630 val |= mask ;
2631 /* Avoid fake wake up */
2632 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2633 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2634 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2635 }
2636 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2637 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2638 }
2639 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2640
2641 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2642 {
2643 u8 val;
2644 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2645 | SDHCI_WAKE_ON_INT;
2646
2647 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2648 val &= ~mask;
2649 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2650 }
2651
2652 int sdhci_suspend_host(struct sdhci_host *host)
2653 {
2654 sdhci_disable_card_detection(host);
2655
2656 mmc_retune_timer_stop(host->mmc);
2657 mmc_retune_needed(host->mmc);
2658
2659 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2660 host->ier = 0;
2661 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2662 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2663 free_irq(host->irq, host);
2664 } else {
2665 sdhci_enable_irq_wakeups(host);
2666 enable_irq_wake(host->irq);
2667 }
2668 return 0;
2669 }
2670
2671 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2672
2673 int sdhci_resume_host(struct sdhci_host *host)
2674 {
2675 struct mmc_host *mmc = host->mmc;
2676 int ret = 0;
2677
2678 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2679 if (host->ops->enable_dma)
2680 host->ops->enable_dma(host);
2681 }
2682
2683 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2684 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2685 /* Card keeps power but host controller does not */
2686 sdhci_init(host, 0);
2687 host->pwr = 0;
2688 host->clock = 0;
2689 mmc->ops->set_ios(mmc, &mmc->ios);
2690 } else {
2691 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2692 mmiowb();
2693 }
2694
2695 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2696 ret = request_threaded_irq(host->irq, sdhci_irq,
2697 sdhci_thread_irq, IRQF_SHARED,
2698 mmc_hostname(host->mmc), host);
2699 if (ret)
2700 return ret;
2701 } else {
2702 sdhci_disable_irq_wakeups(host);
2703 disable_irq_wake(host->irq);
2704 }
2705
2706 sdhci_enable_card_detection(host);
2707
2708 return ret;
2709 }
2710
2711 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2712
2713 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2714 {
2715 unsigned long flags;
2716
2717 mmc_retune_timer_stop(host->mmc);
2718 mmc_retune_needed(host->mmc);
2719
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->ier &= SDHCI_INT_CARD_INT;
2722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2724 spin_unlock_irqrestore(&host->lock, flags);
2725
2726 synchronize_hardirq(host->irq);
2727
2728 spin_lock_irqsave(&host->lock, flags);
2729 host->runtime_suspended = true;
2730 spin_unlock_irqrestore(&host->lock, flags);
2731
2732 return 0;
2733 }
2734 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2735
2736 int sdhci_runtime_resume_host(struct sdhci_host *host)
2737 {
2738 struct mmc_host *mmc = host->mmc;
2739 unsigned long flags;
2740 int host_flags = host->flags;
2741
2742 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2743 if (host->ops->enable_dma)
2744 host->ops->enable_dma(host);
2745 }
2746
2747 sdhci_init(host, 0);
2748
2749 /* Force clock and power re-program */
2750 host->pwr = 0;
2751 host->clock = 0;
2752 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2753 mmc->ops->set_ios(mmc, &mmc->ios);
2754
2755 if ((host_flags & SDHCI_PV_ENABLED) &&
2756 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2757 spin_lock_irqsave(&host->lock, flags);
2758 sdhci_enable_preset_value(host, true);
2759 spin_unlock_irqrestore(&host->lock, flags);
2760 }
2761
2762 spin_lock_irqsave(&host->lock, flags);
2763
2764 host->runtime_suspended = false;
2765
2766 /* Enable SDIO IRQ */
2767 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2768 sdhci_enable_sdio_irq_nolock(host, true);
2769
2770 /* Enable Card Detection */
2771 sdhci_enable_card_detection(host);
2772
2773 spin_unlock_irqrestore(&host->lock, flags);
2774
2775 return 0;
2776 }
2777 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2778
2779 #endif /* CONFIG_PM */
2780
2781 /*****************************************************************************\
2782 * *
2783 * Device allocation/registration *
2784 * *
2785 \*****************************************************************************/
2786
2787 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2788 size_t priv_size)
2789 {
2790 struct mmc_host *mmc;
2791 struct sdhci_host *host;
2792
2793 WARN_ON(dev == NULL);
2794
2795 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2796 if (!mmc)
2797 return ERR_PTR(-ENOMEM);
2798
2799 host = mmc_priv(mmc);
2800 host->mmc = mmc;
2801 host->mmc_host_ops = sdhci_ops;
2802 mmc->ops = &host->mmc_host_ops;
2803
2804 host->flags = SDHCI_SIGNALING_330;
2805
2806 return host;
2807 }
2808
2809 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2810
2811 static int sdhci_set_dma_mask(struct sdhci_host *host)
2812 {
2813 struct mmc_host *mmc = host->mmc;
2814 struct device *dev = mmc_dev(mmc);
2815 int ret = -EINVAL;
2816
2817 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2818 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2819
2820 /* Try 64-bit mask if hardware is capable of it */
2821 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2822 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2823 if (ret) {
2824 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2825 mmc_hostname(mmc));
2826 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2827 }
2828 }
2829
2830 /* 32-bit mask as default & fallback */
2831 if (ret) {
2832 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2833 if (ret)
2834 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2835 mmc_hostname(mmc));
2836 }
2837
2838 return ret;
2839 }
2840
2841 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2842 {
2843 u16 v;
2844
2845 if (host->read_caps)
2846 return;
2847
2848 host->read_caps = true;
2849
2850 if (debug_quirks)
2851 host->quirks = debug_quirks;
2852
2853 if (debug_quirks2)
2854 host->quirks2 = debug_quirks2;
2855
2856 sdhci_do_reset(host, SDHCI_RESET_ALL);
2857
2858 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2859 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2860
2861 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2862 return;
2863
2864 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2865
2866 if (host->version < SDHCI_SPEC_300)
2867 return;
2868
2869 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2870 }
2871 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2872
2873 int sdhci_setup_host(struct sdhci_host *host)
2874 {
2875 struct mmc_host *mmc;
2876 u32 max_current_caps;
2877 unsigned int ocr_avail;
2878 unsigned int override_timeout_clk;
2879 u32 max_clk;
2880 int ret;
2881
2882 WARN_ON(host == NULL);
2883 if (host == NULL)
2884 return -EINVAL;
2885
2886 mmc = host->mmc;
2887
2888 sdhci_read_caps(host);
2889
2890 override_timeout_clk = host->timeout_clk;
2891
2892 if (host->version > SDHCI_SPEC_300) {
2893 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2894 mmc_hostname(mmc), host->version);
2895 }
2896
2897 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2898 host->flags |= SDHCI_USE_SDMA;
2899 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
2900 DBG("Controller doesn't have SDMA capability\n");
2901 else
2902 host->flags |= SDHCI_USE_SDMA;
2903
2904 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2905 (host->flags & SDHCI_USE_SDMA)) {
2906 DBG("Disabling DMA as it is marked broken\n");
2907 host->flags &= ~SDHCI_USE_SDMA;
2908 }
2909
2910 if ((host->version >= SDHCI_SPEC_200) &&
2911 (host->caps & SDHCI_CAN_DO_ADMA2))
2912 host->flags |= SDHCI_USE_ADMA;
2913
2914 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2915 (host->flags & SDHCI_USE_ADMA)) {
2916 DBG("Disabling ADMA as it is marked broken\n");
2917 host->flags &= ~SDHCI_USE_ADMA;
2918 }
2919
2920 /*
2921 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2922 * and *must* do 64-bit DMA. A driver has the opportunity to change
2923 * that during the first call to ->enable_dma(). Similarly
2924 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2925 * implement.
2926 */
2927 if (host->caps & SDHCI_CAN_64BIT)
2928 host->flags |= SDHCI_USE_64_BIT_DMA;
2929
2930 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2931 ret = sdhci_set_dma_mask(host);
2932
2933 if (!ret && host->ops->enable_dma)
2934 ret = host->ops->enable_dma(host);
2935
2936 if (ret) {
2937 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2938 mmc_hostname(mmc));
2939 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2940
2941 ret = 0;
2942 }
2943 }
2944
2945 /* SDMA does not support 64-bit DMA */
2946 if (host->flags & SDHCI_USE_64_BIT_DMA)
2947 host->flags &= ~SDHCI_USE_SDMA;
2948
2949 if (host->flags & SDHCI_USE_ADMA) {
2950 dma_addr_t dma;
2951 void *buf;
2952
2953 /*
2954 * The DMA descriptor table size is calculated as the maximum
2955 * number of segments times 2, to allow for an alignment
2956 * descriptor for each segment, plus 1 for a nop end descriptor,
2957 * all multipled by the descriptor size.
2958 */
2959 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2960 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2961 SDHCI_ADMA2_64_DESC_SZ;
2962 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2963 } else {
2964 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2965 SDHCI_ADMA2_32_DESC_SZ;
2966 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2967 }
2968
2969 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2970 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2971 host->adma_table_sz, &dma, GFP_KERNEL);
2972 if (!buf) {
2973 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2974 mmc_hostname(mmc));
2975 host->flags &= ~SDHCI_USE_ADMA;
2976 } else if ((dma + host->align_buffer_sz) &
2977 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2978 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2979 mmc_hostname(mmc));
2980 host->flags &= ~SDHCI_USE_ADMA;
2981 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2982 host->adma_table_sz, buf, dma);
2983 } else {
2984 host->align_buffer = buf;
2985 host->align_addr = dma;
2986
2987 host->adma_table = buf + host->align_buffer_sz;
2988 host->adma_addr = dma + host->align_buffer_sz;
2989 }
2990 }
2991
2992 /*
2993 * If we use DMA, then it's up to the caller to set the DMA
2994 * mask, but PIO does not need the hw shim so we set a new
2995 * mask here in that case.
2996 */
2997 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2998 host->dma_mask = DMA_BIT_MASK(64);
2999 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3000 }
3001
3002 if (host->version >= SDHCI_SPEC_300)
3003 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3004 >> SDHCI_CLOCK_BASE_SHIFT;
3005 else
3006 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3007 >> SDHCI_CLOCK_BASE_SHIFT;
3008
3009 host->max_clk *= 1000000;
3010 if (host->max_clk == 0 || host->quirks &
3011 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3012 if (!host->ops->get_max_clock) {
3013 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3014 mmc_hostname(mmc));
3015 ret = -ENODEV;
3016 goto undma;
3017 }
3018 host->max_clk = host->ops->get_max_clock(host);
3019 }
3020
3021 /*
3022 * In case of Host Controller v3.00, find out whether clock
3023 * multiplier is supported.
3024 */
3025 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3026 SDHCI_CLOCK_MUL_SHIFT;
3027
3028 /*
3029 * In case the value in Clock Multiplier is 0, then programmable
3030 * clock mode is not supported, otherwise the actual clock
3031 * multiplier is one more than the value of Clock Multiplier
3032 * in the Capabilities Register.
3033 */
3034 if (host->clk_mul)
3035 host->clk_mul += 1;
3036
3037 /*
3038 * Set host parameters.
3039 */
3040 max_clk = host->max_clk;
3041
3042 if (host->ops->get_min_clock)
3043 mmc->f_min = host->ops->get_min_clock(host);
3044 else if (host->version >= SDHCI_SPEC_300) {
3045 if (host->clk_mul) {
3046 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3047 max_clk = host->max_clk * host->clk_mul;
3048 } else
3049 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3050 } else
3051 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3052
3053 if (!mmc->f_max || mmc->f_max > max_clk)
3054 mmc->f_max = max_clk;
3055
3056 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3057 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3058 SDHCI_TIMEOUT_CLK_SHIFT;
3059 if (host->timeout_clk == 0) {
3060 if (host->ops->get_timeout_clock) {
3061 host->timeout_clk =
3062 host->ops->get_timeout_clock(host);
3063 } else {
3064 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3065 mmc_hostname(mmc));
3066 ret = -ENODEV;
3067 goto undma;
3068 }
3069 }
3070
3071 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3072 host->timeout_clk *= 1000;
3073
3074 if (override_timeout_clk)
3075 host->timeout_clk = override_timeout_clk;
3076
3077 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3078 host->ops->get_max_timeout_count(host) : 1 << 27;
3079 mmc->max_busy_timeout /= host->timeout_clk;
3080 }
3081
3082 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3083 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3084
3085 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3086 host->flags |= SDHCI_AUTO_CMD12;
3087
3088 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3089 if ((host->version >= SDHCI_SPEC_300) &&
3090 ((host->flags & SDHCI_USE_ADMA) ||
3091 !(host->flags & SDHCI_USE_SDMA)) &&
3092 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3093 host->flags |= SDHCI_AUTO_CMD23;
3094 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3095 } else {
3096 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3097 }
3098
3099 /*
3100 * A controller may support 8-bit width, but the board itself
3101 * might not have the pins brought out. Boards that support
3102 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3103 * their platform code before calling sdhci_add_host(), and we
3104 * won't assume 8-bit width for hosts without that CAP.
3105 */
3106 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3107 mmc->caps |= MMC_CAP_4_BIT_DATA;
3108
3109 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3110 mmc->caps &= ~MMC_CAP_CMD23;
3111
3112 if (host->caps & SDHCI_CAN_DO_HISPD)
3113 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3114
3115 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3116 mmc_card_is_removable(mmc) &&
3117 mmc_gpio_get_cd(host->mmc) < 0)
3118 mmc->caps |= MMC_CAP_NEEDS_POLL;
3119
3120 /* If there are external regulators, get them */
3121 ret = mmc_regulator_get_supply(mmc);
3122 if (ret == -EPROBE_DEFER)
3123 goto undma;
3124
3125 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3126 if (!IS_ERR(mmc->supply.vqmmc)) {
3127 ret = regulator_enable(mmc->supply.vqmmc);
3128 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3129 1950000))
3130 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3131 SDHCI_SUPPORT_SDR50 |
3132 SDHCI_SUPPORT_DDR50);
3133 if (ret) {
3134 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3135 mmc_hostname(mmc), ret);
3136 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3137 }
3138 }
3139
3140 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3141 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3142 SDHCI_SUPPORT_DDR50);
3143 }
3144
3145 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3146 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3147 SDHCI_SUPPORT_DDR50))
3148 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3149
3150 /* SDR104 supports also implies SDR50 support */
3151 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3152 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3153 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3154 * field can be promoted to support HS200.
3155 */
3156 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3157 mmc->caps2 |= MMC_CAP2_HS200;
3158 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3159 mmc->caps |= MMC_CAP_UHS_SDR50;
3160 }
3161
3162 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3163 (host->caps1 & SDHCI_SUPPORT_HS400))
3164 mmc->caps2 |= MMC_CAP2_HS400;
3165
3166 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3167 (IS_ERR(mmc->supply.vqmmc) ||
3168 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3169 1300000)))
3170 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3171
3172 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3173 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3174 mmc->caps |= MMC_CAP_UHS_DDR50;
3175
3176 /* Does the host need tuning for SDR50? */
3177 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3178 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3179
3180 /* Driver Type(s) (A, C, D) supported by the host */
3181 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3182 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3183 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3184 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3185 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3186 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3187
3188 /* Initial value for re-tuning timer count */
3189 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3190 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3191
3192 /*
3193 * In case Re-tuning Timer is not disabled, the actual value of
3194 * re-tuning timer will be 2 ^ (n - 1).
3195 */
3196 if (host->tuning_count)
3197 host->tuning_count = 1 << (host->tuning_count - 1);
3198
3199 /* Re-tuning mode supported by the Host Controller */
3200 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3201 SDHCI_RETUNING_MODE_SHIFT;
3202
3203 ocr_avail = 0;
3204
3205 /*
3206 * According to SD Host Controller spec v3.00, if the Host System
3207 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3208 * the value is meaningful only if Voltage Support in the Capabilities
3209 * register is set. The actual current value is 4 times the register
3210 * value.
3211 */
3212 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3213 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3214 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3215 if (curr > 0) {
3216
3217 /* convert to SDHCI_MAX_CURRENT format */
3218 curr = curr/1000; /* convert to mA */
3219 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3220
3221 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3222 max_current_caps =
3223 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3224 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3225 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3226 }
3227 }
3228
3229 if (host->caps & SDHCI_CAN_VDD_330) {
3230 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3231
3232 mmc->max_current_330 = ((max_current_caps &
3233 SDHCI_MAX_CURRENT_330_MASK) >>
3234 SDHCI_MAX_CURRENT_330_SHIFT) *
3235 SDHCI_MAX_CURRENT_MULTIPLIER;
3236 }
3237 if (host->caps & SDHCI_CAN_VDD_300) {
3238 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3239
3240 mmc->max_current_300 = ((max_current_caps &
3241 SDHCI_MAX_CURRENT_300_MASK) >>
3242 SDHCI_MAX_CURRENT_300_SHIFT) *
3243 SDHCI_MAX_CURRENT_MULTIPLIER;
3244 }
3245 if (host->caps & SDHCI_CAN_VDD_180) {
3246 ocr_avail |= MMC_VDD_165_195;
3247
3248 mmc->max_current_180 = ((max_current_caps &
3249 SDHCI_MAX_CURRENT_180_MASK) >>
3250 SDHCI_MAX_CURRENT_180_SHIFT) *
3251 SDHCI_MAX_CURRENT_MULTIPLIER;
3252 }
3253
3254 /* If OCR set by host, use it instead. */
3255 if (host->ocr_mask)
3256 ocr_avail = host->ocr_mask;
3257
3258 /* If OCR set by external regulators, give it highest prio. */
3259 if (mmc->ocr_avail)
3260 ocr_avail = mmc->ocr_avail;
3261
3262 mmc->ocr_avail = ocr_avail;
3263 mmc->ocr_avail_sdio = ocr_avail;
3264 if (host->ocr_avail_sdio)
3265 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3266 mmc->ocr_avail_sd = ocr_avail;
3267 if (host->ocr_avail_sd)
3268 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3269 else /* normal SD controllers don't support 1.8V */
3270 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3271 mmc->ocr_avail_mmc = ocr_avail;
3272 if (host->ocr_avail_mmc)
3273 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3274
3275 if (mmc->ocr_avail == 0) {
3276 pr_err("%s: Hardware doesn't report any support voltages.\n",
3277 mmc_hostname(mmc));
3278 ret = -ENODEV;
3279 goto unreg;
3280 }
3281
3282 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3283 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3284 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3285 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3286 host->flags |= SDHCI_SIGNALING_180;
3287
3288 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3289 host->flags |= SDHCI_SIGNALING_120;
3290
3291 spin_lock_init(&host->lock);
3292
3293 /*
3294 * Maximum number of segments. Depends on if the hardware
3295 * can do scatter/gather or not.
3296 */
3297 if (host->flags & SDHCI_USE_ADMA)
3298 mmc->max_segs = SDHCI_MAX_SEGS;
3299 else if (host->flags & SDHCI_USE_SDMA)
3300 mmc->max_segs = 1;
3301 else /* PIO */
3302 mmc->max_segs = SDHCI_MAX_SEGS;
3303
3304 /*
3305 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3306 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3307 * is less anyway.
3308 */
3309 mmc->max_req_size = 524288;
3310
3311 /*
3312 * Maximum segment size. Could be one segment with the maximum number
3313 * of bytes. When doing hardware scatter/gather, each entry cannot
3314 * be larger than 64 KiB though.
3315 */
3316 if (host->flags & SDHCI_USE_ADMA) {
3317 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3318 mmc->max_seg_size = 65535;
3319 else
3320 mmc->max_seg_size = 65536;
3321 } else {
3322 mmc->max_seg_size = mmc->max_req_size;
3323 }
3324
3325 /*
3326 * Maximum block size. This varies from controller to controller and
3327 * is specified in the capabilities register.
3328 */
3329 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3330 mmc->max_blk_size = 2;
3331 } else {
3332 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3333 SDHCI_MAX_BLOCK_SHIFT;
3334 if (mmc->max_blk_size >= 3) {
3335 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3336 mmc_hostname(mmc));
3337 mmc->max_blk_size = 0;
3338 }
3339 }
3340
3341 mmc->max_blk_size = 512 << mmc->max_blk_size;
3342
3343 /*
3344 * Maximum block count.
3345 */
3346 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3347
3348 return 0;
3349
3350 unreg:
3351 if (!IS_ERR(mmc->supply.vqmmc))
3352 regulator_disable(mmc->supply.vqmmc);
3353 undma:
3354 if (host->align_buffer)
3355 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3356 host->adma_table_sz, host->align_buffer,
3357 host->align_addr);
3358 host->adma_table = NULL;
3359 host->align_buffer = NULL;
3360
3361 return ret;
3362 }
3363 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3364
3365 int __sdhci_add_host(struct sdhci_host *host)
3366 {
3367 struct mmc_host *mmc = host->mmc;
3368 int ret;
3369
3370 /*
3371 * Init tasklets.
3372 */
3373 tasklet_init(&host->finish_tasklet,
3374 sdhci_tasklet_finish, (unsigned long)host);
3375
3376 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3377
3378 init_waitqueue_head(&host->buf_ready_int);
3379
3380 sdhci_init(host, 0);
3381
3382 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3383 IRQF_SHARED, mmc_hostname(mmc), host);
3384 if (ret) {
3385 pr_err("%s: Failed to request IRQ %d: %d\n",
3386 mmc_hostname(mmc), host->irq, ret);
3387 goto untasklet;
3388 }
3389
3390 #ifdef CONFIG_MMC_DEBUG
3391 sdhci_dumpregs(host);
3392 #endif
3393
3394 ret = sdhci_led_register(host);
3395 if (ret) {
3396 pr_err("%s: Failed to register LED device: %d\n",
3397 mmc_hostname(mmc), ret);
3398 goto unirq;
3399 }
3400
3401 mmiowb();
3402
3403 ret = mmc_add_host(mmc);
3404 if (ret)
3405 goto unled;
3406
3407 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3408 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3409 (host->flags & SDHCI_USE_ADMA) ?
3410 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3411 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3412
3413 sdhci_enable_card_detection(host);
3414
3415 return 0;
3416
3417 unled:
3418 sdhci_led_unregister(host);
3419 unirq:
3420 sdhci_do_reset(host, SDHCI_RESET_ALL);
3421 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3422 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3423 free_irq(host->irq, host);
3424 untasklet:
3425 tasklet_kill(&host->finish_tasklet);
3426
3427 if (!IS_ERR(mmc->supply.vqmmc))
3428 regulator_disable(mmc->supply.vqmmc);
3429
3430 if (host->align_buffer)
3431 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3432 host->adma_table_sz, host->align_buffer,
3433 host->align_addr);
3434 host->adma_table = NULL;
3435 host->align_buffer = NULL;
3436
3437 return ret;
3438 }
3439 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3440
3441 int sdhci_add_host(struct sdhci_host *host)
3442 {
3443 int ret;
3444
3445 ret = sdhci_setup_host(host);
3446 if (ret)
3447 return ret;
3448
3449 return __sdhci_add_host(host);
3450 }
3451 EXPORT_SYMBOL_GPL(sdhci_add_host);
3452
3453 void sdhci_remove_host(struct sdhci_host *host, int dead)
3454 {
3455 struct mmc_host *mmc = host->mmc;
3456 unsigned long flags;
3457
3458 if (dead) {
3459 spin_lock_irqsave(&host->lock, flags);
3460
3461 host->flags |= SDHCI_DEVICE_DEAD;
3462
3463 if (host->mrq) {
3464 pr_err("%s: Controller removed during "
3465 " transfer!\n", mmc_hostname(mmc));
3466
3467 host->mrq->cmd->error = -ENOMEDIUM;
3468 tasklet_schedule(&host->finish_tasklet);
3469 }
3470
3471 spin_unlock_irqrestore(&host->lock, flags);
3472 }
3473
3474 sdhci_disable_card_detection(host);
3475
3476 mmc_remove_host(mmc);
3477
3478 sdhci_led_unregister(host);
3479
3480 if (!dead)
3481 sdhci_do_reset(host, SDHCI_RESET_ALL);
3482
3483 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3484 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3485 free_irq(host->irq, host);
3486
3487 del_timer_sync(&host->timer);
3488
3489 tasklet_kill(&host->finish_tasklet);
3490
3491 if (!IS_ERR(mmc->supply.vqmmc))
3492 regulator_disable(mmc->supply.vqmmc);
3493
3494 if (host->align_buffer)
3495 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3496 host->adma_table_sz, host->align_buffer,
3497 host->align_addr);
3498
3499 host->adma_table = NULL;
3500 host->align_buffer = NULL;
3501 }
3502
3503 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3504
3505 void sdhci_free_host(struct sdhci_host *host)
3506 {
3507 mmc_free_host(host->mmc);
3508 }
3509
3510 EXPORT_SYMBOL_GPL(sdhci_free_host);
3511
3512 /*****************************************************************************\
3513 * *
3514 * Driver init/exit *
3515 * *
3516 \*****************************************************************************/
3517
3518 static int __init sdhci_drv_init(void)
3519 {
3520 pr_info(DRIVER_NAME
3521 ": Secure Digital Host Controller Interface driver\n");
3522 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3523
3524 return 0;
3525 }
3526
3527 static void __exit sdhci_drv_exit(void)
3528 {
3529 }
3530
3531 module_init(sdhci_drv_init);
3532 module_exit(sdhci_drv_exit);
3533
3534 module_param(debug_quirks, uint, 0444);
3535 module_param(debug_quirks2, uint, 0444);
3536
3537 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3538 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3539 MODULE_LICENSE("GPL");
3540
3541 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3542 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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