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mmc: sdhci: Fix incorrect switch to HS mode
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/ktime.h>
18 #include <linux/highmem.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/sizes.h>
25 #include <linux/swiotlb.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/of.h>
29
30 #include <linux/leds.h>
31
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/sdio.h>
36 #include <linux/mmc/slot-gpio.h>
37
38 #include "sdhci.h"
39
40 #define DRIVER_NAME "sdhci"
41
42 #define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45 #define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48 #define MAX_TUNING_LOOP 40
49
50 static unsigned int debug_quirks = 0;
51 static unsigned int debug_quirks2;
52
53 static void sdhci_finish_data(struct sdhci_host *);
54
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57 void sdhci_dumpregs(struct sdhci_host *host)
58 {
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117 }
118 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120 /*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124 \*****************************************************************************/
125
126 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127 {
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129 }
130
131 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132 {
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151 }
152
153 static void sdhci_enable_card_detection(struct sdhci_host *host)
154 {
155 sdhci_set_card_detection(host, true);
156 }
157
158 static void sdhci_disable_card_detection(struct sdhci_host *host)
159 {
160 sdhci_set_card_detection(host, false);
161 }
162
163 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164 {
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169 }
170
171 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172 {
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177 }
178
179 void sdhci_reset(struct sdhci_host *host, u8 mask)
180 {
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (1) {
197 bool timedout = ktime_after(ktime_get(), timeout);
198
199 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
200 break;
201 if (timedout) {
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 udelay(10);
208 }
209 }
210 EXPORT_SYMBOL_GPL(sdhci_reset);
211
212 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
213 {
214 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
215 struct mmc_host *mmc = host->mmc;
216
217 if (!mmc->ops->get_cd(mmc))
218 return;
219 }
220
221 host->ops->reset(host, mask);
222
223 if (mask & SDHCI_RESET_ALL) {
224 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
225 if (host->ops->enable_dma)
226 host->ops->enable_dma(host);
227 }
228
229 /* Resetting the controller clears many */
230 host->preset_enabled = false;
231 }
232 }
233
234 static void sdhci_set_default_irqs(struct sdhci_host *host)
235 {
236 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
238 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
239 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
240 SDHCI_INT_RESPONSE;
241
242 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
243 host->tuning_mode == SDHCI_TUNING_MODE_3)
244 host->ier |= SDHCI_INT_RETUNE;
245
246 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
247 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
248 }
249
250 static void sdhci_init(struct sdhci_host *host, int soft)
251 {
252 struct mmc_host *mmc = host->mmc;
253
254 if (soft)
255 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
256 else
257 sdhci_do_reset(host, SDHCI_RESET_ALL);
258
259 sdhci_set_default_irqs(host);
260
261 host->cqe_on = false;
262
263 if (soft) {
264 /* force clock reconfiguration */
265 host->clock = 0;
266 mmc->ops->set_ios(mmc, &mmc->ios);
267 }
268 }
269
270 static void sdhci_reinit(struct sdhci_host *host)
271 {
272 sdhci_init(host, 0);
273 sdhci_enable_card_detection(host);
274 }
275
276 static void __sdhci_led_activate(struct sdhci_host *host)
277 {
278 u8 ctrl;
279
280 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
281 ctrl |= SDHCI_CTRL_LED;
282 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
283 }
284
285 static void __sdhci_led_deactivate(struct sdhci_host *host)
286 {
287 u8 ctrl;
288
289 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
290 ctrl &= ~SDHCI_CTRL_LED;
291 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
292 }
293
294 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
295 static void sdhci_led_control(struct led_classdev *led,
296 enum led_brightness brightness)
297 {
298 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
299 unsigned long flags;
300
301 spin_lock_irqsave(&host->lock, flags);
302
303 if (host->runtime_suspended)
304 goto out;
305
306 if (brightness == LED_OFF)
307 __sdhci_led_deactivate(host);
308 else
309 __sdhci_led_activate(host);
310 out:
311 spin_unlock_irqrestore(&host->lock, flags);
312 }
313
314 static int sdhci_led_register(struct sdhci_host *host)
315 {
316 struct mmc_host *mmc = host->mmc;
317
318 snprintf(host->led_name, sizeof(host->led_name),
319 "%s::", mmc_hostname(mmc));
320
321 host->led.name = host->led_name;
322 host->led.brightness = LED_OFF;
323 host->led.default_trigger = mmc_hostname(mmc);
324 host->led.brightness_set = sdhci_led_control;
325
326 return led_classdev_register(mmc_dev(mmc), &host->led);
327 }
328
329 static void sdhci_led_unregister(struct sdhci_host *host)
330 {
331 led_classdev_unregister(&host->led);
332 }
333
334 static inline void sdhci_led_activate(struct sdhci_host *host)
335 {
336 }
337
338 static inline void sdhci_led_deactivate(struct sdhci_host *host)
339 {
340 }
341
342 #else
343
344 static inline int sdhci_led_register(struct sdhci_host *host)
345 {
346 return 0;
347 }
348
349 static inline void sdhci_led_unregister(struct sdhci_host *host)
350 {
351 }
352
353 static inline void sdhci_led_activate(struct sdhci_host *host)
354 {
355 __sdhci_led_activate(host);
356 }
357
358 static inline void sdhci_led_deactivate(struct sdhci_host *host)
359 {
360 __sdhci_led_deactivate(host);
361 }
362
363 #endif
364
365 /*****************************************************************************\
366 * *
367 * Core functions *
368 * *
369 \*****************************************************************************/
370
371 static void sdhci_read_block_pio(struct sdhci_host *host)
372 {
373 unsigned long flags;
374 size_t blksize, len, chunk;
375 u32 uninitialized_var(scratch);
376 u8 *buf;
377
378 DBG("PIO reading\n");
379
380 blksize = host->data->blksz;
381 chunk = 0;
382
383 local_irq_save(flags);
384
385 while (blksize) {
386 BUG_ON(!sg_miter_next(&host->sg_miter));
387
388 len = min(host->sg_miter.length, blksize);
389
390 blksize -= len;
391 host->sg_miter.consumed = len;
392
393 buf = host->sg_miter.addr;
394
395 while (len) {
396 if (chunk == 0) {
397 scratch = sdhci_readl(host, SDHCI_BUFFER);
398 chunk = 4;
399 }
400
401 *buf = scratch & 0xFF;
402
403 buf++;
404 scratch >>= 8;
405 chunk--;
406 len--;
407 }
408 }
409
410 sg_miter_stop(&host->sg_miter);
411
412 local_irq_restore(flags);
413 }
414
415 static void sdhci_write_block_pio(struct sdhci_host *host)
416 {
417 unsigned long flags;
418 size_t blksize, len, chunk;
419 u32 scratch;
420 u8 *buf;
421
422 DBG("PIO writing\n");
423
424 blksize = host->data->blksz;
425 chunk = 0;
426 scratch = 0;
427
428 local_irq_save(flags);
429
430 while (blksize) {
431 BUG_ON(!sg_miter_next(&host->sg_miter));
432
433 len = min(host->sg_miter.length, blksize);
434
435 blksize -= len;
436 host->sg_miter.consumed = len;
437
438 buf = host->sg_miter.addr;
439
440 while (len) {
441 scratch |= (u32)*buf << (chunk * 8);
442
443 buf++;
444 chunk++;
445 len--;
446
447 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
448 sdhci_writel(host, scratch, SDHCI_BUFFER);
449 chunk = 0;
450 scratch = 0;
451 }
452 }
453 }
454
455 sg_miter_stop(&host->sg_miter);
456
457 local_irq_restore(flags);
458 }
459
460 static void sdhci_transfer_pio(struct sdhci_host *host)
461 {
462 u32 mask;
463
464 if (host->blocks == 0)
465 return;
466
467 if (host->data->flags & MMC_DATA_READ)
468 mask = SDHCI_DATA_AVAILABLE;
469 else
470 mask = SDHCI_SPACE_AVAILABLE;
471
472 /*
473 * Some controllers (JMicron JMB38x) mess up the buffer bits
474 * for transfers < 4 bytes. As long as it is just one block,
475 * we can ignore the bits.
476 */
477 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
478 (host->data->blocks == 1))
479 mask = ~0;
480
481 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
482 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
483 udelay(100);
484
485 if (host->data->flags & MMC_DATA_READ)
486 sdhci_read_block_pio(host);
487 else
488 sdhci_write_block_pio(host);
489
490 host->blocks--;
491 if (host->blocks == 0)
492 break;
493 }
494
495 DBG("PIO transfer complete.\n");
496 }
497
498 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
499 struct mmc_data *data, int cookie)
500 {
501 int sg_count;
502
503 /*
504 * If the data buffers are already mapped, return the previous
505 * dma_map_sg() result.
506 */
507 if (data->host_cookie == COOKIE_PRE_MAPPED)
508 return data->sg_count;
509
510 /* Bounce write requests to the bounce buffer */
511 if (host->bounce_buffer) {
512 unsigned int length = data->blksz * data->blocks;
513
514 if (length > host->bounce_buffer_size) {
515 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
516 mmc_hostname(host->mmc), length,
517 host->bounce_buffer_size);
518 return -EIO;
519 }
520 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
521 /* Copy the data to the bounce buffer */
522 sg_copy_to_buffer(data->sg, data->sg_len,
523 host->bounce_buffer,
524 length);
525 }
526 /* Switch ownership to the DMA */
527 dma_sync_single_for_device(host->mmc->parent,
528 host->bounce_addr,
529 host->bounce_buffer_size,
530 mmc_get_dma_dir(data));
531 /* Just a dummy value */
532 sg_count = 1;
533 } else {
534 /* Just access the data directly from memory */
535 sg_count = dma_map_sg(mmc_dev(host->mmc),
536 data->sg, data->sg_len,
537 mmc_get_dma_dir(data));
538 }
539
540 if (sg_count == 0)
541 return -ENOSPC;
542
543 data->sg_count = sg_count;
544 data->host_cookie = cookie;
545
546 return sg_count;
547 }
548
549 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
550 {
551 local_irq_save(*flags);
552 return kmap_atomic(sg_page(sg)) + sg->offset;
553 }
554
555 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
556 {
557 kunmap_atomic(buffer);
558 local_irq_restore(*flags);
559 }
560
561 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
562 dma_addr_t addr, int len, unsigned cmd)
563 {
564 struct sdhci_adma2_64_desc *dma_desc = desc;
565
566 /* 32-bit and 64-bit descriptors have these members in same position */
567 dma_desc->cmd = cpu_to_le16(cmd);
568 dma_desc->len = cpu_to_le16(len);
569 dma_desc->addr_lo = cpu_to_le32((u32)addr);
570
571 if (host->flags & SDHCI_USE_64_BIT_DMA)
572 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
573 }
574
575 static void sdhci_adma_mark_end(void *desc)
576 {
577 struct sdhci_adma2_64_desc *dma_desc = desc;
578
579 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
580 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
581 }
582
583 static void sdhci_adma_table_pre(struct sdhci_host *host,
584 struct mmc_data *data, int sg_count)
585 {
586 struct scatterlist *sg;
587 unsigned long flags;
588 dma_addr_t addr, align_addr;
589 void *desc, *align;
590 char *buffer;
591 int len, offset, i;
592
593 /*
594 * The spec does not specify endianness of descriptor table.
595 * We currently guess that it is LE.
596 */
597
598 host->sg_count = sg_count;
599
600 desc = host->adma_table;
601 align = host->align_buffer;
602
603 align_addr = host->align_addr;
604
605 for_each_sg(data->sg, sg, host->sg_count, i) {
606 addr = sg_dma_address(sg);
607 len = sg_dma_len(sg);
608
609 /*
610 * The SDHCI specification states that ADMA addresses must
611 * be 32-bit aligned. If they aren't, then we use a bounce
612 * buffer for the (up to three) bytes that screw up the
613 * alignment.
614 */
615 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
616 SDHCI_ADMA2_MASK;
617 if (offset) {
618 if (data->flags & MMC_DATA_WRITE) {
619 buffer = sdhci_kmap_atomic(sg, &flags);
620 memcpy(align, buffer, offset);
621 sdhci_kunmap_atomic(buffer, &flags);
622 }
623
624 /* tran, valid */
625 sdhci_adma_write_desc(host, desc, align_addr, offset,
626 ADMA2_TRAN_VALID);
627
628 BUG_ON(offset > 65536);
629
630 align += SDHCI_ADMA2_ALIGN;
631 align_addr += SDHCI_ADMA2_ALIGN;
632
633 desc += host->desc_sz;
634
635 addr += offset;
636 len -= offset;
637 }
638
639 BUG_ON(len > 65536);
640
641 if (len) {
642 /* tran, valid */
643 sdhci_adma_write_desc(host, desc, addr, len,
644 ADMA2_TRAN_VALID);
645 desc += host->desc_sz;
646 }
647
648 /*
649 * If this triggers then we have a calculation bug
650 * somewhere. :/
651 */
652 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
653 }
654
655 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
656 /* Mark the last descriptor as the terminating descriptor */
657 if (desc != host->adma_table) {
658 desc -= host->desc_sz;
659 sdhci_adma_mark_end(desc);
660 }
661 } else {
662 /* Add a terminating entry - nop, end, valid */
663 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
664 }
665 }
666
667 static void sdhci_adma_table_post(struct sdhci_host *host,
668 struct mmc_data *data)
669 {
670 struct scatterlist *sg;
671 int i, size;
672 void *align;
673 char *buffer;
674 unsigned long flags;
675
676 if (data->flags & MMC_DATA_READ) {
677 bool has_unaligned = false;
678
679 /* Do a quick scan of the SG list for any unaligned mappings */
680 for_each_sg(data->sg, sg, host->sg_count, i)
681 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
682 has_unaligned = true;
683 break;
684 }
685
686 if (has_unaligned) {
687 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
688 data->sg_len, DMA_FROM_DEVICE);
689
690 align = host->align_buffer;
691
692 for_each_sg(data->sg, sg, host->sg_count, i) {
693 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
694 size = SDHCI_ADMA2_ALIGN -
695 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
696
697 buffer = sdhci_kmap_atomic(sg, &flags);
698 memcpy(buffer, align, size);
699 sdhci_kunmap_atomic(buffer, &flags);
700
701 align += SDHCI_ADMA2_ALIGN;
702 }
703 }
704 }
705 }
706 }
707
708 static u32 sdhci_sdma_address(struct sdhci_host *host)
709 {
710 if (host->bounce_buffer)
711 return host->bounce_addr;
712 else
713 return sg_dma_address(host->data->sg);
714 }
715
716 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
717 {
718 u8 count;
719 struct mmc_data *data = cmd->data;
720 unsigned target_timeout, current_timeout;
721
722 /*
723 * If the host controller provides us with an incorrect timeout
724 * value, just skip the check and use 0xE. The hardware may take
725 * longer to time out, but that's much better than having a too-short
726 * timeout value.
727 */
728 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
729 return 0xE;
730
731 /* Unspecified timeout, assume max */
732 if (!data && !cmd->busy_timeout)
733 return 0xE;
734
735 /* timeout in us */
736 if (!data)
737 target_timeout = cmd->busy_timeout * 1000;
738 else {
739 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
740 if (host->clock && data->timeout_clks) {
741 unsigned long long val;
742
743 /*
744 * data->timeout_clks is in units of clock cycles.
745 * host->clock is in Hz. target_timeout is in us.
746 * Hence, us = 1000000 * cycles / Hz. Round up.
747 */
748 val = 1000000ULL * data->timeout_clks;
749 if (do_div(val, host->clock))
750 target_timeout++;
751 target_timeout += val;
752 }
753 }
754
755 /*
756 * Figure out needed cycles.
757 * We do this in steps in order to fit inside a 32 bit int.
758 * The first step is the minimum timeout, which will have a
759 * minimum resolution of 6 bits:
760 * (1) 2^13*1000 > 2^22,
761 * (2) host->timeout_clk < 2^16
762 * =>
763 * (1) / (2) > 2^6
764 */
765 count = 0;
766 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
767 while (current_timeout < target_timeout) {
768 count++;
769 current_timeout <<= 1;
770 if (count >= 0xF)
771 break;
772 }
773
774 if (count >= 0xF) {
775 DBG("Too large timeout 0x%x requested for CMD%d!\n",
776 count, cmd->opcode);
777 count = 0xE;
778 }
779
780 return count;
781 }
782
783 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
784 {
785 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
786 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
787
788 if (host->flags & SDHCI_REQ_USE_DMA)
789 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
790 else
791 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
792
793 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
794 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
795 else
796 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
797
798 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
799 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
800 }
801
802 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
803 {
804 u8 count;
805
806 if (host->ops->set_timeout) {
807 host->ops->set_timeout(host, cmd);
808 } else {
809 count = sdhci_calc_timeout(host, cmd);
810 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
811 }
812 }
813
814 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
815 {
816 u8 ctrl;
817 struct mmc_data *data = cmd->data;
818
819 if (sdhci_data_line_cmd(cmd))
820 sdhci_set_timeout(host, cmd);
821
822 if (!data)
823 return;
824
825 WARN_ON(host->data);
826
827 /* Sanity checks */
828 BUG_ON(data->blksz * data->blocks > 524288);
829 BUG_ON(data->blksz > host->mmc->max_blk_size);
830 BUG_ON(data->blocks > 65535);
831
832 host->data = data;
833 host->data_early = 0;
834 host->data->bytes_xfered = 0;
835
836 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
837 struct scatterlist *sg;
838 unsigned int length_mask, offset_mask;
839 int i;
840
841 host->flags |= SDHCI_REQ_USE_DMA;
842
843 /*
844 * FIXME: This doesn't account for merging when mapping the
845 * scatterlist.
846 *
847 * The assumption here being that alignment and lengths are
848 * the same after DMA mapping to device address space.
849 */
850 length_mask = 0;
851 offset_mask = 0;
852 if (host->flags & SDHCI_USE_ADMA) {
853 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
854 length_mask = 3;
855 /*
856 * As we use up to 3 byte chunks to work
857 * around alignment problems, we need to
858 * check the offset as well.
859 */
860 offset_mask = 3;
861 }
862 } else {
863 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
864 length_mask = 3;
865 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
866 offset_mask = 3;
867 }
868
869 if (unlikely(length_mask | offset_mask)) {
870 for_each_sg(data->sg, sg, data->sg_len, i) {
871 if (sg->length & length_mask) {
872 DBG("Reverting to PIO because of transfer size (%d)\n",
873 sg->length);
874 host->flags &= ~SDHCI_REQ_USE_DMA;
875 break;
876 }
877 if (sg->offset & offset_mask) {
878 DBG("Reverting to PIO because of bad alignment\n");
879 host->flags &= ~SDHCI_REQ_USE_DMA;
880 break;
881 }
882 }
883 }
884 }
885
886 if (host->flags & SDHCI_REQ_USE_DMA) {
887 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
888
889 if (sg_cnt <= 0) {
890 /*
891 * This only happens when someone fed
892 * us an invalid request.
893 */
894 WARN_ON(1);
895 host->flags &= ~SDHCI_REQ_USE_DMA;
896 } else if (host->flags & SDHCI_USE_ADMA) {
897 sdhci_adma_table_pre(host, data, sg_cnt);
898
899 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
900 if (host->flags & SDHCI_USE_64_BIT_DMA)
901 sdhci_writel(host,
902 (u64)host->adma_addr >> 32,
903 SDHCI_ADMA_ADDRESS_HI);
904 } else {
905 WARN_ON(sg_cnt != 1);
906 sdhci_writel(host, sdhci_sdma_address(host),
907 SDHCI_DMA_ADDRESS);
908 }
909 }
910
911 /*
912 * Always adjust the DMA selection as some controllers
913 * (e.g. JMicron) can't do PIO properly when the selection
914 * is ADMA.
915 */
916 if (host->version >= SDHCI_SPEC_200) {
917 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
918 ctrl &= ~SDHCI_CTRL_DMA_MASK;
919 if ((host->flags & SDHCI_REQ_USE_DMA) &&
920 (host->flags & SDHCI_USE_ADMA)) {
921 if (host->flags & SDHCI_USE_64_BIT_DMA)
922 ctrl |= SDHCI_CTRL_ADMA64;
923 else
924 ctrl |= SDHCI_CTRL_ADMA32;
925 } else {
926 ctrl |= SDHCI_CTRL_SDMA;
927 }
928 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
929 }
930
931 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
932 int flags;
933
934 flags = SG_MITER_ATOMIC;
935 if (host->data->flags & MMC_DATA_READ)
936 flags |= SG_MITER_TO_SG;
937 else
938 flags |= SG_MITER_FROM_SG;
939 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
940 host->blocks = data->blocks;
941 }
942
943 sdhci_set_transfer_irqs(host);
944
945 /* Set the DMA boundary value and block size */
946 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
947 SDHCI_BLOCK_SIZE);
948 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
949 }
950
951 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
952 struct mmc_request *mrq)
953 {
954 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
955 !mrq->cap_cmd_during_tfr;
956 }
957
958 static void sdhci_set_transfer_mode(struct sdhci_host *host,
959 struct mmc_command *cmd)
960 {
961 u16 mode = 0;
962 struct mmc_data *data = cmd->data;
963
964 if (data == NULL) {
965 if (host->quirks2 &
966 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
967 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
968 } else {
969 /* clear Auto CMD settings for no data CMDs */
970 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
971 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
972 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
973 }
974 return;
975 }
976
977 WARN_ON(!host->data);
978
979 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
980 mode = SDHCI_TRNS_BLK_CNT_EN;
981
982 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
983 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
984 /*
985 * If we are sending CMD23, CMD12 never gets sent
986 * on successful completion (so no Auto-CMD12).
987 */
988 if (sdhci_auto_cmd12(host, cmd->mrq) &&
989 (cmd->opcode != SD_IO_RW_EXTENDED))
990 mode |= SDHCI_TRNS_AUTO_CMD12;
991 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
992 mode |= SDHCI_TRNS_AUTO_CMD23;
993 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
994 }
995 }
996
997 if (data->flags & MMC_DATA_READ)
998 mode |= SDHCI_TRNS_READ;
999 if (host->flags & SDHCI_REQ_USE_DMA)
1000 mode |= SDHCI_TRNS_DMA;
1001
1002 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1003 }
1004
1005 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1006 {
1007 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1008 ((mrq->cmd && mrq->cmd->error) ||
1009 (mrq->sbc && mrq->sbc->error) ||
1010 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1011 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1012 }
1013
1014 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1015 {
1016 int i;
1017
1018 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1019 if (host->mrqs_done[i] == mrq) {
1020 WARN_ON(1);
1021 return;
1022 }
1023 }
1024
1025 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1026 if (!host->mrqs_done[i]) {
1027 host->mrqs_done[i] = mrq;
1028 break;
1029 }
1030 }
1031
1032 WARN_ON(i >= SDHCI_MAX_MRQS);
1033
1034 tasklet_schedule(&host->finish_tasklet);
1035 }
1036
1037 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1038 {
1039 if (host->cmd && host->cmd->mrq == mrq)
1040 host->cmd = NULL;
1041
1042 if (host->data_cmd && host->data_cmd->mrq == mrq)
1043 host->data_cmd = NULL;
1044
1045 if (host->data && host->data->mrq == mrq)
1046 host->data = NULL;
1047
1048 if (sdhci_needs_reset(host, mrq))
1049 host->pending_reset = true;
1050
1051 __sdhci_finish_mrq(host, mrq);
1052 }
1053
1054 static void sdhci_finish_data(struct sdhci_host *host)
1055 {
1056 struct mmc_command *data_cmd = host->data_cmd;
1057 struct mmc_data *data = host->data;
1058
1059 host->data = NULL;
1060 host->data_cmd = NULL;
1061
1062 /*
1063 * The controller needs a reset of internal state machines upon error
1064 * conditions.
1065 */
1066 if (data->error) {
1067 if (!host->cmd || host->cmd == data_cmd)
1068 sdhci_do_reset(host, SDHCI_RESET_CMD);
1069 sdhci_do_reset(host, SDHCI_RESET_DATA);
1070 }
1071
1072 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1073 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1074 sdhci_adma_table_post(host, data);
1075
1076 /*
1077 * The specification states that the block count register must
1078 * be updated, but it does not specify at what point in the
1079 * data flow. That makes the register entirely useless to read
1080 * back so we have to assume that nothing made it to the card
1081 * in the event of an error.
1082 */
1083 if (data->error)
1084 data->bytes_xfered = 0;
1085 else
1086 data->bytes_xfered = data->blksz * data->blocks;
1087
1088 /*
1089 * Need to send CMD12 if -
1090 * a) open-ended multiblock transfer (no CMD23)
1091 * b) error in multiblock transfer
1092 */
1093 if (data->stop &&
1094 (data->error ||
1095 !data->mrq->sbc)) {
1096 /*
1097 * 'cap_cmd_during_tfr' request must not use the command line
1098 * after mmc_command_done() has been called. It is upper layer's
1099 * responsibility to send the stop command if required.
1100 */
1101 if (data->mrq->cap_cmd_during_tfr) {
1102 sdhci_finish_mrq(host, data->mrq);
1103 } else {
1104 /* Avoid triggering warning in sdhci_send_command() */
1105 host->cmd = NULL;
1106 sdhci_send_command(host, data->stop);
1107 }
1108 } else {
1109 sdhci_finish_mrq(host, data->mrq);
1110 }
1111 }
1112
1113 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1114 unsigned long timeout)
1115 {
1116 if (sdhci_data_line_cmd(mrq->cmd))
1117 mod_timer(&host->data_timer, timeout);
1118 else
1119 mod_timer(&host->timer, timeout);
1120 }
1121
1122 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1123 {
1124 if (sdhci_data_line_cmd(mrq->cmd))
1125 del_timer(&host->data_timer);
1126 else
1127 del_timer(&host->timer);
1128 }
1129
1130 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1131 {
1132 int flags;
1133 u32 mask;
1134 unsigned long timeout;
1135
1136 WARN_ON(host->cmd);
1137
1138 /* Initially, a command has no error */
1139 cmd->error = 0;
1140
1141 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1142 cmd->opcode == MMC_STOP_TRANSMISSION)
1143 cmd->flags |= MMC_RSP_BUSY;
1144
1145 /* Wait max 10 ms */
1146 timeout = 10;
1147
1148 mask = SDHCI_CMD_INHIBIT;
1149 if (sdhci_data_line_cmd(cmd))
1150 mask |= SDHCI_DATA_INHIBIT;
1151
1152 /* We shouldn't wait for data inihibit for stop commands, even
1153 though they might use busy signaling */
1154 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1155 mask &= ~SDHCI_DATA_INHIBIT;
1156
1157 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1158 if (timeout == 0) {
1159 pr_err("%s: Controller never released inhibit bit(s).\n",
1160 mmc_hostname(host->mmc));
1161 sdhci_dumpregs(host);
1162 cmd->error = -EIO;
1163 sdhci_finish_mrq(host, cmd->mrq);
1164 return;
1165 }
1166 timeout--;
1167 mdelay(1);
1168 }
1169
1170 timeout = jiffies;
1171 if (!cmd->data && cmd->busy_timeout > 9000)
1172 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1173 else
1174 timeout += 10 * HZ;
1175 sdhci_mod_timer(host, cmd->mrq, timeout);
1176
1177 host->cmd = cmd;
1178 if (sdhci_data_line_cmd(cmd)) {
1179 WARN_ON(host->data_cmd);
1180 host->data_cmd = cmd;
1181 }
1182
1183 sdhci_prepare_data(host, cmd);
1184
1185 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1186
1187 sdhci_set_transfer_mode(host, cmd);
1188
1189 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1190 pr_err("%s: Unsupported response type!\n",
1191 mmc_hostname(host->mmc));
1192 cmd->error = -EINVAL;
1193 sdhci_finish_mrq(host, cmd->mrq);
1194 return;
1195 }
1196
1197 if (!(cmd->flags & MMC_RSP_PRESENT))
1198 flags = SDHCI_CMD_RESP_NONE;
1199 else if (cmd->flags & MMC_RSP_136)
1200 flags = SDHCI_CMD_RESP_LONG;
1201 else if (cmd->flags & MMC_RSP_BUSY)
1202 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1203 else
1204 flags = SDHCI_CMD_RESP_SHORT;
1205
1206 if (cmd->flags & MMC_RSP_CRC)
1207 flags |= SDHCI_CMD_CRC;
1208 if (cmd->flags & MMC_RSP_OPCODE)
1209 flags |= SDHCI_CMD_INDEX;
1210
1211 /* CMD19 is special in that the Data Present Select should be set */
1212 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1213 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1214 flags |= SDHCI_CMD_DATA;
1215
1216 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1217 }
1218 EXPORT_SYMBOL_GPL(sdhci_send_command);
1219
1220 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1221 {
1222 int i, reg;
1223
1224 for (i = 0; i < 4; i++) {
1225 reg = SDHCI_RESPONSE + (3 - i) * 4;
1226 cmd->resp[i] = sdhci_readl(host, reg);
1227 }
1228
1229 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1230 return;
1231
1232 /* CRC is stripped so we need to do some shifting */
1233 for (i = 0; i < 4; i++) {
1234 cmd->resp[i] <<= 8;
1235 if (i != 3)
1236 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1237 }
1238 }
1239
1240 static void sdhci_finish_command(struct sdhci_host *host)
1241 {
1242 struct mmc_command *cmd = host->cmd;
1243
1244 host->cmd = NULL;
1245
1246 if (cmd->flags & MMC_RSP_PRESENT) {
1247 if (cmd->flags & MMC_RSP_136) {
1248 sdhci_read_rsp_136(host, cmd);
1249 } else {
1250 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1251 }
1252 }
1253
1254 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1255 mmc_command_done(host->mmc, cmd->mrq);
1256
1257 /*
1258 * The host can send and interrupt when the busy state has
1259 * ended, allowing us to wait without wasting CPU cycles.
1260 * The busy signal uses DAT0 so this is similar to waiting
1261 * for data to complete.
1262 *
1263 * Note: The 1.0 specification is a bit ambiguous about this
1264 * feature so there might be some problems with older
1265 * controllers.
1266 */
1267 if (cmd->flags & MMC_RSP_BUSY) {
1268 if (cmd->data) {
1269 DBG("Cannot wait for busy signal when also doing a data transfer");
1270 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1271 cmd == host->data_cmd) {
1272 /* Command complete before busy is ended */
1273 return;
1274 }
1275 }
1276
1277 /* Finished CMD23, now send actual command. */
1278 if (cmd == cmd->mrq->sbc) {
1279 sdhci_send_command(host, cmd->mrq->cmd);
1280 } else {
1281
1282 /* Processed actual command. */
1283 if (host->data && host->data_early)
1284 sdhci_finish_data(host);
1285
1286 if (!cmd->data)
1287 sdhci_finish_mrq(host, cmd->mrq);
1288 }
1289 }
1290
1291 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1292 {
1293 u16 preset = 0;
1294
1295 switch (host->timing) {
1296 case MMC_TIMING_UHS_SDR12:
1297 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1298 break;
1299 case MMC_TIMING_UHS_SDR25:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1301 break;
1302 case MMC_TIMING_UHS_SDR50:
1303 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1304 break;
1305 case MMC_TIMING_UHS_SDR104:
1306 case MMC_TIMING_MMC_HS200:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1308 break;
1309 case MMC_TIMING_UHS_DDR50:
1310 case MMC_TIMING_MMC_DDR52:
1311 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1312 break;
1313 case MMC_TIMING_MMC_HS400:
1314 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1315 break;
1316 default:
1317 pr_warn("%s: Invalid UHS-I mode selected\n",
1318 mmc_hostname(host->mmc));
1319 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1320 break;
1321 }
1322 return preset;
1323 }
1324
1325 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1326 unsigned int *actual_clock)
1327 {
1328 int div = 0; /* Initialized for compiler warning */
1329 int real_div = div, clk_mul = 1;
1330 u16 clk = 0;
1331 bool switch_base_clk = false;
1332
1333 if (host->version >= SDHCI_SPEC_300) {
1334 if (host->preset_enabled) {
1335 u16 pre_val;
1336
1337 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1338 pre_val = sdhci_get_preset_value(host);
1339 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1340 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1341 if (host->clk_mul &&
1342 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1343 clk = SDHCI_PROG_CLOCK_MODE;
1344 real_div = div + 1;
1345 clk_mul = host->clk_mul;
1346 } else {
1347 real_div = max_t(int, 1, div << 1);
1348 }
1349 goto clock_set;
1350 }
1351
1352 /*
1353 * Check if the Host Controller supports Programmable Clock
1354 * Mode.
1355 */
1356 if (host->clk_mul) {
1357 for (div = 1; div <= 1024; div++) {
1358 if ((host->max_clk * host->clk_mul / div)
1359 <= clock)
1360 break;
1361 }
1362 if ((host->max_clk * host->clk_mul / div) <= clock) {
1363 /*
1364 * Set Programmable Clock Mode in the Clock
1365 * Control register.
1366 */
1367 clk = SDHCI_PROG_CLOCK_MODE;
1368 real_div = div;
1369 clk_mul = host->clk_mul;
1370 div--;
1371 } else {
1372 /*
1373 * Divisor can be too small to reach clock
1374 * speed requirement. Then use the base clock.
1375 */
1376 switch_base_clk = true;
1377 }
1378 }
1379
1380 if (!host->clk_mul || switch_base_clk) {
1381 /* Version 3.00 divisors must be a multiple of 2. */
1382 if (host->max_clk <= clock)
1383 div = 1;
1384 else {
1385 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1386 div += 2) {
1387 if ((host->max_clk / div) <= clock)
1388 break;
1389 }
1390 }
1391 real_div = div;
1392 div >>= 1;
1393 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1394 && !div && host->max_clk <= 25000000)
1395 div = 1;
1396 }
1397 } else {
1398 /* Version 2.00 divisors must be a power of 2. */
1399 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1400 if ((host->max_clk / div) <= clock)
1401 break;
1402 }
1403 real_div = div;
1404 div >>= 1;
1405 }
1406
1407 clock_set:
1408 if (real_div)
1409 *actual_clock = (host->max_clk * clk_mul) / real_div;
1410 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1411 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1412 << SDHCI_DIVIDER_HI_SHIFT;
1413
1414 return clk;
1415 }
1416 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1417
1418 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1419 {
1420 ktime_t timeout;
1421
1422 clk |= SDHCI_CLOCK_INT_EN;
1423 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1424
1425 /* Wait max 20 ms */
1426 timeout = ktime_add_ms(ktime_get(), 20);
1427 while (1) {
1428 bool timedout = ktime_after(ktime_get(), timeout);
1429
1430 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1431 if (clk & SDHCI_CLOCK_INT_STABLE)
1432 break;
1433 if (timedout) {
1434 pr_err("%s: Internal clock never stabilised.\n",
1435 mmc_hostname(host->mmc));
1436 sdhci_dumpregs(host);
1437 return;
1438 }
1439 udelay(10);
1440 }
1441
1442 clk |= SDHCI_CLOCK_CARD_EN;
1443 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1444 }
1445 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1446
1447 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1448 {
1449 u16 clk;
1450
1451 host->mmc->actual_clock = 0;
1452
1453 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1454
1455 if (clock == 0)
1456 return;
1457
1458 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1459 sdhci_enable_clk(host, clk);
1460 }
1461 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1462
1463 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1464 unsigned short vdd)
1465 {
1466 struct mmc_host *mmc = host->mmc;
1467
1468 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1469
1470 if (mode != MMC_POWER_OFF)
1471 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1472 else
1473 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1474 }
1475
1476 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1477 unsigned short vdd)
1478 {
1479 u8 pwr = 0;
1480
1481 if (mode != MMC_POWER_OFF) {
1482 switch (1 << vdd) {
1483 case MMC_VDD_165_195:
1484 /*
1485 * Without a regulator, SDHCI does not support 2.0v
1486 * so we only get here if the driver deliberately
1487 * added the 2.0v range to ocr_avail. Map it to 1.8v
1488 * for the purpose of turning on the power.
1489 */
1490 case MMC_VDD_20_21:
1491 pwr = SDHCI_POWER_180;
1492 break;
1493 case MMC_VDD_29_30:
1494 case MMC_VDD_30_31:
1495 pwr = SDHCI_POWER_300;
1496 break;
1497 case MMC_VDD_32_33:
1498 case MMC_VDD_33_34:
1499 pwr = SDHCI_POWER_330;
1500 break;
1501 default:
1502 WARN(1, "%s: Invalid vdd %#x\n",
1503 mmc_hostname(host->mmc), vdd);
1504 break;
1505 }
1506 }
1507
1508 if (host->pwr == pwr)
1509 return;
1510
1511 host->pwr = pwr;
1512
1513 if (pwr == 0) {
1514 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1515 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1516 sdhci_runtime_pm_bus_off(host);
1517 } else {
1518 /*
1519 * Spec says that we should clear the power reg before setting
1520 * a new value. Some controllers don't seem to like this though.
1521 */
1522 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1523 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1524
1525 /*
1526 * At least the Marvell CaFe chip gets confused if we set the
1527 * voltage and set turn on power at the same time, so set the
1528 * voltage first.
1529 */
1530 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1531 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1532
1533 pwr |= SDHCI_POWER_ON;
1534
1535 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1536
1537 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1538 sdhci_runtime_pm_bus_on(host);
1539
1540 /*
1541 * Some controllers need an extra 10ms delay of 10ms before
1542 * they can apply clock after applying power
1543 */
1544 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1545 mdelay(10);
1546 }
1547 }
1548 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1549
1550 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1551 unsigned short vdd)
1552 {
1553 if (IS_ERR(host->mmc->supply.vmmc))
1554 sdhci_set_power_noreg(host, mode, vdd);
1555 else
1556 sdhci_set_power_reg(host, mode, vdd);
1557 }
1558 EXPORT_SYMBOL_GPL(sdhci_set_power);
1559
1560 /*****************************************************************************\
1561 * *
1562 * MMC callbacks *
1563 * *
1564 \*****************************************************************************/
1565
1566 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1567 {
1568 struct sdhci_host *host;
1569 int present;
1570 unsigned long flags;
1571
1572 host = mmc_priv(mmc);
1573
1574 /* Firstly check card presence */
1575 present = mmc->ops->get_cd(mmc);
1576
1577 spin_lock_irqsave(&host->lock, flags);
1578
1579 sdhci_led_activate(host);
1580
1581 /*
1582 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1583 * requests if Auto-CMD12 is enabled.
1584 */
1585 if (sdhci_auto_cmd12(host, mrq)) {
1586 if (mrq->stop) {
1587 mrq->data->stop = NULL;
1588 mrq->stop = NULL;
1589 }
1590 }
1591
1592 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1593 mrq->cmd->error = -ENOMEDIUM;
1594 sdhci_finish_mrq(host, mrq);
1595 } else {
1596 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1597 sdhci_send_command(host, mrq->sbc);
1598 else
1599 sdhci_send_command(host, mrq->cmd);
1600 }
1601
1602 mmiowb();
1603 spin_unlock_irqrestore(&host->lock, flags);
1604 }
1605
1606 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1607 {
1608 u8 ctrl;
1609
1610 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1611 if (width == MMC_BUS_WIDTH_8) {
1612 ctrl &= ~SDHCI_CTRL_4BITBUS;
1613 ctrl |= SDHCI_CTRL_8BITBUS;
1614 } else {
1615 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1616 ctrl &= ~SDHCI_CTRL_8BITBUS;
1617 if (width == MMC_BUS_WIDTH_4)
1618 ctrl |= SDHCI_CTRL_4BITBUS;
1619 else
1620 ctrl &= ~SDHCI_CTRL_4BITBUS;
1621 }
1622 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1623 }
1624 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1625
1626 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1627 {
1628 u16 ctrl_2;
1629
1630 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1631 /* Select Bus Speed Mode for host */
1632 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1633 if ((timing == MMC_TIMING_MMC_HS200) ||
1634 (timing == MMC_TIMING_UHS_SDR104))
1635 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1636 else if (timing == MMC_TIMING_UHS_SDR12)
1637 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1638 else if (timing == MMC_TIMING_SD_HS ||
1639 timing == MMC_TIMING_MMC_HS ||
1640 timing == MMC_TIMING_UHS_SDR25)
1641 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1642 else if (timing == MMC_TIMING_UHS_SDR50)
1643 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1644 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1645 (timing == MMC_TIMING_MMC_DDR52))
1646 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1647 else if (timing == MMC_TIMING_MMC_HS400)
1648 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1649 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1650 }
1651 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1652
1653 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1654 {
1655 struct sdhci_host *host = mmc_priv(mmc);
1656 u8 ctrl;
1657
1658 if (ios->power_mode == MMC_POWER_UNDEFINED)
1659 return;
1660
1661 if (host->flags & SDHCI_DEVICE_DEAD) {
1662 if (!IS_ERR(mmc->supply.vmmc) &&
1663 ios->power_mode == MMC_POWER_OFF)
1664 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1665 return;
1666 }
1667
1668 /*
1669 * Reset the chip on each power off.
1670 * Should clear out any weird states.
1671 */
1672 if (ios->power_mode == MMC_POWER_OFF) {
1673 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1674 sdhci_reinit(host);
1675 }
1676
1677 if (host->version >= SDHCI_SPEC_300 &&
1678 (ios->power_mode == MMC_POWER_UP) &&
1679 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1680 sdhci_enable_preset_value(host, false);
1681
1682 if (!ios->clock || ios->clock != host->clock) {
1683 host->ops->set_clock(host, ios->clock);
1684 host->clock = ios->clock;
1685
1686 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1687 host->clock) {
1688 host->timeout_clk = host->mmc->actual_clock ?
1689 host->mmc->actual_clock / 1000 :
1690 host->clock / 1000;
1691 host->mmc->max_busy_timeout =
1692 host->ops->get_max_timeout_count ?
1693 host->ops->get_max_timeout_count(host) :
1694 1 << 27;
1695 host->mmc->max_busy_timeout /= host->timeout_clk;
1696 }
1697 }
1698
1699 if (host->ops->set_power)
1700 host->ops->set_power(host, ios->power_mode, ios->vdd);
1701 else
1702 sdhci_set_power(host, ios->power_mode, ios->vdd);
1703
1704 if (host->ops->platform_send_init_74_clocks)
1705 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1706
1707 host->ops->set_bus_width(host, ios->bus_width);
1708
1709 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1710
1711 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1712 if (ios->timing == MMC_TIMING_SD_HS ||
1713 ios->timing == MMC_TIMING_MMC_HS ||
1714 ios->timing == MMC_TIMING_MMC_HS400 ||
1715 ios->timing == MMC_TIMING_MMC_HS200 ||
1716 ios->timing == MMC_TIMING_MMC_DDR52 ||
1717 ios->timing == MMC_TIMING_UHS_SDR50 ||
1718 ios->timing == MMC_TIMING_UHS_SDR104 ||
1719 ios->timing == MMC_TIMING_UHS_DDR50 ||
1720 ios->timing == MMC_TIMING_UHS_SDR25)
1721 ctrl |= SDHCI_CTRL_HISPD;
1722 else
1723 ctrl &= ~SDHCI_CTRL_HISPD;
1724 }
1725
1726 if (host->version >= SDHCI_SPEC_300) {
1727 u16 clk, ctrl_2;
1728
1729 if (!host->preset_enabled) {
1730 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1731 /*
1732 * We only need to set Driver Strength if the
1733 * preset value enable is not set.
1734 */
1735 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1736 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1737 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1738 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1739 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1740 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1741 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1742 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1743 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1744 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1745 else {
1746 pr_warn("%s: invalid driver type, default to driver type B\n",
1747 mmc_hostname(mmc));
1748 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1749 }
1750
1751 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1752 } else {
1753 /*
1754 * According to SDHC Spec v3.00, if the Preset Value
1755 * Enable in the Host Control 2 register is set, we
1756 * need to reset SD Clock Enable before changing High
1757 * Speed Enable to avoid generating clock gliches.
1758 */
1759
1760 /* Reset SD Clock Enable */
1761 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1762 clk &= ~SDHCI_CLOCK_CARD_EN;
1763 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1764
1765 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1766
1767 /* Re-enable SD Clock */
1768 host->ops->set_clock(host, host->clock);
1769 }
1770
1771 /* Reset SD Clock Enable */
1772 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1773 clk &= ~SDHCI_CLOCK_CARD_EN;
1774 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1775
1776 host->ops->set_uhs_signaling(host, ios->timing);
1777 host->timing = ios->timing;
1778
1779 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1780 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1781 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1782 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1783 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1784 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1785 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1786 u16 preset;
1787
1788 sdhci_enable_preset_value(host, true);
1789 preset = sdhci_get_preset_value(host);
1790 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1791 >> SDHCI_PRESET_DRV_SHIFT;
1792 }
1793
1794 /* Re-enable SD Clock */
1795 host->ops->set_clock(host, host->clock);
1796 } else
1797 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1798
1799 /*
1800 * Some (ENE) controllers go apeshit on some ios operation,
1801 * signalling timeout and CRC errors even on CMD0. Resetting
1802 * it on each ios seems to solve the problem.
1803 */
1804 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1805 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1806
1807 mmiowb();
1808 }
1809 EXPORT_SYMBOL_GPL(sdhci_set_ios);
1810
1811 static int sdhci_get_cd(struct mmc_host *mmc)
1812 {
1813 struct sdhci_host *host = mmc_priv(mmc);
1814 int gpio_cd = mmc_gpio_get_cd(mmc);
1815
1816 if (host->flags & SDHCI_DEVICE_DEAD)
1817 return 0;
1818
1819 /* If nonremovable, assume that the card is always present. */
1820 if (!mmc_card_is_removable(host->mmc))
1821 return 1;
1822
1823 /*
1824 * Try slot gpio detect, if defined it take precedence
1825 * over build in controller functionality
1826 */
1827 if (gpio_cd >= 0)
1828 return !!gpio_cd;
1829
1830 /* If polling, assume that the card is always present. */
1831 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1832 return 1;
1833
1834 /* Host native card detect */
1835 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1836 }
1837
1838 static int sdhci_check_ro(struct sdhci_host *host)
1839 {
1840 unsigned long flags;
1841 int is_readonly;
1842
1843 spin_lock_irqsave(&host->lock, flags);
1844
1845 if (host->flags & SDHCI_DEVICE_DEAD)
1846 is_readonly = 0;
1847 else if (host->ops->get_ro)
1848 is_readonly = host->ops->get_ro(host);
1849 else
1850 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1851 & SDHCI_WRITE_PROTECT);
1852
1853 spin_unlock_irqrestore(&host->lock, flags);
1854
1855 /* This quirk needs to be replaced by a callback-function later */
1856 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1857 !is_readonly : is_readonly;
1858 }
1859
1860 #define SAMPLE_COUNT 5
1861
1862 static int sdhci_get_ro(struct mmc_host *mmc)
1863 {
1864 struct sdhci_host *host = mmc_priv(mmc);
1865 int i, ro_count;
1866
1867 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1868 return sdhci_check_ro(host);
1869
1870 ro_count = 0;
1871 for (i = 0; i < SAMPLE_COUNT; i++) {
1872 if (sdhci_check_ro(host)) {
1873 if (++ro_count > SAMPLE_COUNT / 2)
1874 return 1;
1875 }
1876 msleep(30);
1877 }
1878 return 0;
1879 }
1880
1881 static void sdhci_hw_reset(struct mmc_host *mmc)
1882 {
1883 struct sdhci_host *host = mmc_priv(mmc);
1884
1885 if (host->ops && host->ops->hw_reset)
1886 host->ops->hw_reset(host);
1887 }
1888
1889 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1890 {
1891 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1892 if (enable)
1893 host->ier |= SDHCI_INT_CARD_INT;
1894 else
1895 host->ier &= ~SDHCI_INT_CARD_INT;
1896
1897 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1898 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1899 mmiowb();
1900 }
1901 }
1902
1903 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1904 {
1905 struct sdhci_host *host = mmc_priv(mmc);
1906 unsigned long flags;
1907
1908 if (enable)
1909 pm_runtime_get_noresume(host->mmc->parent);
1910
1911 spin_lock_irqsave(&host->lock, flags);
1912 if (enable)
1913 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1914 else
1915 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1916
1917 sdhci_enable_sdio_irq_nolock(host, enable);
1918 spin_unlock_irqrestore(&host->lock, flags);
1919
1920 if (!enable)
1921 pm_runtime_put_noidle(host->mmc->parent);
1922 }
1923 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1924
1925 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1926 struct mmc_ios *ios)
1927 {
1928 struct sdhci_host *host = mmc_priv(mmc);
1929 u16 ctrl;
1930 int ret;
1931
1932 /*
1933 * Signal Voltage Switching is only applicable for Host Controllers
1934 * v3.00 and above.
1935 */
1936 if (host->version < SDHCI_SPEC_300)
1937 return 0;
1938
1939 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1940
1941 switch (ios->signal_voltage) {
1942 case MMC_SIGNAL_VOLTAGE_330:
1943 if (!(host->flags & SDHCI_SIGNALING_330))
1944 return -EINVAL;
1945 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1946 ctrl &= ~SDHCI_CTRL_VDD_180;
1947 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1948
1949 if (!IS_ERR(mmc->supply.vqmmc)) {
1950 ret = mmc_regulator_set_vqmmc(mmc, ios);
1951 if (ret) {
1952 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1953 mmc_hostname(mmc));
1954 return -EIO;
1955 }
1956 }
1957 /* Wait for 5ms */
1958 usleep_range(5000, 5500);
1959
1960 /* 3.3V regulator output should be stable within 5 ms */
1961 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1962 if (!(ctrl & SDHCI_CTRL_VDD_180))
1963 return 0;
1964
1965 pr_warn("%s: 3.3V regulator output did not became stable\n",
1966 mmc_hostname(mmc));
1967
1968 return -EAGAIN;
1969 case MMC_SIGNAL_VOLTAGE_180:
1970 if (!(host->flags & SDHCI_SIGNALING_180))
1971 return -EINVAL;
1972 if (!IS_ERR(mmc->supply.vqmmc)) {
1973 ret = mmc_regulator_set_vqmmc(mmc, ios);
1974 if (ret) {
1975 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1976 mmc_hostname(mmc));
1977 return -EIO;
1978 }
1979 }
1980
1981 /*
1982 * Enable 1.8V Signal Enable in the Host Control2
1983 * register
1984 */
1985 ctrl |= SDHCI_CTRL_VDD_180;
1986 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1987
1988 /* Some controller need to do more when switching */
1989 if (host->ops->voltage_switch)
1990 host->ops->voltage_switch(host);
1991
1992 /* 1.8V regulator output should be stable within 5 ms */
1993 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1994 if (ctrl & SDHCI_CTRL_VDD_180)
1995 return 0;
1996
1997 pr_warn("%s: 1.8V regulator output did not became stable\n",
1998 mmc_hostname(mmc));
1999
2000 return -EAGAIN;
2001 case MMC_SIGNAL_VOLTAGE_120:
2002 if (!(host->flags & SDHCI_SIGNALING_120))
2003 return -EINVAL;
2004 if (!IS_ERR(mmc->supply.vqmmc)) {
2005 ret = mmc_regulator_set_vqmmc(mmc, ios);
2006 if (ret) {
2007 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2008 mmc_hostname(mmc));
2009 return -EIO;
2010 }
2011 }
2012 return 0;
2013 default:
2014 /* No signal voltage switch required */
2015 return 0;
2016 }
2017 }
2018 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2019
2020 static int sdhci_card_busy(struct mmc_host *mmc)
2021 {
2022 struct sdhci_host *host = mmc_priv(mmc);
2023 u32 present_state;
2024
2025 /* Check whether DAT[0] is 0 */
2026 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2027
2028 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2029 }
2030
2031 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2032 {
2033 struct sdhci_host *host = mmc_priv(mmc);
2034 unsigned long flags;
2035
2036 spin_lock_irqsave(&host->lock, flags);
2037 host->flags |= SDHCI_HS400_TUNING;
2038 spin_unlock_irqrestore(&host->lock, flags);
2039
2040 return 0;
2041 }
2042
2043 static void sdhci_start_tuning(struct sdhci_host *host)
2044 {
2045 u16 ctrl;
2046
2047 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2048 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2049 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2050 ctrl |= SDHCI_CTRL_TUNED_CLK;
2051 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2052
2053 /*
2054 * As per the Host Controller spec v3.00, tuning command
2055 * generates Buffer Read Ready interrupt, so enable that.
2056 *
2057 * Note: The spec clearly says that when tuning sequence
2058 * is being performed, the controller does not generate
2059 * interrupts other than Buffer Read Ready interrupt. But
2060 * to make sure we don't hit a controller bug, we _only_
2061 * enable Buffer Read Ready interrupt here.
2062 */
2063 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2064 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2065 }
2066
2067 static void sdhci_end_tuning(struct sdhci_host *host)
2068 {
2069 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2070 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2071 }
2072
2073 static void sdhci_reset_tuning(struct sdhci_host *host)
2074 {
2075 u16 ctrl;
2076
2077 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2078 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2079 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2080 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2081 }
2082
2083 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2084 {
2085 sdhci_reset_tuning(host);
2086
2087 sdhci_do_reset(host, SDHCI_RESET_CMD);
2088 sdhci_do_reset(host, SDHCI_RESET_DATA);
2089
2090 sdhci_end_tuning(host);
2091
2092 mmc_abort_tuning(host->mmc, opcode);
2093 }
2094
2095 /*
2096 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2097 * tuning command does not have a data payload (or rather the hardware does it
2098 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2099 * interrupt setup is different to other commands and there is no timeout
2100 * interrupt so special handling is needed.
2101 */
2102 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2103 {
2104 struct mmc_host *mmc = host->mmc;
2105 struct mmc_command cmd = {};
2106 struct mmc_request mrq = {};
2107 unsigned long flags;
2108 u32 b = host->sdma_boundary;
2109
2110 spin_lock_irqsave(&host->lock, flags);
2111
2112 cmd.opcode = opcode;
2113 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2114 cmd.mrq = &mrq;
2115
2116 mrq.cmd = &cmd;
2117 /*
2118 * In response to CMD19, the card sends 64 bytes of tuning
2119 * block to the Host Controller. So we set the block size
2120 * to 64 here.
2121 */
2122 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2123 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2124 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2125 else
2126 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2127
2128 /*
2129 * The tuning block is sent by the card to the host controller.
2130 * So we set the TRNS_READ bit in the Transfer Mode register.
2131 * This also takes care of setting DMA Enable and Multi Block
2132 * Select in the same register to 0.
2133 */
2134 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2135
2136 sdhci_send_command(host, &cmd);
2137
2138 host->cmd = NULL;
2139
2140 sdhci_del_timer(host, &mrq);
2141
2142 host->tuning_done = 0;
2143
2144 mmiowb();
2145 spin_unlock_irqrestore(&host->lock, flags);
2146
2147 /* Wait for Buffer Read Ready interrupt */
2148 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2149 msecs_to_jiffies(50));
2150
2151 }
2152
2153 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2154 {
2155 int i;
2156
2157 /*
2158 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2159 * of loops reaches 40 times.
2160 */
2161 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2162 u16 ctrl;
2163
2164 sdhci_send_tuning(host, opcode);
2165
2166 if (!host->tuning_done) {
2167 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2168 mmc_hostname(host->mmc));
2169 sdhci_abort_tuning(host, opcode);
2170 return;
2171 }
2172
2173 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2174 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2175 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2176 return; /* Success! */
2177 break;
2178 }
2179
2180 /* Spec does not require a delay between tuning cycles */
2181 if (host->tuning_delay > 0)
2182 mdelay(host->tuning_delay);
2183 }
2184
2185 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2186 mmc_hostname(host->mmc));
2187 sdhci_reset_tuning(host);
2188 }
2189
2190 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2191 {
2192 struct sdhci_host *host = mmc_priv(mmc);
2193 int err = 0;
2194 unsigned int tuning_count = 0;
2195 bool hs400_tuning;
2196
2197 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2198
2199 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2200 tuning_count = host->tuning_count;
2201
2202 /*
2203 * The Host Controller needs tuning in case of SDR104 and DDR50
2204 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2205 * the Capabilities register.
2206 * If the Host Controller supports the HS200 mode then the
2207 * tuning function has to be executed.
2208 */
2209 switch (host->timing) {
2210 /* HS400 tuning is done in HS200 mode */
2211 case MMC_TIMING_MMC_HS400:
2212 err = -EINVAL;
2213 goto out;
2214
2215 case MMC_TIMING_MMC_HS200:
2216 /*
2217 * Periodic re-tuning for HS400 is not expected to be needed, so
2218 * disable it here.
2219 */
2220 if (hs400_tuning)
2221 tuning_count = 0;
2222 break;
2223
2224 case MMC_TIMING_UHS_SDR104:
2225 case MMC_TIMING_UHS_DDR50:
2226 break;
2227
2228 case MMC_TIMING_UHS_SDR50:
2229 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2230 break;
2231 /* FALLTHROUGH */
2232
2233 default:
2234 goto out;
2235 }
2236
2237 if (host->ops->platform_execute_tuning) {
2238 err = host->ops->platform_execute_tuning(host, opcode);
2239 goto out;
2240 }
2241
2242 host->mmc->retune_period = tuning_count;
2243
2244 if (host->tuning_delay < 0)
2245 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2246
2247 sdhci_start_tuning(host);
2248
2249 __sdhci_execute_tuning(host, opcode);
2250
2251 sdhci_end_tuning(host);
2252 out:
2253 host->flags &= ~SDHCI_HS400_TUNING;
2254
2255 return err;
2256 }
2257 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2258
2259 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2260 {
2261 /* Host Controller v3.00 defines preset value registers */
2262 if (host->version < SDHCI_SPEC_300)
2263 return;
2264
2265 /*
2266 * We only enable or disable Preset Value if they are not already
2267 * enabled or disabled respectively. Otherwise, we bail out.
2268 */
2269 if (host->preset_enabled != enable) {
2270 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2271
2272 if (enable)
2273 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2274 else
2275 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2276
2277 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2278
2279 if (enable)
2280 host->flags |= SDHCI_PV_ENABLED;
2281 else
2282 host->flags &= ~SDHCI_PV_ENABLED;
2283
2284 host->preset_enabled = enable;
2285 }
2286 }
2287
2288 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2289 int err)
2290 {
2291 struct sdhci_host *host = mmc_priv(mmc);
2292 struct mmc_data *data = mrq->data;
2293
2294 if (data->host_cookie != COOKIE_UNMAPPED)
2295 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2296 mmc_get_dma_dir(data));
2297
2298 data->host_cookie = COOKIE_UNMAPPED;
2299 }
2300
2301 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2302 {
2303 struct sdhci_host *host = mmc_priv(mmc);
2304
2305 mrq->data->host_cookie = COOKIE_UNMAPPED;
2306
2307 /*
2308 * No pre-mapping in the pre hook if we're using the bounce buffer,
2309 * for that we would need two bounce buffers since one buffer is
2310 * in flight when this is getting called.
2311 */
2312 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2313 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2314 }
2315
2316 static inline bool sdhci_has_requests(struct sdhci_host *host)
2317 {
2318 return host->cmd || host->data_cmd;
2319 }
2320
2321 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2322 {
2323 if (host->data_cmd) {
2324 host->data_cmd->error = err;
2325 sdhci_finish_mrq(host, host->data_cmd->mrq);
2326 }
2327
2328 if (host->cmd) {
2329 host->cmd->error = err;
2330 sdhci_finish_mrq(host, host->cmd->mrq);
2331 }
2332 }
2333
2334 static void sdhci_card_event(struct mmc_host *mmc)
2335 {
2336 struct sdhci_host *host = mmc_priv(mmc);
2337 unsigned long flags;
2338 int present;
2339
2340 /* First check if client has provided their own card event */
2341 if (host->ops->card_event)
2342 host->ops->card_event(host);
2343
2344 present = mmc->ops->get_cd(mmc);
2345
2346 spin_lock_irqsave(&host->lock, flags);
2347
2348 /* Check sdhci_has_requests() first in case we are runtime suspended */
2349 if (sdhci_has_requests(host) && !present) {
2350 pr_err("%s: Card removed during transfer!\n",
2351 mmc_hostname(host->mmc));
2352 pr_err("%s: Resetting controller.\n",
2353 mmc_hostname(host->mmc));
2354
2355 sdhci_do_reset(host, SDHCI_RESET_CMD);
2356 sdhci_do_reset(host, SDHCI_RESET_DATA);
2357
2358 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2359 }
2360
2361 spin_unlock_irqrestore(&host->lock, flags);
2362 }
2363
2364 static const struct mmc_host_ops sdhci_ops = {
2365 .request = sdhci_request,
2366 .post_req = sdhci_post_req,
2367 .pre_req = sdhci_pre_req,
2368 .set_ios = sdhci_set_ios,
2369 .get_cd = sdhci_get_cd,
2370 .get_ro = sdhci_get_ro,
2371 .hw_reset = sdhci_hw_reset,
2372 .enable_sdio_irq = sdhci_enable_sdio_irq,
2373 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2374 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2375 .execute_tuning = sdhci_execute_tuning,
2376 .card_event = sdhci_card_event,
2377 .card_busy = sdhci_card_busy,
2378 };
2379
2380 /*****************************************************************************\
2381 * *
2382 * Tasklets *
2383 * *
2384 \*****************************************************************************/
2385
2386 static bool sdhci_request_done(struct sdhci_host *host)
2387 {
2388 unsigned long flags;
2389 struct mmc_request *mrq;
2390 int i;
2391
2392 spin_lock_irqsave(&host->lock, flags);
2393
2394 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2395 mrq = host->mrqs_done[i];
2396 if (mrq)
2397 break;
2398 }
2399
2400 if (!mrq) {
2401 spin_unlock_irqrestore(&host->lock, flags);
2402 return true;
2403 }
2404
2405 sdhci_del_timer(host, mrq);
2406
2407 /*
2408 * Always unmap the data buffers if they were mapped by
2409 * sdhci_prepare_data() whenever we finish with a request.
2410 * This avoids leaking DMA mappings on error.
2411 */
2412 if (host->flags & SDHCI_REQ_USE_DMA) {
2413 struct mmc_data *data = mrq->data;
2414
2415 if (data && data->host_cookie == COOKIE_MAPPED) {
2416 if (host->bounce_buffer) {
2417 /*
2418 * On reads, copy the bounced data into the
2419 * sglist
2420 */
2421 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2422 unsigned int length = data->bytes_xfered;
2423
2424 if (length > host->bounce_buffer_size) {
2425 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2426 mmc_hostname(host->mmc),
2427 host->bounce_buffer_size,
2428 data->bytes_xfered);
2429 /* Cap it down and continue */
2430 length = host->bounce_buffer_size;
2431 }
2432 dma_sync_single_for_cpu(
2433 host->mmc->parent,
2434 host->bounce_addr,
2435 host->bounce_buffer_size,
2436 DMA_FROM_DEVICE);
2437 sg_copy_from_buffer(data->sg,
2438 data->sg_len,
2439 host->bounce_buffer,
2440 length);
2441 } else {
2442 /* No copying, just switch ownership */
2443 dma_sync_single_for_cpu(
2444 host->mmc->parent,
2445 host->bounce_addr,
2446 host->bounce_buffer_size,
2447 mmc_get_dma_dir(data));
2448 }
2449 } else {
2450 /* Unmap the raw data */
2451 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2452 data->sg_len,
2453 mmc_get_dma_dir(data));
2454 }
2455 data->host_cookie = COOKIE_UNMAPPED;
2456 }
2457 }
2458
2459 /*
2460 * The controller needs a reset of internal state machines
2461 * upon error conditions.
2462 */
2463 if (sdhci_needs_reset(host, mrq)) {
2464 /*
2465 * Do not finish until command and data lines are available for
2466 * reset. Note there can only be one other mrq, so it cannot
2467 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2468 * would both be null.
2469 */
2470 if (host->cmd || host->data_cmd) {
2471 spin_unlock_irqrestore(&host->lock, flags);
2472 return true;
2473 }
2474
2475 /* Some controllers need this kick or reset won't work here */
2476 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2477 /* This is to force an update */
2478 host->ops->set_clock(host, host->clock);
2479
2480 /* Spec says we should do both at the same time, but Ricoh
2481 controllers do not like that. */
2482 sdhci_do_reset(host, SDHCI_RESET_CMD);
2483 sdhci_do_reset(host, SDHCI_RESET_DATA);
2484
2485 host->pending_reset = false;
2486 }
2487
2488 if (!sdhci_has_requests(host))
2489 sdhci_led_deactivate(host);
2490
2491 host->mrqs_done[i] = NULL;
2492
2493 mmiowb();
2494 spin_unlock_irqrestore(&host->lock, flags);
2495
2496 mmc_request_done(host->mmc, mrq);
2497
2498 return false;
2499 }
2500
2501 static void sdhci_tasklet_finish(unsigned long param)
2502 {
2503 struct sdhci_host *host = (struct sdhci_host *)param;
2504
2505 while (!sdhci_request_done(host))
2506 ;
2507 }
2508
2509 static void sdhci_timeout_timer(struct timer_list *t)
2510 {
2511 struct sdhci_host *host;
2512 unsigned long flags;
2513
2514 host = from_timer(host, t, timer);
2515
2516 spin_lock_irqsave(&host->lock, flags);
2517
2518 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2519 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2520 mmc_hostname(host->mmc));
2521 sdhci_dumpregs(host);
2522
2523 host->cmd->error = -ETIMEDOUT;
2524 sdhci_finish_mrq(host, host->cmd->mrq);
2525 }
2526
2527 mmiowb();
2528 spin_unlock_irqrestore(&host->lock, flags);
2529 }
2530
2531 static void sdhci_timeout_data_timer(struct timer_list *t)
2532 {
2533 struct sdhci_host *host;
2534 unsigned long flags;
2535
2536 host = from_timer(host, t, data_timer);
2537
2538 spin_lock_irqsave(&host->lock, flags);
2539
2540 if (host->data || host->data_cmd ||
2541 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2542 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2543 mmc_hostname(host->mmc));
2544 sdhci_dumpregs(host);
2545
2546 if (host->data) {
2547 host->data->error = -ETIMEDOUT;
2548 sdhci_finish_data(host);
2549 } else if (host->data_cmd) {
2550 host->data_cmd->error = -ETIMEDOUT;
2551 sdhci_finish_mrq(host, host->data_cmd->mrq);
2552 } else {
2553 host->cmd->error = -ETIMEDOUT;
2554 sdhci_finish_mrq(host, host->cmd->mrq);
2555 }
2556 }
2557
2558 mmiowb();
2559 spin_unlock_irqrestore(&host->lock, flags);
2560 }
2561
2562 /*****************************************************************************\
2563 * *
2564 * Interrupt handling *
2565 * *
2566 \*****************************************************************************/
2567
2568 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2569 {
2570 /* Handle auto-CMD12 error */
2571 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
2572 struct mmc_request *mrq = host->data_cmd->mrq;
2573 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2574 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2575 SDHCI_INT_DATA_TIMEOUT :
2576 SDHCI_INT_DATA_CRC;
2577
2578 /* Treat auto-CMD12 error the same as data error */
2579 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
2580 *intmask_p |= data_err_bit;
2581 return;
2582 }
2583 }
2584
2585 if (!host->cmd) {
2586 /*
2587 * SDHCI recovers from errors by resetting the cmd and data
2588 * circuits. Until that is done, there very well might be more
2589 * interrupts, so ignore them in that case.
2590 */
2591 if (host->pending_reset)
2592 return;
2593 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2594 mmc_hostname(host->mmc), (unsigned)intmask);
2595 sdhci_dumpregs(host);
2596 return;
2597 }
2598
2599 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2600 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2601 if (intmask & SDHCI_INT_TIMEOUT)
2602 host->cmd->error = -ETIMEDOUT;
2603 else
2604 host->cmd->error = -EILSEQ;
2605
2606 /* Treat data command CRC error the same as data CRC error */
2607 if (host->cmd->data &&
2608 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2609 SDHCI_INT_CRC) {
2610 host->cmd = NULL;
2611 *intmask_p |= SDHCI_INT_DATA_CRC;
2612 return;
2613 }
2614
2615 sdhci_finish_mrq(host, host->cmd->mrq);
2616 return;
2617 }
2618
2619 /* Handle auto-CMD23 error */
2620 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
2621 struct mmc_request *mrq = host->cmd->mrq;
2622 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2623 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2624 -ETIMEDOUT :
2625 -EILSEQ;
2626
2627 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2628 mrq->sbc->error = err;
2629 sdhci_finish_mrq(host, mrq);
2630 return;
2631 }
2632 }
2633
2634 if (intmask & SDHCI_INT_RESPONSE)
2635 sdhci_finish_command(host);
2636 }
2637
2638 static void sdhci_adma_show_error(struct sdhci_host *host)
2639 {
2640 void *desc = host->adma_table;
2641
2642 sdhci_dumpregs(host);
2643
2644 while (true) {
2645 struct sdhci_adma2_64_desc *dma_desc = desc;
2646
2647 if (host->flags & SDHCI_USE_64_BIT_DMA)
2648 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2649 desc, le32_to_cpu(dma_desc->addr_hi),
2650 le32_to_cpu(dma_desc->addr_lo),
2651 le16_to_cpu(dma_desc->len),
2652 le16_to_cpu(dma_desc->cmd));
2653 else
2654 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2655 desc, le32_to_cpu(dma_desc->addr_lo),
2656 le16_to_cpu(dma_desc->len),
2657 le16_to_cpu(dma_desc->cmd));
2658
2659 desc += host->desc_sz;
2660
2661 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2662 break;
2663 }
2664 }
2665
2666 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2667 {
2668 u32 command;
2669
2670 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2671 if (intmask & SDHCI_INT_DATA_AVAIL) {
2672 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2673 if (command == MMC_SEND_TUNING_BLOCK ||
2674 command == MMC_SEND_TUNING_BLOCK_HS200) {
2675 host->tuning_done = 1;
2676 wake_up(&host->buf_ready_int);
2677 return;
2678 }
2679 }
2680
2681 if (!host->data) {
2682 struct mmc_command *data_cmd = host->data_cmd;
2683
2684 /*
2685 * The "data complete" interrupt is also used to
2686 * indicate that a busy state has ended. See comment
2687 * above in sdhci_cmd_irq().
2688 */
2689 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2690 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2691 host->data_cmd = NULL;
2692 data_cmd->error = -ETIMEDOUT;
2693 sdhci_finish_mrq(host, data_cmd->mrq);
2694 return;
2695 }
2696 if (intmask & SDHCI_INT_DATA_END) {
2697 host->data_cmd = NULL;
2698 /*
2699 * Some cards handle busy-end interrupt
2700 * before the command completed, so make
2701 * sure we do things in the proper order.
2702 */
2703 if (host->cmd == data_cmd)
2704 return;
2705
2706 sdhci_finish_mrq(host, data_cmd->mrq);
2707 return;
2708 }
2709 }
2710
2711 /*
2712 * SDHCI recovers from errors by resetting the cmd and data
2713 * circuits. Until that is done, there very well might be more
2714 * interrupts, so ignore them in that case.
2715 */
2716 if (host->pending_reset)
2717 return;
2718
2719 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2720 mmc_hostname(host->mmc), (unsigned)intmask);
2721 sdhci_dumpregs(host);
2722
2723 return;
2724 }
2725
2726 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2727 host->data->error = -ETIMEDOUT;
2728 else if (intmask & SDHCI_INT_DATA_END_BIT)
2729 host->data->error = -EILSEQ;
2730 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2731 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2732 != MMC_BUS_TEST_R)
2733 host->data->error = -EILSEQ;
2734 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2735 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2736 sdhci_adma_show_error(host);
2737 host->data->error = -EIO;
2738 if (host->ops->adma_workaround)
2739 host->ops->adma_workaround(host, intmask);
2740 }
2741
2742 if (host->data->error)
2743 sdhci_finish_data(host);
2744 else {
2745 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2746 sdhci_transfer_pio(host);
2747
2748 /*
2749 * We currently don't do anything fancy with DMA
2750 * boundaries, but as we can't disable the feature
2751 * we need to at least restart the transfer.
2752 *
2753 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2754 * should return a valid address to continue from, but as
2755 * some controllers are faulty, don't trust them.
2756 */
2757 if (intmask & SDHCI_INT_DMA_END) {
2758 u32 dmastart, dmanow;
2759
2760 dmastart = sdhci_sdma_address(host);
2761 dmanow = dmastart + host->data->bytes_xfered;
2762 /*
2763 * Force update to the next DMA block boundary.
2764 */
2765 dmanow = (dmanow &
2766 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2767 SDHCI_DEFAULT_BOUNDARY_SIZE;
2768 host->data->bytes_xfered = dmanow - dmastart;
2769 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2770 dmastart, host->data->bytes_xfered, dmanow);
2771 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2772 }
2773
2774 if (intmask & SDHCI_INT_DATA_END) {
2775 if (host->cmd == host->data_cmd) {
2776 /*
2777 * Data managed to finish before the
2778 * command completed. Make sure we do
2779 * things in the proper order.
2780 */
2781 host->data_early = 1;
2782 } else {
2783 sdhci_finish_data(host);
2784 }
2785 }
2786 }
2787 }
2788
2789 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2790 {
2791 irqreturn_t result = IRQ_NONE;
2792 struct sdhci_host *host = dev_id;
2793 u32 intmask, mask, unexpected = 0;
2794 int max_loops = 16;
2795
2796 spin_lock(&host->lock);
2797
2798 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2799 spin_unlock(&host->lock);
2800 return IRQ_NONE;
2801 }
2802
2803 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2804 if (!intmask || intmask == 0xffffffff) {
2805 result = IRQ_NONE;
2806 goto out;
2807 }
2808
2809 do {
2810 DBG("IRQ status 0x%08x\n", intmask);
2811
2812 if (host->ops->irq) {
2813 intmask = host->ops->irq(host, intmask);
2814 if (!intmask)
2815 goto cont;
2816 }
2817
2818 /* Clear selected interrupts. */
2819 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2820 SDHCI_INT_BUS_POWER);
2821 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2822
2823 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2824 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2825 SDHCI_CARD_PRESENT;
2826
2827 /*
2828 * There is a observation on i.mx esdhc. INSERT
2829 * bit will be immediately set again when it gets
2830 * cleared, if a card is inserted. We have to mask
2831 * the irq to prevent interrupt storm which will
2832 * freeze the system. And the REMOVE gets the
2833 * same situation.
2834 *
2835 * More testing are needed here to ensure it works
2836 * for other platforms though.
2837 */
2838 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2839 SDHCI_INT_CARD_REMOVE);
2840 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2841 SDHCI_INT_CARD_INSERT;
2842 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2843 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2844
2845 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2846 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2847
2848 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2849 SDHCI_INT_CARD_REMOVE);
2850 result = IRQ_WAKE_THREAD;
2851 }
2852
2853 if (intmask & SDHCI_INT_CMD_MASK)
2854 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
2855
2856 if (intmask & SDHCI_INT_DATA_MASK)
2857 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2858
2859 if (intmask & SDHCI_INT_BUS_POWER)
2860 pr_err("%s: Card is consuming too much power!\n",
2861 mmc_hostname(host->mmc));
2862
2863 if (intmask & SDHCI_INT_RETUNE)
2864 mmc_retune_needed(host->mmc);
2865
2866 if ((intmask & SDHCI_INT_CARD_INT) &&
2867 (host->ier & SDHCI_INT_CARD_INT)) {
2868 sdhci_enable_sdio_irq_nolock(host, false);
2869 host->thread_isr |= SDHCI_INT_CARD_INT;
2870 result = IRQ_WAKE_THREAD;
2871 }
2872
2873 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2874 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2875 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2876 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2877
2878 if (intmask) {
2879 unexpected |= intmask;
2880 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2881 }
2882 cont:
2883 if (result == IRQ_NONE)
2884 result = IRQ_HANDLED;
2885
2886 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2887 } while (intmask && --max_loops);
2888 out:
2889 spin_unlock(&host->lock);
2890
2891 if (unexpected) {
2892 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2893 mmc_hostname(host->mmc), unexpected);
2894 sdhci_dumpregs(host);
2895 }
2896
2897 return result;
2898 }
2899
2900 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2901 {
2902 struct sdhci_host *host = dev_id;
2903 unsigned long flags;
2904 u32 isr;
2905
2906 spin_lock_irqsave(&host->lock, flags);
2907 isr = host->thread_isr;
2908 host->thread_isr = 0;
2909 spin_unlock_irqrestore(&host->lock, flags);
2910
2911 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2912 struct mmc_host *mmc = host->mmc;
2913
2914 mmc->ops->card_event(mmc);
2915 mmc_detect_change(mmc, msecs_to_jiffies(200));
2916 }
2917
2918 if (isr & SDHCI_INT_CARD_INT) {
2919 sdio_run_irqs(host->mmc);
2920
2921 spin_lock_irqsave(&host->lock, flags);
2922 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2923 sdhci_enable_sdio_irq_nolock(host, true);
2924 spin_unlock_irqrestore(&host->lock, flags);
2925 }
2926
2927 return isr ? IRQ_HANDLED : IRQ_NONE;
2928 }
2929
2930 /*****************************************************************************\
2931 * *
2932 * Suspend/resume *
2933 * *
2934 \*****************************************************************************/
2935
2936 #ifdef CONFIG_PM
2937 /*
2938 * To enable wakeup events, the corresponding events have to be enabled in
2939 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2940 * Table' in the SD Host Controller Standard Specification.
2941 * It is useless to restore SDHCI_INT_ENABLE state in
2942 * sdhci_disable_irq_wakeups() since it will be set by
2943 * sdhci_enable_card_detection() or sdhci_init().
2944 */
2945 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2946 {
2947 u8 val;
2948 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2949 | SDHCI_WAKE_ON_INT;
2950 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2951 SDHCI_INT_CARD_INT;
2952
2953 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2954 val |= mask ;
2955 /* Avoid fake wake up */
2956 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2957 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2958 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2959 }
2960 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2961 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2962 }
2963 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2964
2965 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2966 {
2967 u8 val;
2968 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2969 | SDHCI_WAKE_ON_INT;
2970
2971 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2972 val &= ~mask;
2973 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2974 }
2975
2976 int sdhci_suspend_host(struct sdhci_host *host)
2977 {
2978 sdhci_disable_card_detection(host);
2979
2980 mmc_retune_timer_stop(host->mmc);
2981
2982 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2983 host->ier = 0;
2984 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2985 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2986 free_irq(host->irq, host);
2987 } else {
2988 sdhci_enable_irq_wakeups(host);
2989 enable_irq_wake(host->irq);
2990 }
2991 return 0;
2992 }
2993
2994 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2995
2996 int sdhci_resume_host(struct sdhci_host *host)
2997 {
2998 struct mmc_host *mmc = host->mmc;
2999 int ret = 0;
3000
3001 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3002 if (host->ops->enable_dma)
3003 host->ops->enable_dma(host);
3004 }
3005
3006 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3007 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3008 /* Card keeps power but host controller does not */
3009 sdhci_init(host, 0);
3010 host->pwr = 0;
3011 host->clock = 0;
3012 mmc->ops->set_ios(mmc, &mmc->ios);
3013 } else {
3014 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3015 mmiowb();
3016 }
3017
3018 if (!device_may_wakeup(mmc_dev(host->mmc))) {
3019 ret = request_threaded_irq(host->irq, sdhci_irq,
3020 sdhci_thread_irq, IRQF_SHARED,
3021 mmc_hostname(host->mmc), host);
3022 if (ret)
3023 return ret;
3024 } else {
3025 sdhci_disable_irq_wakeups(host);
3026 disable_irq_wake(host->irq);
3027 }
3028
3029 sdhci_enable_card_detection(host);
3030
3031 return ret;
3032 }
3033
3034 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3035
3036 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3037 {
3038 unsigned long flags;
3039
3040 mmc_retune_timer_stop(host->mmc);
3041
3042 spin_lock_irqsave(&host->lock, flags);
3043 host->ier &= SDHCI_INT_CARD_INT;
3044 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3045 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3046 spin_unlock_irqrestore(&host->lock, flags);
3047
3048 synchronize_hardirq(host->irq);
3049
3050 spin_lock_irqsave(&host->lock, flags);
3051 host->runtime_suspended = true;
3052 spin_unlock_irqrestore(&host->lock, flags);
3053
3054 return 0;
3055 }
3056 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3057
3058 int sdhci_runtime_resume_host(struct sdhci_host *host)
3059 {
3060 struct mmc_host *mmc = host->mmc;
3061 unsigned long flags;
3062 int host_flags = host->flags;
3063
3064 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3065 if (host->ops->enable_dma)
3066 host->ops->enable_dma(host);
3067 }
3068
3069 sdhci_init(host, 0);
3070
3071 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3072 mmc->ios.power_mode != MMC_POWER_OFF) {
3073 /* Force clock and power re-program */
3074 host->pwr = 0;
3075 host->clock = 0;
3076 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3077 mmc->ops->set_ios(mmc, &mmc->ios);
3078
3079 if ((host_flags & SDHCI_PV_ENABLED) &&
3080 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3081 spin_lock_irqsave(&host->lock, flags);
3082 sdhci_enable_preset_value(host, true);
3083 spin_unlock_irqrestore(&host->lock, flags);
3084 }
3085
3086 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3087 mmc->ops->hs400_enhanced_strobe)
3088 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3089 }
3090
3091 spin_lock_irqsave(&host->lock, flags);
3092
3093 host->runtime_suspended = false;
3094
3095 /* Enable SDIO IRQ */
3096 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3097 sdhci_enable_sdio_irq_nolock(host, true);
3098
3099 /* Enable Card Detection */
3100 sdhci_enable_card_detection(host);
3101
3102 spin_unlock_irqrestore(&host->lock, flags);
3103
3104 return 0;
3105 }
3106 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3107
3108 #endif /* CONFIG_PM */
3109
3110 /*****************************************************************************\
3111 * *
3112 * Command Queue Engine (CQE) helpers *
3113 * *
3114 \*****************************************************************************/
3115
3116 void sdhci_cqe_enable(struct mmc_host *mmc)
3117 {
3118 struct sdhci_host *host = mmc_priv(mmc);
3119 unsigned long flags;
3120 u8 ctrl;
3121
3122 spin_lock_irqsave(&host->lock, flags);
3123
3124 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3125 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3126 if (host->flags & SDHCI_USE_64_BIT_DMA)
3127 ctrl |= SDHCI_CTRL_ADMA64;
3128 else
3129 ctrl |= SDHCI_CTRL_ADMA32;
3130 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3131
3132 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3133 SDHCI_BLOCK_SIZE);
3134
3135 /* Set maximum timeout */
3136 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3137
3138 host->ier = host->cqe_ier;
3139
3140 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3141 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3142
3143 host->cqe_on = true;
3144
3145 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3146 mmc_hostname(mmc), host->ier,
3147 sdhci_readl(host, SDHCI_INT_STATUS));
3148
3149 mmiowb();
3150 spin_unlock_irqrestore(&host->lock, flags);
3151 }
3152 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3153
3154 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3155 {
3156 struct sdhci_host *host = mmc_priv(mmc);
3157 unsigned long flags;
3158
3159 spin_lock_irqsave(&host->lock, flags);
3160
3161 sdhci_set_default_irqs(host);
3162
3163 host->cqe_on = false;
3164
3165 if (recovery) {
3166 sdhci_do_reset(host, SDHCI_RESET_CMD);
3167 sdhci_do_reset(host, SDHCI_RESET_DATA);
3168 }
3169
3170 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3171 mmc_hostname(mmc), host->ier,
3172 sdhci_readl(host, SDHCI_INT_STATUS));
3173
3174 mmiowb();
3175 spin_unlock_irqrestore(&host->lock, flags);
3176 }
3177 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3178
3179 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3180 int *data_error)
3181 {
3182 u32 mask;
3183
3184 if (!host->cqe_on)
3185 return false;
3186
3187 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3188 *cmd_error = -EILSEQ;
3189 else if (intmask & SDHCI_INT_TIMEOUT)
3190 *cmd_error = -ETIMEDOUT;
3191 else
3192 *cmd_error = 0;
3193
3194 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3195 *data_error = -EILSEQ;
3196 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3197 *data_error = -ETIMEDOUT;
3198 else if (intmask & SDHCI_INT_ADMA_ERROR)
3199 *data_error = -EIO;
3200 else
3201 *data_error = 0;
3202
3203 /* Clear selected interrupts. */
3204 mask = intmask & host->cqe_ier;
3205 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3206
3207 if (intmask & SDHCI_INT_BUS_POWER)
3208 pr_err("%s: Card is consuming too much power!\n",
3209 mmc_hostname(host->mmc));
3210
3211 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3212 if (intmask) {
3213 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3214 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3215 mmc_hostname(host->mmc), intmask);
3216 sdhci_dumpregs(host);
3217 }
3218
3219 return true;
3220 }
3221 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3222
3223 /*****************************************************************************\
3224 * *
3225 * Device allocation/registration *
3226 * *
3227 \*****************************************************************************/
3228
3229 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3230 size_t priv_size)
3231 {
3232 struct mmc_host *mmc;
3233 struct sdhci_host *host;
3234
3235 WARN_ON(dev == NULL);
3236
3237 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3238 if (!mmc)
3239 return ERR_PTR(-ENOMEM);
3240
3241 host = mmc_priv(mmc);
3242 host->mmc = mmc;
3243 host->mmc_host_ops = sdhci_ops;
3244 mmc->ops = &host->mmc_host_ops;
3245
3246 host->flags = SDHCI_SIGNALING_330;
3247
3248 host->cqe_ier = SDHCI_CQE_INT_MASK;
3249 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3250
3251 host->tuning_delay = -1;
3252
3253 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3254
3255 return host;
3256 }
3257
3258 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3259
3260 static int sdhci_set_dma_mask(struct sdhci_host *host)
3261 {
3262 struct mmc_host *mmc = host->mmc;
3263 struct device *dev = mmc_dev(mmc);
3264 int ret = -EINVAL;
3265
3266 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3267 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3268
3269 /* Try 64-bit mask if hardware is capable of it */
3270 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3271 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3272 if (ret) {
3273 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3274 mmc_hostname(mmc));
3275 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3276 }
3277 }
3278
3279 /* 32-bit mask as default & fallback */
3280 if (ret) {
3281 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3282 if (ret)
3283 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3284 mmc_hostname(mmc));
3285 }
3286
3287 return ret;
3288 }
3289
3290 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3291 {
3292 u16 v;
3293 u64 dt_caps_mask = 0;
3294 u64 dt_caps = 0;
3295
3296 if (host->read_caps)
3297 return;
3298
3299 host->read_caps = true;
3300
3301 if (debug_quirks)
3302 host->quirks = debug_quirks;
3303
3304 if (debug_quirks2)
3305 host->quirks2 = debug_quirks2;
3306
3307 sdhci_do_reset(host, SDHCI_RESET_ALL);
3308
3309 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3310 "sdhci-caps-mask", &dt_caps_mask);
3311 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3312 "sdhci-caps", &dt_caps);
3313
3314 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3315 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3316
3317 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3318 return;
3319
3320 if (caps) {
3321 host->caps = *caps;
3322 } else {
3323 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3324 host->caps &= ~lower_32_bits(dt_caps_mask);
3325 host->caps |= lower_32_bits(dt_caps);
3326 }
3327
3328 if (host->version < SDHCI_SPEC_300)
3329 return;
3330
3331 if (caps1) {
3332 host->caps1 = *caps1;
3333 } else {
3334 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3335 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3336 host->caps1 |= upper_32_bits(dt_caps);
3337 }
3338 }
3339 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3340
3341 static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3342 {
3343 struct mmc_host *mmc = host->mmc;
3344 unsigned int max_blocks;
3345 unsigned int bounce_size;
3346 int ret;
3347
3348 /*
3349 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3350 * has diminishing returns, this is probably because SD/MMC
3351 * cards are usually optimized to handle this size of requests.
3352 */
3353 bounce_size = SZ_64K;
3354 /*
3355 * Adjust downwards to maximum request size if this is less
3356 * than our segment size, else hammer down the maximum
3357 * request size to the maximum buffer size.
3358 */
3359 if (mmc->max_req_size < bounce_size)
3360 bounce_size = mmc->max_req_size;
3361 max_blocks = bounce_size / 512;
3362
3363 /*
3364 * When we just support one segment, we can get significant
3365 * speedups by the help of a bounce buffer to group scattered
3366 * reads/writes together.
3367 */
3368 host->bounce_buffer = devm_kmalloc(mmc->parent,
3369 bounce_size,
3370 GFP_KERNEL);
3371 if (!host->bounce_buffer) {
3372 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3373 mmc_hostname(mmc),
3374 bounce_size);
3375 /*
3376 * Exiting with zero here makes sure we proceed with
3377 * mmc->max_segs == 1.
3378 */
3379 return 0;
3380 }
3381
3382 host->bounce_addr = dma_map_single(mmc->parent,
3383 host->bounce_buffer,
3384 bounce_size,
3385 DMA_BIDIRECTIONAL);
3386 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3387 if (ret)
3388 /* Again fall back to max_segs == 1 */
3389 return 0;
3390 host->bounce_buffer_size = bounce_size;
3391
3392 /* Lie about this since we're bouncing */
3393 mmc->max_segs = max_blocks;
3394 mmc->max_seg_size = bounce_size;
3395 mmc->max_req_size = bounce_size;
3396
3397 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3398 mmc_hostname(mmc), max_blocks, bounce_size);
3399
3400 return 0;
3401 }
3402
3403 int sdhci_setup_host(struct sdhci_host *host)
3404 {
3405 struct mmc_host *mmc;
3406 u32 max_current_caps;
3407 unsigned int ocr_avail;
3408 unsigned int override_timeout_clk;
3409 u32 max_clk;
3410 int ret;
3411
3412 WARN_ON(host == NULL);
3413 if (host == NULL)
3414 return -EINVAL;
3415
3416 mmc = host->mmc;
3417
3418 /*
3419 * If there are external regulators, get them. Note this must be done
3420 * early before resetting the host and reading the capabilities so that
3421 * the host can take the appropriate action if regulators are not
3422 * available.
3423 */
3424 ret = mmc_regulator_get_supply(mmc);
3425 if (ret)
3426 return ret;
3427
3428 DBG("Version: 0x%08x | Present: 0x%08x\n",
3429 sdhci_readw(host, SDHCI_HOST_VERSION),
3430 sdhci_readl(host, SDHCI_PRESENT_STATE));
3431 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3432 sdhci_readl(host, SDHCI_CAPABILITIES),
3433 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3434
3435 sdhci_read_caps(host);
3436
3437 override_timeout_clk = host->timeout_clk;
3438
3439 if (host->version > SDHCI_SPEC_300) {
3440 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3441 mmc_hostname(mmc), host->version);
3442 }
3443
3444 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3445 host->flags |= SDHCI_USE_SDMA;
3446 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3447 DBG("Controller doesn't have SDMA capability\n");
3448 else
3449 host->flags |= SDHCI_USE_SDMA;
3450
3451 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3452 (host->flags & SDHCI_USE_SDMA)) {
3453 DBG("Disabling DMA as it is marked broken\n");
3454 host->flags &= ~SDHCI_USE_SDMA;
3455 }
3456
3457 if ((host->version >= SDHCI_SPEC_200) &&
3458 (host->caps & SDHCI_CAN_DO_ADMA2))
3459 host->flags |= SDHCI_USE_ADMA;
3460
3461 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3462 (host->flags & SDHCI_USE_ADMA)) {
3463 DBG("Disabling ADMA as it is marked broken\n");
3464 host->flags &= ~SDHCI_USE_ADMA;
3465 }
3466
3467 /*
3468 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3469 * and *must* do 64-bit DMA. A driver has the opportunity to change
3470 * that during the first call to ->enable_dma(). Similarly
3471 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3472 * implement.
3473 */
3474 if (host->caps & SDHCI_CAN_64BIT)
3475 host->flags |= SDHCI_USE_64_BIT_DMA;
3476
3477 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3478 ret = sdhci_set_dma_mask(host);
3479
3480 if (!ret && host->ops->enable_dma)
3481 ret = host->ops->enable_dma(host);
3482
3483 if (ret) {
3484 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3485 mmc_hostname(mmc));
3486 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3487
3488 ret = 0;
3489 }
3490 }
3491
3492 /* SDMA does not support 64-bit DMA */
3493 if (host->flags & SDHCI_USE_64_BIT_DMA)
3494 host->flags &= ~SDHCI_USE_SDMA;
3495
3496 if (host->flags & SDHCI_USE_ADMA) {
3497 dma_addr_t dma;
3498 void *buf;
3499
3500 /*
3501 * The DMA descriptor table size is calculated as the maximum
3502 * number of segments times 2, to allow for an alignment
3503 * descriptor for each segment, plus 1 for a nop end descriptor,
3504 * all multipled by the descriptor size.
3505 */
3506 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3507 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3508 SDHCI_ADMA2_64_DESC_SZ;
3509 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3510 } else {
3511 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3512 SDHCI_ADMA2_32_DESC_SZ;
3513 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3514 }
3515
3516 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3517 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3518 host->adma_table_sz, &dma, GFP_KERNEL);
3519 if (!buf) {
3520 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3521 mmc_hostname(mmc));
3522 host->flags &= ~SDHCI_USE_ADMA;
3523 } else if ((dma + host->align_buffer_sz) &
3524 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3525 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3526 mmc_hostname(mmc));
3527 host->flags &= ~SDHCI_USE_ADMA;
3528 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3529 host->adma_table_sz, buf, dma);
3530 } else {
3531 host->align_buffer = buf;
3532 host->align_addr = dma;
3533
3534 host->adma_table = buf + host->align_buffer_sz;
3535 host->adma_addr = dma + host->align_buffer_sz;
3536 }
3537 }
3538
3539 /*
3540 * If we use DMA, then it's up to the caller to set the DMA
3541 * mask, but PIO does not need the hw shim so we set a new
3542 * mask here in that case.
3543 */
3544 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3545 host->dma_mask = DMA_BIT_MASK(64);
3546 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3547 }
3548
3549 if (host->version >= SDHCI_SPEC_300)
3550 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3551 >> SDHCI_CLOCK_BASE_SHIFT;
3552 else
3553 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3554 >> SDHCI_CLOCK_BASE_SHIFT;
3555
3556 host->max_clk *= 1000000;
3557 if (host->max_clk == 0 || host->quirks &
3558 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3559 if (!host->ops->get_max_clock) {
3560 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3561 mmc_hostname(mmc));
3562 ret = -ENODEV;
3563 goto undma;
3564 }
3565 host->max_clk = host->ops->get_max_clock(host);
3566 }
3567
3568 /*
3569 * In case of Host Controller v3.00, find out whether clock
3570 * multiplier is supported.
3571 */
3572 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3573 SDHCI_CLOCK_MUL_SHIFT;
3574
3575 /*
3576 * In case the value in Clock Multiplier is 0, then programmable
3577 * clock mode is not supported, otherwise the actual clock
3578 * multiplier is one more than the value of Clock Multiplier
3579 * in the Capabilities Register.
3580 */
3581 if (host->clk_mul)
3582 host->clk_mul += 1;
3583
3584 /*
3585 * Set host parameters.
3586 */
3587 max_clk = host->max_clk;
3588
3589 if (host->ops->get_min_clock)
3590 mmc->f_min = host->ops->get_min_clock(host);
3591 else if (host->version >= SDHCI_SPEC_300) {
3592 if (host->clk_mul) {
3593 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3594 max_clk = host->max_clk * host->clk_mul;
3595 } else
3596 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3597 } else
3598 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3599
3600 if (!mmc->f_max || mmc->f_max > max_clk)
3601 mmc->f_max = max_clk;
3602
3603 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3604 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3605 SDHCI_TIMEOUT_CLK_SHIFT;
3606
3607 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3608 host->timeout_clk *= 1000;
3609
3610 if (host->timeout_clk == 0) {
3611 if (!host->ops->get_timeout_clock) {
3612 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3613 mmc_hostname(mmc));
3614 ret = -ENODEV;
3615 goto undma;
3616 }
3617
3618 host->timeout_clk =
3619 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3620 1000);
3621 }
3622
3623 if (override_timeout_clk)
3624 host->timeout_clk = override_timeout_clk;
3625
3626 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3627 host->ops->get_max_timeout_count(host) : 1 << 27;
3628 mmc->max_busy_timeout /= host->timeout_clk;
3629 }
3630
3631 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3632 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3633
3634 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3635 host->flags |= SDHCI_AUTO_CMD12;
3636
3637 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3638 if ((host->version >= SDHCI_SPEC_300) &&
3639 ((host->flags & SDHCI_USE_ADMA) ||
3640 !(host->flags & SDHCI_USE_SDMA)) &&
3641 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3642 host->flags |= SDHCI_AUTO_CMD23;
3643 DBG("Auto-CMD23 available\n");
3644 } else {
3645 DBG("Auto-CMD23 unavailable\n");
3646 }
3647
3648 /*
3649 * A controller may support 8-bit width, but the board itself
3650 * might not have the pins brought out. Boards that support
3651 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3652 * their platform code before calling sdhci_add_host(), and we
3653 * won't assume 8-bit width for hosts without that CAP.
3654 */
3655 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3656 mmc->caps |= MMC_CAP_4_BIT_DATA;
3657
3658 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3659 mmc->caps &= ~MMC_CAP_CMD23;
3660
3661 if (host->caps & SDHCI_CAN_DO_HISPD)
3662 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3663
3664 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3665 mmc_card_is_removable(mmc) &&
3666 mmc_gpio_get_cd(host->mmc) < 0)
3667 mmc->caps |= MMC_CAP_NEEDS_POLL;
3668
3669 if (!IS_ERR(mmc->supply.vqmmc)) {
3670 ret = regulator_enable(mmc->supply.vqmmc);
3671
3672 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3673 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3674 1950000))
3675 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3676 SDHCI_SUPPORT_SDR50 |
3677 SDHCI_SUPPORT_DDR50);
3678
3679 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3680 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3681 3600000))
3682 host->flags &= ~SDHCI_SIGNALING_330;
3683
3684 if (ret) {
3685 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3686 mmc_hostname(mmc), ret);
3687 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3688 }
3689 }
3690
3691 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3692 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3693 SDHCI_SUPPORT_DDR50);
3694 /*
3695 * The SDHCI controller in a SoC might support HS200/HS400
3696 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
3697 * but if the board is modeled such that the IO lines are not
3698 * connected to 1.8v then HS200/HS400 cannot be supported.
3699 * Disable HS200/HS400 if the board does not have 1.8v connected
3700 * to the IO lines. (Applicable for other modes in 1.8v)
3701 */
3702 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
3703 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
3704 }
3705
3706 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3707 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3708 SDHCI_SUPPORT_DDR50))
3709 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3710
3711 /* SDR104 supports also implies SDR50 support */
3712 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3713 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3714 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3715 * field can be promoted to support HS200.
3716 */
3717 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3718 mmc->caps2 |= MMC_CAP2_HS200;
3719 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3720 mmc->caps |= MMC_CAP_UHS_SDR50;
3721 }
3722
3723 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3724 (host->caps1 & SDHCI_SUPPORT_HS400))
3725 mmc->caps2 |= MMC_CAP2_HS400;
3726
3727 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3728 (IS_ERR(mmc->supply.vqmmc) ||
3729 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3730 1300000)))
3731 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3732
3733 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3734 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3735 mmc->caps |= MMC_CAP_UHS_DDR50;
3736
3737 /* Does the host need tuning for SDR50? */
3738 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3739 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3740
3741 /* Driver Type(s) (A, C, D) supported by the host */
3742 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3743 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3744 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3745 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3746 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3747 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3748
3749 /* Initial value for re-tuning timer count */
3750 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3751 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3752
3753 /*
3754 * In case Re-tuning Timer is not disabled, the actual value of
3755 * re-tuning timer will be 2 ^ (n - 1).
3756 */
3757 if (host->tuning_count)
3758 host->tuning_count = 1 << (host->tuning_count - 1);
3759
3760 /* Re-tuning mode supported by the Host Controller */
3761 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3762 SDHCI_RETUNING_MODE_SHIFT;
3763
3764 ocr_avail = 0;
3765
3766 /*
3767 * According to SD Host Controller spec v3.00, if the Host System
3768 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3769 * the value is meaningful only if Voltage Support in the Capabilities
3770 * register is set. The actual current value is 4 times the register
3771 * value.
3772 */
3773 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3774 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3775 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3776 if (curr > 0) {
3777
3778 /* convert to SDHCI_MAX_CURRENT format */
3779 curr = curr/1000; /* convert to mA */
3780 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3781
3782 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3783 max_current_caps =
3784 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3785 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3786 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3787 }
3788 }
3789
3790 if (host->caps & SDHCI_CAN_VDD_330) {
3791 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3792
3793 mmc->max_current_330 = ((max_current_caps &
3794 SDHCI_MAX_CURRENT_330_MASK) >>
3795 SDHCI_MAX_CURRENT_330_SHIFT) *
3796 SDHCI_MAX_CURRENT_MULTIPLIER;
3797 }
3798 if (host->caps & SDHCI_CAN_VDD_300) {
3799 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3800
3801 mmc->max_current_300 = ((max_current_caps &
3802 SDHCI_MAX_CURRENT_300_MASK) >>
3803 SDHCI_MAX_CURRENT_300_SHIFT) *
3804 SDHCI_MAX_CURRENT_MULTIPLIER;
3805 }
3806 if (host->caps & SDHCI_CAN_VDD_180) {
3807 ocr_avail |= MMC_VDD_165_195;
3808
3809 mmc->max_current_180 = ((max_current_caps &
3810 SDHCI_MAX_CURRENT_180_MASK) >>
3811 SDHCI_MAX_CURRENT_180_SHIFT) *
3812 SDHCI_MAX_CURRENT_MULTIPLIER;
3813 }
3814
3815 /* If OCR set by host, use it instead. */
3816 if (host->ocr_mask)
3817 ocr_avail = host->ocr_mask;
3818
3819 /* If OCR set by external regulators, give it highest prio. */
3820 if (mmc->ocr_avail)
3821 ocr_avail = mmc->ocr_avail;
3822
3823 mmc->ocr_avail = ocr_avail;
3824 mmc->ocr_avail_sdio = ocr_avail;
3825 if (host->ocr_avail_sdio)
3826 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3827 mmc->ocr_avail_sd = ocr_avail;
3828 if (host->ocr_avail_sd)
3829 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3830 else /* normal SD controllers don't support 1.8V */
3831 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3832 mmc->ocr_avail_mmc = ocr_avail;
3833 if (host->ocr_avail_mmc)
3834 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3835
3836 if (mmc->ocr_avail == 0) {
3837 pr_err("%s: Hardware doesn't report any support voltages.\n",
3838 mmc_hostname(mmc));
3839 ret = -ENODEV;
3840 goto unreg;
3841 }
3842
3843 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3844 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3845 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3846 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3847 host->flags |= SDHCI_SIGNALING_180;
3848
3849 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3850 host->flags |= SDHCI_SIGNALING_120;
3851
3852 spin_lock_init(&host->lock);
3853
3854 /*
3855 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3856 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3857 * is less anyway.
3858 */
3859 mmc->max_req_size = 524288;
3860
3861 /*
3862 * Maximum number of segments. Depends on if the hardware
3863 * can do scatter/gather or not.
3864 */
3865 if (host->flags & SDHCI_USE_ADMA) {
3866 mmc->max_segs = SDHCI_MAX_SEGS;
3867 } else if (host->flags & SDHCI_USE_SDMA) {
3868 mmc->max_segs = 1;
3869 if (swiotlb_max_segment()) {
3870 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3871 IO_TLB_SEGSIZE;
3872 mmc->max_req_size = min(mmc->max_req_size,
3873 max_req_size);
3874 }
3875 } else { /* PIO */
3876 mmc->max_segs = SDHCI_MAX_SEGS;
3877 }
3878
3879 /*
3880 * Maximum segment size. Could be one segment with the maximum number
3881 * of bytes. When doing hardware scatter/gather, each entry cannot
3882 * be larger than 64 KiB though.
3883 */
3884 if (host->flags & SDHCI_USE_ADMA) {
3885 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3886 mmc->max_seg_size = 65535;
3887 else
3888 mmc->max_seg_size = 65536;
3889 } else {
3890 mmc->max_seg_size = mmc->max_req_size;
3891 }
3892
3893 /*
3894 * Maximum block size. This varies from controller to controller and
3895 * is specified in the capabilities register.
3896 */
3897 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3898 mmc->max_blk_size = 2;
3899 } else {
3900 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3901 SDHCI_MAX_BLOCK_SHIFT;
3902 if (mmc->max_blk_size >= 3) {
3903 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3904 mmc_hostname(mmc));
3905 mmc->max_blk_size = 0;
3906 }
3907 }
3908
3909 mmc->max_blk_size = 512 << mmc->max_blk_size;
3910
3911 /*
3912 * Maximum block count.
3913 */
3914 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3915
3916 if (mmc->max_segs == 1) {
3917 /* This may alter mmc->*_blk_* parameters */
3918 ret = sdhci_allocate_bounce_buffer(host);
3919 if (ret)
3920 return ret;
3921 }
3922
3923 return 0;
3924
3925 unreg:
3926 if (!IS_ERR(mmc->supply.vqmmc))
3927 regulator_disable(mmc->supply.vqmmc);
3928 undma:
3929 if (host->align_buffer)
3930 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3931 host->adma_table_sz, host->align_buffer,
3932 host->align_addr);
3933 host->adma_table = NULL;
3934 host->align_buffer = NULL;
3935
3936 return ret;
3937 }
3938 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3939
3940 void sdhci_cleanup_host(struct sdhci_host *host)
3941 {
3942 struct mmc_host *mmc = host->mmc;
3943
3944 if (!IS_ERR(mmc->supply.vqmmc))
3945 regulator_disable(mmc->supply.vqmmc);
3946
3947 if (host->align_buffer)
3948 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3949 host->adma_table_sz, host->align_buffer,
3950 host->align_addr);
3951 host->adma_table = NULL;
3952 host->align_buffer = NULL;
3953 }
3954 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3955
3956 int __sdhci_add_host(struct sdhci_host *host)
3957 {
3958 struct mmc_host *mmc = host->mmc;
3959 int ret;
3960
3961 /*
3962 * Init tasklets.
3963 */
3964 tasklet_init(&host->finish_tasklet,
3965 sdhci_tasklet_finish, (unsigned long)host);
3966
3967 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3968 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3969
3970 init_waitqueue_head(&host->buf_ready_int);
3971
3972 sdhci_init(host, 0);
3973
3974 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3975 IRQF_SHARED, mmc_hostname(mmc), host);
3976 if (ret) {
3977 pr_err("%s: Failed to request IRQ %d: %d\n",
3978 mmc_hostname(mmc), host->irq, ret);
3979 goto untasklet;
3980 }
3981
3982 ret = sdhci_led_register(host);
3983 if (ret) {
3984 pr_err("%s: Failed to register LED device: %d\n",
3985 mmc_hostname(mmc), ret);
3986 goto unirq;
3987 }
3988
3989 mmiowb();
3990
3991 ret = mmc_add_host(mmc);
3992 if (ret)
3993 goto unled;
3994
3995 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3996 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3997 (host->flags & SDHCI_USE_ADMA) ?
3998 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3999 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4000
4001 sdhci_enable_card_detection(host);
4002
4003 return 0;
4004
4005 unled:
4006 sdhci_led_unregister(host);
4007 unirq:
4008 sdhci_do_reset(host, SDHCI_RESET_ALL);
4009 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4010 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4011 free_irq(host->irq, host);
4012 untasklet:
4013 tasklet_kill(&host->finish_tasklet);
4014
4015 return ret;
4016 }
4017 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4018
4019 int sdhci_add_host(struct sdhci_host *host)
4020 {
4021 int ret;
4022
4023 ret = sdhci_setup_host(host);
4024 if (ret)
4025 return ret;
4026
4027 ret = __sdhci_add_host(host);
4028 if (ret)
4029 goto cleanup;
4030
4031 return 0;
4032
4033 cleanup:
4034 sdhci_cleanup_host(host);
4035
4036 return ret;
4037 }
4038 EXPORT_SYMBOL_GPL(sdhci_add_host);
4039
4040 void sdhci_remove_host(struct sdhci_host *host, int dead)
4041 {
4042 struct mmc_host *mmc = host->mmc;
4043 unsigned long flags;
4044
4045 if (dead) {
4046 spin_lock_irqsave(&host->lock, flags);
4047
4048 host->flags |= SDHCI_DEVICE_DEAD;
4049
4050 if (sdhci_has_requests(host)) {
4051 pr_err("%s: Controller removed during "
4052 " transfer!\n", mmc_hostname(mmc));
4053 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4054 }
4055
4056 spin_unlock_irqrestore(&host->lock, flags);
4057 }
4058
4059 sdhci_disable_card_detection(host);
4060
4061 mmc_remove_host(mmc);
4062
4063 sdhci_led_unregister(host);
4064
4065 if (!dead)
4066 sdhci_do_reset(host, SDHCI_RESET_ALL);
4067
4068 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4069 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4070 free_irq(host->irq, host);
4071
4072 del_timer_sync(&host->timer);
4073 del_timer_sync(&host->data_timer);
4074
4075 tasklet_kill(&host->finish_tasklet);
4076
4077 if (!IS_ERR(mmc->supply.vqmmc))
4078 regulator_disable(mmc->supply.vqmmc);
4079
4080 if (host->align_buffer)
4081 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4082 host->adma_table_sz, host->align_buffer,
4083 host->align_addr);
4084
4085 host->adma_table = NULL;
4086 host->align_buffer = NULL;
4087 }
4088
4089 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4090
4091 void sdhci_free_host(struct sdhci_host *host)
4092 {
4093 mmc_free_host(host->mmc);
4094 }
4095
4096 EXPORT_SYMBOL_GPL(sdhci_free_host);
4097
4098 /*****************************************************************************\
4099 * *
4100 * Driver init/exit *
4101 * *
4102 \*****************************************************************************/
4103
4104 static int __init sdhci_drv_init(void)
4105 {
4106 pr_info(DRIVER_NAME
4107 ": Secure Digital Host Controller Interface driver\n");
4108 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4109
4110 return 0;
4111 }
4112
4113 static void __exit sdhci_drv_exit(void)
4114 {
4115 }
4116
4117 module_init(sdhci_drv_init);
4118 module_exit(sdhci_drv_exit);
4119
4120 module_param(debug_quirks, uint, 0444);
4121 module_param(debug_quirks2, uint, 0444);
4122
4123 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4124 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4125 MODULE_LICENSE("GPL");
4126
4127 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4128 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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