2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #define MAX_TUNING_LOOP 40
43 static unsigned int debug_quirks
= 0;
44 static unsigned int debug_quirks2
;
46 static void sdhci_finish_data(struct sdhci_host
*);
48 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
);
50 static void sdhci_dumpregs(struct sdhci_host
*host
)
52 pr_err(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host
->mmc
));
55 pr_err(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
57 sdhci_readw(host
, SDHCI_HOST_VERSION
));
58 pr_err(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
60 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
61 pr_err(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host
, SDHCI_ARGUMENT
),
63 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
64 pr_err(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
66 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
67 pr_err(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
69 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
70 pr_err(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
72 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
73 pr_err(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
75 sdhci_readl(host
, SDHCI_INT_STATUS
));
76 pr_err(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host
, SDHCI_INT_ENABLE
),
78 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
79 pr_err(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
81 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
82 pr_err(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host
, SDHCI_CAPABILITIES
),
84 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
85 pr_err(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host
, SDHCI_COMMAND
),
87 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
88 pr_err(DRIVER_NAME
": Host ctl2: 0x%08x\n",
89 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
91 if (host
->flags
& SDHCI_USE_ADMA
) {
92 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
93 pr_err(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
95 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS_HI
),
96 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
98 pr_err(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
100 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
103 pr_err(DRIVER_NAME
": ===========================================\n");
106 /*****************************************************************************\
108 * Low level functions *
110 \*****************************************************************************/
112 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
116 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
117 !mmc_card_is_removable(host
->mmc
))
121 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
124 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
125 SDHCI_INT_CARD_INSERT
;
127 host
->ier
&= ~(SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
);
130 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
131 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
134 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
136 sdhci_set_card_detection(host
, true);
139 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
141 sdhci_set_card_detection(host
, false);
144 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
149 pm_runtime_get_noresume(host
->mmc
->parent
);
152 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
156 host
->bus_on
= false;
157 pm_runtime_put_noidle(host
->mmc
->parent
);
160 void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
162 unsigned long timeout
;
164 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
166 if (mask
& SDHCI_RESET_ALL
) {
168 /* Reset-all turns off SD Bus Power */
169 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
170 sdhci_runtime_pm_bus_off(host
);
173 /* Wait max 100 ms */
176 /* hw clears the bit when it's done */
177 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
179 pr_err("%s: Reset 0x%x never completed.\n",
180 mmc_hostname(host
->mmc
), (int)mask
);
181 sdhci_dumpregs(host
);
188 EXPORT_SYMBOL_GPL(sdhci_reset
);
190 static void sdhci_do_reset(struct sdhci_host
*host
, u8 mask
)
192 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
193 struct mmc_host
*mmc
= host
->mmc
;
195 if (!mmc
->ops
->get_cd(mmc
))
199 host
->ops
->reset(host
, mask
);
201 if (mask
& SDHCI_RESET_ALL
) {
202 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
203 if (host
->ops
->enable_dma
)
204 host
->ops
->enable_dma(host
);
207 /* Resetting the controller clears many */
208 host
->preset_enabled
= false;
212 static void sdhci_init(struct sdhci_host
*host
, int soft
)
214 struct mmc_host
*mmc
= host
->mmc
;
217 sdhci_do_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
219 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
221 host
->ier
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
222 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
|
223 SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
|
224 SDHCI_INT_TIMEOUT
| SDHCI_INT_DATA_END
|
227 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
228 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
231 /* force clock reconfiguration */
233 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
237 static void sdhci_reinit(struct sdhci_host
*host
)
240 sdhci_enable_card_detection(host
);
243 static void __sdhci_led_activate(struct sdhci_host
*host
)
247 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
248 ctrl
|= SDHCI_CTRL_LED
;
249 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
252 static void __sdhci_led_deactivate(struct sdhci_host
*host
)
256 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
257 ctrl
&= ~SDHCI_CTRL_LED
;
258 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
261 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
262 static void sdhci_led_control(struct led_classdev
*led
,
263 enum led_brightness brightness
)
265 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
268 spin_lock_irqsave(&host
->lock
, flags
);
270 if (host
->runtime_suspended
)
273 if (brightness
== LED_OFF
)
274 __sdhci_led_deactivate(host
);
276 __sdhci_led_activate(host
);
278 spin_unlock_irqrestore(&host
->lock
, flags
);
281 static int sdhci_led_register(struct sdhci_host
*host
)
283 struct mmc_host
*mmc
= host
->mmc
;
285 snprintf(host
->led_name
, sizeof(host
->led_name
),
286 "%s::", mmc_hostname(mmc
));
288 host
->led
.name
= host
->led_name
;
289 host
->led
.brightness
= LED_OFF
;
290 host
->led
.default_trigger
= mmc_hostname(mmc
);
291 host
->led
.brightness_set
= sdhci_led_control
;
293 return led_classdev_register(mmc_dev(mmc
), &host
->led
);
296 static void sdhci_led_unregister(struct sdhci_host
*host
)
298 led_classdev_unregister(&host
->led
);
301 static inline void sdhci_led_activate(struct sdhci_host
*host
)
305 static inline void sdhci_led_deactivate(struct sdhci_host
*host
)
311 static inline int sdhci_led_register(struct sdhci_host
*host
)
316 static inline void sdhci_led_unregister(struct sdhci_host
*host
)
320 static inline void sdhci_led_activate(struct sdhci_host
*host
)
322 __sdhci_led_activate(host
);
325 static inline void sdhci_led_deactivate(struct sdhci_host
*host
)
327 __sdhci_led_deactivate(host
);
332 /*****************************************************************************\
336 \*****************************************************************************/
338 static void sdhci_read_block_pio(struct sdhci_host
*host
)
341 size_t blksize
, len
, chunk
;
342 u32
uninitialized_var(scratch
);
345 DBG("PIO reading\n");
347 blksize
= host
->data
->blksz
;
350 local_irq_save(flags
);
353 BUG_ON(!sg_miter_next(&host
->sg_miter
));
355 len
= min(host
->sg_miter
.length
, blksize
);
358 host
->sg_miter
.consumed
= len
;
360 buf
= host
->sg_miter
.addr
;
364 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
368 *buf
= scratch
& 0xFF;
377 sg_miter_stop(&host
->sg_miter
);
379 local_irq_restore(flags
);
382 static void sdhci_write_block_pio(struct sdhci_host
*host
)
385 size_t blksize
, len
, chunk
;
389 DBG("PIO writing\n");
391 blksize
= host
->data
->blksz
;
395 local_irq_save(flags
);
398 BUG_ON(!sg_miter_next(&host
->sg_miter
));
400 len
= min(host
->sg_miter
.length
, blksize
);
403 host
->sg_miter
.consumed
= len
;
405 buf
= host
->sg_miter
.addr
;
408 scratch
|= (u32
)*buf
<< (chunk
* 8);
414 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
415 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
422 sg_miter_stop(&host
->sg_miter
);
424 local_irq_restore(flags
);
427 static void sdhci_transfer_pio(struct sdhci_host
*host
)
431 if (host
->blocks
== 0)
434 if (host
->data
->flags
& MMC_DATA_READ
)
435 mask
= SDHCI_DATA_AVAILABLE
;
437 mask
= SDHCI_SPACE_AVAILABLE
;
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
444 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
445 (host
->data
->blocks
== 1))
448 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
449 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
452 if (host
->data
->flags
& MMC_DATA_READ
)
453 sdhci_read_block_pio(host
);
455 sdhci_write_block_pio(host
);
458 if (host
->blocks
== 0)
462 DBG("PIO transfer complete.\n");
465 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
466 struct mmc_data
*data
, int cookie
)
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
474 if (data
->host_cookie
== COOKIE_PRE_MAPPED
)
475 return data
->sg_count
;
477 sg_count
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
478 data
->flags
& MMC_DATA_WRITE
?
479 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
484 data
->sg_count
= sg_count
;
485 data
->host_cookie
= cookie
;
490 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
492 local_irq_save(*flags
);
493 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
496 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
498 kunmap_atomic(buffer
);
499 local_irq_restore(*flags
);
502 static void sdhci_adma_write_desc(struct sdhci_host
*host
, void *desc
,
503 dma_addr_t addr
, int len
, unsigned cmd
)
505 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
507 /* 32-bit and 64-bit descriptors have these members in same position */
508 dma_desc
->cmd
= cpu_to_le16(cmd
);
509 dma_desc
->len
= cpu_to_le16(len
);
510 dma_desc
->addr_lo
= cpu_to_le32((u32
)addr
);
512 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
513 dma_desc
->addr_hi
= cpu_to_le32((u64
)addr
>> 32);
516 static void sdhci_adma_mark_end(void *desc
)
518 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
521 dma_desc
->cmd
|= cpu_to_le16(ADMA2_END
);
524 static void sdhci_adma_table_pre(struct sdhci_host
*host
,
525 struct mmc_data
*data
, int sg_count
)
527 struct scatterlist
*sg
;
529 dma_addr_t addr
, align_addr
;
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
539 host
->sg_count
= sg_count
;
541 desc
= host
->adma_table
;
542 align
= host
->align_buffer
;
544 align_addr
= host
->align_addr
;
546 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
547 addr
= sg_dma_address(sg
);
548 len
= sg_dma_len(sg
);
551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
556 offset
= (SDHCI_ADMA2_ALIGN
- (addr
& SDHCI_ADMA2_MASK
)) &
559 if (data
->flags
& MMC_DATA_WRITE
) {
560 buffer
= sdhci_kmap_atomic(sg
, &flags
);
561 memcpy(align
, buffer
, offset
);
562 sdhci_kunmap_atomic(buffer
, &flags
);
566 sdhci_adma_write_desc(host
, desc
, align_addr
, offset
,
569 BUG_ON(offset
> 65536);
571 align
+= SDHCI_ADMA2_ALIGN
;
572 align_addr
+= SDHCI_ADMA2_ALIGN
;
574 desc
+= host
->desc_sz
;
584 sdhci_adma_write_desc(host
, desc
, addr
, len
,
586 desc
+= host
->desc_sz
;
590 * If this triggers then we have a calculation bug
593 WARN_ON((desc
- host
->adma_table
) >= host
->adma_table_sz
);
596 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
597 /* Mark the last descriptor as the terminating descriptor */
598 if (desc
!= host
->adma_table
) {
599 desc
-= host
->desc_sz
;
600 sdhci_adma_mark_end(desc
);
603 /* Add a terminating entry - nop, end, valid */
604 sdhci_adma_write_desc(host
, desc
, 0, 0, ADMA2_NOP_END_VALID
);
608 static void sdhci_adma_table_post(struct sdhci_host
*host
,
609 struct mmc_data
*data
)
611 struct scatterlist
*sg
;
617 if (data
->flags
& MMC_DATA_READ
) {
618 bool has_unaligned
= false;
620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
)
622 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
623 has_unaligned
= true;
628 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
629 data
->sg_len
, DMA_FROM_DEVICE
);
631 align
= host
->align_buffer
;
633 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
634 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
635 size
= SDHCI_ADMA2_ALIGN
-
636 (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
);
638 buffer
= sdhci_kmap_atomic(sg
, &flags
);
639 memcpy(buffer
, align
, size
);
640 sdhci_kunmap_atomic(buffer
, &flags
);
642 align
+= SDHCI_ADMA2_ALIGN
;
649 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
652 struct mmc_data
*data
= cmd
->data
;
653 unsigned target_timeout
, current_timeout
;
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
661 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
664 /* Unspecified timeout, assume max */
665 if (!data
&& !cmd
->busy_timeout
)
670 target_timeout
= cmd
->busy_timeout
* 1000;
672 target_timeout
= DIV_ROUND_UP(data
->timeout_ns
, 1000);
673 if (host
->clock
&& data
->timeout_clks
) {
674 unsigned long long val
;
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
681 val
= 1000000 * data
->timeout_clks
;
682 if (do_div(val
, host
->clock
))
684 target_timeout
+= val
;
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
699 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
700 while (current_timeout
< target_timeout
) {
702 current_timeout
<<= 1;
708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host
->mmc
), count
, cmd
->opcode
);
716 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
718 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
719 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
721 if (host
->flags
& SDHCI_REQ_USE_DMA
)
722 host
->ier
= (host
->ier
& ~pio_irqs
) | dma_irqs
;
724 host
->ier
= (host
->ier
& ~dma_irqs
) | pio_irqs
;
726 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
727 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
730 static void sdhci_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
734 if (host
->ops
->set_timeout
) {
735 host
->ops
->set_timeout(host
, cmd
);
737 count
= sdhci_calc_timeout(host
, cmd
);
738 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
742 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
745 struct mmc_data
*data
= cmd
->data
;
747 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
))
748 sdhci_set_timeout(host
, cmd
);
756 BUG_ON(data
->blksz
* data
->blocks
> 524288);
757 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
758 BUG_ON(data
->blocks
> 65535);
761 host
->data_early
= 0;
762 host
->data
->bytes_xfered
= 0;
764 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
765 struct scatterlist
*sg
;
766 unsigned int length_mask
, offset_mask
;
769 host
->flags
|= SDHCI_REQ_USE_DMA
;
772 * FIXME: This doesn't account for merging when mapping the
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
780 if (host
->flags
& SDHCI_USE_ADMA
) {
781 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
) {
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
791 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
793 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
797 if (unlikely(length_mask
| offset_mask
)) {
798 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
799 if (sg
->length
& length_mask
) {
800 DBG("Reverting to PIO because of transfer size (%d)\n",
802 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
805 if (sg
->offset
& offset_mask
) {
806 DBG("Reverting to PIO because of bad alignment\n");
807 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
814 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
815 int sg_cnt
= sdhci_pre_dma_transfer(host
, data
, COOKIE_MAPPED
);
819 * This only happens when someone fed
820 * us an invalid request.
823 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
824 } else if (host
->flags
& SDHCI_USE_ADMA
) {
825 sdhci_adma_table_pre(host
, data
, sg_cnt
);
827 sdhci_writel(host
, host
->adma_addr
, SDHCI_ADMA_ADDRESS
);
828 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
830 (u64
)host
->adma_addr
>> 32,
831 SDHCI_ADMA_ADDRESS_HI
);
833 WARN_ON(sg_cnt
!= 1);
834 sdhci_writel(host
, sg_dma_address(data
->sg
),
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
844 if (host
->version
>= SDHCI_SPEC_200
) {
845 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
846 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
847 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
848 (host
->flags
& SDHCI_USE_ADMA
)) {
849 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
850 ctrl
|= SDHCI_CTRL_ADMA64
;
852 ctrl
|= SDHCI_CTRL_ADMA32
;
854 ctrl
|= SDHCI_CTRL_SDMA
;
856 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
859 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
862 flags
= SG_MITER_ATOMIC
;
863 if (host
->data
->flags
& MMC_DATA_READ
)
864 flags
|= SG_MITER_TO_SG
;
866 flags
|= SG_MITER_FROM_SG
;
867 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
868 host
->blocks
= data
->blocks
;
871 sdhci_set_transfer_irqs(host
);
873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
875 data
->blksz
), SDHCI_BLOCK_SIZE
);
876 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
879 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
880 struct mmc_command
*cmd
)
883 struct mmc_data
*data
= cmd
->data
;
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD
) {
888 sdhci_writew(host
, 0x0, SDHCI_TRANSFER_MODE
);
890 /* clear Auto CMD settings for no data CMDs */
891 mode
= sdhci_readw(host
, SDHCI_TRANSFER_MODE
);
892 sdhci_writew(host
, mode
& ~(SDHCI_TRNS_AUTO_CMD12
|
893 SDHCI_TRNS_AUTO_CMD23
), SDHCI_TRANSFER_MODE
);
898 WARN_ON(!host
->data
);
900 if (!(host
->quirks2
& SDHCI_QUIRK2_SUPPORT_SINGLE
))
901 mode
= SDHCI_TRNS_BLK_CNT_EN
;
903 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
904 mode
= SDHCI_TRNS_BLK_CNT_EN
| SDHCI_TRNS_MULTI
;
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
909 if (!cmd
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
) &&
910 (cmd
->opcode
!= SD_IO_RW_EXTENDED
))
911 mode
|= SDHCI_TRNS_AUTO_CMD12
;
912 else if (cmd
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
913 mode
|= SDHCI_TRNS_AUTO_CMD23
;
914 sdhci_writel(host
, cmd
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
918 if (data
->flags
& MMC_DATA_READ
)
919 mode
|= SDHCI_TRNS_READ
;
920 if (host
->flags
& SDHCI_REQ_USE_DMA
)
921 mode
|= SDHCI_TRNS_DMA
;
923 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
926 static bool sdhci_needs_reset(struct sdhci_host
*host
, struct mmc_request
*mrq
)
928 return (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
929 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
930 (mrq
->sbc
&& mrq
->sbc
->error
) ||
931 (mrq
->data
&& ((mrq
->data
->error
&& !mrq
->data
->stop
) ||
932 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
933 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
)));
936 static void sdhci_finish_mrq(struct sdhci_host
*host
, struct mmc_request
*mrq
)
938 tasklet_schedule(&host
->finish_tasklet
);
941 static void sdhci_finish_data(struct sdhci_host
*host
)
943 struct mmc_data
*data
;
947 host
->data_cmd
= NULL
;
949 if ((host
->flags
& (SDHCI_REQ_USE_DMA
| SDHCI_USE_ADMA
)) ==
950 (SDHCI_REQ_USE_DMA
| SDHCI_USE_ADMA
))
951 sdhci_adma_table_post(host
, data
);
954 * The specification states that the block count register must
955 * be updated, but it does not specify at what point in the
956 * data flow. That makes the register entirely useless to read
957 * back so we have to assume that nothing made it to the card
958 * in the event of an error.
961 data
->bytes_xfered
= 0;
963 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
966 * Need to send CMD12 if -
967 * a) open-ended multiblock transfer (no CMD23)
968 * b) error in multiblock transfer
975 * The controller needs a reset of internal state machines
976 * upon error conditions.
979 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
980 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
983 sdhci_send_command(host
, data
->stop
);
985 sdhci_finish_mrq(host
, data
->mrq
);
989 void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
993 unsigned long timeout
;
997 /* Initially, a command has no error */
1000 /* Wait max 10 ms */
1003 mask
= SDHCI_CMD_INHIBIT
;
1004 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
1005 mask
|= SDHCI_DATA_INHIBIT
;
1007 /* We shouldn't wait for data inihibit for stop commands, even
1008 though they might use busy signaling */
1009 if (cmd
->mrq
->data
&& (cmd
== cmd
->mrq
->data
->stop
))
1010 mask
&= ~SDHCI_DATA_INHIBIT
;
1012 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
1014 pr_err("%s: Controller never released inhibit bit(s).\n",
1015 mmc_hostname(host
->mmc
));
1016 sdhci_dumpregs(host
);
1018 sdhci_finish_mrq(host
, cmd
->mrq
);
1026 if (!cmd
->data
&& cmd
->busy_timeout
> 9000)
1027 timeout
+= DIV_ROUND_UP(cmd
->busy_timeout
, 1000) * HZ
+ HZ
;
1030 mod_timer(&host
->timer
, timeout
);
1033 if (cmd
->data
|| cmd
->flags
& MMC_RSP_BUSY
) {
1034 WARN_ON(host
->data_cmd
);
1035 host
->data_cmd
= cmd
;
1038 sdhci_prepare_data(host
, cmd
);
1040 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
1042 sdhci_set_transfer_mode(host
, cmd
);
1044 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
1045 pr_err("%s: Unsupported response type!\n",
1046 mmc_hostname(host
->mmc
));
1047 cmd
->error
= -EINVAL
;
1048 sdhci_finish_mrq(host
, cmd
->mrq
);
1052 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1053 flags
= SDHCI_CMD_RESP_NONE
;
1054 else if (cmd
->flags
& MMC_RSP_136
)
1055 flags
= SDHCI_CMD_RESP_LONG
;
1056 else if (cmd
->flags
& MMC_RSP_BUSY
)
1057 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1059 flags
= SDHCI_CMD_RESP_SHORT
;
1061 if (cmd
->flags
& MMC_RSP_CRC
)
1062 flags
|= SDHCI_CMD_CRC
;
1063 if (cmd
->flags
& MMC_RSP_OPCODE
)
1064 flags
|= SDHCI_CMD_INDEX
;
1066 /* CMD19 is special in that the Data Present Select should be set */
1067 if (cmd
->data
|| cmd
->opcode
== MMC_SEND_TUNING_BLOCK
||
1068 cmd
->opcode
== MMC_SEND_TUNING_BLOCK_HS200
)
1069 flags
|= SDHCI_CMD_DATA
;
1071 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1073 EXPORT_SYMBOL_GPL(sdhci_send_command
);
1075 static void sdhci_finish_command(struct sdhci_host
*host
)
1077 struct mmc_command
*cmd
= host
->cmd
;
1082 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1083 if (cmd
->flags
& MMC_RSP_136
) {
1084 /* CRC is stripped so we need to do some shifting. */
1085 for (i
= 0;i
< 4;i
++) {
1086 cmd
->resp
[i
] = sdhci_readl(host
,
1087 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1091 SDHCI_RESPONSE
+ (3-i
)*4-1);
1094 cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1099 * The host can send and interrupt when the busy state has
1100 * ended, allowing us to wait without wasting CPU cycles.
1101 * The busy signal uses DAT0 so this is similar to waiting
1102 * for data to complete.
1104 * Note: The 1.0 specification is a bit ambiguous about this
1105 * feature so there might be some problems with older
1108 if (cmd
->flags
& MMC_RSP_BUSY
) {
1110 DBG("Cannot wait for busy signal when also doing a data transfer");
1111 } else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
1112 cmd
== host
->data_cmd
) {
1113 /* Command complete before busy is ended */
1118 /* Finished CMD23, now send actual command. */
1119 if (cmd
== cmd
->mrq
->sbc
) {
1120 sdhci_send_command(host
, cmd
->mrq
->cmd
);
1123 /* Processed actual command. */
1124 if (host
->data
&& host
->data_early
)
1125 sdhci_finish_data(host
);
1128 sdhci_finish_mrq(host
, cmd
->mrq
);
1132 static u16
sdhci_get_preset_value(struct sdhci_host
*host
)
1136 switch (host
->timing
) {
1137 case MMC_TIMING_UHS_SDR12
:
1138 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1140 case MMC_TIMING_UHS_SDR25
:
1141 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR25
);
1143 case MMC_TIMING_UHS_SDR50
:
1144 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR50
);
1146 case MMC_TIMING_UHS_SDR104
:
1147 case MMC_TIMING_MMC_HS200
:
1148 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR104
);
1150 case MMC_TIMING_UHS_DDR50
:
1151 case MMC_TIMING_MMC_DDR52
:
1152 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_DDR50
);
1154 case MMC_TIMING_MMC_HS400
:
1155 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_HS400
);
1158 pr_warn("%s: Invalid UHS-I mode selected\n",
1159 mmc_hostname(host
->mmc
));
1160 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1166 u16
sdhci_calc_clk(struct sdhci_host
*host
, unsigned int clock
,
1167 unsigned int *actual_clock
)
1169 int div
= 0; /* Initialized for compiler warning */
1170 int real_div
= div
, clk_mul
= 1;
1172 bool switch_base_clk
= false;
1174 if (host
->version
>= SDHCI_SPEC_300
) {
1175 if (host
->preset_enabled
) {
1178 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1179 pre_val
= sdhci_get_preset_value(host
);
1180 div
= (pre_val
& SDHCI_PRESET_SDCLK_FREQ_MASK
)
1181 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT
;
1182 if (host
->clk_mul
&&
1183 (pre_val
& SDHCI_PRESET_CLKGEN_SEL_MASK
)) {
1184 clk
= SDHCI_PROG_CLOCK_MODE
;
1186 clk_mul
= host
->clk_mul
;
1188 real_div
= max_t(int, 1, div
<< 1);
1194 * Check if the Host Controller supports Programmable Clock
1197 if (host
->clk_mul
) {
1198 for (div
= 1; div
<= 1024; div
++) {
1199 if ((host
->max_clk
* host
->clk_mul
/ div
)
1203 if ((host
->max_clk
* host
->clk_mul
/ div
) <= clock
) {
1205 * Set Programmable Clock Mode in the Clock
1208 clk
= SDHCI_PROG_CLOCK_MODE
;
1210 clk_mul
= host
->clk_mul
;
1214 * Divisor can be too small to reach clock
1215 * speed requirement. Then use the base clock.
1217 switch_base_clk
= true;
1221 if (!host
->clk_mul
|| switch_base_clk
) {
1222 /* Version 3.00 divisors must be a multiple of 2. */
1223 if (host
->max_clk
<= clock
)
1226 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1228 if ((host
->max_clk
/ div
) <= clock
)
1234 if ((host
->quirks2
& SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
)
1235 && !div
&& host
->max_clk
<= 25000000)
1239 /* Version 2.00 divisors must be a power of 2. */
1240 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1241 if ((host
->max_clk
/ div
) <= clock
)
1250 *actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1251 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1252 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1253 << SDHCI_DIVIDER_HI_SHIFT
;
1257 EXPORT_SYMBOL_GPL(sdhci_calc_clk
);
1259 void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1262 unsigned long timeout
;
1264 host
->mmc
->actual_clock
= 0;
1266 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1271 clk
= sdhci_calc_clk(host
, clock
, &host
->mmc
->actual_clock
);
1273 clk
|= SDHCI_CLOCK_INT_EN
;
1274 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1276 /* Wait max 20 ms */
1278 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1279 & SDHCI_CLOCK_INT_STABLE
)) {
1281 pr_err("%s: Internal clock never stabilised.\n",
1282 mmc_hostname(host
->mmc
));
1283 sdhci_dumpregs(host
);
1290 clk
|= SDHCI_CLOCK_CARD_EN
;
1291 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1293 EXPORT_SYMBOL_GPL(sdhci_set_clock
);
1295 static void sdhci_set_power_reg(struct sdhci_host
*host
, unsigned char mode
,
1298 struct mmc_host
*mmc
= host
->mmc
;
1300 spin_unlock_irq(&host
->lock
);
1301 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
1302 spin_lock_irq(&host
->lock
);
1304 if (mode
!= MMC_POWER_OFF
)
1305 sdhci_writeb(host
, SDHCI_POWER_ON
, SDHCI_POWER_CONTROL
);
1307 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1310 void sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1315 if (mode
!= MMC_POWER_OFF
) {
1317 case MMC_VDD_165_195
:
1318 pwr
= SDHCI_POWER_180
;
1322 pwr
= SDHCI_POWER_300
;
1326 pwr
= SDHCI_POWER_330
;
1329 WARN(1, "%s: Invalid vdd %#x\n",
1330 mmc_hostname(host
->mmc
), vdd
);
1335 if (host
->pwr
== pwr
)
1341 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1342 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1343 sdhci_runtime_pm_bus_off(host
);
1346 * Spec says that we should clear the power reg before setting
1347 * a new value. Some controllers don't seem to like this though.
1349 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1350 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1353 * At least the Marvell CaFe chip gets confused if we set the
1354 * voltage and set turn on power at the same time, so set the
1357 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1358 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1360 pwr
|= SDHCI_POWER_ON
;
1362 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1364 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1365 sdhci_runtime_pm_bus_on(host
);
1368 * Some controllers need an extra 10ms delay of 10ms before
1369 * they can apply clock after applying power
1371 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1375 EXPORT_SYMBOL_GPL(sdhci_set_power
);
1377 static void __sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1380 struct mmc_host
*mmc
= host
->mmc
;
1382 if (host
->ops
->set_power
)
1383 host
->ops
->set_power(host
, mode
, vdd
);
1384 else if (!IS_ERR(mmc
->supply
.vmmc
))
1385 sdhci_set_power_reg(host
, mode
, vdd
);
1387 sdhci_set_power(host
, mode
, vdd
);
1390 /*****************************************************************************\
1394 \*****************************************************************************/
1396 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1398 struct sdhci_host
*host
;
1400 unsigned long flags
;
1402 host
= mmc_priv(mmc
);
1404 /* Firstly check card presence */
1405 present
= mmc
->ops
->get_cd(mmc
);
1407 spin_lock_irqsave(&host
->lock
, flags
);
1409 WARN_ON(host
->mrq
!= NULL
);
1411 sdhci_led_activate(host
);
1414 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1415 * requests if Auto-CMD12 is enabled.
1417 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1419 mrq
->data
->stop
= NULL
;
1426 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1427 mrq
->cmd
->error
= -ENOMEDIUM
;
1428 sdhci_finish_mrq(host
, mrq
);
1430 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1431 sdhci_send_command(host
, mrq
->sbc
);
1433 sdhci_send_command(host
, mrq
->cmd
);
1437 spin_unlock_irqrestore(&host
->lock
, flags
);
1440 void sdhci_set_bus_width(struct sdhci_host
*host
, int width
)
1444 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1445 if (width
== MMC_BUS_WIDTH_8
) {
1446 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1447 if (host
->version
>= SDHCI_SPEC_300
)
1448 ctrl
|= SDHCI_CTRL_8BITBUS
;
1450 if (host
->version
>= SDHCI_SPEC_300
)
1451 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1452 if (width
== MMC_BUS_WIDTH_4
)
1453 ctrl
|= SDHCI_CTRL_4BITBUS
;
1455 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1457 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1459 EXPORT_SYMBOL_GPL(sdhci_set_bus_width
);
1461 void sdhci_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
1465 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1466 /* Select Bus Speed Mode for host */
1467 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1468 if ((timing
== MMC_TIMING_MMC_HS200
) ||
1469 (timing
== MMC_TIMING_UHS_SDR104
))
1470 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1471 else if (timing
== MMC_TIMING_UHS_SDR12
)
1472 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1473 else if (timing
== MMC_TIMING_UHS_SDR25
)
1474 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1475 else if (timing
== MMC_TIMING_UHS_SDR50
)
1476 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1477 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
1478 (timing
== MMC_TIMING_MMC_DDR52
))
1479 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1480 else if (timing
== MMC_TIMING_MMC_HS400
)
1481 ctrl_2
|= SDHCI_CTRL_HS400
; /* Non-standard */
1482 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1484 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling
);
1486 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1488 struct sdhci_host
*host
= mmc_priv(mmc
);
1489 unsigned long flags
;
1492 spin_lock_irqsave(&host
->lock
, flags
);
1494 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1495 spin_unlock_irqrestore(&host
->lock
, flags
);
1496 if (!IS_ERR(mmc
->supply
.vmmc
) &&
1497 ios
->power_mode
== MMC_POWER_OFF
)
1498 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1503 * Reset the chip on each power off.
1504 * Should clear out any weird states.
1506 if (ios
->power_mode
== MMC_POWER_OFF
) {
1507 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1511 if (host
->version
>= SDHCI_SPEC_300
&&
1512 (ios
->power_mode
== MMC_POWER_UP
) &&
1513 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
))
1514 sdhci_enable_preset_value(host
, false);
1516 if (!ios
->clock
|| ios
->clock
!= host
->clock
) {
1517 host
->ops
->set_clock(host
, ios
->clock
);
1518 host
->clock
= ios
->clock
;
1520 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
&&
1522 host
->timeout_clk
= host
->mmc
->actual_clock
?
1523 host
->mmc
->actual_clock
/ 1000 :
1525 host
->mmc
->max_busy_timeout
=
1526 host
->ops
->get_max_timeout_count
?
1527 host
->ops
->get_max_timeout_count(host
) :
1529 host
->mmc
->max_busy_timeout
/= host
->timeout_clk
;
1533 __sdhci_set_power(host
, ios
->power_mode
, ios
->vdd
);
1535 if (host
->ops
->platform_send_init_74_clocks
)
1536 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1538 host
->ops
->set_bus_width(host
, ios
->bus_width
);
1540 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1542 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1543 ios
->timing
== MMC_TIMING_MMC_HS
)
1544 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1545 ctrl
|= SDHCI_CTRL_HISPD
;
1547 ctrl
&= ~SDHCI_CTRL_HISPD
;
1549 if (host
->version
>= SDHCI_SPEC_300
) {
1552 /* In case of UHS-I modes, set High Speed Enable */
1553 if ((ios
->timing
== MMC_TIMING_MMC_HS400
) ||
1554 (ios
->timing
== MMC_TIMING_MMC_HS200
) ||
1555 (ios
->timing
== MMC_TIMING_MMC_DDR52
) ||
1556 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1557 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1558 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1559 (ios
->timing
== MMC_TIMING_UHS_SDR25
))
1560 ctrl
|= SDHCI_CTRL_HISPD
;
1562 if (!host
->preset_enabled
) {
1563 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1565 * We only need to set Driver Strength if the
1566 * preset value enable is not set.
1568 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1569 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1570 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1571 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1572 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_B
)
1573 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1574 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1575 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1576 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_D
)
1577 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_D
;
1579 pr_warn("%s: invalid driver type, default to driver type B\n",
1581 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1584 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1587 * According to SDHC Spec v3.00, if the Preset Value
1588 * Enable in the Host Control 2 register is set, we
1589 * need to reset SD Clock Enable before changing High
1590 * Speed Enable to avoid generating clock gliches.
1593 /* Reset SD Clock Enable */
1594 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1595 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1596 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1598 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1600 /* Re-enable SD Clock */
1601 host
->ops
->set_clock(host
, host
->clock
);
1604 /* Reset SD Clock Enable */
1605 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1606 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1607 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1609 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1610 host
->timing
= ios
->timing
;
1612 if (!(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
) &&
1613 ((ios
->timing
== MMC_TIMING_UHS_SDR12
) ||
1614 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1615 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1616 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1617 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1618 (ios
->timing
== MMC_TIMING_MMC_DDR52
))) {
1621 sdhci_enable_preset_value(host
, true);
1622 preset
= sdhci_get_preset_value(host
);
1623 ios
->drv_type
= (preset
& SDHCI_PRESET_DRV_MASK
)
1624 >> SDHCI_PRESET_DRV_SHIFT
;
1627 /* Re-enable SD Clock */
1628 host
->ops
->set_clock(host
, host
->clock
);
1630 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1633 * Some (ENE) controllers go apeshit on some ios operation,
1634 * signalling timeout and CRC errors even on CMD0. Resetting
1635 * it on each ios seems to solve the problem.
1637 if (host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1638 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1641 spin_unlock_irqrestore(&host
->lock
, flags
);
1644 static int sdhci_get_cd(struct mmc_host
*mmc
)
1646 struct sdhci_host
*host
= mmc_priv(mmc
);
1647 int gpio_cd
= mmc_gpio_get_cd(mmc
);
1649 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1652 /* If nonremovable, assume that the card is always present. */
1653 if (!mmc_card_is_removable(host
->mmc
))
1657 * Try slot gpio detect, if defined it take precedence
1658 * over build in controller functionality
1663 /* If polling, assume that the card is always present. */
1664 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1667 /* Host native card detect */
1668 return !!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
);
1671 static int sdhci_check_ro(struct sdhci_host
*host
)
1673 unsigned long flags
;
1676 spin_lock_irqsave(&host
->lock
, flags
);
1678 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1680 else if (host
->ops
->get_ro
)
1681 is_readonly
= host
->ops
->get_ro(host
);
1683 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1684 & SDHCI_WRITE_PROTECT
);
1686 spin_unlock_irqrestore(&host
->lock
, flags
);
1688 /* This quirk needs to be replaced by a callback-function later */
1689 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1690 !is_readonly
: is_readonly
;
1693 #define SAMPLE_COUNT 5
1695 static int sdhci_get_ro(struct mmc_host
*mmc
)
1697 struct sdhci_host
*host
= mmc_priv(mmc
);
1700 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1701 return sdhci_check_ro(host
);
1704 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1705 if (sdhci_check_ro(host
)) {
1706 if (++ro_count
> SAMPLE_COUNT
/ 2)
1714 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1716 struct sdhci_host
*host
= mmc_priv(mmc
);
1718 if (host
->ops
&& host
->ops
->hw_reset
)
1719 host
->ops
->hw_reset(host
);
1722 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1724 if (!(host
->flags
& SDHCI_DEVICE_DEAD
)) {
1726 host
->ier
|= SDHCI_INT_CARD_INT
;
1728 host
->ier
&= ~SDHCI_INT_CARD_INT
;
1730 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
1731 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
1736 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1738 struct sdhci_host
*host
= mmc_priv(mmc
);
1739 unsigned long flags
;
1741 spin_lock_irqsave(&host
->lock
, flags
);
1743 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1745 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1747 sdhci_enable_sdio_irq_nolock(host
, enable
);
1748 spin_unlock_irqrestore(&host
->lock
, flags
);
1751 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1752 struct mmc_ios
*ios
)
1754 struct sdhci_host
*host
= mmc_priv(mmc
);
1759 * Signal Voltage Switching is only applicable for Host Controllers
1762 if (host
->version
< SDHCI_SPEC_300
)
1765 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1767 switch (ios
->signal_voltage
) {
1768 case MMC_SIGNAL_VOLTAGE_330
:
1769 if (!(host
->flags
& SDHCI_SIGNALING_330
))
1771 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1772 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1773 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1775 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1776 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 2700000,
1779 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1785 usleep_range(5000, 5500);
1787 /* 3.3V regulator output should be stable within 5 ms */
1788 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1789 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1792 pr_warn("%s: 3.3V regulator output did not became stable\n",
1796 case MMC_SIGNAL_VOLTAGE_180
:
1797 if (!(host
->flags
& SDHCI_SIGNALING_180
))
1799 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1800 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1803 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1810 * Enable 1.8V Signal Enable in the Host Control2
1813 ctrl
|= SDHCI_CTRL_VDD_180
;
1814 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1816 /* Some controller need to do more when switching */
1817 if (host
->ops
->voltage_switch
)
1818 host
->ops
->voltage_switch(host
);
1820 /* 1.8V regulator output should be stable within 5 ms */
1821 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1822 if (ctrl
& SDHCI_CTRL_VDD_180
)
1825 pr_warn("%s: 1.8V regulator output did not became stable\n",
1829 case MMC_SIGNAL_VOLTAGE_120
:
1830 if (!(host
->flags
& SDHCI_SIGNALING_120
))
1832 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1833 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 1100000,
1836 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1843 /* No signal voltage switch required */
1848 static int sdhci_card_busy(struct mmc_host
*mmc
)
1850 struct sdhci_host
*host
= mmc_priv(mmc
);
1853 /* Check whether DAT[0] is 0 */
1854 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1856 return !(present_state
& SDHCI_DATA_0_LVL_MASK
);
1859 static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1861 struct sdhci_host
*host
= mmc_priv(mmc
);
1862 unsigned long flags
;
1864 spin_lock_irqsave(&host
->lock
, flags
);
1865 host
->flags
|= SDHCI_HS400_TUNING
;
1866 spin_unlock_irqrestore(&host
->lock
, flags
);
1871 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1873 struct sdhci_host
*host
= mmc_priv(mmc
);
1875 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1877 unsigned long flags
;
1878 unsigned int tuning_count
= 0;
1881 spin_lock_irqsave(&host
->lock
, flags
);
1883 hs400_tuning
= host
->flags
& SDHCI_HS400_TUNING
;
1884 host
->flags
&= ~SDHCI_HS400_TUNING
;
1886 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1887 tuning_count
= host
->tuning_count
;
1890 * The Host Controller needs tuning in case of SDR104 and DDR50
1891 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1892 * the Capabilities register.
1893 * If the Host Controller supports the HS200 mode then the
1894 * tuning function has to be executed.
1896 switch (host
->timing
) {
1897 /* HS400 tuning is done in HS200 mode */
1898 case MMC_TIMING_MMC_HS400
:
1902 case MMC_TIMING_MMC_HS200
:
1904 * Periodic re-tuning for HS400 is not expected to be needed, so
1911 case MMC_TIMING_UHS_SDR104
:
1912 case MMC_TIMING_UHS_DDR50
:
1915 case MMC_TIMING_UHS_SDR50
:
1916 if (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
)
1924 if (host
->ops
->platform_execute_tuning
) {
1925 spin_unlock_irqrestore(&host
->lock
, flags
);
1926 err
= host
->ops
->platform_execute_tuning(host
, opcode
);
1930 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1931 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1932 if (host
->quirks2
& SDHCI_QUIRK2_TUNING_WORK_AROUND
)
1933 ctrl
|= SDHCI_CTRL_TUNED_CLK
;
1934 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1937 * As per the Host Controller spec v3.00, tuning command
1938 * generates Buffer Read Ready interrupt, so enable that.
1940 * Note: The spec clearly says that when tuning sequence
1941 * is being performed, the controller does not generate
1942 * interrupts other than Buffer Read Ready interrupt. But
1943 * to make sure we don't hit a controller bug, we _only_
1944 * enable Buffer Read Ready interrupt here.
1946 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_INT_ENABLE
);
1947 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_SIGNAL_ENABLE
);
1950 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1951 * of loops reaches 40 times.
1954 struct mmc_command cmd
= {0};
1955 struct mmc_request mrq
= {NULL
};
1957 cmd
.opcode
= opcode
;
1959 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1964 if (tuning_loop_counter
-- == 0)
1971 * In response to CMD19, the card sends 64 bytes of tuning
1972 * block to the Host Controller. So we set the block size
1975 if (cmd
.opcode
== MMC_SEND_TUNING_BLOCK_HS200
) {
1976 if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
1977 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 128),
1979 else if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
1980 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1983 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1988 * The tuning block is sent by the card to the host controller.
1989 * So we set the TRNS_READ bit in the Transfer Mode register.
1990 * This also takes care of setting DMA Enable and Multi Block
1991 * Select in the same register to 0.
1993 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
1995 sdhci_send_command(host
, &cmd
);
2000 spin_unlock_irqrestore(&host
->lock
, flags
);
2001 /* Wait for Buffer Read Ready interrupt */
2002 wait_event_interruptible_timeout(host
->buf_ready_int
,
2003 (host
->tuning_done
== 1),
2004 msecs_to_jiffies(50));
2005 spin_lock_irqsave(&host
->lock
, flags
);
2007 if (!host
->tuning_done
) {
2008 pr_info(DRIVER_NAME
": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2009 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2010 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2011 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
2012 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2018 host
->tuning_done
= 0;
2020 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2022 /* eMMC spec does not require a delay between tuning cycles */
2023 if (opcode
== MMC_SEND_TUNING_BLOCK
)
2025 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
2028 * The Host Driver has exhausted the maximum number of loops allowed,
2029 * so use fixed sampling frequency.
2031 if (tuning_loop_counter
< 0) {
2032 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2033 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2035 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
2036 pr_info(DRIVER_NAME
": Tuning procedure failed, falling back to fixed sampling clock\n");
2043 * In case tuning fails, host controllers which support
2044 * re-tuning can try tuning again at a later time, when the
2045 * re-tuning timer expires. So for these controllers, we
2046 * return 0. Since there might be other controllers who do not
2047 * have this capability, we return error for them.
2052 host
->mmc
->retune_period
= err
? 0 : tuning_count
;
2054 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2055 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2057 spin_unlock_irqrestore(&host
->lock
, flags
);
2061 static int sdhci_select_drive_strength(struct mmc_card
*card
,
2062 unsigned int max_dtr
, int host_drv
,
2063 int card_drv
, int *drv_type
)
2065 struct sdhci_host
*host
= mmc_priv(card
->host
);
2067 if (!host
->ops
->select_drive_strength
)
2070 return host
->ops
->select_drive_strength(host
, card
, max_dtr
, host_drv
,
2071 card_drv
, drv_type
);
2074 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
)
2076 /* Host Controller v3.00 defines preset value registers */
2077 if (host
->version
< SDHCI_SPEC_300
)
2081 * We only enable or disable Preset Value if they are not already
2082 * enabled or disabled respectively. Otherwise, we bail out.
2084 if (host
->preset_enabled
!= enable
) {
2085 u16 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2088 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
2090 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
2092 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2095 host
->flags
|= SDHCI_PV_ENABLED
;
2097 host
->flags
&= ~SDHCI_PV_ENABLED
;
2099 host
->preset_enabled
= enable
;
2103 static void sdhci_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2106 struct sdhci_host
*host
= mmc_priv(mmc
);
2107 struct mmc_data
*data
= mrq
->data
;
2109 if (data
->host_cookie
!= COOKIE_UNMAPPED
)
2110 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2111 data
->flags
& MMC_DATA_WRITE
?
2112 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2114 data
->host_cookie
= COOKIE_UNMAPPED
;
2117 static void sdhci_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2120 struct sdhci_host
*host
= mmc_priv(mmc
);
2122 mrq
->data
->host_cookie
= COOKIE_UNMAPPED
;
2124 if (host
->flags
& SDHCI_REQ_USE_DMA
)
2125 sdhci_pre_dma_transfer(host
, mrq
->data
, COOKIE_PRE_MAPPED
);
2128 static void sdhci_card_event(struct mmc_host
*mmc
)
2130 struct sdhci_host
*host
= mmc_priv(mmc
);
2131 unsigned long flags
;
2134 /* First check if client has provided their own card event */
2135 if (host
->ops
->card_event
)
2136 host
->ops
->card_event(host
);
2138 present
= mmc
->ops
->get_cd(mmc
);
2140 spin_lock_irqsave(&host
->lock
, flags
);
2142 /* Check host->mrq first in case we are runtime suspended */
2143 if (host
->mrq
&& !present
) {
2144 pr_err("%s: Card removed during transfer!\n",
2145 mmc_hostname(host
->mmc
));
2146 pr_err("%s: Resetting controller.\n",
2147 mmc_hostname(host
->mmc
));
2149 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2150 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2152 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2153 sdhci_finish_mrq(host
, host
->mrq
);
2156 spin_unlock_irqrestore(&host
->lock
, flags
);
2159 static const struct mmc_host_ops sdhci_ops
= {
2160 .request
= sdhci_request
,
2161 .post_req
= sdhci_post_req
,
2162 .pre_req
= sdhci_pre_req
,
2163 .set_ios
= sdhci_set_ios
,
2164 .get_cd
= sdhci_get_cd
,
2165 .get_ro
= sdhci_get_ro
,
2166 .hw_reset
= sdhci_hw_reset
,
2167 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
2168 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
2169 .prepare_hs400_tuning
= sdhci_prepare_hs400_tuning
,
2170 .execute_tuning
= sdhci_execute_tuning
,
2171 .select_drive_strength
= sdhci_select_drive_strength
,
2172 .card_event
= sdhci_card_event
,
2173 .card_busy
= sdhci_card_busy
,
2176 /*****************************************************************************\
2180 \*****************************************************************************/
2182 static void sdhci_tasklet_finish(unsigned long param
)
2184 struct sdhci_host
*host
;
2185 unsigned long flags
;
2186 struct mmc_request
*mrq
;
2188 host
= (struct sdhci_host
*)param
;
2190 spin_lock_irqsave(&host
->lock
, flags
);
2193 * If this tasklet gets rescheduled while running, it will
2194 * be run again afterwards but without any active request.
2197 spin_unlock_irqrestore(&host
->lock
, flags
);
2201 del_timer(&host
->timer
);
2206 * Always unmap the data buffers if they were mapped by
2207 * sdhci_prepare_data() whenever we finish with a request.
2208 * This avoids leaking DMA mappings on error.
2210 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
2211 struct mmc_data
*data
= mrq
->data
;
2213 if (data
&& data
->host_cookie
== COOKIE_MAPPED
) {
2214 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2215 (data
->flags
& MMC_DATA_READ
) ?
2216 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
2217 data
->host_cookie
= COOKIE_UNMAPPED
;
2222 * The controller needs a reset of internal state machines
2223 * upon error conditions.
2225 if (sdhci_needs_reset(host
, mrq
)) {
2226 /* Some controllers need this kick or reset won't work here */
2227 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
)
2228 /* This is to force an update */
2229 host
->ops
->set_clock(host
, host
->clock
);
2231 /* Spec says we should do both at the same time, but Ricoh
2232 controllers do not like that. */
2233 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2234 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2240 host
->data_cmd
= NULL
;
2242 sdhci_led_deactivate(host
);
2245 spin_unlock_irqrestore(&host
->lock
, flags
);
2247 mmc_request_done(host
->mmc
, mrq
);
2250 static void sdhci_timeout_timer(unsigned long data
)
2252 struct sdhci_host
*host
;
2253 unsigned long flags
;
2255 host
= (struct sdhci_host
*)data
;
2257 spin_lock_irqsave(&host
->lock
, flags
);
2260 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2261 mmc_hostname(host
->mmc
));
2262 sdhci_dumpregs(host
);
2265 host
->data
->error
= -ETIMEDOUT
;
2266 sdhci_finish_data(host
);
2269 host
->cmd
->error
= -ETIMEDOUT
;
2271 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2273 sdhci_finish_mrq(host
, host
->mrq
);
2278 spin_unlock_irqrestore(&host
->lock
, flags
);
2281 /*****************************************************************************\
2283 * Interrupt handling *
2285 \*****************************************************************************/
2287 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
, u32
*mask
)
2290 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2291 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2292 sdhci_dumpregs(host
);
2296 if (intmask
& (SDHCI_INT_TIMEOUT
| SDHCI_INT_CRC
|
2297 SDHCI_INT_END_BIT
| SDHCI_INT_INDEX
)) {
2298 if (intmask
& SDHCI_INT_TIMEOUT
)
2299 host
->cmd
->error
= -ETIMEDOUT
;
2301 host
->cmd
->error
= -EILSEQ
;
2304 * If this command initiates a data phase and a response
2305 * CRC error is signalled, the card can start transferring
2306 * data - the card may have received the command without
2307 * error. We must not terminate the mmc_request early.
2309 * If the card did not receive the command or returned an
2310 * error which prevented it sending data, the data phase
2313 if (host
->cmd
->data
&&
2314 (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
)) ==
2320 sdhci_finish_mrq(host
, host
->cmd
->mrq
);
2324 if ((host
->quirks2
& SDHCI_QUIRK2_STOP_WITH_TC
) &&
2325 !(host
->cmd
->flags
& MMC_RSP_BUSY
) && !host
->data
&&
2326 host
->cmd
->opcode
== MMC_STOP_TRANSMISSION
)
2327 *mask
&= ~SDHCI_INT_DATA_END
;
2329 if (intmask
& SDHCI_INT_RESPONSE
)
2330 sdhci_finish_command(host
);
2333 #ifdef CONFIG_MMC_DEBUG
2334 static void sdhci_adma_show_error(struct sdhci_host
*host
)
2336 const char *name
= mmc_hostname(host
->mmc
);
2337 void *desc
= host
->adma_table
;
2339 sdhci_dumpregs(host
);
2342 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
2344 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2345 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2346 name
, desc
, le32_to_cpu(dma_desc
->addr_hi
),
2347 le32_to_cpu(dma_desc
->addr_lo
),
2348 le16_to_cpu(dma_desc
->len
),
2349 le16_to_cpu(dma_desc
->cmd
));
2351 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2352 name
, desc
, le32_to_cpu(dma_desc
->addr_lo
),
2353 le16_to_cpu(dma_desc
->len
),
2354 le16_to_cpu(dma_desc
->cmd
));
2356 desc
+= host
->desc_sz
;
2358 if (dma_desc
->cmd
& cpu_to_le16(ADMA2_END
))
2363 static void sdhci_adma_show_error(struct sdhci_host
*host
) { }
2366 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2370 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2371 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2372 command
= SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
));
2373 if (command
== MMC_SEND_TUNING_BLOCK
||
2374 command
== MMC_SEND_TUNING_BLOCK_HS200
) {
2375 host
->tuning_done
= 1;
2376 wake_up(&host
->buf_ready_int
);
2382 struct mmc_command
*data_cmd
= host
->data_cmd
;
2385 host
->data_cmd
= NULL
;
2388 * The "data complete" interrupt is also used to
2389 * indicate that a busy state has ended. See comment
2390 * above in sdhci_cmd_irq().
2392 if (data_cmd
&& (data_cmd
->flags
& MMC_RSP_BUSY
)) {
2393 if (intmask
& SDHCI_INT_DATA_TIMEOUT
) {
2394 data_cmd
->error
= -ETIMEDOUT
;
2395 sdhci_finish_mrq(host
, data_cmd
->mrq
);
2398 if (intmask
& SDHCI_INT_DATA_END
) {
2400 * Some cards handle busy-end interrupt
2401 * before the command completed, so make
2402 * sure we do things in the proper order.
2404 if (host
->cmd
== data_cmd
)
2407 sdhci_finish_mrq(host
, data_cmd
->mrq
);
2412 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2413 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2414 sdhci_dumpregs(host
);
2419 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2420 host
->data
->error
= -ETIMEDOUT
;
2421 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2422 host
->data
->error
= -EILSEQ
;
2423 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2424 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2426 host
->data
->error
= -EILSEQ
;
2427 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2428 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2429 sdhci_adma_show_error(host
);
2430 host
->data
->error
= -EIO
;
2431 if (host
->ops
->adma_workaround
)
2432 host
->ops
->adma_workaround(host
, intmask
);
2435 if (host
->data
->error
)
2436 sdhci_finish_data(host
);
2438 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2439 sdhci_transfer_pio(host
);
2442 * We currently don't do anything fancy with DMA
2443 * boundaries, but as we can't disable the feature
2444 * we need to at least restart the transfer.
2446 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2447 * should return a valid address to continue from, but as
2448 * some controllers are faulty, don't trust them.
2450 if (intmask
& SDHCI_INT_DMA_END
) {
2451 u32 dmastart
, dmanow
;
2452 dmastart
= sg_dma_address(host
->data
->sg
);
2453 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2455 * Force update to the next DMA block boundary.
2458 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2459 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2460 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2461 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2463 mmc_hostname(host
->mmc
), dmastart
,
2464 host
->data
->bytes_xfered
, dmanow
);
2465 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2468 if (intmask
& SDHCI_INT_DATA_END
) {
2469 if (host
->cmd
== host
->data_cmd
) {
2471 * Data managed to finish before the
2472 * command completed. Make sure we do
2473 * things in the proper order.
2475 host
->data_early
= 1;
2477 sdhci_finish_data(host
);
2483 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2485 irqreturn_t result
= IRQ_NONE
;
2486 struct sdhci_host
*host
= dev_id
;
2487 u32 intmask
, mask
, unexpected
= 0;
2490 spin_lock(&host
->lock
);
2492 if (host
->runtime_suspended
&& !sdhci_sdio_irq_enabled(host
)) {
2493 spin_unlock(&host
->lock
);
2497 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2498 if (!intmask
|| intmask
== 0xffffffff) {
2504 /* Clear selected interrupts. */
2505 mask
= intmask
& (SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2506 SDHCI_INT_BUS_POWER
);
2507 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
2509 DBG("*** %s got interrupt: 0x%08x\n",
2510 mmc_hostname(host
->mmc
), intmask
);
2512 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2513 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2517 * There is a observation on i.mx esdhc. INSERT
2518 * bit will be immediately set again when it gets
2519 * cleared, if a card is inserted. We have to mask
2520 * the irq to prevent interrupt storm which will
2521 * freeze the system. And the REMOVE gets the
2524 * More testing are needed here to ensure it works
2525 * for other platforms though.
2527 host
->ier
&= ~(SDHCI_INT_CARD_INSERT
|
2528 SDHCI_INT_CARD_REMOVE
);
2529 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
2530 SDHCI_INT_CARD_INSERT
;
2531 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2532 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2534 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2535 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2537 host
->thread_isr
|= intmask
& (SDHCI_INT_CARD_INSERT
|
2538 SDHCI_INT_CARD_REMOVE
);
2539 result
= IRQ_WAKE_THREAD
;
2542 if (intmask
& SDHCI_INT_CMD_MASK
)
2543 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
,
2546 if (intmask
& SDHCI_INT_DATA_MASK
)
2547 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2549 if (intmask
& SDHCI_INT_BUS_POWER
)
2550 pr_err("%s: Card is consuming too much power!\n",
2551 mmc_hostname(host
->mmc
));
2553 if (intmask
& SDHCI_INT_CARD_INT
) {
2554 sdhci_enable_sdio_irq_nolock(host
, false);
2555 host
->thread_isr
|= SDHCI_INT_CARD_INT
;
2556 result
= IRQ_WAKE_THREAD
;
2559 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2560 SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2561 SDHCI_INT_ERROR
| SDHCI_INT_BUS_POWER
|
2562 SDHCI_INT_CARD_INT
);
2565 unexpected
|= intmask
;
2566 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2569 if (result
== IRQ_NONE
)
2570 result
= IRQ_HANDLED
;
2572 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2573 } while (intmask
&& --max_loops
);
2575 spin_unlock(&host
->lock
);
2578 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2579 mmc_hostname(host
->mmc
), unexpected
);
2580 sdhci_dumpregs(host
);
2586 static irqreturn_t
sdhci_thread_irq(int irq
, void *dev_id
)
2588 struct sdhci_host
*host
= dev_id
;
2589 unsigned long flags
;
2592 spin_lock_irqsave(&host
->lock
, flags
);
2593 isr
= host
->thread_isr
;
2594 host
->thread_isr
= 0;
2595 spin_unlock_irqrestore(&host
->lock
, flags
);
2597 if (isr
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2598 struct mmc_host
*mmc
= host
->mmc
;
2600 mmc
->ops
->card_event(mmc
);
2601 mmc_detect_change(mmc
, msecs_to_jiffies(200));
2604 if (isr
& SDHCI_INT_CARD_INT
) {
2605 sdio_run_irqs(host
->mmc
);
2607 spin_lock_irqsave(&host
->lock
, flags
);
2608 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2609 sdhci_enable_sdio_irq_nolock(host
, true);
2610 spin_unlock_irqrestore(&host
->lock
, flags
);
2613 return isr
? IRQ_HANDLED
: IRQ_NONE
;
2616 /*****************************************************************************\
2620 \*****************************************************************************/
2624 * To enable wakeup events, the corresponding events have to be enabled in
2625 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2626 * Table' in the SD Host Controller Standard Specification.
2627 * It is useless to restore SDHCI_INT_ENABLE state in
2628 * sdhci_disable_irq_wakeups() since it will be set by
2629 * sdhci_enable_card_detection() or sdhci_init().
2631 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2634 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2635 | SDHCI_WAKE_ON_INT
;
2636 u32 irq_val
= SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2639 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2641 /* Avoid fake wake up */
2642 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) {
2643 val
&= ~(SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
);
2644 irq_val
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
2646 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2647 sdhci_writel(host
, irq_val
, SDHCI_INT_ENABLE
);
2649 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2651 static void sdhci_disable_irq_wakeups(struct sdhci_host
*host
)
2654 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2655 | SDHCI_WAKE_ON_INT
;
2657 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2659 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2662 int sdhci_suspend_host(struct sdhci_host
*host
)
2664 sdhci_disable_card_detection(host
);
2666 mmc_retune_timer_stop(host
->mmc
);
2667 mmc_retune_needed(host
->mmc
);
2669 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2671 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
2672 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
2673 free_irq(host
->irq
, host
);
2675 sdhci_enable_irq_wakeups(host
);
2676 enable_irq_wake(host
->irq
);
2681 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2683 int sdhci_resume_host(struct sdhci_host
*host
)
2685 struct mmc_host
*mmc
= host
->mmc
;
2688 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2689 if (host
->ops
->enable_dma
)
2690 host
->ops
->enable_dma(host
);
2693 if ((host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) &&
2694 (host
->quirks2
& SDHCI_QUIRK2_HOST_OFF_CARD_ON
)) {
2695 /* Card keeps power but host controller does not */
2696 sdhci_init(host
, 0);
2699 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
2701 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2705 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2706 ret
= request_threaded_irq(host
->irq
, sdhci_irq
,
2707 sdhci_thread_irq
, IRQF_SHARED
,
2708 mmc_hostname(host
->mmc
), host
);
2712 sdhci_disable_irq_wakeups(host
);
2713 disable_irq_wake(host
->irq
);
2716 sdhci_enable_card_detection(host
);
2721 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2723 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2725 unsigned long flags
;
2727 mmc_retune_timer_stop(host
->mmc
);
2728 mmc_retune_needed(host
->mmc
);
2730 spin_lock_irqsave(&host
->lock
, flags
);
2731 host
->ier
&= SDHCI_INT_CARD_INT
;
2732 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2733 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2734 spin_unlock_irqrestore(&host
->lock
, flags
);
2736 synchronize_hardirq(host
->irq
);
2738 spin_lock_irqsave(&host
->lock
, flags
);
2739 host
->runtime_suspended
= true;
2740 spin_unlock_irqrestore(&host
->lock
, flags
);
2744 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2746 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2748 struct mmc_host
*mmc
= host
->mmc
;
2749 unsigned long flags
;
2750 int host_flags
= host
->flags
;
2752 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2753 if (host
->ops
->enable_dma
)
2754 host
->ops
->enable_dma(host
);
2757 sdhci_init(host
, 0);
2759 /* Force clock and power re-program */
2762 mmc
->ops
->start_signal_voltage_switch(mmc
, &mmc
->ios
);
2763 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
2765 if ((host_flags
& SDHCI_PV_ENABLED
) &&
2766 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)) {
2767 spin_lock_irqsave(&host
->lock
, flags
);
2768 sdhci_enable_preset_value(host
, true);
2769 spin_unlock_irqrestore(&host
->lock
, flags
);
2772 spin_lock_irqsave(&host
->lock
, flags
);
2774 host
->runtime_suspended
= false;
2776 /* Enable SDIO IRQ */
2777 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2778 sdhci_enable_sdio_irq_nolock(host
, true);
2780 /* Enable Card Detection */
2781 sdhci_enable_card_detection(host
);
2783 spin_unlock_irqrestore(&host
->lock
, flags
);
2787 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2789 #endif /* CONFIG_PM */
2791 /*****************************************************************************\
2793 * Device allocation/registration *
2795 \*****************************************************************************/
2797 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2800 struct mmc_host
*mmc
;
2801 struct sdhci_host
*host
;
2803 WARN_ON(dev
== NULL
);
2805 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2807 return ERR_PTR(-ENOMEM
);
2809 host
= mmc_priv(mmc
);
2811 host
->mmc_host_ops
= sdhci_ops
;
2812 mmc
->ops
= &host
->mmc_host_ops
;
2814 host
->flags
= SDHCI_SIGNALING_330
;
2819 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2821 static int sdhci_set_dma_mask(struct sdhci_host
*host
)
2823 struct mmc_host
*mmc
= host
->mmc
;
2824 struct device
*dev
= mmc_dev(mmc
);
2827 if (host
->quirks2
& SDHCI_QUIRK2_BROKEN_64_BIT_DMA
)
2828 host
->flags
&= ~SDHCI_USE_64_BIT_DMA
;
2830 /* Try 64-bit mask if hardware is capable of it */
2831 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
2832 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(64));
2834 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2836 host
->flags
&= ~SDHCI_USE_64_BIT_DMA
;
2840 /* 32-bit mask as default & fallback */
2842 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
2844 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2851 void __sdhci_read_caps(struct sdhci_host
*host
, u16
*ver
, u32
*caps
, u32
*caps1
)
2855 if (host
->read_caps
)
2858 host
->read_caps
= true;
2861 host
->quirks
= debug_quirks
;
2864 host
->quirks2
= debug_quirks2
;
2866 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
2868 v
= ver
? *ver
: sdhci_readw(host
, SDHCI_HOST_VERSION
);
2869 host
->version
= (v
& SDHCI_SPEC_VER_MASK
) >> SDHCI_SPEC_VER_SHIFT
;
2871 if (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
)
2874 host
->caps
= caps
? *caps
: sdhci_readl(host
, SDHCI_CAPABILITIES
);
2876 if (host
->version
< SDHCI_SPEC_300
)
2879 host
->caps1
= caps1
? *caps1
: sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
2881 EXPORT_SYMBOL_GPL(__sdhci_read_caps
);
2883 int sdhci_setup_host(struct sdhci_host
*host
)
2885 struct mmc_host
*mmc
;
2886 u32 max_current_caps
;
2887 unsigned int ocr_avail
;
2888 unsigned int override_timeout_clk
;
2892 WARN_ON(host
== NULL
);
2898 sdhci_read_caps(host
);
2900 override_timeout_clk
= host
->timeout_clk
;
2902 if (host
->version
> SDHCI_SPEC_300
) {
2903 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2904 mmc_hostname(mmc
), host
->version
);
2907 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2908 host
->flags
|= SDHCI_USE_SDMA
;
2909 else if (!(host
->caps
& SDHCI_CAN_DO_SDMA
))
2910 DBG("Controller doesn't have SDMA capability\n");
2912 host
->flags
|= SDHCI_USE_SDMA
;
2914 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2915 (host
->flags
& SDHCI_USE_SDMA
)) {
2916 DBG("Disabling DMA as it is marked broken\n");
2917 host
->flags
&= ~SDHCI_USE_SDMA
;
2920 if ((host
->version
>= SDHCI_SPEC_200
) &&
2921 (host
->caps
& SDHCI_CAN_DO_ADMA2
))
2922 host
->flags
|= SDHCI_USE_ADMA
;
2924 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2925 (host
->flags
& SDHCI_USE_ADMA
)) {
2926 DBG("Disabling ADMA as it is marked broken\n");
2927 host
->flags
&= ~SDHCI_USE_ADMA
;
2931 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2932 * and *must* do 64-bit DMA. A driver has the opportunity to change
2933 * that during the first call to ->enable_dma(). Similarly
2934 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2937 if (host
->caps
& SDHCI_CAN_64BIT
)
2938 host
->flags
|= SDHCI_USE_64_BIT_DMA
;
2940 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2941 ret
= sdhci_set_dma_mask(host
);
2943 if (!ret
&& host
->ops
->enable_dma
)
2944 ret
= host
->ops
->enable_dma(host
);
2947 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2949 host
->flags
&= ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2955 /* SDMA does not support 64-bit DMA */
2956 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2957 host
->flags
&= ~SDHCI_USE_SDMA
;
2959 if (host
->flags
& SDHCI_USE_ADMA
) {
2964 * The DMA descriptor table size is calculated as the maximum
2965 * number of segments times 2, to allow for an alignment
2966 * descriptor for each segment, plus 1 for a nop end descriptor,
2967 * all multipled by the descriptor size.
2969 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
2970 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2971 SDHCI_ADMA2_64_DESC_SZ
;
2972 host
->desc_sz
= SDHCI_ADMA2_64_DESC_SZ
;
2974 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2975 SDHCI_ADMA2_32_DESC_SZ
;
2976 host
->desc_sz
= SDHCI_ADMA2_32_DESC_SZ
;
2979 host
->align_buffer_sz
= SDHCI_MAX_SEGS
* SDHCI_ADMA2_ALIGN
;
2980 buf
= dma_alloc_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
2981 host
->adma_table_sz
, &dma
, GFP_KERNEL
);
2983 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2985 host
->flags
&= ~SDHCI_USE_ADMA
;
2986 } else if ((dma
+ host
->align_buffer_sz
) &
2987 (SDHCI_ADMA2_DESC_ALIGN
- 1)) {
2988 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2990 host
->flags
&= ~SDHCI_USE_ADMA
;
2991 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
2992 host
->adma_table_sz
, buf
, dma
);
2994 host
->align_buffer
= buf
;
2995 host
->align_addr
= dma
;
2997 host
->adma_table
= buf
+ host
->align_buffer_sz
;
2998 host
->adma_addr
= dma
+ host
->align_buffer_sz
;
3003 * If we use DMA, then it's up to the caller to set the DMA
3004 * mask, but PIO does not need the hw shim so we set a new
3005 * mask here in that case.
3007 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
3008 host
->dma_mask
= DMA_BIT_MASK(64);
3009 mmc_dev(mmc
)->dma_mask
= &host
->dma_mask
;
3012 if (host
->version
>= SDHCI_SPEC_300
)
3013 host
->max_clk
= (host
->caps
& SDHCI_CLOCK_V3_BASE_MASK
)
3014 >> SDHCI_CLOCK_BASE_SHIFT
;
3016 host
->max_clk
= (host
->caps
& SDHCI_CLOCK_BASE_MASK
)
3017 >> SDHCI_CLOCK_BASE_SHIFT
;
3019 host
->max_clk
*= 1000000;
3020 if (host
->max_clk
== 0 || host
->quirks
&
3021 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
3022 if (!host
->ops
->get_max_clock
) {
3023 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3028 host
->max_clk
= host
->ops
->get_max_clock(host
);
3032 * In case of Host Controller v3.00, find out whether clock
3033 * multiplier is supported.
3035 host
->clk_mul
= (host
->caps1
& SDHCI_CLOCK_MUL_MASK
) >>
3036 SDHCI_CLOCK_MUL_SHIFT
;
3039 * In case the value in Clock Multiplier is 0, then programmable
3040 * clock mode is not supported, otherwise the actual clock
3041 * multiplier is one more than the value of Clock Multiplier
3042 * in the Capabilities Register.
3048 * Set host parameters.
3050 max_clk
= host
->max_clk
;
3052 if (host
->ops
->get_min_clock
)
3053 mmc
->f_min
= host
->ops
->get_min_clock(host
);
3054 else if (host
->version
>= SDHCI_SPEC_300
) {
3055 if (host
->clk_mul
) {
3056 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
3057 max_clk
= host
->max_clk
* host
->clk_mul
;
3059 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
3061 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
3063 if (!mmc
->f_max
|| mmc
->f_max
> max_clk
)
3064 mmc
->f_max
= max_clk
;
3066 if (!(host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
3067 host
->timeout_clk
= (host
->caps
& SDHCI_TIMEOUT_CLK_MASK
) >>
3068 SDHCI_TIMEOUT_CLK_SHIFT
;
3069 if (host
->timeout_clk
== 0) {
3070 if (host
->ops
->get_timeout_clock
) {
3072 host
->ops
->get_timeout_clock(host
);
3074 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3081 if (host
->caps
& SDHCI_TIMEOUT_CLK_UNIT
)
3082 host
->timeout_clk
*= 1000;
3084 if (override_timeout_clk
)
3085 host
->timeout_clk
= override_timeout_clk
;
3087 mmc
->max_busy_timeout
= host
->ops
->get_max_timeout_count
?
3088 host
->ops
->get_max_timeout_count(host
) : 1 << 27;
3089 mmc
->max_busy_timeout
/= host
->timeout_clk
;
3092 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
3093 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
3095 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
3096 host
->flags
|= SDHCI_AUTO_CMD12
;
3098 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3099 if ((host
->version
>= SDHCI_SPEC_300
) &&
3100 ((host
->flags
& SDHCI_USE_ADMA
) ||
3101 !(host
->flags
& SDHCI_USE_SDMA
)) &&
3102 !(host
->quirks2
& SDHCI_QUIRK2_ACMD23_BROKEN
)) {
3103 host
->flags
|= SDHCI_AUTO_CMD23
;
3104 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
3106 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
3110 * A controller may support 8-bit width, but the board itself
3111 * might not have the pins brought out. Boards that support
3112 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3113 * their platform code before calling sdhci_add_host(), and we
3114 * won't assume 8-bit width for hosts without that CAP.
3116 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
3117 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
3119 if (host
->quirks2
& SDHCI_QUIRK2_HOST_NO_CMD23
)
3120 mmc
->caps
&= ~MMC_CAP_CMD23
;
3122 if (host
->caps
& SDHCI_CAN_DO_HISPD
)
3123 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
3125 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
3126 mmc_card_is_removable(mmc
) &&
3127 mmc_gpio_get_cd(host
->mmc
) < 0)
3128 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
3130 /* If there are external regulators, get them */
3131 ret
= mmc_regulator_get_supply(mmc
);
3132 if (ret
== -EPROBE_DEFER
)
3135 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3136 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
3137 ret
= regulator_enable(mmc
->supply
.vqmmc
);
3138 if (!regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1700000,
3140 host
->caps1
&= ~(SDHCI_SUPPORT_SDR104
|
3141 SDHCI_SUPPORT_SDR50
|
3142 SDHCI_SUPPORT_DDR50
);
3144 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3145 mmc_hostname(mmc
), ret
);
3146 mmc
->supply
.vqmmc
= ERR_PTR(-EINVAL
);
3150 if (host
->quirks2
& SDHCI_QUIRK2_NO_1_8_V
) {
3151 host
->caps1
&= ~(SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3152 SDHCI_SUPPORT_DDR50
);
3155 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3156 if (host
->caps1
& (SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3157 SDHCI_SUPPORT_DDR50
))
3158 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
3160 /* SDR104 supports also implies SDR50 support */
3161 if (host
->caps1
& SDHCI_SUPPORT_SDR104
) {
3162 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
3163 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3164 * field can be promoted to support HS200.
3166 if (!(host
->quirks2
& SDHCI_QUIRK2_BROKEN_HS200
))
3167 mmc
->caps2
|= MMC_CAP2_HS200
;
3168 } else if (host
->caps1
& SDHCI_SUPPORT_SDR50
) {
3169 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
3172 if (host
->quirks2
& SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400
&&
3173 (host
->caps1
& SDHCI_SUPPORT_HS400
))
3174 mmc
->caps2
|= MMC_CAP2_HS400
;
3176 if ((mmc
->caps2
& MMC_CAP2_HSX00_1_2V
) &&
3177 (IS_ERR(mmc
->supply
.vqmmc
) ||
3178 !regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1100000,
3180 mmc
->caps2
&= ~MMC_CAP2_HSX00_1_2V
;
3182 if ((host
->caps1
& SDHCI_SUPPORT_DDR50
) &&
3183 !(host
->quirks2
& SDHCI_QUIRK2_BROKEN_DDR50
))
3184 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
3186 /* Does the host need tuning for SDR50? */
3187 if (host
->caps1
& SDHCI_USE_SDR50_TUNING
)
3188 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
3190 /* Driver Type(s) (A, C, D) supported by the host */
3191 if (host
->caps1
& SDHCI_DRIVER_TYPE_A
)
3192 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
3193 if (host
->caps1
& SDHCI_DRIVER_TYPE_C
)
3194 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
3195 if (host
->caps1
& SDHCI_DRIVER_TYPE_D
)
3196 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
3198 /* Initial value for re-tuning timer count */
3199 host
->tuning_count
= (host
->caps1
& SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
3200 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
3203 * In case Re-tuning Timer is not disabled, the actual value of
3204 * re-tuning timer will be 2 ^ (n - 1).
3206 if (host
->tuning_count
)
3207 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
3209 /* Re-tuning mode supported by the Host Controller */
3210 host
->tuning_mode
= (host
->caps1
& SDHCI_RETUNING_MODE_MASK
) >>
3211 SDHCI_RETUNING_MODE_SHIFT
;
3216 * According to SD Host Controller spec v3.00, if the Host System
3217 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3218 * the value is meaningful only if Voltage Support in the Capabilities
3219 * register is set. The actual current value is 4 times the register
3222 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
3223 if (!max_current_caps
&& !IS_ERR(mmc
->supply
.vmmc
)) {
3224 int curr
= regulator_get_current_limit(mmc
->supply
.vmmc
);
3227 /* convert to SDHCI_MAX_CURRENT format */
3228 curr
= curr
/1000; /* convert to mA */
3229 curr
= curr
/SDHCI_MAX_CURRENT_MULTIPLIER
;
3231 curr
= min_t(u32
, curr
, SDHCI_MAX_CURRENT_LIMIT
);
3233 (curr
<< SDHCI_MAX_CURRENT_330_SHIFT
) |
3234 (curr
<< SDHCI_MAX_CURRENT_300_SHIFT
) |
3235 (curr
<< SDHCI_MAX_CURRENT_180_SHIFT
);
3239 if (host
->caps
& SDHCI_CAN_VDD_330
) {
3240 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
3242 mmc
->max_current_330
= ((max_current_caps
&
3243 SDHCI_MAX_CURRENT_330_MASK
) >>
3244 SDHCI_MAX_CURRENT_330_SHIFT
) *
3245 SDHCI_MAX_CURRENT_MULTIPLIER
;
3247 if (host
->caps
& SDHCI_CAN_VDD_300
) {
3248 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
3250 mmc
->max_current_300
= ((max_current_caps
&
3251 SDHCI_MAX_CURRENT_300_MASK
) >>
3252 SDHCI_MAX_CURRENT_300_SHIFT
) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER
;
3255 if (host
->caps
& SDHCI_CAN_VDD_180
) {
3256 ocr_avail
|= MMC_VDD_165_195
;
3258 mmc
->max_current_180
= ((max_current_caps
&
3259 SDHCI_MAX_CURRENT_180_MASK
) >>
3260 SDHCI_MAX_CURRENT_180_SHIFT
) *
3261 SDHCI_MAX_CURRENT_MULTIPLIER
;
3264 /* If OCR set by host, use it instead. */
3266 ocr_avail
= host
->ocr_mask
;
3268 /* If OCR set by external regulators, give it highest prio. */
3270 ocr_avail
= mmc
->ocr_avail
;
3272 mmc
->ocr_avail
= ocr_avail
;
3273 mmc
->ocr_avail_sdio
= ocr_avail
;
3274 if (host
->ocr_avail_sdio
)
3275 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
3276 mmc
->ocr_avail_sd
= ocr_avail
;
3277 if (host
->ocr_avail_sd
)
3278 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
3279 else /* normal SD controllers don't support 1.8V */
3280 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
3281 mmc
->ocr_avail_mmc
= ocr_avail
;
3282 if (host
->ocr_avail_mmc
)
3283 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
3285 if (mmc
->ocr_avail
== 0) {
3286 pr_err("%s: Hardware doesn't report any support voltages.\n",
3292 if ((mmc
->caps
& (MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
|
3293 MMC_CAP_UHS_SDR50
| MMC_CAP_UHS_SDR104
|
3294 MMC_CAP_UHS_DDR50
| MMC_CAP_1_8V_DDR
)) ||
3295 (mmc
->caps2
& (MMC_CAP2_HS200_1_8V_SDR
| MMC_CAP2_HS400_1_8V
)))
3296 host
->flags
|= SDHCI_SIGNALING_180
;
3298 if (mmc
->caps2
& MMC_CAP2_HSX00_1_2V
)
3299 host
->flags
|= SDHCI_SIGNALING_120
;
3301 spin_lock_init(&host
->lock
);
3304 * Maximum number of segments. Depends on if the hardware
3305 * can do scatter/gather or not.
3307 if (host
->flags
& SDHCI_USE_ADMA
)
3308 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3309 else if (host
->flags
& SDHCI_USE_SDMA
)
3312 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3315 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3316 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3319 mmc
->max_req_size
= 524288;
3322 * Maximum segment size. Could be one segment with the maximum number
3323 * of bytes. When doing hardware scatter/gather, each entry cannot
3324 * be larger than 64 KiB though.
3326 if (host
->flags
& SDHCI_USE_ADMA
) {
3327 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
3328 mmc
->max_seg_size
= 65535;
3330 mmc
->max_seg_size
= 65536;
3332 mmc
->max_seg_size
= mmc
->max_req_size
;
3336 * Maximum block size. This varies from controller to controller and
3337 * is specified in the capabilities register.
3339 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
3340 mmc
->max_blk_size
= 2;
3342 mmc
->max_blk_size
= (host
->caps
& SDHCI_MAX_BLOCK_MASK
) >>
3343 SDHCI_MAX_BLOCK_SHIFT
;
3344 if (mmc
->max_blk_size
>= 3) {
3345 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3347 mmc
->max_blk_size
= 0;
3351 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
3354 * Maximum block count.
3356 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
3361 if (!IS_ERR(mmc
->supply
.vqmmc
))
3362 regulator_disable(mmc
->supply
.vqmmc
);
3364 if (host
->align_buffer
)
3365 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3366 host
->adma_table_sz
, host
->align_buffer
,
3368 host
->adma_table
= NULL
;
3369 host
->align_buffer
= NULL
;
3373 EXPORT_SYMBOL_GPL(sdhci_setup_host
);
3375 int __sdhci_add_host(struct sdhci_host
*host
)
3377 struct mmc_host
*mmc
= host
->mmc
;
3383 tasklet_init(&host
->finish_tasklet
,
3384 sdhci_tasklet_finish
, (unsigned long)host
);
3386 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
3388 init_waitqueue_head(&host
->buf_ready_int
);
3390 sdhci_init(host
, 0);
3392 ret
= request_threaded_irq(host
->irq
, sdhci_irq
, sdhci_thread_irq
,
3393 IRQF_SHARED
, mmc_hostname(mmc
), host
);
3395 pr_err("%s: Failed to request IRQ %d: %d\n",
3396 mmc_hostname(mmc
), host
->irq
, ret
);
3400 #ifdef CONFIG_MMC_DEBUG
3401 sdhci_dumpregs(host
);
3404 ret
= sdhci_led_register(host
);
3406 pr_err("%s: Failed to register LED device: %d\n",
3407 mmc_hostname(mmc
), ret
);
3413 ret
= mmc_add_host(mmc
);
3417 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3418 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
3419 (host
->flags
& SDHCI_USE_ADMA
) ?
3420 (host
->flags
& SDHCI_USE_64_BIT_DMA
) ? "ADMA 64-bit" : "ADMA" :
3421 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
3423 sdhci_enable_card_detection(host
);
3428 sdhci_led_unregister(host
);
3430 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3431 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3432 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3433 free_irq(host
->irq
, host
);
3435 tasklet_kill(&host
->finish_tasklet
);
3437 if (!IS_ERR(mmc
->supply
.vqmmc
))
3438 regulator_disable(mmc
->supply
.vqmmc
);
3440 if (host
->align_buffer
)
3441 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3442 host
->adma_table_sz
, host
->align_buffer
,
3444 host
->adma_table
= NULL
;
3445 host
->align_buffer
= NULL
;
3449 EXPORT_SYMBOL_GPL(__sdhci_add_host
);
3451 int sdhci_add_host(struct sdhci_host
*host
)
3455 ret
= sdhci_setup_host(host
);
3459 return __sdhci_add_host(host
);
3461 EXPORT_SYMBOL_GPL(sdhci_add_host
);
3463 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
3465 struct mmc_host
*mmc
= host
->mmc
;
3466 unsigned long flags
;
3469 spin_lock_irqsave(&host
->lock
, flags
);
3471 host
->flags
|= SDHCI_DEVICE_DEAD
;
3474 pr_err("%s: Controller removed during "
3475 " transfer!\n", mmc_hostname(mmc
));
3477 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
3478 sdhci_finish_mrq(host
, host
->mrq
);
3481 spin_unlock_irqrestore(&host
->lock
, flags
);
3484 sdhci_disable_card_detection(host
);
3486 mmc_remove_host(mmc
);
3488 sdhci_led_unregister(host
);
3491 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3493 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3494 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3495 free_irq(host
->irq
, host
);
3497 del_timer_sync(&host
->timer
);
3499 tasklet_kill(&host
->finish_tasklet
);
3501 if (!IS_ERR(mmc
->supply
.vqmmc
))
3502 regulator_disable(mmc
->supply
.vqmmc
);
3504 if (host
->align_buffer
)
3505 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3506 host
->adma_table_sz
, host
->align_buffer
,
3509 host
->adma_table
= NULL
;
3510 host
->align_buffer
= NULL
;
3513 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3515 void sdhci_free_host(struct sdhci_host
*host
)
3517 mmc_free_host(host
->mmc
);
3520 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3522 /*****************************************************************************\
3524 * Driver init/exit *
3526 \*****************************************************************************/
3528 static int __init
sdhci_drv_init(void)
3531 ": Secure Digital Host Controller Interface driver\n");
3532 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3537 static void __exit
sdhci_drv_exit(void)
3541 module_init(sdhci_drv_init
);
3542 module_exit(sdhci_drv_exit
);
3544 module_param(debug_quirks
, uint
, 0444);
3545 module_param(debug_quirks2
, uint
, 0444);
3547 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3548 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3549 MODULE_LICENSE("GPL");
3551 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3552 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");