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Revert "mmc: sdhci: Reset cmd and data circuits after tuning failure"
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/of.h>
26
27 #include <linux/leds.h>
28
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/card.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #include "sdhci.h"
36
37 #define DRIVER_NAME "sdhci"
38
39 #define DBG(f, x...) \
40 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41
42 #define MAX_TUNING_LOOP 40
43
44 static unsigned int debug_quirks = 0;
45 static unsigned int debug_quirks2;
46
47 static void sdhci_finish_data(struct sdhci_host *);
48
49 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
50
51 static void sdhci_dumpregs(struct sdhci_host *host)
52 {
53 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
54 mmc_hostname(host->mmc));
55
56 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
80 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_ACMD12_ERR),
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
90 sdhci_readw(host, SDHCI_HOST_CONTROL2));
91
92 if (host->flags & SDHCI_USE_ADMA) {
93 if (host->flags & SDHCI_USE_64_BIT_DMA)
94 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
98 else
99 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
100 readl(host->ioaddr + SDHCI_ADMA_ERROR),
101 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
102 }
103
104 pr_err(DRIVER_NAME ": ===========================================\n");
105 }
106
107 /*****************************************************************************\
108 * *
109 * Low level functions *
110 * *
111 \*****************************************************************************/
112
113 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
114 {
115 return cmd->data || cmd->flags & MMC_RSP_BUSY;
116 }
117
118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
119 {
120 u32 present;
121
122 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
123 !mmc_card_is_removable(host->mmc))
124 return;
125
126 if (enable) {
127 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
128 SDHCI_CARD_PRESENT;
129
130 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
131 SDHCI_INT_CARD_INSERT;
132 } else {
133 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
134 }
135
136 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
137 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
138 }
139
140 static void sdhci_enable_card_detection(struct sdhci_host *host)
141 {
142 sdhci_set_card_detection(host, true);
143 }
144
145 static void sdhci_disable_card_detection(struct sdhci_host *host)
146 {
147 sdhci_set_card_detection(host, false);
148 }
149
150 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
151 {
152 if (host->bus_on)
153 return;
154 host->bus_on = true;
155 pm_runtime_get_noresume(host->mmc->parent);
156 }
157
158 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
159 {
160 if (!host->bus_on)
161 return;
162 host->bus_on = false;
163 pm_runtime_put_noidle(host->mmc->parent);
164 }
165
166 void sdhci_reset(struct sdhci_host *host, u8 mask)
167 {
168 unsigned long timeout;
169
170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
171
172 if (mask & SDHCI_RESET_ALL) {
173 host->clock = 0;
174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
177 }
178
179 /* Wait max 100 ms */
180 timeout = 100;
181
182 /* hw clears the bit when it's done */
183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
184 if (timeout == 0) {
185 pr_err("%s: Reset 0x%x never completed.\n",
186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
188 return;
189 }
190 timeout--;
191 mdelay(1);
192 }
193 }
194 EXPORT_SYMBOL_GPL(sdhci_reset);
195
196 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197 {
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 struct mmc_host *mmc = host->mmc;
200
201 if (!mmc->ops->get_cd(mmc))
202 return;
203 }
204
205 host->ops->reset(host, mask);
206
207 if (mask & SDHCI_RESET_ALL) {
208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if (host->ops->enable_dma)
210 host->ops->enable_dma(host);
211 }
212
213 /* Resetting the controller clears many */
214 host->preset_enabled = false;
215 }
216 }
217
218 static void sdhci_init(struct sdhci_host *host, int soft)
219 {
220 struct mmc_host *mmc = host->mmc;
221
222 if (soft)
223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
224 else
225 sdhci_do_reset(host, SDHCI_RESET_ALL);
226
227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
231 SDHCI_INT_RESPONSE;
232
233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
234 host->tuning_mode == SDHCI_TUNING_MODE_3)
235 host->ier |= SDHCI_INT_RETUNE;
236
237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
243 mmc->ops->set_ios(mmc, &mmc->ios);
244 }
245 }
246
247 static void sdhci_reinit(struct sdhci_host *host)
248 {
249 sdhci_init(host, 0);
250 sdhci_enable_card_detection(host);
251 }
252
253 static void __sdhci_led_activate(struct sdhci_host *host)
254 {
255 u8 ctrl;
256
257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
258 ctrl |= SDHCI_CTRL_LED;
259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
260 }
261
262 static void __sdhci_led_deactivate(struct sdhci_host *host)
263 {
264 u8 ctrl;
265
266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
267 ctrl &= ~SDHCI_CTRL_LED;
268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
269 }
270
271 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
272 static void sdhci_led_control(struct led_classdev *led,
273 enum led_brightness brightness)
274 {
275 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
276 unsigned long flags;
277
278 spin_lock_irqsave(&host->lock, flags);
279
280 if (host->runtime_suspended)
281 goto out;
282
283 if (brightness == LED_OFF)
284 __sdhci_led_deactivate(host);
285 else
286 __sdhci_led_activate(host);
287 out:
288 spin_unlock_irqrestore(&host->lock, flags);
289 }
290
291 static int sdhci_led_register(struct sdhci_host *host)
292 {
293 struct mmc_host *mmc = host->mmc;
294
295 snprintf(host->led_name, sizeof(host->led_name),
296 "%s::", mmc_hostname(mmc));
297
298 host->led.name = host->led_name;
299 host->led.brightness = LED_OFF;
300 host->led.default_trigger = mmc_hostname(mmc);
301 host->led.brightness_set = sdhci_led_control;
302
303 return led_classdev_register(mmc_dev(mmc), &host->led);
304 }
305
306 static void sdhci_led_unregister(struct sdhci_host *host)
307 {
308 led_classdev_unregister(&host->led);
309 }
310
311 static inline void sdhci_led_activate(struct sdhci_host *host)
312 {
313 }
314
315 static inline void sdhci_led_deactivate(struct sdhci_host *host)
316 {
317 }
318
319 #else
320
321 static inline int sdhci_led_register(struct sdhci_host *host)
322 {
323 return 0;
324 }
325
326 static inline void sdhci_led_unregister(struct sdhci_host *host)
327 {
328 }
329
330 static inline void sdhci_led_activate(struct sdhci_host *host)
331 {
332 __sdhci_led_activate(host);
333 }
334
335 static inline void sdhci_led_deactivate(struct sdhci_host *host)
336 {
337 __sdhci_led_deactivate(host);
338 }
339
340 #endif
341
342 /*****************************************************************************\
343 * *
344 * Core functions *
345 * *
346 \*****************************************************************************/
347
348 static void sdhci_read_block_pio(struct sdhci_host *host)
349 {
350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 uninitialized_var(scratch);
353 u8 *buf;
354
355 DBG("PIO reading\n");
356
357 blksize = host->data->blksz;
358 chunk = 0;
359
360 local_irq_save(flags);
361
362 while (blksize) {
363 BUG_ON(!sg_miter_next(&host->sg_miter));
364
365 len = min(host->sg_miter.length, blksize);
366
367 blksize -= len;
368 host->sg_miter.consumed = len;
369
370 buf = host->sg_miter.addr;
371
372 while (len) {
373 if (chunk == 0) {
374 scratch = sdhci_readl(host, SDHCI_BUFFER);
375 chunk = 4;
376 }
377
378 *buf = scratch & 0xFF;
379
380 buf++;
381 scratch >>= 8;
382 chunk--;
383 len--;
384 }
385 }
386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
390 }
391
392 static void sdhci_write_block_pio(struct sdhci_host *host)
393 {
394 unsigned long flags;
395 size_t blksize, len, chunk;
396 u32 scratch;
397 u8 *buf;
398
399 DBG("PIO writing\n");
400
401 blksize = host->data->blksz;
402 chunk = 0;
403 scratch = 0;
404
405 local_irq_save(flags);
406
407 while (blksize) {
408 BUG_ON(!sg_miter_next(&host->sg_miter));
409
410 len = min(host->sg_miter.length, blksize);
411
412 blksize -= len;
413 host->sg_miter.consumed = len;
414
415 buf = host->sg_miter.addr;
416
417 while (len) {
418 scratch |= (u32)*buf << (chunk * 8);
419
420 buf++;
421 chunk++;
422 len--;
423
424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
425 sdhci_writel(host, scratch, SDHCI_BUFFER);
426 chunk = 0;
427 scratch = 0;
428 }
429 }
430 }
431
432 sg_miter_stop(&host->sg_miter);
433
434 local_irq_restore(flags);
435 }
436
437 static void sdhci_transfer_pio(struct sdhci_host *host)
438 {
439 u32 mask;
440
441 if (host->blocks == 0)
442 return;
443
444 if (host->data->flags & MMC_DATA_READ)
445 mask = SDHCI_DATA_AVAILABLE;
446 else
447 mask = SDHCI_SPACE_AVAILABLE;
448
449 /*
450 * Some controllers (JMicron JMB38x) mess up the buffer bits
451 * for transfers < 4 bytes. As long as it is just one block,
452 * we can ignore the bits.
453 */
454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
455 (host->data->blocks == 1))
456 mask = ~0;
457
458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
460 udelay(100);
461
462 if (host->data->flags & MMC_DATA_READ)
463 sdhci_read_block_pio(host);
464 else
465 sdhci_write_block_pio(host);
466
467 host->blocks--;
468 if (host->blocks == 0)
469 break;
470 }
471
472 DBG("PIO transfer complete.\n");
473 }
474
475 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
476 struct mmc_data *data, int cookie)
477 {
478 int sg_count;
479
480 /*
481 * If the data buffers are already mapped, return the previous
482 * dma_map_sg() result.
483 */
484 if (data->host_cookie == COOKIE_PRE_MAPPED)
485 return data->sg_count;
486
487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
488 data->flags & MMC_DATA_WRITE ?
489 DMA_TO_DEVICE : DMA_FROM_DEVICE);
490
491 if (sg_count == 0)
492 return -ENOSPC;
493
494 data->sg_count = sg_count;
495 data->host_cookie = cookie;
496
497 return sg_count;
498 }
499
500 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
501 {
502 local_irq_save(*flags);
503 return kmap_atomic(sg_page(sg)) + sg->offset;
504 }
505
506 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
507 {
508 kunmap_atomic(buffer);
509 local_irq_restore(*flags);
510 }
511
512 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
513 dma_addr_t addr, int len, unsigned cmd)
514 {
515 struct sdhci_adma2_64_desc *dma_desc = desc;
516
517 /* 32-bit and 64-bit descriptors have these members in same position */
518 dma_desc->cmd = cpu_to_le16(cmd);
519 dma_desc->len = cpu_to_le16(len);
520 dma_desc->addr_lo = cpu_to_le32((u32)addr);
521
522 if (host->flags & SDHCI_USE_64_BIT_DMA)
523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
524 }
525
526 static void sdhci_adma_mark_end(void *desc)
527 {
528 struct sdhci_adma2_64_desc *dma_desc = desc;
529
530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
531 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
532 }
533
534 static void sdhci_adma_table_pre(struct sdhci_host *host,
535 struct mmc_data *data, int sg_count)
536 {
537 struct scatterlist *sg;
538 unsigned long flags;
539 dma_addr_t addr, align_addr;
540 void *desc, *align;
541 char *buffer;
542 int len, offset, i;
543
544 /*
545 * The spec does not specify endianness of descriptor table.
546 * We currently guess that it is LE.
547 */
548
549 host->sg_count = sg_count;
550
551 desc = host->adma_table;
552 align = host->align_buffer;
553
554 align_addr = host->align_addr;
555
556 for_each_sg(data->sg, sg, host->sg_count, i) {
557 addr = sg_dma_address(sg);
558 len = sg_dma_len(sg);
559
560 /*
561 * The SDHCI specification states that ADMA addresses must
562 * be 32-bit aligned. If they aren't, then we use a bounce
563 * buffer for the (up to three) bytes that screw up the
564 * alignment.
565 */
566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
567 SDHCI_ADMA2_MASK;
568 if (offset) {
569 if (data->flags & MMC_DATA_WRITE) {
570 buffer = sdhci_kmap_atomic(sg, &flags);
571 memcpy(align, buffer, offset);
572 sdhci_kunmap_atomic(buffer, &flags);
573 }
574
575 /* tran, valid */
576 sdhci_adma_write_desc(host, desc, align_addr, offset,
577 ADMA2_TRAN_VALID);
578
579 BUG_ON(offset > 65536);
580
581 align += SDHCI_ADMA2_ALIGN;
582 align_addr += SDHCI_ADMA2_ALIGN;
583
584 desc += host->desc_sz;
585
586 addr += offset;
587 len -= offset;
588 }
589
590 BUG_ON(len > 65536);
591
592 if (len) {
593 /* tran, valid */
594 sdhci_adma_write_desc(host, desc, addr, len,
595 ADMA2_TRAN_VALID);
596 desc += host->desc_sz;
597 }
598
599 /*
600 * If this triggers then we have a calculation bug
601 * somewhere. :/
602 */
603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
604 }
605
606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
607 /* Mark the last descriptor as the terminating descriptor */
608 if (desc != host->adma_table) {
609 desc -= host->desc_sz;
610 sdhci_adma_mark_end(desc);
611 }
612 } else {
613 /* Add a terminating entry - nop, end, valid */
614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
615 }
616 }
617
618 static void sdhci_adma_table_post(struct sdhci_host *host,
619 struct mmc_data *data)
620 {
621 struct scatterlist *sg;
622 int i, size;
623 void *align;
624 char *buffer;
625 unsigned long flags;
626
627 if (data->flags & MMC_DATA_READ) {
628 bool has_unaligned = false;
629
630 /* Do a quick scan of the SG list for any unaligned mappings */
631 for_each_sg(data->sg, sg, host->sg_count, i)
632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
633 has_unaligned = true;
634 break;
635 }
636
637 if (has_unaligned) {
638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
639 data->sg_len, DMA_FROM_DEVICE);
640
641 align = host->align_buffer;
642
643 for_each_sg(data->sg, sg, host->sg_count, i) {
644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
645 size = SDHCI_ADMA2_ALIGN -
646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
647
648 buffer = sdhci_kmap_atomic(sg, &flags);
649 memcpy(buffer, align, size);
650 sdhci_kunmap_atomic(buffer, &flags);
651
652 align += SDHCI_ADMA2_ALIGN;
653 }
654 }
655 }
656 }
657 }
658
659 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
660 {
661 u8 count;
662 struct mmc_data *data = cmd->data;
663 unsigned target_timeout, current_timeout;
664
665 /*
666 * If the host controller provides us with an incorrect timeout
667 * value, just skip the check and use 0xE. The hardware may take
668 * longer to time out, but that's much better than having a too-short
669 * timeout value.
670 */
671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
672 return 0xE;
673
674 /* Unspecified timeout, assume max */
675 if (!data && !cmd->busy_timeout)
676 return 0xE;
677
678 /* timeout in us */
679 if (!data)
680 target_timeout = cmd->busy_timeout * 1000;
681 else {
682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
683 if (host->clock && data->timeout_clks) {
684 unsigned long long val;
685
686 /*
687 * data->timeout_clks is in units of clock cycles.
688 * host->clock is in Hz. target_timeout is in us.
689 * Hence, us = 1000000 * cycles / Hz. Round up.
690 */
691 val = 1000000ULL * data->timeout_clks;
692 if (do_div(val, host->clock))
693 target_timeout++;
694 target_timeout += val;
695 }
696 }
697
698 /*
699 * Figure out needed cycles.
700 * We do this in steps in order to fit inside a 32 bit int.
701 * The first step is the minimum timeout, which will have a
702 * minimum resolution of 6 bits:
703 * (1) 2^13*1000 > 2^22,
704 * (2) host->timeout_clk < 2^16
705 * =>
706 * (1) / (2) > 2^6
707 */
708 count = 0;
709 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
710 while (current_timeout < target_timeout) {
711 count++;
712 current_timeout <<= 1;
713 if (count >= 0xF)
714 break;
715 }
716
717 if (count >= 0xF) {
718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
719 mmc_hostname(host->mmc), count, cmd->opcode);
720 count = 0xE;
721 }
722
723 return count;
724 }
725
726 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
727 {
728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
730
731 if (host->flags & SDHCI_REQ_USE_DMA)
732 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
733 else
734 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
735
736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
738 }
739
740 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
741 {
742 u8 count;
743
744 if (host->ops->set_timeout) {
745 host->ops->set_timeout(host, cmd);
746 } else {
747 count = sdhci_calc_timeout(host, cmd);
748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
749 }
750 }
751
752 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
753 {
754 u8 ctrl;
755 struct mmc_data *data = cmd->data;
756
757 if (sdhci_data_line_cmd(cmd))
758 sdhci_set_timeout(host, cmd);
759
760 if (!data)
761 return;
762
763 WARN_ON(host->data);
764
765 /* Sanity checks */
766 BUG_ON(data->blksz * data->blocks > 524288);
767 BUG_ON(data->blksz > host->mmc->max_blk_size);
768 BUG_ON(data->blocks > 65535);
769
770 host->data = data;
771 host->data_early = 0;
772 host->data->bytes_xfered = 0;
773
774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
775 struct scatterlist *sg;
776 unsigned int length_mask, offset_mask;
777 int i;
778
779 host->flags |= SDHCI_REQ_USE_DMA;
780
781 /*
782 * FIXME: This doesn't account for merging when mapping the
783 * scatterlist.
784 *
785 * The assumption here being that alignment and lengths are
786 * the same after DMA mapping to device address space.
787 */
788 length_mask = 0;
789 offset_mask = 0;
790 if (host->flags & SDHCI_USE_ADMA) {
791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
792 length_mask = 3;
793 /*
794 * As we use up to 3 byte chunks to work
795 * around alignment problems, we need to
796 * check the offset as well.
797 */
798 offset_mask = 3;
799 }
800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
802 length_mask = 3;
803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
804 offset_mask = 3;
805 }
806
807 if (unlikely(length_mask | offset_mask)) {
808 for_each_sg(data->sg, sg, data->sg_len, i) {
809 if (sg->length & length_mask) {
810 DBG("Reverting to PIO because of transfer size (%d)\n",
811 sg->length);
812 host->flags &= ~SDHCI_REQ_USE_DMA;
813 break;
814 }
815 if (sg->offset & offset_mask) {
816 DBG("Reverting to PIO because of bad alignment\n");
817 host->flags &= ~SDHCI_REQ_USE_DMA;
818 break;
819 }
820 }
821 }
822 }
823
824 if (host->flags & SDHCI_REQ_USE_DMA) {
825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
826
827 if (sg_cnt <= 0) {
828 /*
829 * This only happens when someone fed
830 * us an invalid request.
831 */
832 WARN_ON(1);
833 host->flags &= ~SDHCI_REQ_USE_DMA;
834 } else if (host->flags & SDHCI_USE_ADMA) {
835 sdhci_adma_table_pre(host, data, sg_cnt);
836
837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
838 if (host->flags & SDHCI_USE_64_BIT_DMA)
839 sdhci_writel(host,
840 (u64)host->adma_addr >> 32,
841 SDHCI_ADMA_ADDRESS_HI);
842 } else {
843 WARN_ON(sg_cnt != 1);
844 sdhci_writel(host, sg_dma_address(data->sg),
845 SDHCI_DMA_ADDRESS);
846 }
847 }
848
849 /*
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
858 (host->flags & SDHCI_USE_ADMA)) {
859 if (host->flags & SDHCI_USE_64_BIT_DMA)
860 ctrl |= SDHCI_CTRL_ADMA64;
861 else
862 ctrl |= SDHCI_CTRL_ADMA32;
863 } else {
864 ctrl |= SDHCI_CTRL_SDMA;
865 }
866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
867 }
868
869 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
870 int flags;
871
872 flags = SG_MITER_ATOMIC;
873 if (host->data->flags & MMC_DATA_READ)
874 flags |= SG_MITER_TO_SG;
875 else
876 flags |= SG_MITER_FROM_SG;
877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
878 host->blocks = data->blocks;
879 }
880
881 sdhci_set_transfer_irqs(host);
882
883 /* Set the DMA boundary value and block size */
884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
885 data->blksz), SDHCI_BLOCK_SIZE);
886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
887 }
888
889 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
890 struct mmc_request *mrq)
891 {
892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
893 !mrq->cap_cmd_during_tfr;
894 }
895
896 static void sdhci_set_transfer_mode(struct sdhci_host *host,
897 struct mmc_command *cmd)
898 {
899 u16 mode = 0;
900 struct mmc_data *data = cmd->data;
901
902 if (data == NULL) {
903 if (host->quirks2 &
904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
906 } else {
907 /* clear Auto CMD settings for no data CMDs */
908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
911 }
912 return;
913 }
914
915 WARN_ON(!host->data);
916
917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
918 mode = SDHCI_TRNS_BLK_CNT_EN;
919
920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
922 /*
923 * If we are sending CMD23, CMD12 never gets sent
924 * on successful completion (so no Auto-CMD12).
925 */
926 if (sdhci_auto_cmd12(host, cmd->mrq) &&
927 (cmd->opcode != SD_IO_RW_EXTENDED))
928 mode |= SDHCI_TRNS_AUTO_CMD12;
929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
930 mode |= SDHCI_TRNS_AUTO_CMD23;
931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
932 }
933 }
934
935 if (data->flags & MMC_DATA_READ)
936 mode |= SDHCI_TRNS_READ;
937 if (host->flags & SDHCI_REQ_USE_DMA)
938 mode |= SDHCI_TRNS_DMA;
939
940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
941 }
942
943 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
944 {
945 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
946 ((mrq->cmd && mrq->cmd->error) ||
947 (mrq->sbc && mrq->sbc->error) ||
948 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
949 (mrq->data->stop && mrq->data->stop->error))) ||
950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
951 }
952
953 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
954 {
955 int i;
956
957 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
958 if (host->mrqs_done[i] == mrq) {
959 WARN_ON(1);
960 return;
961 }
962 }
963
964 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
965 if (!host->mrqs_done[i]) {
966 host->mrqs_done[i] = mrq;
967 break;
968 }
969 }
970
971 WARN_ON(i >= SDHCI_MAX_MRQS);
972
973 tasklet_schedule(&host->finish_tasklet);
974 }
975
976 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
977 {
978 if (host->cmd && host->cmd->mrq == mrq)
979 host->cmd = NULL;
980
981 if (host->data_cmd && host->data_cmd->mrq == mrq)
982 host->data_cmd = NULL;
983
984 if (host->data && host->data->mrq == mrq)
985 host->data = NULL;
986
987 if (sdhci_needs_reset(host, mrq))
988 host->pending_reset = true;
989
990 __sdhci_finish_mrq(host, mrq);
991 }
992
993 static void sdhci_finish_data(struct sdhci_host *host)
994 {
995 struct mmc_command *data_cmd = host->data_cmd;
996 struct mmc_data *data = host->data;
997
998 host->data = NULL;
999 host->data_cmd = NULL;
1000
1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1003 sdhci_adma_table_post(host, data);
1004
1005 /*
1006 * The specification states that the block count register must
1007 * be updated, but it does not specify at what point in the
1008 * data flow. That makes the register entirely useless to read
1009 * back so we have to assume that nothing made it to the card
1010 * in the event of an error.
1011 */
1012 if (data->error)
1013 data->bytes_xfered = 0;
1014 else
1015 data->bytes_xfered = data->blksz * data->blocks;
1016
1017 /*
1018 * Need to send CMD12 if -
1019 * a) open-ended multiblock transfer (no CMD23)
1020 * b) error in multiblock transfer
1021 */
1022 if (data->stop &&
1023 (data->error ||
1024 !data->mrq->sbc)) {
1025
1026 /*
1027 * The controller needs a reset of internal state machines
1028 * upon error conditions.
1029 */
1030 if (data->error) {
1031 if (!host->cmd || host->cmd == data_cmd)
1032 sdhci_do_reset(host, SDHCI_RESET_CMD);
1033 sdhci_do_reset(host, SDHCI_RESET_DATA);
1034 }
1035
1036 /*
1037 * 'cap_cmd_during_tfr' request must not use the command line
1038 * after mmc_command_done() has been called. It is upper layer's
1039 * responsibility to send the stop command if required.
1040 */
1041 if (data->mrq->cap_cmd_during_tfr) {
1042 sdhci_finish_mrq(host, data->mrq);
1043 } else {
1044 /* Avoid triggering warning in sdhci_send_command() */
1045 host->cmd = NULL;
1046 sdhci_send_command(host, data->stop);
1047 }
1048 } else {
1049 sdhci_finish_mrq(host, data->mrq);
1050 }
1051 }
1052
1053 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1054 unsigned long timeout)
1055 {
1056 if (sdhci_data_line_cmd(mrq->cmd))
1057 mod_timer(&host->data_timer, timeout);
1058 else
1059 mod_timer(&host->timer, timeout);
1060 }
1061
1062 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1063 {
1064 if (sdhci_data_line_cmd(mrq->cmd))
1065 del_timer(&host->data_timer);
1066 else
1067 del_timer(&host->timer);
1068 }
1069
1070 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1071 {
1072 int flags;
1073 u32 mask;
1074 unsigned long timeout;
1075
1076 WARN_ON(host->cmd);
1077
1078 /* Initially, a command has no error */
1079 cmd->error = 0;
1080
1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1082 cmd->opcode == MMC_STOP_TRANSMISSION)
1083 cmd->flags |= MMC_RSP_BUSY;
1084
1085 /* Wait max 10 ms */
1086 timeout = 10;
1087
1088 mask = SDHCI_CMD_INHIBIT;
1089 if (sdhci_data_line_cmd(cmd))
1090 mask |= SDHCI_DATA_INHIBIT;
1091
1092 /* We shouldn't wait for data inihibit for stop commands, even
1093 though they might use busy signaling */
1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1095 mask &= ~SDHCI_DATA_INHIBIT;
1096
1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1098 if (timeout == 0) {
1099 pr_err("%s: Controller never released inhibit bit(s).\n",
1100 mmc_hostname(host->mmc));
1101 sdhci_dumpregs(host);
1102 cmd->error = -EIO;
1103 sdhci_finish_mrq(host, cmd->mrq);
1104 return;
1105 }
1106 timeout--;
1107 mdelay(1);
1108 }
1109
1110 timeout = jiffies;
1111 if (!cmd->data && cmd->busy_timeout > 9000)
1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1113 else
1114 timeout += 10 * HZ;
1115 sdhci_mod_timer(host, cmd->mrq, timeout);
1116
1117 host->cmd = cmd;
1118 if (sdhci_data_line_cmd(cmd)) {
1119 WARN_ON(host->data_cmd);
1120 host->data_cmd = cmd;
1121 }
1122
1123 sdhci_prepare_data(host, cmd);
1124
1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1126
1127 sdhci_set_transfer_mode(host, cmd);
1128
1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1130 pr_err("%s: Unsupported response type!\n",
1131 mmc_hostname(host->mmc));
1132 cmd->error = -EINVAL;
1133 sdhci_finish_mrq(host, cmd->mrq);
1134 return;
1135 }
1136
1137 if (!(cmd->flags & MMC_RSP_PRESENT))
1138 flags = SDHCI_CMD_RESP_NONE;
1139 else if (cmd->flags & MMC_RSP_136)
1140 flags = SDHCI_CMD_RESP_LONG;
1141 else if (cmd->flags & MMC_RSP_BUSY)
1142 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1143 else
1144 flags = SDHCI_CMD_RESP_SHORT;
1145
1146 if (cmd->flags & MMC_RSP_CRC)
1147 flags |= SDHCI_CMD_CRC;
1148 if (cmd->flags & MMC_RSP_OPCODE)
1149 flags |= SDHCI_CMD_INDEX;
1150
1151 /* CMD19 is special in that the Data Present Select should be set */
1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1154 flags |= SDHCI_CMD_DATA;
1155
1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1157 }
1158 EXPORT_SYMBOL_GPL(sdhci_send_command);
1159
1160 static void sdhci_finish_command(struct sdhci_host *host)
1161 {
1162 struct mmc_command *cmd = host->cmd;
1163 int i;
1164
1165 host->cmd = NULL;
1166
1167 if (cmd->flags & MMC_RSP_PRESENT) {
1168 if (cmd->flags & MMC_RSP_136) {
1169 /* CRC is stripped so we need to do some shifting. */
1170 for (i = 0;i < 4;i++) {
1171 cmd->resp[i] = sdhci_readl(host,
1172 SDHCI_RESPONSE + (3-i)*4) << 8;
1173 if (i != 3)
1174 cmd->resp[i] |=
1175 sdhci_readb(host,
1176 SDHCI_RESPONSE + (3-i)*4-1);
1177 }
1178 } else {
1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1180 }
1181 }
1182
1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1184 mmc_command_done(host->mmc, cmd->mrq);
1185
1186 /*
1187 * The host can send and interrupt when the busy state has
1188 * ended, allowing us to wait without wasting CPU cycles.
1189 * The busy signal uses DAT0 so this is similar to waiting
1190 * for data to complete.
1191 *
1192 * Note: The 1.0 specification is a bit ambiguous about this
1193 * feature so there might be some problems with older
1194 * controllers.
1195 */
1196 if (cmd->flags & MMC_RSP_BUSY) {
1197 if (cmd->data) {
1198 DBG("Cannot wait for busy signal when also doing a data transfer");
1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1200 cmd == host->data_cmd) {
1201 /* Command complete before busy is ended */
1202 return;
1203 }
1204 }
1205
1206 /* Finished CMD23, now send actual command. */
1207 if (cmd == cmd->mrq->sbc) {
1208 sdhci_send_command(host, cmd->mrq->cmd);
1209 } else {
1210
1211 /* Processed actual command. */
1212 if (host->data && host->data_early)
1213 sdhci_finish_data(host);
1214
1215 if (!cmd->data)
1216 sdhci_finish_mrq(host, cmd->mrq);
1217 }
1218 }
1219
1220 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1221 {
1222 u16 preset = 0;
1223
1224 switch (host->timing) {
1225 case MMC_TIMING_UHS_SDR12:
1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1227 break;
1228 case MMC_TIMING_UHS_SDR25:
1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1230 break;
1231 case MMC_TIMING_UHS_SDR50:
1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1233 break;
1234 case MMC_TIMING_UHS_SDR104:
1235 case MMC_TIMING_MMC_HS200:
1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1237 break;
1238 case MMC_TIMING_UHS_DDR50:
1239 case MMC_TIMING_MMC_DDR52:
1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1241 break;
1242 case MMC_TIMING_MMC_HS400:
1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1244 break;
1245 default:
1246 pr_warn("%s: Invalid UHS-I mode selected\n",
1247 mmc_hostname(host->mmc));
1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1249 break;
1250 }
1251 return preset;
1252 }
1253
1254 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1255 unsigned int *actual_clock)
1256 {
1257 int div = 0; /* Initialized for compiler warning */
1258 int real_div = div, clk_mul = 1;
1259 u16 clk = 0;
1260 bool switch_base_clk = false;
1261
1262 if (host->version >= SDHCI_SPEC_300) {
1263 if (host->preset_enabled) {
1264 u16 pre_val;
1265
1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1267 pre_val = sdhci_get_preset_value(host);
1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1270 if (host->clk_mul &&
1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1272 clk = SDHCI_PROG_CLOCK_MODE;
1273 real_div = div + 1;
1274 clk_mul = host->clk_mul;
1275 } else {
1276 real_div = max_t(int, 1, div << 1);
1277 }
1278 goto clock_set;
1279 }
1280
1281 /*
1282 * Check if the Host Controller supports Programmable Clock
1283 * Mode.
1284 */
1285 if (host->clk_mul) {
1286 for (div = 1; div <= 1024; div++) {
1287 if ((host->max_clk * host->clk_mul / div)
1288 <= clock)
1289 break;
1290 }
1291 if ((host->max_clk * host->clk_mul / div) <= clock) {
1292 /*
1293 * Set Programmable Clock Mode in the Clock
1294 * Control register.
1295 */
1296 clk = SDHCI_PROG_CLOCK_MODE;
1297 real_div = div;
1298 clk_mul = host->clk_mul;
1299 div--;
1300 } else {
1301 /*
1302 * Divisor can be too small to reach clock
1303 * speed requirement. Then use the base clock.
1304 */
1305 switch_base_clk = true;
1306 }
1307 }
1308
1309 if (!host->clk_mul || switch_base_clk) {
1310 /* Version 3.00 divisors must be a multiple of 2. */
1311 if (host->max_clk <= clock)
1312 div = 1;
1313 else {
1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1315 div += 2) {
1316 if ((host->max_clk / div) <= clock)
1317 break;
1318 }
1319 }
1320 real_div = div;
1321 div >>= 1;
1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1323 && !div && host->max_clk <= 25000000)
1324 div = 1;
1325 }
1326 } else {
1327 /* Version 2.00 divisors must be a power of 2. */
1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1329 if ((host->max_clk / div) <= clock)
1330 break;
1331 }
1332 real_div = div;
1333 div >>= 1;
1334 }
1335
1336 clock_set:
1337 if (real_div)
1338 *actual_clock = (host->max_clk * clk_mul) / real_div;
1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1341 << SDHCI_DIVIDER_HI_SHIFT;
1342
1343 return clk;
1344 }
1345 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1346
1347 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1348 {
1349 unsigned long timeout;
1350
1351 clk |= SDHCI_CLOCK_INT_EN;
1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1353
1354 /* Wait max 20 ms */
1355 timeout = 20;
1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1357 & SDHCI_CLOCK_INT_STABLE)) {
1358 if (timeout == 0) {
1359 pr_err("%s: Internal clock never stabilised.\n",
1360 mmc_hostname(host->mmc));
1361 sdhci_dumpregs(host);
1362 return;
1363 }
1364 timeout--;
1365 mdelay(1);
1366 }
1367
1368 clk |= SDHCI_CLOCK_CARD_EN;
1369 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1370 }
1371 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1372
1373 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1374 {
1375 u16 clk;
1376
1377 host->mmc->actual_clock = 0;
1378
1379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1380
1381 if (clock == 0)
1382 return;
1383
1384 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1385 sdhci_enable_clk(host, clk);
1386 }
1387 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1388
1389 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1390 unsigned short vdd)
1391 {
1392 struct mmc_host *mmc = host->mmc;
1393
1394 spin_unlock_irq(&host->lock);
1395 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1396 spin_lock_irq(&host->lock);
1397
1398 if (mode != MMC_POWER_OFF)
1399 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1400 else
1401 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1402 }
1403
1404 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1405 unsigned short vdd)
1406 {
1407 u8 pwr = 0;
1408
1409 if (mode != MMC_POWER_OFF) {
1410 switch (1 << vdd) {
1411 case MMC_VDD_165_195:
1412 pwr = SDHCI_POWER_180;
1413 break;
1414 case MMC_VDD_29_30:
1415 case MMC_VDD_30_31:
1416 pwr = SDHCI_POWER_300;
1417 break;
1418 case MMC_VDD_32_33:
1419 case MMC_VDD_33_34:
1420 pwr = SDHCI_POWER_330;
1421 break;
1422 default:
1423 WARN(1, "%s: Invalid vdd %#x\n",
1424 mmc_hostname(host->mmc), vdd);
1425 break;
1426 }
1427 }
1428
1429 if (host->pwr == pwr)
1430 return;
1431
1432 host->pwr = pwr;
1433
1434 if (pwr == 0) {
1435 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1436 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1437 sdhci_runtime_pm_bus_off(host);
1438 } else {
1439 /*
1440 * Spec says that we should clear the power reg before setting
1441 * a new value. Some controllers don't seem to like this though.
1442 */
1443 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1444 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1445
1446 /*
1447 * At least the Marvell CaFe chip gets confused if we set the
1448 * voltage and set turn on power at the same time, so set the
1449 * voltage first.
1450 */
1451 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1452 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1453
1454 pwr |= SDHCI_POWER_ON;
1455
1456 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1457
1458 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1459 sdhci_runtime_pm_bus_on(host);
1460
1461 /*
1462 * Some controllers need an extra 10ms delay of 10ms before
1463 * they can apply clock after applying power
1464 */
1465 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1466 mdelay(10);
1467 }
1468 }
1469 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1470
1471 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1472 unsigned short vdd)
1473 {
1474 if (IS_ERR(host->mmc->supply.vmmc))
1475 sdhci_set_power_noreg(host, mode, vdd);
1476 else
1477 sdhci_set_power_reg(host, mode, vdd);
1478 }
1479 EXPORT_SYMBOL_GPL(sdhci_set_power);
1480
1481 /*****************************************************************************\
1482 * *
1483 * MMC callbacks *
1484 * *
1485 \*****************************************************************************/
1486
1487 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1488 {
1489 struct sdhci_host *host;
1490 int present;
1491 unsigned long flags;
1492
1493 host = mmc_priv(mmc);
1494
1495 /* Firstly check card presence */
1496 present = mmc->ops->get_cd(mmc);
1497
1498 spin_lock_irqsave(&host->lock, flags);
1499
1500 sdhci_led_activate(host);
1501
1502 /*
1503 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1504 * requests if Auto-CMD12 is enabled.
1505 */
1506 if (sdhci_auto_cmd12(host, mrq)) {
1507 if (mrq->stop) {
1508 mrq->data->stop = NULL;
1509 mrq->stop = NULL;
1510 }
1511 }
1512
1513 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1514 mrq->cmd->error = -ENOMEDIUM;
1515 sdhci_finish_mrq(host, mrq);
1516 } else {
1517 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1518 sdhci_send_command(host, mrq->sbc);
1519 else
1520 sdhci_send_command(host, mrq->cmd);
1521 }
1522
1523 mmiowb();
1524 spin_unlock_irqrestore(&host->lock, flags);
1525 }
1526
1527 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1528 {
1529 u8 ctrl;
1530
1531 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1532 if (width == MMC_BUS_WIDTH_8) {
1533 ctrl &= ~SDHCI_CTRL_4BITBUS;
1534 if (host->version >= SDHCI_SPEC_300)
1535 ctrl |= SDHCI_CTRL_8BITBUS;
1536 } else {
1537 if (host->version >= SDHCI_SPEC_300)
1538 ctrl &= ~SDHCI_CTRL_8BITBUS;
1539 if (width == MMC_BUS_WIDTH_4)
1540 ctrl |= SDHCI_CTRL_4BITBUS;
1541 else
1542 ctrl &= ~SDHCI_CTRL_4BITBUS;
1543 }
1544 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1545 }
1546 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1547
1548 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1549 {
1550 u16 ctrl_2;
1551
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 /* Select Bus Speed Mode for host */
1554 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1555 if ((timing == MMC_TIMING_MMC_HS200) ||
1556 (timing == MMC_TIMING_UHS_SDR104))
1557 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1558 else if (timing == MMC_TIMING_UHS_SDR12)
1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1560 else if (timing == MMC_TIMING_UHS_SDR25)
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1562 else if (timing == MMC_TIMING_UHS_SDR50)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1564 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1565 (timing == MMC_TIMING_MMC_DDR52))
1566 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1567 else if (timing == MMC_TIMING_MMC_HS400)
1568 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1569 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1570 }
1571 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1572
1573 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1574 {
1575 struct sdhci_host *host = mmc_priv(mmc);
1576 unsigned long flags;
1577 u8 ctrl;
1578
1579 spin_lock_irqsave(&host->lock, flags);
1580
1581 if (host->flags & SDHCI_DEVICE_DEAD) {
1582 spin_unlock_irqrestore(&host->lock, flags);
1583 if (!IS_ERR(mmc->supply.vmmc) &&
1584 ios->power_mode == MMC_POWER_OFF)
1585 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1586 return;
1587 }
1588
1589 /*
1590 * Reset the chip on each power off.
1591 * Should clear out any weird states.
1592 */
1593 if (ios->power_mode == MMC_POWER_OFF) {
1594 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1595 sdhci_reinit(host);
1596 }
1597
1598 if (host->version >= SDHCI_SPEC_300 &&
1599 (ios->power_mode == MMC_POWER_UP) &&
1600 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1601 sdhci_enable_preset_value(host, false);
1602
1603 if (!ios->clock || ios->clock != host->clock) {
1604 host->ops->set_clock(host, ios->clock);
1605 host->clock = ios->clock;
1606
1607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1608 host->clock) {
1609 host->timeout_clk = host->mmc->actual_clock ?
1610 host->mmc->actual_clock / 1000 :
1611 host->clock / 1000;
1612 host->mmc->max_busy_timeout =
1613 host->ops->get_max_timeout_count ?
1614 host->ops->get_max_timeout_count(host) :
1615 1 << 27;
1616 host->mmc->max_busy_timeout /= host->timeout_clk;
1617 }
1618 }
1619
1620 if (host->ops->set_power)
1621 host->ops->set_power(host, ios->power_mode, ios->vdd);
1622 else
1623 sdhci_set_power(host, ios->power_mode, ios->vdd);
1624
1625 if (host->ops->platform_send_init_74_clocks)
1626 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1627
1628 host->ops->set_bus_width(host, ios->bus_width);
1629
1630 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1631
1632 if ((ios->timing == MMC_TIMING_SD_HS ||
1633 ios->timing == MMC_TIMING_MMC_HS ||
1634 ios->timing == MMC_TIMING_MMC_HS400 ||
1635 ios->timing == MMC_TIMING_MMC_HS200 ||
1636 ios->timing == MMC_TIMING_MMC_DDR52 ||
1637 ios->timing == MMC_TIMING_UHS_SDR50 ||
1638 ios->timing == MMC_TIMING_UHS_SDR104 ||
1639 ios->timing == MMC_TIMING_UHS_DDR50 ||
1640 ios->timing == MMC_TIMING_UHS_SDR25)
1641 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1642 ctrl |= SDHCI_CTRL_HISPD;
1643 else
1644 ctrl &= ~SDHCI_CTRL_HISPD;
1645
1646 if (host->version >= SDHCI_SPEC_300) {
1647 u16 clk, ctrl_2;
1648
1649 if (!host->preset_enabled) {
1650 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1651 /*
1652 * We only need to set Driver Strength if the
1653 * preset value enable is not set.
1654 */
1655 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1656 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1657 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1658 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1659 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1661 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1662 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1663 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1664 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1665 else {
1666 pr_warn("%s: invalid driver type, default to driver type B\n",
1667 mmc_hostname(mmc));
1668 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1669 }
1670
1671 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1672 } else {
1673 /*
1674 * According to SDHC Spec v3.00, if the Preset Value
1675 * Enable in the Host Control 2 register is set, we
1676 * need to reset SD Clock Enable before changing High
1677 * Speed Enable to avoid generating clock gliches.
1678 */
1679
1680 /* Reset SD Clock Enable */
1681 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1682 clk &= ~SDHCI_CLOCK_CARD_EN;
1683 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1684
1685 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1686
1687 /* Re-enable SD Clock */
1688 host->ops->set_clock(host, host->clock);
1689 }
1690
1691 /* Reset SD Clock Enable */
1692 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1693 clk &= ~SDHCI_CLOCK_CARD_EN;
1694 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1695
1696 host->ops->set_uhs_signaling(host, ios->timing);
1697 host->timing = ios->timing;
1698
1699 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1700 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1701 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1702 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1703 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1704 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1705 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1706 u16 preset;
1707
1708 sdhci_enable_preset_value(host, true);
1709 preset = sdhci_get_preset_value(host);
1710 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1711 >> SDHCI_PRESET_DRV_SHIFT;
1712 }
1713
1714 /* Re-enable SD Clock */
1715 host->ops->set_clock(host, host->clock);
1716 } else
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718
1719 /*
1720 * Some (ENE) controllers go apeshit on some ios operation,
1721 * signalling timeout and CRC errors even on CMD0. Resetting
1722 * it on each ios seems to solve the problem.
1723 */
1724 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1725 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1726
1727 mmiowb();
1728 spin_unlock_irqrestore(&host->lock, flags);
1729 }
1730
1731 static int sdhci_get_cd(struct mmc_host *mmc)
1732 {
1733 struct sdhci_host *host = mmc_priv(mmc);
1734 int gpio_cd = mmc_gpio_get_cd(mmc);
1735
1736 if (host->flags & SDHCI_DEVICE_DEAD)
1737 return 0;
1738
1739 /* If nonremovable, assume that the card is always present. */
1740 if (!mmc_card_is_removable(host->mmc))
1741 return 1;
1742
1743 /*
1744 * Try slot gpio detect, if defined it take precedence
1745 * over build in controller functionality
1746 */
1747 if (gpio_cd >= 0)
1748 return !!gpio_cd;
1749
1750 /* If polling, assume that the card is always present. */
1751 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1752 return 1;
1753
1754 /* Host native card detect */
1755 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1756 }
1757
1758 static int sdhci_check_ro(struct sdhci_host *host)
1759 {
1760 unsigned long flags;
1761 int is_readonly;
1762
1763 spin_lock_irqsave(&host->lock, flags);
1764
1765 if (host->flags & SDHCI_DEVICE_DEAD)
1766 is_readonly = 0;
1767 else if (host->ops->get_ro)
1768 is_readonly = host->ops->get_ro(host);
1769 else
1770 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1771 & SDHCI_WRITE_PROTECT);
1772
1773 spin_unlock_irqrestore(&host->lock, flags);
1774
1775 /* This quirk needs to be replaced by a callback-function later */
1776 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1777 !is_readonly : is_readonly;
1778 }
1779
1780 #define SAMPLE_COUNT 5
1781
1782 static int sdhci_get_ro(struct mmc_host *mmc)
1783 {
1784 struct sdhci_host *host = mmc_priv(mmc);
1785 int i, ro_count;
1786
1787 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1788 return sdhci_check_ro(host);
1789
1790 ro_count = 0;
1791 for (i = 0; i < SAMPLE_COUNT; i++) {
1792 if (sdhci_check_ro(host)) {
1793 if (++ro_count > SAMPLE_COUNT / 2)
1794 return 1;
1795 }
1796 msleep(30);
1797 }
1798 return 0;
1799 }
1800
1801 static void sdhci_hw_reset(struct mmc_host *mmc)
1802 {
1803 struct sdhci_host *host = mmc_priv(mmc);
1804
1805 if (host->ops && host->ops->hw_reset)
1806 host->ops->hw_reset(host);
1807 }
1808
1809 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1810 {
1811 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1812 if (enable)
1813 host->ier |= SDHCI_INT_CARD_INT;
1814 else
1815 host->ier &= ~SDHCI_INT_CARD_INT;
1816
1817 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1818 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1819 mmiowb();
1820 }
1821 }
1822
1823 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1824 {
1825 struct sdhci_host *host = mmc_priv(mmc);
1826 unsigned long flags;
1827
1828 spin_lock_irqsave(&host->lock, flags);
1829 if (enable)
1830 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1831 else
1832 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1833
1834 sdhci_enable_sdio_irq_nolock(host, enable);
1835 spin_unlock_irqrestore(&host->lock, flags);
1836 }
1837
1838 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1839 struct mmc_ios *ios)
1840 {
1841 struct sdhci_host *host = mmc_priv(mmc);
1842 u16 ctrl;
1843 int ret;
1844
1845 /*
1846 * Signal Voltage Switching is only applicable for Host Controllers
1847 * v3.00 and above.
1848 */
1849 if (host->version < SDHCI_SPEC_300)
1850 return 0;
1851
1852 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1853
1854 switch (ios->signal_voltage) {
1855 case MMC_SIGNAL_VOLTAGE_330:
1856 if (!(host->flags & SDHCI_SIGNALING_330))
1857 return -EINVAL;
1858 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1859 ctrl &= ~SDHCI_CTRL_VDD_180;
1860 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1861
1862 if (!IS_ERR(mmc->supply.vqmmc)) {
1863 ret = mmc_regulator_set_vqmmc(mmc, ios);
1864 if (ret) {
1865 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1866 mmc_hostname(mmc));
1867 return -EIO;
1868 }
1869 }
1870 /* Wait for 5ms */
1871 usleep_range(5000, 5500);
1872
1873 /* 3.3V regulator output should be stable within 5 ms */
1874 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1875 if (!(ctrl & SDHCI_CTRL_VDD_180))
1876 return 0;
1877
1878 pr_warn("%s: 3.3V regulator output did not became stable\n",
1879 mmc_hostname(mmc));
1880
1881 return -EAGAIN;
1882 case MMC_SIGNAL_VOLTAGE_180:
1883 if (!(host->flags & SDHCI_SIGNALING_180))
1884 return -EINVAL;
1885 if (!IS_ERR(mmc->supply.vqmmc)) {
1886 ret = mmc_regulator_set_vqmmc(mmc, ios);
1887 if (ret) {
1888 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1889 mmc_hostname(mmc));
1890 return -EIO;
1891 }
1892 }
1893
1894 /*
1895 * Enable 1.8V Signal Enable in the Host Control2
1896 * register
1897 */
1898 ctrl |= SDHCI_CTRL_VDD_180;
1899 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1900
1901 /* Some controller need to do more when switching */
1902 if (host->ops->voltage_switch)
1903 host->ops->voltage_switch(host);
1904
1905 /* 1.8V regulator output should be stable within 5 ms */
1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907 if (ctrl & SDHCI_CTRL_VDD_180)
1908 return 0;
1909
1910 pr_warn("%s: 1.8V regulator output did not became stable\n",
1911 mmc_hostname(mmc));
1912
1913 return -EAGAIN;
1914 case MMC_SIGNAL_VOLTAGE_120:
1915 if (!(host->flags & SDHCI_SIGNALING_120))
1916 return -EINVAL;
1917 if (!IS_ERR(mmc->supply.vqmmc)) {
1918 ret = mmc_regulator_set_vqmmc(mmc, ios);
1919 if (ret) {
1920 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1921 mmc_hostname(mmc));
1922 return -EIO;
1923 }
1924 }
1925 return 0;
1926 default:
1927 /* No signal voltage switch required */
1928 return 0;
1929 }
1930 }
1931
1932 static int sdhci_card_busy(struct mmc_host *mmc)
1933 {
1934 struct sdhci_host *host = mmc_priv(mmc);
1935 u32 present_state;
1936
1937 /* Check whether DAT[0] is 0 */
1938 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1939
1940 return !(present_state & SDHCI_DATA_0_LVL_MASK);
1941 }
1942
1943 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1944 {
1945 struct sdhci_host *host = mmc_priv(mmc);
1946 unsigned long flags;
1947
1948 spin_lock_irqsave(&host->lock, flags);
1949 host->flags |= SDHCI_HS400_TUNING;
1950 spin_unlock_irqrestore(&host->lock, flags);
1951
1952 return 0;
1953 }
1954
1955 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1956 {
1957 struct sdhci_host *host = mmc_priv(mmc);
1958 u16 ctrl;
1959 int tuning_loop_counter = MAX_TUNING_LOOP;
1960 int err = 0;
1961 unsigned long flags;
1962 unsigned int tuning_count = 0;
1963 bool hs400_tuning;
1964
1965 spin_lock_irqsave(&host->lock, flags);
1966
1967 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1968 host->flags &= ~SDHCI_HS400_TUNING;
1969
1970 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1971 tuning_count = host->tuning_count;
1972
1973 /*
1974 * The Host Controller needs tuning in case of SDR104 and DDR50
1975 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1976 * the Capabilities register.
1977 * If the Host Controller supports the HS200 mode then the
1978 * tuning function has to be executed.
1979 */
1980 switch (host->timing) {
1981 /* HS400 tuning is done in HS200 mode */
1982 case MMC_TIMING_MMC_HS400:
1983 err = -EINVAL;
1984 goto out_unlock;
1985
1986 case MMC_TIMING_MMC_HS200:
1987 /*
1988 * Periodic re-tuning for HS400 is not expected to be needed, so
1989 * disable it here.
1990 */
1991 if (hs400_tuning)
1992 tuning_count = 0;
1993 break;
1994
1995 case MMC_TIMING_UHS_SDR104:
1996 case MMC_TIMING_UHS_DDR50:
1997 break;
1998
1999 case MMC_TIMING_UHS_SDR50:
2000 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2001 break;
2002 /* FALLTHROUGH */
2003
2004 default:
2005 goto out_unlock;
2006 }
2007
2008 if (host->ops->platform_execute_tuning) {
2009 spin_unlock_irqrestore(&host->lock, flags);
2010 err = host->ops->platform_execute_tuning(host, opcode);
2011 return err;
2012 }
2013
2014 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2015 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2016 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2017 ctrl |= SDHCI_CTRL_TUNED_CLK;
2018 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2019
2020 /*
2021 * As per the Host Controller spec v3.00, tuning command
2022 * generates Buffer Read Ready interrupt, so enable that.
2023 *
2024 * Note: The spec clearly says that when tuning sequence
2025 * is being performed, the controller does not generate
2026 * interrupts other than Buffer Read Ready interrupt. But
2027 * to make sure we don't hit a controller bug, we _only_
2028 * enable Buffer Read Ready interrupt here.
2029 */
2030 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2031 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2032
2033 /*
2034 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2035 * of loops reaches 40 times.
2036 */
2037 do {
2038 struct mmc_command cmd = {0};
2039 struct mmc_request mrq = {NULL};
2040
2041 cmd.opcode = opcode;
2042 cmd.arg = 0;
2043 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2044 cmd.retries = 0;
2045 cmd.data = NULL;
2046 cmd.mrq = &mrq;
2047 cmd.error = 0;
2048
2049 if (tuning_loop_counter-- == 0)
2050 break;
2051
2052 mrq.cmd = &cmd;
2053
2054 /*
2055 * In response to CMD19, the card sends 64 bytes of tuning
2056 * block to the Host Controller. So we set the block size
2057 * to 64 here.
2058 */
2059 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2060 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2061 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2062 SDHCI_BLOCK_SIZE);
2063 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2064 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2065 SDHCI_BLOCK_SIZE);
2066 } else {
2067 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2068 SDHCI_BLOCK_SIZE);
2069 }
2070
2071 /*
2072 * The tuning block is sent by the card to the host controller.
2073 * So we set the TRNS_READ bit in the Transfer Mode register.
2074 * This also takes care of setting DMA Enable and Multi Block
2075 * Select in the same register to 0.
2076 */
2077 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2078
2079 sdhci_send_command(host, &cmd);
2080
2081 host->cmd = NULL;
2082 sdhci_del_timer(host, &mrq);
2083
2084 spin_unlock_irqrestore(&host->lock, flags);
2085 /* Wait for Buffer Read Ready interrupt */
2086 wait_event_timeout(host->buf_ready_int,
2087 (host->tuning_done == 1),
2088 msecs_to_jiffies(50));
2089 spin_lock_irqsave(&host->lock, flags);
2090
2091 if (!host->tuning_done) {
2092 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2093 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2094 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2095 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2096 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2097
2098 err = -EIO;
2099 goto out;
2100 }
2101
2102 host->tuning_done = 0;
2103
2104 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2105
2106 /* eMMC spec does not require a delay between tuning cycles */
2107 if (opcode == MMC_SEND_TUNING_BLOCK)
2108 mdelay(1);
2109 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2110
2111 /*
2112 * The Host Driver has exhausted the maximum number of loops allowed,
2113 * so use fixed sampling frequency.
2114 */
2115 if (tuning_loop_counter < 0) {
2116 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2117 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2118 }
2119 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2120 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2121 err = -EIO;
2122 }
2123
2124 out:
2125 if (tuning_count) {
2126 /*
2127 * In case tuning fails, host controllers which support
2128 * re-tuning can try tuning again at a later time, when the
2129 * re-tuning timer expires. So for these controllers, we
2130 * return 0. Since there might be other controllers who do not
2131 * have this capability, we return error for them.
2132 */
2133 err = 0;
2134 }
2135
2136 host->mmc->retune_period = err ? 0 : tuning_count;
2137
2138 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2139 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2140 out_unlock:
2141 spin_unlock_irqrestore(&host->lock, flags);
2142 return err;
2143 }
2144
2145 static int sdhci_select_drive_strength(struct mmc_card *card,
2146 unsigned int max_dtr, int host_drv,
2147 int card_drv, int *drv_type)
2148 {
2149 struct sdhci_host *host = mmc_priv(card->host);
2150
2151 if (!host->ops->select_drive_strength)
2152 return 0;
2153
2154 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2155 card_drv, drv_type);
2156 }
2157
2158 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2159 {
2160 /* Host Controller v3.00 defines preset value registers */
2161 if (host->version < SDHCI_SPEC_300)
2162 return;
2163
2164 /*
2165 * We only enable or disable Preset Value if they are not already
2166 * enabled or disabled respectively. Otherwise, we bail out.
2167 */
2168 if (host->preset_enabled != enable) {
2169 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2170
2171 if (enable)
2172 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2173 else
2174 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2175
2176 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2177
2178 if (enable)
2179 host->flags |= SDHCI_PV_ENABLED;
2180 else
2181 host->flags &= ~SDHCI_PV_ENABLED;
2182
2183 host->preset_enabled = enable;
2184 }
2185 }
2186
2187 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2188 int err)
2189 {
2190 struct sdhci_host *host = mmc_priv(mmc);
2191 struct mmc_data *data = mrq->data;
2192
2193 if (data->host_cookie != COOKIE_UNMAPPED)
2194 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2195 data->flags & MMC_DATA_WRITE ?
2196 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2197
2198 data->host_cookie = COOKIE_UNMAPPED;
2199 }
2200
2201 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2202 {
2203 struct sdhci_host *host = mmc_priv(mmc);
2204
2205 mrq->data->host_cookie = COOKIE_UNMAPPED;
2206
2207 if (host->flags & SDHCI_REQ_USE_DMA)
2208 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2209 }
2210
2211 static inline bool sdhci_has_requests(struct sdhci_host *host)
2212 {
2213 return host->cmd || host->data_cmd;
2214 }
2215
2216 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2217 {
2218 if (host->data_cmd) {
2219 host->data_cmd->error = err;
2220 sdhci_finish_mrq(host, host->data_cmd->mrq);
2221 }
2222
2223 if (host->cmd) {
2224 host->cmd->error = err;
2225 sdhci_finish_mrq(host, host->cmd->mrq);
2226 }
2227 }
2228
2229 static void sdhci_card_event(struct mmc_host *mmc)
2230 {
2231 struct sdhci_host *host = mmc_priv(mmc);
2232 unsigned long flags;
2233 int present;
2234
2235 /* First check if client has provided their own card event */
2236 if (host->ops->card_event)
2237 host->ops->card_event(host);
2238
2239 present = mmc->ops->get_cd(mmc);
2240
2241 spin_lock_irqsave(&host->lock, flags);
2242
2243 /* Check sdhci_has_requests() first in case we are runtime suspended */
2244 if (sdhci_has_requests(host) && !present) {
2245 pr_err("%s: Card removed during transfer!\n",
2246 mmc_hostname(host->mmc));
2247 pr_err("%s: Resetting controller.\n",
2248 mmc_hostname(host->mmc));
2249
2250 sdhci_do_reset(host, SDHCI_RESET_CMD);
2251 sdhci_do_reset(host, SDHCI_RESET_DATA);
2252
2253 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2254 }
2255
2256 spin_unlock_irqrestore(&host->lock, flags);
2257 }
2258
2259 static const struct mmc_host_ops sdhci_ops = {
2260 .request = sdhci_request,
2261 .post_req = sdhci_post_req,
2262 .pre_req = sdhci_pre_req,
2263 .set_ios = sdhci_set_ios,
2264 .get_cd = sdhci_get_cd,
2265 .get_ro = sdhci_get_ro,
2266 .hw_reset = sdhci_hw_reset,
2267 .enable_sdio_irq = sdhci_enable_sdio_irq,
2268 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2269 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2270 .execute_tuning = sdhci_execute_tuning,
2271 .select_drive_strength = sdhci_select_drive_strength,
2272 .card_event = sdhci_card_event,
2273 .card_busy = sdhci_card_busy,
2274 };
2275
2276 /*****************************************************************************\
2277 * *
2278 * Tasklets *
2279 * *
2280 \*****************************************************************************/
2281
2282 static bool sdhci_request_done(struct sdhci_host *host)
2283 {
2284 unsigned long flags;
2285 struct mmc_request *mrq;
2286 int i;
2287
2288 spin_lock_irqsave(&host->lock, flags);
2289
2290 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2291 mrq = host->mrqs_done[i];
2292 if (mrq)
2293 break;
2294 }
2295
2296 if (!mrq) {
2297 spin_unlock_irqrestore(&host->lock, flags);
2298 return true;
2299 }
2300
2301 sdhci_del_timer(host, mrq);
2302
2303 /*
2304 * Always unmap the data buffers if they were mapped by
2305 * sdhci_prepare_data() whenever we finish with a request.
2306 * This avoids leaking DMA mappings on error.
2307 */
2308 if (host->flags & SDHCI_REQ_USE_DMA) {
2309 struct mmc_data *data = mrq->data;
2310
2311 if (data && data->host_cookie == COOKIE_MAPPED) {
2312 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2313 (data->flags & MMC_DATA_READ) ?
2314 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2315 data->host_cookie = COOKIE_UNMAPPED;
2316 }
2317 }
2318
2319 /*
2320 * The controller needs a reset of internal state machines
2321 * upon error conditions.
2322 */
2323 if (sdhci_needs_reset(host, mrq)) {
2324 /*
2325 * Do not finish until command and data lines are available for
2326 * reset. Note there can only be one other mrq, so it cannot
2327 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2328 * would both be null.
2329 */
2330 if (host->cmd || host->data_cmd) {
2331 spin_unlock_irqrestore(&host->lock, flags);
2332 return true;
2333 }
2334
2335 /* Some controllers need this kick or reset won't work here */
2336 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2337 /* This is to force an update */
2338 host->ops->set_clock(host, host->clock);
2339
2340 /* Spec says we should do both at the same time, but Ricoh
2341 controllers do not like that. */
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 host->pending_reset = false;
2346 }
2347
2348 if (!sdhci_has_requests(host))
2349 sdhci_led_deactivate(host);
2350
2351 host->mrqs_done[i] = NULL;
2352
2353 mmiowb();
2354 spin_unlock_irqrestore(&host->lock, flags);
2355
2356 mmc_request_done(host->mmc, mrq);
2357
2358 return false;
2359 }
2360
2361 static void sdhci_tasklet_finish(unsigned long param)
2362 {
2363 struct sdhci_host *host = (struct sdhci_host *)param;
2364
2365 while (!sdhci_request_done(host))
2366 ;
2367 }
2368
2369 static void sdhci_timeout_timer(unsigned long data)
2370 {
2371 struct sdhci_host *host;
2372 unsigned long flags;
2373
2374 host = (struct sdhci_host*)data;
2375
2376 spin_lock_irqsave(&host->lock, flags);
2377
2378 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2379 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2380 mmc_hostname(host->mmc));
2381 sdhci_dumpregs(host);
2382
2383 host->cmd->error = -ETIMEDOUT;
2384 sdhci_finish_mrq(host, host->cmd->mrq);
2385 }
2386
2387 mmiowb();
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 }
2390
2391 static void sdhci_timeout_data_timer(unsigned long data)
2392 {
2393 struct sdhci_host *host;
2394 unsigned long flags;
2395
2396 host = (struct sdhci_host *)data;
2397
2398 spin_lock_irqsave(&host->lock, flags);
2399
2400 if (host->data || host->data_cmd ||
2401 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2402 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2403 mmc_hostname(host->mmc));
2404 sdhci_dumpregs(host);
2405
2406 if (host->data) {
2407 host->data->error = -ETIMEDOUT;
2408 sdhci_finish_data(host);
2409 } else if (host->data_cmd) {
2410 host->data_cmd->error = -ETIMEDOUT;
2411 sdhci_finish_mrq(host, host->data_cmd->mrq);
2412 } else {
2413 host->cmd->error = -ETIMEDOUT;
2414 sdhci_finish_mrq(host, host->cmd->mrq);
2415 }
2416 }
2417
2418 mmiowb();
2419 spin_unlock_irqrestore(&host->lock, flags);
2420 }
2421
2422 /*****************************************************************************\
2423 * *
2424 * Interrupt handling *
2425 * *
2426 \*****************************************************************************/
2427
2428 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2429 {
2430 if (!host->cmd) {
2431 /*
2432 * SDHCI recovers from errors by resetting the cmd and data
2433 * circuits. Until that is done, there very well might be more
2434 * interrupts, so ignore them in that case.
2435 */
2436 if (host->pending_reset)
2437 return;
2438 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2439 mmc_hostname(host->mmc), (unsigned)intmask);
2440 sdhci_dumpregs(host);
2441 return;
2442 }
2443
2444 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2445 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2446 if (intmask & SDHCI_INT_TIMEOUT)
2447 host->cmd->error = -ETIMEDOUT;
2448 else
2449 host->cmd->error = -EILSEQ;
2450
2451 /*
2452 * If this command initiates a data phase and a response
2453 * CRC error is signalled, the card can start transferring
2454 * data - the card may have received the command without
2455 * error. We must not terminate the mmc_request early.
2456 *
2457 * If the card did not receive the command or returned an
2458 * error which prevented it sending data, the data phase
2459 * will time out.
2460 */
2461 if (host->cmd->data &&
2462 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2463 SDHCI_INT_CRC) {
2464 host->cmd = NULL;
2465 return;
2466 }
2467
2468 sdhci_finish_mrq(host, host->cmd->mrq);
2469 return;
2470 }
2471
2472 if (intmask & SDHCI_INT_RESPONSE)
2473 sdhci_finish_command(host);
2474 }
2475
2476 #ifdef CONFIG_MMC_DEBUG
2477 static void sdhci_adma_show_error(struct sdhci_host *host)
2478 {
2479 const char *name = mmc_hostname(host->mmc);
2480 void *desc = host->adma_table;
2481
2482 sdhci_dumpregs(host);
2483
2484 while (true) {
2485 struct sdhci_adma2_64_desc *dma_desc = desc;
2486
2487 if (host->flags & SDHCI_USE_64_BIT_DMA)
2488 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2489 name, desc, le32_to_cpu(dma_desc->addr_hi),
2490 le32_to_cpu(dma_desc->addr_lo),
2491 le16_to_cpu(dma_desc->len),
2492 le16_to_cpu(dma_desc->cmd));
2493 else
2494 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2495 name, desc, le32_to_cpu(dma_desc->addr_lo),
2496 le16_to_cpu(dma_desc->len),
2497 le16_to_cpu(dma_desc->cmd));
2498
2499 desc += host->desc_sz;
2500
2501 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2502 break;
2503 }
2504 }
2505 #else
2506 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2507 #endif
2508
2509 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2510 {
2511 u32 command;
2512
2513 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2514 if (intmask & SDHCI_INT_DATA_AVAIL) {
2515 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2516 if (command == MMC_SEND_TUNING_BLOCK ||
2517 command == MMC_SEND_TUNING_BLOCK_HS200) {
2518 host->tuning_done = 1;
2519 wake_up(&host->buf_ready_int);
2520 return;
2521 }
2522 }
2523
2524 if (!host->data) {
2525 struct mmc_command *data_cmd = host->data_cmd;
2526
2527 /*
2528 * The "data complete" interrupt is also used to
2529 * indicate that a busy state has ended. See comment
2530 * above in sdhci_cmd_irq().
2531 */
2532 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2533 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2534 host->data_cmd = NULL;
2535 data_cmd->error = -ETIMEDOUT;
2536 sdhci_finish_mrq(host, data_cmd->mrq);
2537 return;
2538 }
2539 if (intmask & SDHCI_INT_DATA_END) {
2540 host->data_cmd = NULL;
2541 /*
2542 * Some cards handle busy-end interrupt
2543 * before the command completed, so make
2544 * sure we do things in the proper order.
2545 */
2546 if (host->cmd == data_cmd)
2547 return;
2548
2549 sdhci_finish_mrq(host, data_cmd->mrq);
2550 return;
2551 }
2552 }
2553
2554 /*
2555 * SDHCI recovers from errors by resetting the cmd and data
2556 * circuits. Until that is done, there very well might be more
2557 * interrupts, so ignore them in that case.
2558 */
2559 if (host->pending_reset)
2560 return;
2561
2562 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2563 mmc_hostname(host->mmc), (unsigned)intmask);
2564 sdhci_dumpregs(host);
2565
2566 return;
2567 }
2568
2569 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2570 host->data->error = -ETIMEDOUT;
2571 else if (intmask & SDHCI_INT_DATA_END_BIT)
2572 host->data->error = -EILSEQ;
2573 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2574 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2575 != MMC_BUS_TEST_R)
2576 host->data->error = -EILSEQ;
2577 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2578 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2579 sdhci_adma_show_error(host);
2580 host->data->error = -EIO;
2581 if (host->ops->adma_workaround)
2582 host->ops->adma_workaround(host, intmask);
2583 }
2584
2585 if (host->data->error)
2586 sdhci_finish_data(host);
2587 else {
2588 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2589 sdhci_transfer_pio(host);
2590
2591 /*
2592 * We currently don't do anything fancy with DMA
2593 * boundaries, but as we can't disable the feature
2594 * we need to at least restart the transfer.
2595 *
2596 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2597 * should return a valid address to continue from, but as
2598 * some controllers are faulty, don't trust them.
2599 */
2600 if (intmask & SDHCI_INT_DMA_END) {
2601 u32 dmastart, dmanow;
2602 dmastart = sg_dma_address(host->data->sg);
2603 dmanow = dmastart + host->data->bytes_xfered;
2604 /*
2605 * Force update to the next DMA block boundary.
2606 */
2607 dmanow = (dmanow &
2608 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2609 SDHCI_DEFAULT_BOUNDARY_SIZE;
2610 host->data->bytes_xfered = dmanow - dmastart;
2611 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2612 " next 0x%08x\n",
2613 mmc_hostname(host->mmc), dmastart,
2614 host->data->bytes_xfered, dmanow);
2615 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2616 }
2617
2618 if (intmask & SDHCI_INT_DATA_END) {
2619 if (host->cmd == host->data_cmd) {
2620 /*
2621 * Data managed to finish before the
2622 * command completed. Make sure we do
2623 * things in the proper order.
2624 */
2625 host->data_early = 1;
2626 } else {
2627 sdhci_finish_data(host);
2628 }
2629 }
2630 }
2631 }
2632
2633 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2634 {
2635 irqreturn_t result = IRQ_NONE;
2636 struct sdhci_host *host = dev_id;
2637 u32 intmask, mask, unexpected = 0;
2638 int max_loops = 16;
2639
2640 spin_lock(&host->lock);
2641
2642 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2643 spin_unlock(&host->lock);
2644 return IRQ_NONE;
2645 }
2646
2647 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2648 if (!intmask || intmask == 0xffffffff) {
2649 result = IRQ_NONE;
2650 goto out;
2651 }
2652
2653 do {
2654 /* Clear selected interrupts. */
2655 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2656 SDHCI_INT_BUS_POWER);
2657 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2658
2659 DBG("*** %s got interrupt: 0x%08x\n",
2660 mmc_hostname(host->mmc), intmask);
2661
2662 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2663 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2664 SDHCI_CARD_PRESENT;
2665
2666 /*
2667 * There is a observation on i.mx esdhc. INSERT
2668 * bit will be immediately set again when it gets
2669 * cleared, if a card is inserted. We have to mask
2670 * the irq to prevent interrupt storm which will
2671 * freeze the system. And the REMOVE gets the
2672 * same situation.
2673 *
2674 * More testing are needed here to ensure it works
2675 * for other platforms though.
2676 */
2677 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2678 SDHCI_INT_CARD_REMOVE);
2679 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2680 SDHCI_INT_CARD_INSERT;
2681 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2682 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2683
2684 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2685 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2686
2687 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2688 SDHCI_INT_CARD_REMOVE);
2689 result = IRQ_WAKE_THREAD;
2690 }
2691
2692 if (intmask & SDHCI_INT_CMD_MASK)
2693 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2694
2695 if (intmask & SDHCI_INT_DATA_MASK)
2696 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2697
2698 if (intmask & SDHCI_INT_BUS_POWER)
2699 pr_err("%s: Card is consuming too much power!\n",
2700 mmc_hostname(host->mmc));
2701
2702 if (intmask & SDHCI_INT_RETUNE)
2703 mmc_retune_needed(host->mmc);
2704
2705 if (intmask & SDHCI_INT_CARD_INT) {
2706 sdhci_enable_sdio_irq_nolock(host, false);
2707 host->thread_isr |= SDHCI_INT_CARD_INT;
2708 result = IRQ_WAKE_THREAD;
2709 }
2710
2711 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2712 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2713 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2714 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2715
2716 if (intmask) {
2717 unexpected |= intmask;
2718 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2719 }
2720
2721 if (result == IRQ_NONE)
2722 result = IRQ_HANDLED;
2723
2724 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2725 } while (intmask && --max_loops);
2726 out:
2727 spin_unlock(&host->lock);
2728
2729 if (unexpected) {
2730 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2731 mmc_hostname(host->mmc), unexpected);
2732 sdhci_dumpregs(host);
2733 }
2734
2735 return result;
2736 }
2737
2738 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2739 {
2740 struct sdhci_host *host = dev_id;
2741 unsigned long flags;
2742 u32 isr;
2743
2744 spin_lock_irqsave(&host->lock, flags);
2745 isr = host->thread_isr;
2746 host->thread_isr = 0;
2747 spin_unlock_irqrestore(&host->lock, flags);
2748
2749 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2750 struct mmc_host *mmc = host->mmc;
2751
2752 mmc->ops->card_event(mmc);
2753 mmc_detect_change(mmc, msecs_to_jiffies(200));
2754 }
2755
2756 if (isr & SDHCI_INT_CARD_INT) {
2757 sdio_run_irqs(host->mmc);
2758
2759 spin_lock_irqsave(&host->lock, flags);
2760 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2761 sdhci_enable_sdio_irq_nolock(host, true);
2762 spin_unlock_irqrestore(&host->lock, flags);
2763 }
2764
2765 return isr ? IRQ_HANDLED : IRQ_NONE;
2766 }
2767
2768 /*****************************************************************************\
2769 * *
2770 * Suspend/resume *
2771 * *
2772 \*****************************************************************************/
2773
2774 #ifdef CONFIG_PM
2775 /*
2776 * To enable wakeup events, the corresponding events have to be enabled in
2777 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2778 * Table' in the SD Host Controller Standard Specification.
2779 * It is useless to restore SDHCI_INT_ENABLE state in
2780 * sdhci_disable_irq_wakeups() since it will be set by
2781 * sdhci_enable_card_detection() or sdhci_init().
2782 */
2783 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2784 {
2785 u8 val;
2786 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2787 | SDHCI_WAKE_ON_INT;
2788 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2789 SDHCI_INT_CARD_INT;
2790
2791 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2792 val |= mask ;
2793 /* Avoid fake wake up */
2794 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2795 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2796 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2797 }
2798 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2799 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2800 }
2801 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2802
2803 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2804 {
2805 u8 val;
2806 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2807 | SDHCI_WAKE_ON_INT;
2808
2809 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2810 val &= ~mask;
2811 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2812 }
2813
2814 int sdhci_suspend_host(struct sdhci_host *host)
2815 {
2816 sdhci_disable_card_detection(host);
2817
2818 mmc_retune_timer_stop(host->mmc);
2819 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2820 mmc_retune_needed(host->mmc);
2821
2822 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2823 host->ier = 0;
2824 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2825 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2826 free_irq(host->irq, host);
2827 } else {
2828 sdhci_enable_irq_wakeups(host);
2829 enable_irq_wake(host->irq);
2830 }
2831 return 0;
2832 }
2833
2834 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2835
2836 int sdhci_resume_host(struct sdhci_host *host)
2837 {
2838 struct mmc_host *mmc = host->mmc;
2839 int ret = 0;
2840
2841 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2842 if (host->ops->enable_dma)
2843 host->ops->enable_dma(host);
2844 }
2845
2846 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2847 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2848 /* Card keeps power but host controller does not */
2849 sdhci_init(host, 0);
2850 host->pwr = 0;
2851 host->clock = 0;
2852 mmc->ops->set_ios(mmc, &mmc->ios);
2853 } else {
2854 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2855 mmiowb();
2856 }
2857
2858 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2859 ret = request_threaded_irq(host->irq, sdhci_irq,
2860 sdhci_thread_irq, IRQF_SHARED,
2861 mmc_hostname(host->mmc), host);
2862 if (ret)
2863 return ret;
2864 } else {
2865 sdhci_disable_irq_wakeups(host);
2866 disable_irq_wake(host->irq);
2867 }
2868
2869 sdhci_enable_card_detection(host);
2870
2871 return ret;
2872 }
2873
2874 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2875
2876 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2877 {
2878 unsigned long flags;
2879
2880 mmc_retune_timer_stop(host->mmc);
2881 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2882 mmc_retune_needed(host->mmc);
2883
2884 spin_lock_irqsave(&host->lock, flags);
2885 host->ier &= SDHCI_INT_CARD_INT;
2886 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2887 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2888 spin_unlock_irqrestore(&host->lock, flags);
2889
2890 synchronize_hardirq(host->irq);
2891
2892 spin_lock_irqsave(&host->lock, flags);
2893 host->runtime_suspended = true;
2894 spin_unlock_irqrestore(&host->lock, flags);
2895
2896 return 0;
2897 }
2898 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2899
2900 int sdhci_runtime_resume_host(struct sdhci_host *host)
2901 {
2902 struct mmc_host *mmc = host->mmc;
2903 unsigned long flags;
2904 int host_flags = host->flags;
2905
2906 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2907 if (host->ops->enable_dma)
2908 host->ops->enable_dma(host);
2909 }
2910
2911 sdhci_init(host, 0);
2912
2913 /* Force clock and power re-program */
2914 host->pwr = 0;
2915 host->clock = 0;
2916 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2917 mmc->ops->set_ios(mmc, &mmc->ios);
2918
2919 if ((host_flags & SDHCI_PV_ENABLED) &&
2920 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2921 spin_lock_irqsave(&host->lock, flags);
2922 sdhci_enable_preset_value(host, true);
2923 spin_unlock_irqrestore(&host->lock, flags);
2924 }
2925
2926 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2927 mmc->ops->hs400_enhanced_strobe)
2928 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2929
2930 spin_lock_irqsave(&host->lock, flags);
2931
2932 host->runtime_suspended = false;
2933
2934 /* Enable SDIO IRQ */
2935 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2936 sdhci_enable_sdio_irq_nolock(host, true);
2937
2938 /* Enable Card Detection */
2939 sdhci_enable_card_detection(host);
2940
2941 spin_unlock_irqrestore(&host->lock, flags);
2942
2943 return 0;
2944 }
2945 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2946
2947 #endif /* CONFIG_PM */
2948
2949 /*****************************************************************************\
2950 * *
2951 * Device allocation/registration *
2952 * *
2953 \*****************************************************************************/
2954
2955 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2956 size_t priv_size)
2957 {
2958 struct mmc_host *mmc;
2959 struct sdhci_host *host;
2960
2961 WARN_ON(dev == NULL);
2962
2963 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2964 if (!mmc)
2965 return ERR_PTR(-ENOMEM);
2966
2967 host = mmc_priv(mmc);
2968 host->mmc = mmc;
2969 host->mmc_host_ops = sdhci_ops;
2970 mmc->ops = &host->mmc_host_ops;
2971
2972 host->flags = SDHCI_SIGNALING_330;
2973
2974 return host;
2975 }
2976
2977 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2978
2979 static int sdhci_set_dma_mask(struct sdhci_host *host)
2980 {
2981 struct mmc_host *mmc = host->mmc;
2982 struct device *dev = mmc_dev(mmc);
2983 int ret = -EINVAL;
2984
2985 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2986 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2987
2988 /* Try 64-bit mask if hardware is capable of it */
2989 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2990 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2991 if (ret) {
2992 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2993 mmc_hostname(mmc));
2994 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2995 }
2996 }
2997
2998 /* 32-bit mask as default & fallback */
2999 if (ret) {
3000 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3001 if (ret)
3002 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3003 mmc_hostname(mmc));
3004 }
3005
3006 return ret;
3007 }
3008
3009 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3010 {
3011 u16 v;
3012 u64 dt_caps_mask = 0;
3013 u64 dt_caps = 0;
3014
3015 if (host->read_caps)
3016 return;
3017
3018 host->read_caps = true;
3019
3020 if (debug_quirks)
3021 host->quirks = debug_quirks;
3022
3023 if (debug_quirks2)
3024 host->quirks2 = debug_quirks2;
3025
3026 sdhci_do_reset(host, SDHCI_RESET_ALL);
3027
3028 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3029 "sdhci-caps-mask", &dt_caps_mask);
3030 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3031 "sdhci-caps", &dt_caps);
3032
3033 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3034 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3035
3036 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3037 return;
3038
3039 if (caps) {
3040 host->caps = *caps;
3041 } else {
3042 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3043 host->caps &= ~lower_32_bits(dt_caps_mask);
3044 host->caps |= lower_32_bits(dt_caps);
3045 }
3046
3047 if (host->version < SDHCI_SPEC_300)
3048 return;
3049
3050 if (caps1) {
3051 host->caps1 = *caps1;
3052 } else {
3053 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3054 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3055 host->caps1 |= upper_32_bits(dt_caps);
3056 }
3057 }
3058 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3059
3060 int sdhci_setup_host(struct sdhci_host *host)
3061 {
3062 struct mmc_host *mmc;
3063 u32 max_current_caps;
3064 unsigned int ocr_avail;
3065 unsigned int override_timeout_clk;
3066 u32 max_clk;
3067 int ret;
3068
3069 WARN_ON(host == NULL);
3070 if (host == NULL)
3071 return -EINVAL;
3072
3073 mmc = host->mmc;
3074
3075 /*
3076 * If there are external regulators, get them. Note this must be done
3077 * early before resetting the host and reading the capabilities so that
3078 * the host can take the appropriate action if regulators are not
3079 * available.
3080 */
3081 ret = mmc_regulator_get_supply(mmc);
3082 if (ret == -EPROBE_DEFER)
3083 return ret;
3084
3085 sdhci_read_caps(host);
3086
3087 override_timeout_clk = host->timeout_clk;
3088
3089 if (host->version > SDHCI_SPEC_300) {
3090 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3091 mmc_hostname(mmc), host->version);
3092 }
3093
3094 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3095 host->flags |= SDHCI_USE_SDMA;
3096 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3097 DBG("Controller doesn't have SDMA capability\n");
3098 else
3099 host->flags |= SDHCI_USE_SDMA;
3100
3101 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3102 (host->flags & SDHCI_USE_SDMA)) {
3103 DBG("Disabling DMA as it is marked broken\n");
3104 host->flags &= ~SDHCI_USE_SDMA;
3105 }
3106
3107 if ((host->version >= SDHCI_SPEC_200) &&
3108 (host->caps & SDHCI_CAN_DO_ADMA2))
3109 host->flags |= SDHCI_USE_ADMA;
3110
3111 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3112 (host->flags & SDHCI_USE_ADMA)) {
3113 DBG("Disabling ADMA as it is marked broken\n");
3114 host->flags &= ~SDHCI_USE_ADMA;
3115 }
3116
3117 /*
3118 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3119 * and *must* do 64-bit DMA. A driver has the opportunity to change
3120 * that during the first call to ->enable_dma(). Similarly
3121 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3122 * implement.
3123 */
3124 if (host->caps & SDHCI_CAN_64BIT)
3125 host->flags |= SDHCI_USE_64_BIT_DMA;
3126
3127 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3128 ret = sdhci_set_dma_mask(host);
3129
3130 if (!ret && host->ops->enable_dma)
3131 ret = host->ops->enable_dma(host);
3132
3133 if (ret) {
3134 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3135 mmc_hostname(mmc));
3136 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3137
3138 ret = 0;
3139 }
3140 }
3141
3142 /* SDMA does not support 64-bit DMA */
3143 if (host->flags & SDHCI_USE_64_BIT_DMA)
3144 host->flags &= ~SDHCI_USE_SDMA;
3145
3146 if (host->flags & SDHCI_USE_ADMA) {
3147 dma_addr_t dma;
3148 void *buf;
3149
3150 /*
3151 * The DMA descriptor table size is calculated as the maximum
3152 * number of segments times 2, to allow for an alignment
3153 * descriptor for each segment, plus 1 for a nop end descriptor,
3154 * all multipled by the descriptor size.
3155 */
3156 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3157 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3158 SDHCI_ADMA2_64_DESC_SZ;
3159 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3160 } else {
3161 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3162 SDHCI_ADMA2_32_DESC_SZ;
3163 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3164 }
3165
3166 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3167 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3168 host->adma_table_sz, &dma, GFP_KERNEL);
3169 if (!buf) {
3170 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3171 mmc_hostname(mmc));
3172 host->flags &= ~SDHCI_USE_ADMA;
3173 } else if ((dma + host->align_buffer_sz) &
3174 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3175 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3176 mmc_hostname(mmc));
3177 host->flags &= ~SDHCI_USE_ADMA;
3178 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3179 host->adma_table_sz, buf, dma);
3180 } else {
3181 host->align_buffer = buf;
3182 host->align_addr = dma;
3183
3184 host->adma_table = buf + host->align_buffer_sz;
3185 host->adma_addr = dma + host->align_buffer_sz;
3186 }
3187 }
3188
3189 /*
3190 * If we use DMA, then it's up to the caller to set the DMA
3191 * mask, but PIO does not need the hw shim so we set a new
3192 * mask here in that case.
3193 */
3194 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3195 host->dma_mask = DMA_BIT_MASK(64);
3196 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3197 }
3198
3199 if (host->version >= SDHCI_SPEC_300)
3200 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3201 >> SDHCI_CLOCK_BASE_SHIFT;
3202 else
3203 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3204 >> SDHCI_CLOCK_BASE_SHIFT;
3205
3206 host->max_clk *= 1000000;
3207 if (host->max_clk == 0 || host->quirks &
3208 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3209 if (!host->ops->get_max_clock) {
3210 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3211 mmc_hostname(mmc));
3212 ret = -ENODEV;
3213 goto undma;
3214 }
3215 host->max_clk = host->ops->get_max_clock(host);
3216 }
3217
3218 /*
3219 * In case of Host Controller v3.00, find out whether clock
3220 * multiplier is supported.
3221 */
3222 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3223 SDHCI_CLOCK_MUL_SHIFT;
3224
3225 /*
3226 * In case the value in Clock Multiplier is 0, then programmable
3227 * clock mode is not supported, otherwise the actual clock
3228 * multiplier is one more than the value of Clock Multiplier
3229 * in the Capabilities Register.
3230 */
3231 if (host->clk_mul)
3232 host->clk_mul += 1;
3233
3234 /*
3235 * Set host parameters.
3236 */
3237 max_clk = host->max_clk;
3238
3239 if (host->ops->get_min_clock)
3240 mmc->f_min = host->ops->get_min_clock(host);
3241 else if (host->version >= SDHCI_SPEC_300) {
3242 if (host->clk_mul) {
3243 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3244 max_clk = host->max_clk * host->clk_mul;
3245 } else
3246 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3247 } else
3248 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3249
3250 if (!mmc->f_max || mmc->f_max > max_clk)
3251 mmc->f_max = max_clk;
3252
3253 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3254 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3255 SDHCI_TIMEOUT_CLK_SHIFT;
3256 if (host->timeout_clk == 0) {
3257 if (host->ops->get_timeout_clock) {
3258 host->timeout_clk =
3259 host->ops->get_timeout_clock(host);
3260 } else {
3261 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3262 mmc_hostname(mmc));
3263 ret = -ENODEV;
3264 goto undma;
3265 }
3266 }
3267
3268 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3269 host->timeout_clk *= 1000;
3270
3271 if (override_timeout_clk)
3272 host->timeout_clk = override_timeout_clk;
3273
3274 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3275 host->ops->get_max_timeout_count(host) : 1 << 27;
3276 mmc->max_busy_timeout /= host->timeout_clk;
3277 }
3278
3279 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3280 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3281
3282 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3283 host->flags |= SDHCI_AUTO_CMD12;
3284
3285 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3286 if ((host->version >= SDHCI_SPEC_300) &&
3287 ((host->flags & SDHCI_USE_ADMA) ||
3288 !(host->flags & SDHCI_USE_SDMA)) &&
3289 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3290 host->flags |= SDHCI_AUTO_CMD23;
3291 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3292 } else {
3293 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3294 }
3295
3296 /*
3297 * A controller may support 8-bit width, but the board itself
3298 * might not have the pins brought out. Boards that support
3299 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3300 * their platform code before calling sdhci_add_host(), and we
3301 * won't assume 8-bit width for hosts without that CAP.
3302 */
3303 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3304 mmc->caps |= MMC_CAP_4_BIT_DATA;
3305
3306 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3307 mmc->caps &= ~MMC_CAP_CMD23;
3308
3309 if (host->caps & SDHCI_CAN_DO_HISPD)
3310 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3311
3312 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3313 mmc_card_is_removable(mmc) &&
3314 mmc_gpio_get_cd(host->mmc) < 0)
3315 mmc->caps |= MMC_CAP_NEEDS_POLL;
3316
3317 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3318 if (!IS_ERR(mmc->supply.vqmmc)) {
3319 ret = regulator_enable(mmc->supply.vqmmc);
3320 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3321 1950000))
3322 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3323 SDHCI_SUPPORT_SDR50 |
3324 SDHCI_SUPPORT_DDR50);
3325 if (ret) {
3326 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3327 mmc_hostname(mmc), ret);
3328 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3329 }
3330 }
3331
3332 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3333 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3334 SDHCI_SUPPORT_DDR50);
3335 }
3336
3337 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3338 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3339 SDHCI_SUPPORT_DDR50))
3340 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3341
3342 /* SDR104 supports also implies SDR50 support */
3343 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3344 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3345 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3346 * field can be promoted to support HS200.
3347 */
3348 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3349 mmc->caps2 |= MMC_CAP2_HS200;
3350 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3351 mmc->caps |= MMC_CAP_UHS_SDR50;
3352 }
3353
3354 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3355 (host->caps1 & SDHCI_SUPPORT_HS400))
3356 mmc->caps2 |= MMC_CAP2_HS400;
3357
3358 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3359 (IS_ERR(mmc->supply.vqmmc) ||
3360 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3361 1300000)))
3362 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3363
3364 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3365 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3366 mmc->caps |= MMC_CAP_UHS_DDR50;
3367
3368 /* Does the host need tuning for SDR50? */
3369 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3370 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3371
3372 /* Driver Type(s) (A, C, D) supported by the host */
3373 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3374 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3375 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3376 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3377 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3378 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3379
3380 /* Initial value for re-tuning timer count */
3381 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3382 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3383
3384 /*
3385 * In case Re-tuning Timer is not disabled, the actual value of
3386 * re-tuning timer will be 2 ^ (n - 1).
3387 */
3388 if (host->tuning_count)
3389 host->tuning_count = 1 << (host->tuning_count - 1);
3390
3391 /* Re-tuning mode supported by the Host Controller */
3392 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3393 SDHCI_RETUNING_MODE_SHIFT;
3394
3395 ocr_avail = 0;
3396
3397 /*
3398 * According to SD Host Controller spec v3.00, if the Host System
3399 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3400 * the value is meaningful only if Voltage Support in the Capabilities
3401 * register is set. The actual current value is 4 times the register
3402 * value.
3403 */
3404 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3405 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3406 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3407 if (curr > 0) {
3408
3409 /* convert to SDHCI_MAX_CURRENT format */
3410 curr = curr/1000; /* convert to mA */
3411 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3412
3413 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3414 max_current_caps =
3415 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3416 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3417 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3418 }
3419 }
3420
3421 if (host->caps & SDHCI_CAN_VDD_330) {
3422 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3423
3424 mmc->max_current_330 = ((max_current_caps &
3425 SDHCI_MAX_CURRENT_330_MASK) >>
3426 SDHCI_MAX_CURRENT_330_SHIFT) *
3427 SDHCI_MAX_CURRENT_MULTIPLIER;
3428 }
3429 if (host->caps & SDHCI_CAN_VDD_300) {
3430 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3431
3432 mmc->max_current_300 = ((max_current_caps &
3433 SDHCI_MAX_CURRENT_300_MASK) >>
3434 SDHCI_MAX_CURRENT_300_SHIFT) *
3435 SDHCI_MAX_CURRENT_MULTIPLIER;
3436 }
3437 if (host->caps & SDHCI_CAN_VDD_180) {
3438 ocr_avail |= MMC_VDD_165_195;
3439
3440 mmc->max_current_180 = ((max_current_caps &
3441 SDHCI_MAX_CURRENT_180_MASK) >>
3442 SDHCI_MAX_CURRENT_180_SHIFT) *
3443 SDHCI_MAX_CURRENT_MULTIPLIER;
3444 }
3445
3446 /* If OCR set by host, use it instead. */
3447 if (host->ocr_mask)
3448 ocr_avail = host->ocr_mask;
3449
3450 /* If OCR set by external regulators, give it highest prio. */
3451 if (mmc->ocr_avail)
3452 ocr_avail = mmc->ocr_avail;
3453
3454 mmc->ocr_avail = ocr_avail;
3455 mmc->ocr_avail_sdio = ocr_avail;
3456 if (host->ocr_avail_sdio)
3457 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3458 mmc->ocr_avail_sd = ocr_avail;
3459 if (host->ocr_avail_sd)
3460 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3461 else /* normal SD controllers don't support 1.8V */
3462 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3463 mmc->ocr_avail_mmc = ocr_avail;
3464 if (host->ocr_avail_mmc)
3465 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3466
3467 if (mmc->ocr_avail == 0) {
3468 pr_err("%s: Hardware doesn't report any support voltages.\n",
3469 mmc_hostname(mmc));
3470 ret = -ENODEV;
3471 goto unreg;
3472 }
3473
3474 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3475 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3476 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3477 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3478 host->flags |= SDHCI_SIGNALING_180;
3479
3480 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3481 host->flags |= SDHCI_SIGNALING_120;
3482
3483 spin_lock_init(&host->lock);
3484
3485 /*
3486 * Maximum number of segments. Depends on if the hardware
3487 * can do scatter/gather or not.
3488 */
3489 if (host->flags & SDHCI_USE_ADMA)
3490 mmc->max_segs = SDHCI_MAX_SEGS;
3491 else if (host->flags & SDHCI_USE_SDMA)
3492 mmc->max_segs = 1;
3493 else /* PIO */
3494 mmc->max_segs = SDHCI_MAX_SEGS;
3495
3496 /*
3497 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3498 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3499 * is less anyway.
3500 */
3501 mmc->max_req_size = 524288;
3502
3503 /*
3504 * Maximum segment size. Could be one segment with the maximum number
3505 * of bytes. When doing hardware scatter/gather, each entry cannot
3506 * be larger than 64 KiB though.
3507 */
3508 if (host->flags & SDHCI_USE_ADMA) {
3509 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3510 mmc->max_seg_size = 65535;
3511 else
3512 mmc->max_seg_size = 65536;
3513 } else {
3514 mmc->max_seg_size = mmc->max_req_size;
3515 }
3516
3517 /*
3518 * Maximum block size. This varies from controller to controller and
3519 * is specified in the capabilities register.
3520 */
3521 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3522 mmc->max_blk_size = 2;
3523 } else {
3524 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3525 SDHCI_MAX_BLOCK_SHIFT;
3526 if (mmc->max_blk_size >= 3) {
3527 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3528 mmc_hostname(mmc));
3529 mmc->max_blk_size = 0;
3530 }
3531 }
3532
3533 mmc->max_blk_size = 512 << mmc->max_blk_size;
3534
3535 /*
3536 * Maximum block count.
3537 */
3538 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3539
3540 return 0;
3541
3542 unreg:
3543 if (!IS_ERR(mmc->supply.vqmmc))
3544 regulator_disable(mmc->supply.vqmmc);
3545 undma:
3546 if (host->align_buffer)
3547 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3548 host->adma_table_sz, host->align_buffer,
3549 host->align_addr);
3550 host->adma_table = NULL;
3551 host->align_buffer = NULL;
3552
3553 return ret;
3554 }
3555 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3556
3557 int __sdhci_add_host(struct sdhci_host *host)
3558 {
3559 struct mmc_host *mmc = host->mmc;
3560 int ret;
3561
3562 /*
3563 * Init tasklets.
3564 */
3565 tasklet_init(&host->finish_tasklet,
3566 sdhci_tasklet_finish, (unsigned long)host);
3567
3568 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3569 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3570 (unsigned long)host);
3571
3572 init_waitqueue_head(&host->buf_ready_int);
3573
3574 sdhci_init(host, 0);
3575
3576 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3577 IRQF_SHARED, mmc_hostname(mmc), host);
3578 if (ret) {
3579 pr_err("%s: Failed to request IRQ %d: %d\n",
3580 mmc_hostname(mmc), host->irq, ret);
3581 goto untasklet;
3582 }
3583
3584 #ifdef CONFIG_MMC_DEBUG
3585 sdhci_dumpregs(host);
3586 #endif
3587
3588 ret = sdhci_led_register(host);
3589 if (ret) {
3590 pr_err("%s: Failed to register LED device: %d\n",
3591 mmc_hostname(mmc), ret);
3592 goto unirq;
3593 }
3594
3595 mmiowb();
3596
3597 ret = mmc_add_host(mmc);
3598 if (ret)
3599 goto unled;
3600
3601 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3602 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3603 (host->flags & SDHCI_USE_ADMA) ?
3604 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3605 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3606
3607 sdhci_enable_card_detection(host);
3608
3609 return 0;
3610
3611 unled:
3612 sdhci_led_unregister(host);
3613 unirq:
3614 sdhci_do_reset(host, SDHCI_RESET_ALL);
3615 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3616 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3617 free_irq(host->irq, host);
3618 untasklet:
3619 tasklet_kill(&host->finish_tasklet);
3620
3621 if (!IS_ERR(mmc->supply.vqmmc))
3622 regulator_disable(mmc->supply.vqmmc);
3623
3624 if (host->align_buffer)
3625 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3626 host->adma_table_sz, host->align_buffer,
3627 host->align_addr);
3628 host->adma_table = NULL;
3629 host->align_buffer = NULL;
3630
3631 return ret;
3632 }
3633 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3634
3635 int sdhci_add_host(struct sdhci_host *host)
3636 {
3637 int ret;
3638
3639 ret = sdhci_setup_host(host);
3640 if (ret)
3641 return ret;
3642
3643 return __sdhci_add_host(host);
3644 }
3645 EXPORT_SYMBOL_GPL(sdhci_add_host);
3646
3647 void sdhci_remove_host(struct sdhci_host *host, int dead)
3648 {
3649 struct mmc_host *mmc = host->mmc;
3650 unsigned long flags;
3651
3652 if (dead) {
3653 spin_lock_irqsave(&host->lock, flags);
3654
3655 host->flags |= SDHCI_DEVICE_DEAD;
3656
3657 if (sdhci_has_requests(host)) {
3658 pr_err("%s: Controller removed during "
3659 " transfer!\n", mmc_hostname(mmc));
3660 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3661 }
3662
3663 spin_unlock_irqrestore(&host->lock, flags);
3664 }
3665
3666 sdhci_disable_card_detection(host);
3667
3668 mmc_remove_host(mmc);
3669
3670 sdhci_led_unregister(host);
3671
3672 if (!dead)
3673 sdhci_do_reset(host, SDHCI_RESET_ALL);
3674
3675 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3676 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3677 free_irq(host->irq, host);
3678
3679 del_timer_sync(&host->timer);
3680 del_timer_sync(&host->data_timer);
3681
3682 tasklet_kill(&host->finish_tasklet);
3683
3684 if (!IS_ERR(mmc->supply.vqmmc))
3685 regulator_disable(mmc->supply.vqmmc);
3686
3687 if (host->align_buffer)
3688 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3689 host->adma_table_sz, host->align_buffer,
3690 host->align_addr);
3691
3692 host->adma_table = NULL;
3693 host->align_buffer = NULL;
3694 }
3695
3696 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3697
3698 void sdhci_free_host(struct sdhci_host *host)
3699 {
3700 mmc_free_host(host->mmc);
3701 }
3702
3703 EXPORT_SYMBOL_GPL(sdhci_free_host);
3704
3705 /*****************************************************************************\
3706 * *
3707 * Driver init/exit *
3708 * *
3709 \*****************************************************************************/
3710
3711 static int __init sdhci_drv_init(void)
3712 {
3713 pr_info(DRIVER_NAME
3714 ": Secure Digital Host Controller Interface driver\n");
3715 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3716
3717 return 0;
3718 }
3719
3720 static void __exit sdhci_drv_exit(void)
3721 {
3722 }
3723
3724 module_init(sdhci_drv_init);
3725 module_exit(sdhci_drv_exit);
3726
3727 module_param(debug_quirks, uint, 0444);
3728 module_param(debug_quirks2, uint, 0444);
3729
3730 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3731 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3732 MODULE_LICENSE("GPL");
3733
3734 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3735 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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