2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/ktime.h>
18 #include <linux/highmem.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/swiotlb.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/pm_runtime.h>
29 #include <linux/leds.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/slot-gpio.h>
39 #define DRIVER_NAME "sdhci"
41 #define DBG(f, x...) \
42 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44 #define SDHCI_DUMP(f, x...) \
45 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47 #define MAX_TUNING_LOOP 40
49 static unsigned int debug_quirks
= 0;
50 static unsigned int debug_quirks2
;
52 static void sdhci_finish_data(struct sdhci_host
*);
54 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
);
56 void sdhci_dumpregs(struct sdhci_host
*host
)
58 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
61 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
62 sdhci_readw(host
, SDHCI_HOST_VERSION
));
63 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
64 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
65 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
66 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
67 sdhci_readl(host
, SDHCI_ARGUMENT
),
68 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
69 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
70 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
71 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
72 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
73 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
74 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
75 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
76 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
77 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
78 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
79 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
80 sdhci_readl(host
, SDHCI_INT_STATUS
));
81 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
82 sdhci_readl(host
, SDHCI_INT_ENABLE
),
83 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
84 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
85 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
86 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
87 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
88 sdhci_readl(host
, SDHCI_CAPABILITIES
),
89 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
90 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
91 sdhci_readw(host
, SDHCI_COMMAND
),
92 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
93 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
94 sdhci_readl(host
, SDHCI_RESPONSE
),
95 sdhci_readl(host
, SDHCI_RESPONSE
+ 4));
96 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
97 sdhci_readl(host
, SDHCI_RESPONSE
+ 8),
98 sdhci_readl(host
, SDHCI_RESPONSE
+ 12));
99 SDHCI_DUMP("Host ctl2: 0x%08x\n",
100 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
102 if (host
->flags
& SDHCI_USE_ADMA
) {
103 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
104 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
105 sdhci_readl(host
, SDHCI_ADMA_ERROR
),
106 sdhci_readl(host
, SDHCI_ADMA_ADDRESS_HI
),
107 sdhci_readl(host
, SDHCI_ADMA_ADDRESS
));
109 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
110 sdhci_readl(host
, SDHCI_ADMA_ERROR
),
111 sdhci_readl(host
, SDHCI_ADMA_ADDRESS
));
115 SDHCI_DUMP("============================================\n");
117 EXPORT_SYMBOL_GPL(sdhci_dumpregs
);
119 /*****************************************************************************\
121 * Low level functions *
123 \*****************************************************************************/
125 static inline bool sdhci_data_line_cmd(struct mmc_command
*cmd
)
127 return cmd
->data
|| cmd
->flags
& MMC_RSP_BUSY
;
130 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
134 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
135 !mmc_card_is_removable(host
->mmc
))
139 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
142 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
143 SDHCI_INT_CARD_INSERT
;
145 host
->ier
&= ~(SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
);
148 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
149 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
152 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
154 sdhci_set_card_detection(host
, true);
157 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
159 sdhci_set_card_detection(host
, false);
162 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
167 pm_runtime_get_noresume(host
->mmc
->parent
);
170 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
174 host
->bus_on
= false;
175 pm_runtime_put_noidle(host
->mmc
->parent
);
178 void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
182 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
184 if (mask
& SDHCI_RESET_ALL
) {
186 /* Reset-all turns off SD Bus Power */
187 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
188 sdhci_runtime_pm_bus_off(host
);
191 /* Wait max 100 ms */
192 timeout
= ktime_add_ms(ktime_get(), 100);
194 /* hw clears the bit when it's done */
195 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
196 if (ktime_after(ktime_get(), timeout
)) {
197 pr_err("%s: Reset 0x%x never completed.\n",
198 mmc_hostname(host
->mmc
), (int)mask
);
199 sdhci_dumpregs(host
);
205 EXPORT_SYMBOL_GPL(sdhci_reset
);
207 static void sdhci_do_reset(struct sdhci_host
*host
, u8 mask
)
209 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
210 struct mmc_host
*mmc
= host
->mmc
;
212 if (!mmc
->ops
->get_cd(mmc
))
216 host
->ops
->reset(host
, mask
);
218 if (mask
& SDHCI_RESET_ALL
) {
219 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
220 if (host
->ops
->enable_dma
)
221 host
->ops
->enable_dma(host
);
224 /* Resetting the controller clears many */
225 host
->preset_enabled
= false;
229 static void sdhci_set_default_irqs(struct sdhci_host
*host
)
231 host
->ier
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
232 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
|
233 SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
|
234 SDHCI_INT_TIMEOUT
| SDHCI_INT_DATA_END
|
237 if (host
->tuning_mode
== SDHCI_TUNING_MODE_2
||
238 host
->tuning_mode
== SDHCI_TUNING_MODE_3
)
239 host
->ier
|= SDHCI_INT_RETUNE
;
241 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
242 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
245 static void sdhci_init(struct sdhci_host
*host
, int soft
)
247 struct mmc_host
*mmc
= host
->mmc
;
250 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
252 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
254 sdhci_set_default_irqs(host
);
256 host
->cqe_on
= false;
259 /* force clock reconfiguration */
261 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
265 static void sdhci_reinit(struct sdhci_host
*host
)
268 sdhci_enable_card_detection(host
);
271 static void __sdhci_led_activate(struct sdhci_host
*host
)
275 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
276 ctrl
|= SDHCI_CTRL_LED
;
277 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
280 static void __sdhci_led_deactivate(struct sdhci_host
*host
)
284 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
285 ctrl
&= ~SDHCI_CTRL_LED
;
286 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
289 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
290 static void sdhci_led_control(struct led_classdev
*led
,
291 enum led_brightness brightness
)
293 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
296 spin_lock_irqsave(&host
->lock
, flags
);
298 if (host
->runtime_suspended
)
301 if (brightness
== LED_OFF
)
302 __sdhci_led_deactivate(host
);
304 __sdhci_led_activate(host
);
306 spin_unlock_irqrestore(&host
->lock
, flags
);
309 static int sdhci_led_register(struct sdhci_host
*host
)
311 struct mmc_host
*mmc
= host
->mmc
;
313 snprintf(host
->led_name
, sizeof(host
->led_name
),
314 "%s::", mmc_hostname(mmc
));
316 host
->led
.name
= host
->led_name
;
317 host
->led
.brightness
= LED_OFF
;
318 host
->led
.default_trigger
= mmc_hostname(mmc
);
319 host
->led
.brightness_set
= sdhci_led_control
;
321 return led_classdev_register(mmc_dev(mmc
), &host
->led
);
324 static void sdhci_led_unregister(struct sdhci_host
*host
)
326 led_classdev_unregister(&host
->led
);
329 static inline void sdhci_led_activate(struct sdhci_host
*host
)
333 static inline void sdhci_led_deactivate(struct sdhci_host
*host
)
339 static inline int sdhci_led_register(struct sdhci_host
*host
)
344 static inline void sdhci_led_unregister(struct sdhci_host
*host
)
348 static inline void sdhci_led_activate(struct sdhci_host
*host
)
350 __sdhci_led_activate(host
);
353 static inline void sdhci_led_deactivate(struct sdhci_host
*host
)
355 __sdhci_led_deactivate(host
);
360 /*****************************************************************************\
364 \*****************************************************************************/
366 static void sdhci_read_block_pio(struct sdhci_host
*host
)
369 size_t blksize
, len
, chunk
;
370 u32
uninitialized_var(scratch
);
373 DBG("PIO reading\n");
375 blksize
= host
->data
->blksz
;
378 local_irq_save(flags
);
381 BUG_ON(!sg_miter_next(&host
->sg_miter
));
383 len
= min(host
->sg_miter
.length
, blksize
);
386 host
->sg_miter
.consumed
= len
;
388 buf
= host
->sg_miter
.addr
;
392 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
396 *buf
= scratch
& 0xFF;
405 sg_miter_stop(&host
->sg_miter
);
407 local_irq_restore(flags
);
410 static void sdhci_write_block_pio(struct sdhci_host
*host
)
413 size_t blksize
, len
, chunk
;
417 DBG("PIO writing\n");
419 blksize
= host
->data
->blksz
;
423 local_irq_save(flags
);
426 BUG_ON(!sg_miter_next(&host
->sg_miter
));
428 len
= min(host
->sg_miter
.length
, blksize
);
431 host
->sg_miter
.consumed
= len
;
433 buf
= host
->sg_miter
.addr
;
436 scratch
|= (u32
)*buf
<< (chunk
* 8);
442 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
443 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
450 sg_miter_stop(&host
->sg_miter
);
452 local_irq_restore(flags
);
455 static void sdhci_transfer_pio(struct sdhci_host
*host
)
459 if (host
->blocks
== 0)
462 if (host
->data
->flags
& MMC_DATA_READ
)
463 mask
= SDHCI_DATA_AVAILABLE
;
465 mask
= SDHCI_SPACE_AVAILABLE
;
468 * Some controllers (JMicron JMB38x) mess up the buffer bits
469 * for transfers < 4 bytes. As long as it is just one block,
470 * we can ignore the bits.
472 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
473 (host
->data
->blocks
== 1))
476 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
477 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
480 if (host
->data
->flags
& MMC_DATA_READ
)
481 sdhci_read_block_pio(host
);
483 sdhci_write_block_pio(host
);
486 if (host
->blocks
== 0)
490 DBG("PIO transfer complete.\n");
493 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
494 struct mmc_data
*data
, int cookie
)
499 * If the data buffers are already mapped, return the previous
500 * dma_map_sg() result.
502 if (data
->host_cookie
== COOKIE_PRE_MAPPED
)
503 return data
->sg_count
;
505 sg_count
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
506 mmc_get_dma_dir(data
));
511 data
->sg_count
= sg_count
;
512 data
->host_cookie
= cookie
;
517 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
519 local_irq_save(*flags
);
520 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
523 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
525 kunmap_atomic(buffer
);
526 local_irq_restore(*flags
);
529 static void sdhci_adma_write_desc(struct sdhci_host
*host
, void *desc
,
530 dma_addr_t addr
, int len
, unsigned cmd
)
532 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
534 /* 32-bit and 64-bit descriptors have these members in same position */
535 dma_desc
->cmd
= cpu_to_le16(cmd
);
536 dma_desc
->len
= cpu_to_le16(len
);
537 dma_desc
->addr_lo
= cpu_to_le32((u32
)addr
);
539 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
540 dma_desc
->addr_hi
= cpu_to_le32((u64
)addr
>> 32);
543 static void sdhci_adma_mark_end(void *desc
)
545 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
547 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
548 dma_desc
->cmd
|= cpu_to_le16(ADMA2_END
);
551 static void sdhci_adma_table_pre(struct sdhci_host
*host
,
552 struct mmc_data
*data
, int sg_count
)
554 struct scatterlist
*sg
;
556 dma_addr_t addr
, align_addr
;
562 * The spec does not specify endianness of descriptor table.
563 * We currently guess that it is LE.
566 host
->sg_count
= sg_count
;
568 desc
= host
->adma_table
;
569 align
= host
->align_buffer
;
571 align_addr
= host
->align_addr
;
573 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
574 addr
= sg_dma_address(sg
);
575 len
= sg_dma_len(sg
);
578 * The SDHCI specification states that ADMA addresses must
579 * be 32-bit aligned. If they aren't, then we use a bounce
580 * buffer for the (up to three) bytes that screw up the
583 offset
= (SDHCI_ADMA2_ALIGN
- (addr
& SDHCI_ADMA2_MASK
)) &
586 if (data
->flags
& MMC_DATA_WRITE
) {
587 buffer
= sdhci_kmap_atomic(sg
, &flags
);
588 memcpy(align
, buffer
, offset
);
589 sdhci_kunmap_atomic(buffer
, &flags
);
593 sdhci_adma_write_desc(host
, desc
, align_addr
, offset
,
596 BUG_ON(offset
> 65536);
598 align
+= SDHCI_ADMA2_ALIGN
;
599 align_addr
+= SDHCI_ADMA2_ALIGN
;
601 desc
+= host
->desc_sz
;
611 sdhci_adma_write_desc(host
, desc
, addr
, len
,
613 desc
+= host
->desc_sz
;
617 * If this triggers then we have a calculation bug
620 WARN_ON((desc
- host
->adma_table
) >= host
->adma_table_sz
);
623 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
624 /* Mark the last descriptor as the terminating descriptor */
625 if (desc
!= host
->adma_table
) {
626 desc
-= host
->desc_sz
;
627 sdhci_adma_mark_end(desc
);
630 /* Add a terminating entry - nop, end, valid */
631 sdhci_adma_write_desc(host
, desc
, 0, 0, ADMA2_NOP_END_VALID
);
635 static void sdhci_adma_table_post(struct sdhci_host
*host
,
636 struct mmc_data
*data
)
638 struct scatterlist
*sg
;
644 if (data
->flags
& MMC_DATA_READ
) {
645 bool has_unaligned
= false;
647 /* Do a quick scan of the SG list for any unaligned mappings */
648 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
)
649 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
650 has_unaligned
= true;
655 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
656 data
->sg_len
, DMA_FROM_DEVICE
);
658 align
= host
->align_buffer
;
660 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
661 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
662 size
= SDHCI_ADMA2_ALIGN
-
663 (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
);
665 buffer
= sdhci_kmap_atomic(sg
, &flags
);
666 memcpy(buffer
, align
, size
);
667 sdhci_kunmap_atomic(buffer
, &flags
);
669 align
+= SDHCI_ADMA2_ALIGN
;
676 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
679 struct mmc_data
*data
= cmd
->data
;
680 unsigned target_timeout
, current_timeout
;
683 * If the host controller provides us with an incorrect timeout
684 * value, just skip the check and use 0xE. The hardware may take
685 * longer to time out, but that's much better than having a too-short
688 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
691 /* Unspecified timeout, assume max */
692 if (!data
&& !cmd
->busy_timeout
)
697 target_timeout
= cmd
->busy_timeout
* 1000;
699 target_timeout
= DIV_ROUND_UP(data
->timeout_ns
, 1000);
700 if (host
->clock
&& data
->timeout_clks
) {
701 unsigned long long val
;
704 * data->timeout_clks is in units of clock cycles.
705 * host->clock is in Hz. target_timeout is in us.
706 * Hence, us = 1000000 * cycles / Hz. Round up.
708 val
= 1000000ULL * data
->timeout_clks
;
709 if (do_div(val
, host
->clock
))
711 target_timeout
+= val
;
716 * Figure out needed cycles.
717 * We do this in steps in order to fit inside a 32 bit int.
718 * The first step is the minimum timeout, which will have a
719 * minimum resolution of 6 bits:
720 * (1) 2^13*1000 > 2^22,
721 * (2) host->timeout_clk < 2^16
726 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
727 while (current_timeout
< target_timeout
) {
729 current_timeout
<<= 1;
735 DBG("Too large timeout 0x%x requested for CMD%d!\n",
743 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
745 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
746 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
748 if (host
->flags
& SDHCI_REQ_USE_DMA
)
749 host
->ier
= (host
->ier
& ~pio_irqs
) | dma_irqs
;
751 host
->ier
= (host
->ier
& ~dma_irqs
) | pio_irqs
;
753 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
754 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
757 static void sdhci_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
761 if (host
->ops
->set_timeout
) {
762 host
->ops
->set_timeout(host
, cmd
);
764 count
= sdhci_calc_timeout(host
, cmd
);
765 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
769 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
772 struct mmc_data
*data
= cmd
->data
;
774 if (sdhci_data_line_cmd(cmd
))
775 sdhci_set_timeout(host
, cmd
);
783 BUG_ON(data
->blksz
* data
->blocks
> 524288);
784 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
785 BUG_ON(data
->blocks
> 65535);
788 host
->data_early
= 0;
789 host
->data
->bytes_xfered
= 0;
791 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
792 struct scatterlist
*sg
;
793 unsigned int length_mask
, offset_mask
;
796 host
->flags
|= SDHCI_REQ_USE_DMA
;
799 * FIXME: This doesn't account for merging when mapping the
802 * The assumption here being that alignment and lengths are
803 * the same after DMA mapping to device address space.
807 if (host
->flags
& SDHCI_USE_ADMA
) {
808 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
) {
811 * As we use up to 3 byte chunks to work
812 * around alignment problems, we need to
813 * check the offset as well.
818 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
820 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
824 if (unlikely(length_mask
| offset_mask
)) {
825 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
826 if (sg
->length
& length_mask
) {
827 DBG("Reverting to PIO because of transfer size (%d)\n",
829 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
832 if (sg
->offset
& offset_mask
) {
833 DBG("Reverting to PIO because of bad alignment\n");
834 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
841 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
842 int sg_cnt
= sdhci_pre_dma_transfer(host
, data
, COOKIE_MAPPED
);
846 * This only happens when someone fed
847 * us an invalid request.
850 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
851 } else if (host
->flags
& SDHCI_USE_ADMA
) {
852 sdhci_adma_table_pre(host
, data
, sg_cnt
);
854 sdhci_writel(host
, host
->adma_addr
, SDHCI_ADMA_ADDRESS
);
855 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
857 (u64
)host
->adma_addr
>> 32,
858 SDHCI_ADMA_ADDRESS_HI
);
860 WARN_ON(sg_cnt
!= 1);
861 sdhci_writel(host
, sg_dma_address(data
->sg
),
867 * Always adjust the DMA selection as some controllers
868 * (e.g. JMicron) can't do PIO properly when the selection
871 if (host
->version
>= SDHCI_SPEC_200
) {
872 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
873 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
874 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
875 (host
->flags
& SDHCI_USE_ADMA
)) {
876 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
877 ctrl
|= SDHCI_CTRL_ADMA64
;
879 ctrl
|= SDHCI_CTRL_ADMA32
;
881 ctrl
|= SDHCI_CTRL_SDMA
;
883 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
886 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
889 flags
= SG_MITER_ATOMIC
;
890 if (host
->data
->flags
& MMC_DATA_READ
)
891 flags
|= SG_MITER_TO_SG
;
893 flags
|= SG_MITER_FROM_SG
;
894 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
895 host
->blocks
= data
->blocks
;
898 sdhci_set_transfer_irqs(host
);
900 /* Set the DMA boundary value and block size */
901 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(host
->sdma_boundary
, data
->blksz
),
903 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
906 static inline bool sdhci_auto_cmd12(struct sdhci_host
*host
,
907 struct mmc_request
*mrq
)
909 return !mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
) &&
910 !mrq
->cap_cmd_during_tfr
;
913 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
914 struct mmc_command
*cmd
)
917 struct mmc_data
*data
= cmd
->data
;
921 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD
) {
922 sdhci_writew(host
, 0x0, SDHCI_TRANSFER_MODE
);
924 /* clear Auto CMD settings for no data CMDs */
925 mode
= sdhci_readw(host
, SDHCI_TRANSFER_MODE
);
926 sdhci_writew(host
, mode
& ~(SDHCI_TRNS_AUTO_CMD12
|
927 SDHCI_TRNS_AUTO_CMD23
), SDHCI_TRANSFER_MODE
);
932 WARN_ON(!host
->data
);
934 if (!(host
->quirks2
& SDHCI_QUIRK2_SUPPORT_SINGLE
))
935 mode
= SDHCI_TRNS_BLK_CNT_EN
;
937 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
938 mode
= SDHCI_TRNS_BLK_CNT_EN
| SDHCI_TRNS_MULTI
;
940 * If we are sending CMD23, CMD12 never gets sent
941 * on successful completion (so no Auto-CMD12).
943 if (sdhci_auto_cmd12(host
, cmd
->mrq
) &&
944 (cmd
->opcode
!= SD_IO_RW_EXTENDED
))
945 mode
|= SDHCI_TRNS_AUTO_CMD12
;
946 else if (cmd
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
947 mode
|= SDHCI_TRNS_AUTO_CMD23
;
948 sdhci_writel(host
, cmd
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
952 if (data
->flags
& MMC_DATA_READ
)
953 mode
|= SDHCI_TRNS_READ
;
954 if (host
->flags
& SDHCI_REQ_USE_DMA
)
955 mode
|= SDHCI_TRNS_DMA
;
957 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
960 static bool sdhci_needs_reset(struct sdhci_host
*host
, struct mmc_request
*mrq
)
962 return (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
963 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
964 (mrq
->sbc
&& mrq
->sbc
->error
) ||
965 (mrq
->data
&& ((mrq
->data
->error
&& !mrq
->data
->stop
) ||
966 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
967 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
)));
970 static void __sdhci_finish_mrq(struct sdhci_host
*host
, struct mmc_request
*mrq
)
974 for (i
= 0; i
< SDHCI_MAX_MRQS
; i
++) {
975 if (host
->mrqs_done
[i
] == mrq
) {
981 for (i
= 0; i
< SDHCI_MAX_MRQS
; i
++) {
982 if (!host
->mrqs_done
[i
]) {
983 host
->mrqs_done
[i
] = mrq
;
988 WARN_ON(i
>= SDHCI_MAX_MRQS
);
990 tasklet_schedule(&host
->finish_tasklet
);
993 static void sdhci_finish_mrq(struct sdhci_host
*host
, struct mmc_request
*mrq
)
995 if (host
->cmd
&& host
->cmd
->mrq
== mrq
)
998 if (host
->data_cmd
&& host
->data_cmd
->mrq
== mrq
)
999 host
->data_cmd
= NULL
;
1001 if (host
->data
&& host
->data
->mrq
== mrq
)
1004 if (sdhci_needs_reset(host
, mrq
))
1005 host
->pending_reset
= true;
1007 __sdhci_finish_mrq(host
, mrq
);
1010 static void sdhci_finish_data(struct sdhci_host
*host
)
1012 struct mmc_command
*data_cmd
= host
->data_cmd
;
1013 struct mmc_data
*data
= host
->data
;
1016 host
->data_cmd
= NULL
;
1018 if ((host
->flags
& (SDHCI_REQ_USE_DMA
| SDHCI_USE_ADMA
)) ==
1019 (SDHCI_REQ_USE_DMA
| SDHCI_USE_ADMA
))
1020 sdhci_adma_table_post(host
, data
);
1023 * The specification states that the block count register must
1024 * be updated, but it does not specify at what point in the
1025 * data flow. That makes the register entirely useless to read
1026 * back so we have to assume that nothing made it to the card
1027 * in the event of an error.
1030 data
->bytes_xfered
= 0;
1032 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
1035 * Need to send CMD12 if -
1036 * a) open-ended multiblock transfer (no CMD23)
1037 * b) error in multiblock transfer
1044 * The controller needs a reset of internal state machines
1045 * upon error conditions.
1048 if (!host
->cmd
|| host
->cmd
== data_cmd
)
1049 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
1050 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
1054 * 'cap_cmd_during_tfr' request must not use the command line
1055 * after mmc_command_done() has been called. It is upper layer's
1056 * responsibility to send the stop command if required.
1058 if (data
->mrq
->cap_cmd_during_tfr
) {
1059 sdhci_finish_mrq(host
, data
->mrq
);
1061 /* Avoid triggering warning in sdhci_send_command() */
1063 sdhci_send_command(host
, data
->stop
);
1066 sdhci_finish_mrq(host
, data
->mrq
);
1070 static void sdhci_mod_timer(struct sdhci_host
*host
, struct mmc_request
*mrq
,
1071 unsigned long timeout
)
1073 if (sdhci_data_line_cmd(mrq
->cmd
))
1074 mod_timer(&host
->data_timer
, timeout
);
1076 mod_timer(&host
->timer
, timeout
);
1079 static void sdhci_del_timer(struct sdhci_host
*host
, struct mmc_request
*mrq
)
1081 if (sdhci_data_line_cmd(mrq
->cmd
))
1082 del_timer(&host
->data_timer
);
1084 del_timer(&host
->timer
);
1087 void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
1091 unsigned long timeout
;
1095 /* Initially, a command has no error */
1098 if ((host
->quirks2
& SDHCI_QUIRK2_STOP_WITH_TC
) &&
1099 cmd
->opcode
== MMC_STOP_TRANSMISSION
)
1100 cmd
->flags
|= MMC_RSP_BUSY
;
1102 /* Wait max 10 ms */
1105 mask
= SDHCI_CMD_INHIBIT
;
1106 if (sdhci_data_line_cmd(cmd
))
1107 mask
|= SDHCI_DATA_INHIBIT
;
1109 /* We shouldn't wait for data inihibit for stop commands, even
1110 though they might use busy signaling */
1111 if (cmd
->mrq
->data
&& (cmd
== cmd
->mrq
->data
->stop
))
1112 mask
&= ~SDHCI_DATA_INHIBIT
;
1114 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
1116 pr_err("%s: Controller never released inhibit bit(s).\n",
1117 mmc_hostname(host
->mmc
));
1118 sdhci_dumpregs(host
);
1120 sdhci_finish_mrq(host
, cmd
->mrq
);
1128 if (!cmd
->data
&& cmd
->busy_timeout
> 9000)
1129 timeout
+= DIV_ROUND_UP(cmd
->busy_timeout
, 1000) * HZ
+ HZ
;
1132 sdhci_mod_timer(host
, cmd
->mrq
, timeout
);
1135 if (sdhci_data_line_cmd(cmd
)) {
1136 WARN_ON(host
->data_cmd
);
1137 host
->data_cmd
= cmd
;
1140 sdhci_prepare_data(host
, cmd
);
1142 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
1144 sdhci_set_transfer_mode(host
, cmd
);
1146 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
1147 pr_err("%s: Unsupported response type!\n",
1148 mmc_hostname(host
->mmc
));
1149 cmd
->error
= -EINVAL
;
1150 sdhci_finish_mrq(host
, cmd
->mrq
);
1154 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1155 flags
= SDHCI_CMD_RESP_NONE
;
1156 else if (cmd
->flags
& MMC_RSP_136
)
1157 flags
= SDHCI_CMD_RESP_LONG
;
1158 else if (cmd
->flags
& MMC_RSP_BUSY
)
1159 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1161 flags
= SDHCI_CMD_RESP_SHORT
;
1163 if (cmd
->flags
& MMC_RSP_CRC
)
1164 flags
|= SDHCI_CMD_CRC
;
1165 if (cmd
->flags
& MMC_RSP_OPCODE
)
1166 flags
|= SDHCI_CMD_INDEX
;
1168 /* CMD19 is special in that the Data Present Select should be set */
1169 if (cmd
->data
|| cmd
->opcode
== MMC_SEND_TUNING_BLOCK
||
1170 cmd
->opcode
== MMC_SEND_TUNING_BLOCK_HS200
)
1171 flags
|= SDHCI_CMD_DATA
;
1173 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1175 EXPORT_SYMBOL_GPL(sdhci_send_command
);
1177 static void sdhci_read_rsp_136(struct sdhci_host
*host
, struct mmc_command
*cmd
)
1181 for (i
= 0; i
< 4; i
++) {
1182 reg
= SDHCI_RESPONSE
+ (3 - i
) * 4;
1183 cmd
->resp
[i
] = sdhci_readl(host
, reg
);
1186 if (host
->quirks2
& SDHCI_QUIRK2_RSP_136_HAS_CRC
)
1189 /* CRC is stripped so we need to do some shifting */
1190 for (i
= 0; i
< 4; i
++) {
1193 cmd
->resp
[i
] |= cmd
->resp
[i
+ 1] >> 24;
1197 static void sdhci_finish_command(struct sdhci_host
*host
)
1199 struct mmc_command
*cmd
= host
->cmd
;
1203 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1204 if (cmd
->flags
& MMC_RSP_136
) {
1205 sdhci_read_rsp_136(host
, cmd
);
1207 cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1211 if (cmd
->mrq
->cap_cmd_during_tfr
&& cmd
== cmd
->mrq
->cmd
)
1212 mmc_command_done(host
->mmc
, cmd
->mrq
);
1215 * The host can send and interrupt when the busy state has
1216 * ended, allowing us to wait without wasting CPU cycles.
1217 * The busy signal uses DAT0 so this is similar to waiting
1218 * for data to complete.
1220 * Note: The 1.0 specification is a bit ambiguous about this
1221 * feature so there might be some problems with older
1224 if (cmd
->flags
& MMC_RSP_BUSY
) {
1226 DBG("Cannot wait for busy signal when also doing a data transfer");
1227 } else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
1228 cmd
== host
->data_cmd
) {
1229 /* Command complete before busy is ended */
1234 /* Finished CMD23, now send actual command. */
1235 if (cmd
== cmd
->mrq
->sbc
) {
1236 sdhci_send_command(host
, cmd
->mrq
->cmd
);
1239 /* Processed actual command. */
1240 if (host
->data
&& host
->data_early
)
1241 sdhci_finish_data(host
);
1244 sdhci_finish_mrq(host
, cmd
->mrq
);
1248 static u16
sdhci_get_preset_value(struct sdhci_host
*host
)
1252 switch (host
->timing
) {
1253 case MMC_TIMING_UHS_SDR12
:
1254 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1256 case MMC_TIMING_UHS_SDR25
:
1257 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR25
);
1259 case MMC_TIMING_UHS_SDR50
:
1260 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR50
);
1262 case MMC_TIMING_UHS_SDR104
:
1263 case MMC_TIMING_MMC_HS200
:
1264 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR104
);
1266 case MMC_TIMING_UHS_DDR50
:
1267 case MMC_TIMING_MMC_DDR52
:
1268 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_DDR50
);
1270 case MMC_TIMING_MMC_HS400
:
1271 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_HS400
);
1274 pr_warn("%s: Invalid UHS-I mode selected\n",
1275 mmc_hostname(host
->mmc
));
1276 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1282 u16
sdhci_calc_clk(struct sdhci_host
*host
, unsigned int clock
,
1283 unsigned int *actual_clock
)
1285 int div
= 0; /* Initialized for compiler warning */
1286 int real_div
= div
, clk_mul
= 1;
1288 bool switch_base_clk
= false;
1290 if (host
->version
>= SDHCI_SPEC_300
) {
1291 if (host
->preset_enabled
) {
1294 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1295 pre_val
= sdhci_get_preset_value(host
);
1296 div
= (pre_val
& SDHCI_PRESET_SDCLK_FREQ_MASK
)
1297 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT
;
1298 if (host
->clk_mul
&&
1299 (pre_val
& SDHCI_PRESET_CLKGEN_SEL_MASK
)) {
1300 clk
= SDHCI_PROG_CLOCK_MODE
;
1302 clk_mul
= host
->clk_mul
;
1304 real_div
= max_t(int, 1, div
<< 1);
1310 * Check if the Host Controller supports Programmable Clock
1313 if (host
->clk_mul
) {
1314 for (div
= 1; div
<= 1024; div
++) {
1315 if ((host
->max_clk
* host
->clk_mul
/ div
)
1319 if ((host
->max_clk
* host
->clk_mul
/ div
) <= clock
) {
1321 * Set Programmable Clock Mode in the Clock
1324 clk
= SDHCI_PROG_CLOCK_MODE
;
1326 clk_mul
= host
->clk_mul
;
1330 * Divisor can be too small to reach clock
1331 * speed requirement. Then use the base clock.
1333 switch_base_clk
= true;
1337 if (!host
->clk_mul
|| switch_base_clk
) {
1338 /* Version 3.00 divisors must be a multiple of 2. */
1339 if (host
->max_clk
<= clock
)
1342 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1344 if ((host
->max_clk
/ div
) <= clock
)
1350 if ((host
->quirks2
& SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
)
1351 && !div
&& host
->max_clk
<= 25000000)
1355 /* Version 2.00 divisors must be a power of 2. */
1356 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1357 if ((host
->max_clk
/ div
) <= clock
)
1366 *actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1367 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1368 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1369 << SDHCI_DIVIDER_HI_SHIFT
;
1373 EXPORT_SYMBOL_GPL(sdhci_calc_clk
);
1375 void sdhci_enable_clk(struct sdhci_host
*host
, u16 clk
)
1379 clk
|= SDHCI_CLOCK_INT_EN
;
1380 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1382 /* Wait max 20 ms */
1383 timeout
= ktime_add_ms(ktime_get(), 20);
1384 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1385 & SDHCI_CLOCK_INT_STABLE
)) {
1386 if (ktime_after(ktime_get(), timeout
)) {
1387 pr_err("%s: Internal clock never stabilised.\n",
1388 mmc_hostname(host
->mmc
));
1389 sdhci_dumpregs(host
);
1395 clk
|= SDHCI_CLOCK_CARD_EN
;
1396 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1398 EXPORT_SYMBOL_GPL(sdhci_enable_clk
);
1400 void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1404 host
->mmc
->actual_clock
= 0;
1406 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1411 clk
= sdhci_calc_clk(host
, clock
, &host
->mmc
->actual_clock
);
1412 sdhci_enable_clk(host
, clk
);
1414 EXPORT_SYMBOL_GPL(sdhci_set_clock
);
1416 static void sdhci_set_power_reg(struct sdhci_host
*host
, unsigned char mode
,
1419 struct mmc_host
*mmc
= host
->mmc
;
1421 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
1423 if (mode
!= MMC_POWER_OFF
)
1424 sdhci_writeb(host
, SDHCI_POWER_ON
, SDHCI_POWER_CONTROL
);
1426 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1429 void sdhci_set_power_noreg(struct sdhci_host
*host
, unsigned char mode
,
1434 if (mode
!= MMC_POWER_OFF
) {
1436 case MMC_VDD_165_195
:
1437 pwr
= SDHCI_POWER_180
;
1441 pwr
= SDHCI_POWER_300
;
1445 pwr
= SDHCI_POWER_330
;
1448 WARN(1, "%s: Invalid vdd %#x\n",
1449 mmc_hostname(host
->mmc
), vdd
);
1454 if (host
->pwr
== pwr
)
1460 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1461 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1462 sdhci_runtime_pm_bus_off(host
);
1465 * Spec says that we should clear the power reg before setting
1466 * a new value. Some controllers don't seem to like this though.
1468 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1469 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1472 * At least the Marvell CaFe chip gets confused if we set the
1473 * voltage and set turn on power at the same time, so set the
1476 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1477 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1479 pwr
|= SDHCI_POWER_ON
;
1481 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1483 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1484 sdhci_runtime_pm_bus_on(host
);
1487 * Some controllers need an extra 10ms delay of 10ms before
1488 * they can apply clock after applying power
1490 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1494 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg
);
1496 void sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1499 if (IS_ERR(host
->mmc
->supply
.vmmc
))
1500 sdhci_set_power_noreg(host
, mode
, vdd
);
1502 sdhci_set_power_reg(host
, mode
, vdd
);
1504 EXPORT_SYMBOL_GPL(sdhci_set_power
);
1506 /*****************************************************************************\
1510 \*****************************************************************************/
1512 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1514 struct sdhci_host
*host
;
1516 unsigned long flags
;
1518 host
= mmc_priv(mmc
);
1520 /* Firstly check card presence */
1521 present
= mmc
->ops
->get_cd(mmc
);
1523 spin_lock_irqsave(&host
->lock
, flags
);
1525 sdhci_led_activate(host
);
1528 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1529 * requests if Auto-CMD12 is enabled.
1531 if (sdhci_auto_cmd12(host
, mrq
)) {
1533 mrq
->data
->stop
= NULL
;
1538 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1539 mrq
->cmd
->error
= -ENOMEDIUM
;
1540 sdhci_finish_mrq(host
, mrq
);
1542 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1543 sdhci_send_command(host
, mrq
->sbc
);
1545 sdhci_send_command(host
, mrq
->cmd
);
1549 spin_unlock_irqrestore(&host
->lock
, flags
);
1552 void sdhci_set_bus_width(struct sdhci_host
*host
, int width
)
1556 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1557 if (width
== MMC_BUS_WIDTH_8
) {
1558 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1559 ctrl
|= SDHCI_CTRL_8BITBUS
;
1561 if (host
->mmc
->caps
& MMC_CAP_8_BIT_DATA
)
1562 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1563 if (width
== MMC_BUS_WIDTH_4
)
1564 ctrl
|= SDHCI_CTRL_4BITBUS
;
1566 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1568 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1570 EXPORT_SYMBOL_GPL(sdhci_set_bus_width
);
1572 void sdhci_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
1576 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1577 /* Select Bus Speed Mode for host */
1578 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1579 if ((timing
== MMC_TIMING_MMC_HS200
) ||
1580 (timing
== MMC_TIMING_UHS_SDR104
))
1581 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1582 else if (timing
== MMC_TIMING_UHS_SDR12
)
1583 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1584 else if (timing
== MMC_TIMING_UHS_SDR25
)
1585 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1586 else if (timing
== MMC_TIMING_UHS_SDR50
)
1587 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1588 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
1589 (timing
== MMC_TIMING_MMC_DDR52
))
1590 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1591 else if (timing
== MMC_TIMING_MMC_HS400
)
1592 ctrl_2
|= SDHCI_CTRL_HS400
; /* Non-standard */
1593 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1595 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling
);
1597 void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1599 struct sdhci_host
*host
= mmc_priv(mmc
);
1602 if (ios
->power_mode
== MMC_POWER_UNDEFINED
)
1605 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1606 if (!IS_ERR(mmc
->supply
.vmmc
) &&
1607 ios
->power_mode
== MMC_POWER_OFF
)
1608 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1613 * Reset the chip on each power off.
1614 * Should clear out any weird states.
1616 if (ios
->power_mode
== MMC_POWER_OFF
) {
1617 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1621 if (host
->version
>= SDHCI_SPEC_300
&&
1622 (ios
->power_mode
== MMC_POWER_UP
) &&
1623 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
))
1624 sdhci_enable_preset_value(host
, false);
1626 if (!ios
->clock
|| ios
->clock
!= host
->clock
) {
1627 host
->ops
->set_clock(host
, ios
->clock
);
1628 host
->clock
= ios
->clock
;
1630 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
&&
1632 host
->timeout_clk
= host
->mmc
->actual_clock
?
1633 host
->mmc
->actual_clock
/ 1000 :
1635 host
->mmc
->max_busy_timeout
=
1636 host
->ops
->get_max_timeout_count
?
1637 host
->ops
->get_max_timeout_count(host
) :
1639 host
->mmc
->max_busy_timeout
/= host
->timeout_clk
;
1643 if (host
->ops
->set_power
)
1644 host
->ops
->set_power(host
, ios
->power_mode
, ios
->vdd
);
1646 sdhci_set_power(host
, ios
->power_mode
, ios
->vdd
);
1648 if (host
->ops
->platform_send_init_74_clocks
)
1649 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1651 host
->ops
->set_bus_width(host
, ios
->bus_width
);
1653 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1655 if (!(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)) {
1656 if (ios
->timing
== MMC_TIMING_SD_HS
||
1657 ios
->timing
== MMC_TIMING_MMC_HS
||
1658 ios
->timing
== MMC_TIMING_MMC_HS400
||
1659 ios
->timing
== MMC_TIMING_MMC_HS200
||
1660 ios
->timing
== MMC_TIMING_MMC_DDR52
||
1661 ios
->timing
== MMC_TIMING_UHS_SDR50
||
1662 ios
->timing
== MMC_TIMING_UHS_SDR104
||
1663 ios
->timing
== MMC_TIMING_UHS_DDR50
||
1664 ios
->timing
== MMC_TIMING_UHS_SDR25
)
1665 ctrl
|= SDHCI_CTRL_HISPD
;
1667 ctrl
&= ~SDHCI_CTRL_HISPD
;
1670 if (host
->version
>= SDHCI_SPEC_300
) {
1673 if (!host
->preset_enabled
) {
1674 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1676 * We only need to set Driver Strength if the
1677 * preset value enable is not set.
1679 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1680 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1681 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1682 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1683 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_B
)
1684 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1685 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1686 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1687 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_D
)
1688 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_D
;
1690 pr_warn("%s: invalid driver type, default to driver type B\n",
1692 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1695 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1698 * According to SDHC Spec v3.00, if the Preset Value
1699 * Enable in the Host Control 2 register is set, we
1700 * need to reset SD Clock Enable before changing High
1701 * Speed Enable to avoid generating clock gliches.
1704 /* Reset SD Clock Enable */
1705 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1706 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1707 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1709 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1711 /* Re-enable SD Clock */
1712 host
->ops
->set_clock(host
, host
->clock
);
1715 /* Reset SD Clock Enable */
1716 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1717 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1718 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1720 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1721 host
->timing
= ios
->timing
;
1723 if (!(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
) &&
1724 ((ios
->timing
== MMC_TIMING_UHS_SDR12
) ||
1725 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1726 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1727 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1728 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1729 (ios
->timing
== MMC_TIMING_MMC_DDR52
))) {
1732 sdhci_enable_preset_value(host
, true);
1733 preset
= sdhci_get_preset_value(host
);
1734 ios
->drv_type
= (preset
& SDHCI_PRESET_DRV_MASK
)
1735 >> SDHCI_PRESET_DRV_SHIFT
;
1738 /* Re-enable SD Clock */
1739 host
->ops
->set_clock(host
, host
->clock
);
1741 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1744 * Some (ENE) controllers go apeshit on some ios operation,
1745 * signalling timeout and CRC errors even on CMD0. Resetting
1746 * it on each ios seems to solve the problem.
1748 if (host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1749 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1753 EXPORT_SYMBOL_GPL(sdhci_set_ios
);
1755 static int sdhci_get_cd(struct mmc_host
*mmc
)
1757 struct sdhci_host
*host
= mmc_priv(mmc
);
1758 int gpio_cd
= mmc_gpio_get_cd(mmc
);
1760 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1763 /* If nonremovable, assume that the card is always present. */
1764 if (!mmc_card_is_removable(host
->mmc
))
1768 * Try slot gpio detect, if defined it take precedence
1769 * over build in controller functionality
1774 /* If polling, assume that the card is always present. */
1775 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1778 /* Host native card detect */
1779 return !!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
);
1782 static int sdhci_check_ro(struct sdhci_host
*host
)
1784 unsigned long flags
;
1787 spin_lock_irqsave(&host
->lock
, flags
);
1789 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1791 else if (host
->ops
->get_ro
)
1792 is_readonly
= host
->ops
->get_ro(host
);
1794 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1795 & SDHCI_WRITE_PROTECT
);
1797 spin_unlock_irqrestore(&host
->lock
, flags
);
1799 /* This quirk needs to be replaced by a callback-function later */
1800 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1801 !is_readonly
: is_readonly
;
1804 #define SAMPLE_COUNT 5
1806 static int sdhci_get_ro(struct mmc_host
*mmc
)
1808 struct sdhci_host
*host
= mmc_priv(mmc
);
1811 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1812 return sdhci_check_ro(host
);
1815 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1816 if (sdhci_check_ro(host
)) {
1817 if (++ro_count
> SAMPLE_COUNT
/ 2)
1825 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1827 struct sdhci_host
*host
= mmc_priv(mmc
);
1829 if (host
->ops
&& host
->ops
->hw_reset
)
1830 host
->ops
->hw_reset(host
);
1833 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1835 if (!(host
->flags
& SDHCI_DEVICE_DEAD
)) {
1837 host
->ier
|= SDHCI_INT_CARD_INT
;
1839 host
->ier
&= ~SDHCI_INT_CARD_INT
;
1841 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
1842 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
1847 void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1849 struct sdhci_host
*host
= mmc_priv(mmc
);
1850 unsigned long flags
;
1853 pm_runtime_get_noresume(host
->mmc
->parent
);
1855 spin_lock_irqsave(&host
->lock
, flags
);
1857 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1859 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1861 sdhci_enable_sdio_irq_nolock(host
, enable
);
1862 spin_unlock_irqrestore(&host
->lock
, flags
);
1865 pm_runtime_put_noidle(host
->mmc
->parent
);
1867 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq
);
1869 int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1870 struct mmc_ios
*ios
)
1872 struct sdhci_host
*host
= mmc_priv(mmc
);
1877 * Signal Voltage Switching is only applicable for Host Controllers
1880 if (host
->version
< SDHCI_SPEC_300
)
1883 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1885 switch (ios
->signal_voltage
) {
1886 case MMC_SIGNAL_VOLTAGE_330
:
1887 if (!(host
->flags
& SDHCI_SIGNALING_330
))
1889 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1890 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1891 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1893 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1894 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1896 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1902 usleep_range(5000, 5500);
1904 /* 3.3V regulator output should be stable within 5 ms */
1905 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1906 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1909 pr_warn("%s: 3.3V regulator output did not became stable\n",
1913 case MMC_SIGNAL_VOLTAGE_180
:
1914 if (!(host
->flags
& SDHCI_SIGNALING_180
))
1916 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1917 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1919 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1926 * Enable 1.8V Signal Enable in the Host Control2
1929 ctrl
|= SDHCI_CTRL_VDD_180
;
1930 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1932 /* Some controller need to do more when switching */
1933 if (host
->ops
->voltage_switch
)
1934 host
->ops
->voltage_switch(host
);
1936 /* 1.8V regulator output should be stable within 5 ms */
1937 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1938 if (ctrl
& SDHCI_CTRL_VDD_180
)
1941 pr_warn("%s: 1.8V regulator output did not became stable\n",
1945 case MMC_SIGNAL_VOLTAGE_120
:
1946 if (!(host
->flags
& SDHCI_SIGNALING_120
))
1948 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1949 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1951 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1958 /* No signal voltage switch required */
1962 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch
);
1964 static int sdhci_card_busy(struct mmc_host
*mmc
)
1966 struct sdhci_host
*host
= mmc_priv(mmc
);
1969 /* Check whether DAT[0] is 0 */
1970 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1972 return !(present_state
& SDHCI_DATA_0_LVL_MASK
);
1975 static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1977 struct sdhci_host
*host
= mmc_priv(mmc
);
1978 unsigned long flags
;
1980 spin_lock_irqsave(&host
->lock
, flags
);
1981 host
->flags
|= SDHCI_HS400_TUNING
;
1982 spin_unlock_irqrestore(&host
->lock
, flags
);
1987 static void sdhci_start_tuning(struct sdhci_host
*host
)
1991 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1992 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1993 if (host
->quirks2
& SDHCI_QUIRK2_TUNING_WORK_AROUND
)
1994 ctrl
|= SDHCI_CTRL_TUNED_CLK
;
1995 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1998 * As per the Host Controller spec v3.00, tuning command
1999 * generates Buffer Read Ready interrupt, so enable that.
2001 * Note: The spec clearly says that when tuning sequence
2002 * is being performed, the controller does not generate
2003 * interrupts other than Buffer Read Ready interrupt. But
2004 * to make sure we don't hit a controller bug, we _only_
2005 * enable Buffer Read Ready interrupt here.
2007 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_INT_ENABLE
);
2008 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_SIGNAL_ENABLE
);
2011 static void sdhci_end_tuning(struct sdhci_host
*host
)
2013 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2014 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2017 static void sdhci_reset_tuning(struct sdhci_host
*host
)
2021 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2022 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2023 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
2024 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2027 static void sdhci_abort_tuning(struct sdhci_host
*host
, u32 opcode
)
2029 sdhci_reset_tuning(host
);
2031 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2032 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2034 sdhci_end_tuning(host
);
2036 mmc_abort_tuning(host
->mmc
, opcode
);
2040 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2041 * tuning command does not have a data payload (or rather the hardware does it
2042 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2043 * interrupt setup is different to other commands and there is no timeout
2044 * interrupt so special handling is needed.
2046 static void sdhci_send_tuning(struct sdhci_host
*host
, u32 opcode
)
2048 struct mmc_host
*mmc
= host
->mmc
;
2049 struct mmc_command cmd
= {};
2050 struct mmc_request mrq
= {};
2051 unsigned long flags
;
2052 u32 b
= host
->sdma_boundary
;
2054 spin_lock_irqsave(&host
->lock
, flags
);
2056 cmd
.opcode
= opcode
;
2057 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
2062 * In response to CMD19, the card sends 64 bytes of tuning
2063 * block to the Host Controller. So we set the block size
2066 if (cmd
.opcode
== MMC_SEND_TUNING_BLOCK_HS200
&&
2067 mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
2068 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(b
, 128), SDHCI_BLOCK_SIZE
);
2070 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(b
, 64), SDHCI_BLOCK_SIZE
);
2073 * The tuning block is sent by the card to the host controller.
2074 * So we set the TRNS_READ bit in the Transfer Mode register.
2075 * This also takes care of setting DMA Enable and Multi Block
2076 * Select in the same register to 0.
2078 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
2080 sdhci_send_command(host
, &cmd
);
2084 sdhci_del_timer(host
, &mrq
);
2086 host
->tuning_done
= 0;
2089 spin_unlock_irqrestore(&host
->lock
, flags
);
2091 /* Wait for Buffer Read Ready interrupt */
2092 wait_event_timeout(host
->buf_ready_int
, (host
->tuning_done
== 1),
2093 msecs_to_jiffies(50));
2097 static void __sdhci_execute_tuning(struct sdhci_host
*host
, u32 opcode
)
2102 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2103 * of loops reaches 40 times.
2105 for (i
= 0; i
< MAX_TUNING_LOOP
; i
++) {
2108 sdhci_send_tuning(host
, opcode
);
2110 if (!host
->tuning_done
) {
2111 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2112 mmc_hostname(host
->mmc
));
2113 sdhci_abort_tuning(host
, opcode
);
2117 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2118 if (!(ctrl
& SDHCI_CTRL_EXEC_TUNING
)) {
2119 if (ctrl
& SDHCI_CTRL_TUNED_CLK
)
2120 return; /* Success! */
2124 /* Spec does not require a delay between tuning cycles */
2125 if (host
->tuning_delay
> 0)
2126 mdelay(host
->tuning_delay
);
2129 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2130 mmc_hostname(host
->mmc
));
2131 sdhci_reset_tuning(host
);
2134 int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
2136 struct sdhci_host
*host
= mmc_priv(mmc
);
2138 unsigned int tuning_count
= 0;
2141 hs400_tuning
= host
->flags
& SDHCI_HS400_TUNING
;
2143 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
2144 tuning_count
= host
->tuning_count
;
2147 * The Host Controller needs tuning in case of SDR104 and DDR50
2148 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2149 * the Capabilities register.
2150 * If the Host Controller supports the HS200 mode then the
2151 * tuning function has to be executed.
2153 switch (host
->timing
) {
2154 /* HS400 tuning is done in HS200 mode */
2155 case MMC_TIMING_MMC_HS400
:
2159 case MMC_TIMING_MMC_HS200
:
2161 * Periodic re-tuning for HS400 is not expected to be needed, so
2168 case MMC_TIMING_UHS_SDR104
:
2169 case MMC_TIMING_UHS_DDR50
:
2172 case MMC_TIMING_UHS_SDR50
:
2173 if (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
)
2181 if (host
->ops
->platform_execute_tuning
) {
2182 err
= host
->ops
->platform_execute_tuning(host
, opcode
);
2186 host
->mmc
->retune_period
= tuning_count
;
2188 if (host
->tuning_delay
< 0)
2189 host
->tuning_delay
= opcode
== MMC_SEND_TUNING_BLOCK
;
2191 sdhci_start_tuning(host
);
2193 __sdhci_execute_tuning(host
, opcode
);
2195 sdhci_end_tuning(host
);
2197 host
->flags
&= ~SDHCI_HS400_TUNING
;
2201 EXPORT_SYMBOL_GPL(sdhci_execute_tuning
);
2203 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
)
2205 /* Host Controller v3.00 defines preset value registers */
2206 if (host
->version
< SDHCI_SPEC_300
)
2210 * We only enable or disable Preset Value if they are not already
2211 * enabled or disabled respectively. Otherwise, we bail out.
2213 if (host
->preset_enabled
!= enable
) {
2214 u16 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2217 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
2219 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
2221 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2224 host
->flags
|= SDHCI_PV_ENABLED
;
2226 host
->flags
&= ~SDHCI_PV_ENABLED
;
2228 host
->preset_enabled
= enable
;
2232 static void sdhci_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2235 struct sdhci_host
*host
= mmc_priv(mmc
);
2236 struct mmc_data
*data
= mrq
->data
;
2238 if (data
->host_cookie
!= COOKIE_UNMAPPED
)
2239 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2240 mmc_get_dma_dir(data
));
2242 data
->host_cookie
= COOKIE_UNMAPPED
;
2245 static void sdhci_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
2247 struct sdhci_host
*host
= mmc_priv(mmc
);
2249 mrq
->data
->host_cookie
= COOKIE_UNMAPPED
;
2251 if (host
->flags
& SDHCI_REQ_USE_DMA
)
2252 sdhci_pre_dma_transfer(host
, mrq
->data
, COOKIE_PRE_MAPPED
);
2255 static inline bool sdhci_has_requests(struct sdhci_host
*host
)
2257 return host
->cmd
|| host
->data_cmd
;
2260 static void sdhci_error_out_mrqs(struct sdhci_host
*host
, int err
)
2262 if (host
->data_cmd
) {
2263 host
->data_cmd
->error
= err
;
2264 sdhci_finish_mrq(host
, host
->data_cmd
->mrq
);
2268 host
->cmd
->error
= err
;
2269 sdhci_finish_mrq(host
, host
->cmd
->mrq
);
2273 static void sdhci_card_event(struct mmc_host
*mmc
)
2275 struct sdhci_host
*host
= mmc_priv(mmc
);
2276 unsigned long flags
;
2279 /* First check if client has provided their own card event */
2280 if (host
->ops
->card_event
)
2281 host
->ops
->card_event(host
);
2283 present
= mmc
->ops
->get_cd(mmc
);
2285 spin_lock_irqsave(&host
->lock
, flags
);
2287 /* Check sdhci_has_requests() first in case we are runtime suspended */
2288 if (sdhci_has_requests(host
) && !present
) {
2289 pr_err("%s: Card removed during transfer!\n",
2290 mmc_hostname(host
->mmc
));
2291 pr_err("%s: Resetting controller.\n",
2292 mmc_hostname(host
->mmc
));
2294 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2295 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2297 sdhci_error_out_mrqs(host
, -ENOMEDIUM
);
2300 spin_unlock_irqrestore(&host
->lock
, flags
);
2303 static const struct mmc_host_ops sdhci_ops
= {
2304 .request
= sdhci_request
,
2305 .post_req
= sdhci_post_req
,
2306 .pre_req
= sdhci_pre_req
,
2307 .set_ios
= sdhci_set_ios
,
2308 .get_cd
= sdhci_get_cd
,
2309 .get_ro
= sdhci_get_ro
,
2310 .hw_reset
= sdhci_hw_reset
,
2311 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
2312 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
2313 .prepare_hs400_tuning
= sdhci_prepare_hs400_tuning
,
2314 .execute_tuning
= sdhci_execute_tuning
,
2315 .card_event
= sdhci_card_event
,
2316 .card_busy
= sdhci_card_busy
,
2319 /*****************************************************************************\
2323 \*****************************************************************************/
2325 static bool sdhci_request_done(struct sdhci_host
*host
)
2327 unsigned long flags
;
2328 struct mmc_request
*mrq
;
2331 spin_lock_irqsave(&host
->lock
, flags
);
2333 for (i
= 0; i
< SDHCI_MAX_MRQS
; i
++) {
2334 mrq
= host
->mrqs_done
[i
];
2340 spin_unlock_irqrestore(&host
->lock
, flags
);
2344 sdhci_del_timer(host
, mrq
);
2347 * Always unmap the data buffers if they were mapped by
2348 * sdhci_prepare_data() whenever we finish with a request.
2349 * This avoids leaking DMA mappings on error.
2351 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
2352 struct mmc_data
*data
= mrq
->data
;
2354 if (data
&& data
->host_cookie
== COOKIE_MAPPED
) {
2355 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2356 mmc_get_dma_dir(data
));
2357 data
->host_cookie
= COOKIE_UNMAPPED
;
2362 * The controller needs a reset of internal state machines
2363 * upon error conditions.
2365 if (sdhci_needs_reset(host
, mrq
)) {
2367 * Do not finish until command and data lines are available for
2368 * reset. Note there can only be one other mrq, so it cannot
2369 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2370 * would both be null.
2372 if (host
->cmd
|| host
->data_cmd
) {
2373 spin_unlock_irqrestore(&host
->lock
, flags
);
2377 /* Some controllers need this kick or reset won't work here */
2378 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
)
2379 /* This is to force an update */
2380 host
->ops
->set_clock(host
, host
->clock
);
2382 /* Spec says we should do both at the same time, but Ricoh
2383 controllers do not like that. */
2384 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2385 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2387 host
->pending_reset
= false;
2390 if (!sdhci_has_requests(host
))
2391 sdhci_led_deactivate(host
);
2393 host
->mrqs_done
[i
] = NULL
;
2396 spin_unlock_irqrestore(&host
->lock
, flags
);
2398 mmc_request_done(host
->mmc
, mrq
);
2403 static void sdhci_tasklet_finish(unsigned long param
)
2405 struct sdhci_host
*host
= (struct sdhci_host
*)param
;
2407 while (!sdhci_request_done(host
))
2411 static void sdhci_timeout_timer(struct timer_list
*t
)
2413 struct sdhci_host
*host
;
2414 unsigned long flags
;
2416 host
= from_timer(host
, t
, timer
);
2418 spin_lock_irqsave(&host
->lock
, flags
);
2420 if (host
->cmd
&& !sdhci_data_line_cmd(host
->cmd
)) {
2421 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2422 mmc_hostname(host
->mmc
));
2423 sdhci_dumpregs(host
);
2425 host
->cmd
->error
= -ETIMEDOUT
;
2426 sdhci_finish_mrq(host
, host
->cmd
->mrq
);
2430 spin_unlock_irqrestore(&host
->lock
, flags
);
2433 static void sdhci_timeout_data_timer(struct timer_list
*t
)
2435 struct sdhci_host
*host
;
2436 unsigned long flags
;
2438 host
= from_timer(host
, t
, data_timer
);
2440 spin_lock_irqsave(&host
->lock
, flags
);
2442 if (host
->data
|| host
->data_cmd
||
2443 (host
->cmd
&& sdhci_data_line_cmd(host
->cmd
))) {
2444 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2445 mmc_hostname(host
->mmc
));
2446 sdhci_dumpregs(host
);
2449 host
->data
->error
= -ETIMEDOUT
;
2450 sdhci_finish_data(host
);
2451 } else if (host
->data_cmd
) {
2452 host
->data_cmd
->error
= -ETIMEDOUT
;
2453 sdhci_finish_mrq(host
, host
->data_cmd
->mrq
);
2455 host
->cmd
->error
= -ETIMEDOUT
;
2456 sdhci_finish_mrq(host
, host
->cmd
->mrq
);
2461 spin_unlock_irqrestore(&host
->lock
, flags
);
2464 /*****************************************************************************\
2466 * Interrupt handling *
2468 \*****************************************************************************/
2470 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
2474 * SDHCI recovers from errors by resetting the cmd and data
2475 * circuits. Until that is done, there very well might be more
2476 * interrupts, so ignore them in that case.
2478 if (host
->pending_reset
)
2480 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2481 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2482 sdhci_dumpregs(host
);
2486 if (intmask
& (SDHCI_INT_TIMEOUT
| SDHCI_INT_CRC
|
2487 SDHCI_INT_END_BIT
| SDHCI_INT_INDEX
)) {
2488 if (intmask
& SDHCI_INT_TIMEOUT
)
2489 host
->cmd
->error
= -ETIMEDOUT
;
2491 host
->cmd
->error
= -EILSEQ
;
2494 * If this command initiates a data phase and a response
2495 * CRC error is signalled, the card can start transferring
2496 * data - the card may have received the command without
2497 * error. We must not terminate the mmc_request early.
2499 * If the card did not receive the command or returned an
2500 * error which prevented it sending data, the data phase
2503 if (host
->cmd
->data
&&
2504 (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
)) ==
2510 sdhci_finish_mrq(host
, host
->cmd
->mrq
);
2514 if (intmask
& SDHCI_INT_RESPONSE
)
2515 sdhci_finish_command(host
);
2518 static void sdhci_adma_show_error(struct sdhci_host
*host
)
2520 void *desc
= host
->adma_table
;
2522 sdhci_dumpregs(host
);
2525 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
2527 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2528 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2529 desc
, le32_to_cpu(dma_desc
->addr_hi
),
2530 le32_to_cpu(dma_desc
->addr_lo
),
2531 le16_to_cpu(dma_desc
->len
),
2532 le16_to_cpu(dma_desc
->cmd
));
2534 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2535 desc
, le32_to_cpu(dma_desc
->addr_lo
),
2536 le16_to_cpu(dma_desc
->len
),
2537 le16_to_cpu(dma_desc
->cmd
));
2539 desc
+= host
->desc_sz
;
2541 if (dma_desc
->cmd
& cpu_to_le16(ADMA2_END
))
2546 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2550 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2551 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2552 command
= SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
));
2553 if (command
== MMC_SEND_TUNING_BLOCK
||
2554 command
== MMC_SEND_TUNING_BLOCK_HS200
) {
2555 host
->tuning_done
= 1;
2556 wake_up(&host
->buf_ready_int
);
2562 struct mmc_command
*data_cmd
= host
->data_cmd
;
2565 * The "data complete" interrupt is also used to
2566 * indicate that a busy state has ended. See comment
2567 * above in sdhci_cmd_irq().
2569 if (data_cmd
&& (data_cmd
->flags
& MMC_RSP_BUSY
)) {
2570 if (intmask
& SDHCI_INT_DATA_TIMEOUT
) {
2571 host
->data_cmd
= NULL
;
2572 data_cmd
->error
= -ETIMEDOUT
;
2573 sdhci_finish_mrq(host
, data_cmd
->mrq
);
2576 if (intmask
& SDHCI_INT_DATA_END
) {
2577 host
->data_cmd
= NULL
;
2579 * Some cards handle busy-end interrupt
2580 * before the command completed, so make
2581 * sure we do things in the proper order.
2583 if (host
->cmd
== data_cmd
)
2586 sdhci_finish_mrq(host
, data_cmd
->mrq
);
2592 * SDHCI recovers from errors by resetting the cmd and data
2593 * circuits. Until that is done, there very well might be more
2594 * interrupts, so ignore them in that case.
2596 if (host
->pending_reset
)
2599 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2600 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2601 sdhci_dumpregs(host
);
2606 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2607 host
->data
->error
= -ETIMEDOUT
;
2608 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2609 host
->data
->error
= -EILSEQ
;
2610 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2611 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2613 host
->data
->error
= -EILSEQ
;
2614 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2615 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2616 sdhci_adma_show_error(host
);
2617 host
->data
->error
= -EIO
;
2618 if (host
->ops
->adma_workaround
)
2619 host
->ops
->adma_workaround(host
, intmask
);
2622 if (host
->data
->error
)
2623 sdhci_finish_data(host
);
2625 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2626 sdhci_transfer_pio(host
);
2629 * We currently don't do anything fancy with DMA
2630 * boundaries, but as we can't disable the feature
2631 * we need to at least restart the transfer.
2633 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2634 * should return a valid address to continue from, but as
2635 * some controllers are faulty, don't trust them.
2637 if (intmask
& SDHCI_INT_DMA_END
) {
2638 u32 dmastart
, dmanow
;
2639 dmastart
= sg_dma_address(host
->data
->sg
);
2640 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2642 * Force update to the next DMA block boundary.
2645 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2646 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2647 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2648 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2649 dmastart
, host
->data
->bytes_xfered
, dmanow
);
2650 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2653 if (intmask
& SDHCI_INT_DATA_END
) {
2654 if (host
->cmd
== host
->data_cmd
) {
2656 * Data managed to finish before the
2657 * command completed. Make sure we do
2658 * things in the proper order.
2660 host
->data_early
= 1;
2662 sdhci_finish_data(host
);
2668 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2670 irqreturn_t result
= IRQ_NONE
;
2671 struct sdhci_host
*host
= dev_id
;
2672 u32 intmask
, mask
, unexpected
= 0;
2675 spin_lock(&host
->lock
);
2677 if (host
->runtime_suspended
&& !sdhci_sdio_irq_enabled(host
)) {
2678 spin_unlock(&host
->lock
);
2682 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2683 if (!intmask
|| intmask
== 0xffffffff) {
2689 DBG("IRQ status 0x%08x\n", intmask
);
2691 if (host
->ops
->irq
) {
2692 intmask
= host
->ops
->irq(host
, intmask
);
2697 /* Clear selected interrupts. */
2698 mask
= intmask
& (SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2699 SDHCI_INT_BUS_POWER
);
2700 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
2702 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2703 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2707 * There is a observation on i.mx esdhc. INSERT
2708 * bit will be immediately set again when it gets
2709 * cleared, if a card is inserted. We have to mask
2710 * the irq to prevent interrupt storm which will
2711 * freeze the system. And the REMOVE gets the
2714 * More testing are needed here to ensure it works
2715 * for other platforms though.
2717 host
->ier
&= ~(SDHCI_INT_CARD_INSERT
|
2718 SDHCI_INT_CARD_REMOVE
);
2719 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
2720 SDHCI_INT_CARD_INSERT
;
2721 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2722 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2724 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2725 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2727 host
->thread_isr
|= intmask
& (SDHCI_INT_CARD_INSERT
|
2728 SDHCI_INT_CARD_REMOVE
);
2729 result
= IRQ_WAKE_THREAD
;
2732 if (intmask
& SDHCI_INT_CMD_MASK
)
2733 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
2735 if (intmask
& SDHCI_INT_DATA_MASK
)
2736 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2738 if (intmask
& SDHCI_INT_BUS_POWER
)
2739 pr_err("%s: Card is consuming too much power!\n",
2740 mmc_hostname(host
->mmc
));
2742 if (intmask
& SDHCI_INT_RETUNE
)
2743 mmc_retune_needed(host
->mmc
);
2745 if ((intmask
& SDHCI_INT_CARD_INT
) &&
2746 (host
->ier
& SDHCI_INT_CARD_INT
)) {
2747 sdhci_enable_sdio_irq_nolock(host
, false);
2748 host
->thread_isr
|= SDHCI_INT_CARD_INT
;
2749 result
= IRQ_WAKE_THREAD
;
2752 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2753 SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2754 SDHCI_INT_ERROR
| SDHCI_INT_BUS_POWER
|
2755 SDHCI_INT_RETUNE
| SDHCI_INT_CARD_INT
);
2758 unexpected
|= intmask
;
2759 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2762 if (result
== IRQ_NONE
)
2763 result
= IRQ_HANDLED
;
2765 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2766 } while (intmask
&& --max_loops
);
2768 spin_unlock(&host
->lock
);
2771 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2772 mmc_hostname(host
->mmc
), unexpected
);
2773 sdhci_dumpregs(host
);
2779 static irqreturn_t
sdhci_thread_irq(int irq
, void *dev_id
)
2781 struct sdhci_host
*host
= dev_id
;
2782 unsigned long flags
;
2785 spin_lock_irqsave(&host
->lock
, flags
);
2786 isr
= host
->thread_isr
;
2787 host
->thread_isr
= 0;
2788 spin_unlock_irqrestore(&host
->lock
, flags
);
2790 if (isr
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2791 struct mmc_host
*mmc
= host
->mmc
;
2793 mmc
->ops
->card_event(mmc
);
2794 mmc_detect_change(mmc
, msecs_to_jiffies(200));
2797 if (isr
& SDHCI_INT_CARD_INT
) {
2798 sdio_run_irqs(host
->mmc
);
2800 spin_lock_irqsave(&host
->lock
, flags
);
2801 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2802 sdhci_enable_sdio_irq_nolock(host
, true);
2803 spin_unlock_irqrestore(&host
->lock
, flags
);
2806 return isr
? IRQ_HANDLED
: IRQ_NONE
;
2809 /*****************************************************************************\
2813 \*****************************************************************************/
2817 * To enable wakeup events, the corresponding events have to be enabled in
2818 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2819 * Table' in the SD Host Controller Standard Specification.
2820 * It is useless to restore SDHCI_INT_ENABLE state in
2821 * sdhci_disable_irq_wakeups() since it will be set by
2822 * sdhci_enable_card_detection() or sdhci_init().
2824 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2827 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2828 | SDHCI_WAKE_ON_INT
;
2829 u32 irq_val
= SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2832 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2834 /* Avoid fake wake up */
2835 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) {
2836 val
&= ~(SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
);
2837 irq_val
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
2839 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2840 sdhci_writel(host
, irq_val
, SDHCI_INT_ENABLE
);
2842 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2844 static void sdhci_disable_irq_wakeups(struct sdhci_host
*host
)
2847 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2848 | SDHCI_WAKE_ON_INT
;
2850 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2852 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2855 int sdhci_suspend_host(struct sdhci_host
*host
)
2857 sdhci_disable_card_detection(host
);
2859 mmc_retune_timer_stop(host
->mmc
);
2861 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2863 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
2864 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
2865 free_irq(host
->irq
, host
);
2867 sdhci_enable_irq_wakeups(host
);
2868 enable_irq_wake(host
->irq
);
2873 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2875 int sdhci_resume_host(struct sdhci_host
*host
)
2877 struct mmc_host
*mmc
= host
->mmc
;
2880 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2881 if (host
->ops
->enable_dma
)
2882 host
->ops
->enable_dma(host
);
2885 if ((host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) &&
2886 (host
->quirks2
& SDHCI_QUIRK2_HOST_OFF_CARD_ON
)) {
2887 /* Card keeps power but host controller does not */
2888 sdhci_init(host
, 0);
2891 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
2893 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2897 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2898 ret
= request_threaded_irq(host
->irq
, sdhci_irq
,
2899 sdhci_thread_irq
, IRQF_SHARED
,
2900 mmc_hostname(host
->mmc
), host
);
2904 sdhci_disable_irq_wakeups(host
);
2905 disable_irq_wake(host
->irq
);
2908 sdhci_enable_card_detection(host
);
2913 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2915 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2917 unsigned long flags
;
2919 mmc_retune_timer_stop(host
->mmc
);
2921 spin_lock_irqsave(&host
->lock
, flags
);
2922 host
->ier
&= SDHCI_INT_CARD_INT
;
2923 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2924 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2925 spin_unlock_irqrestore(&host
->lock
, flags
);
2927 synchronize_hardirq(host
->irq
);
2929 spin_lock_irqsave(&host
->lock
, flags
);
2930 host
->runtime_suspended
= true;
2931 spin_unlock_irqrestore(&host
->lock
, flags
);
2935 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2937 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2939 struct mmc_host
*mmc
= host
->mmc
;
2940 unsigned long flags
;
2941 int host_flags
= host
->flags
;
2943 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2944 if (host
->ops
->enable_dma
)
2945 host
->ops
->enable_dma(host
);
2948 sdhci_init(host
, 0);
2950 if (mmc
->ios
.power_mode
!= MMC_POWER_UNDEFINED
&&
2951 mmc
->ios
.power_mode
!= MMC_POWER_OFF
) {
2952 /* Force clock and power re-program */
2955 mmc
->ops
->start_signal_voltage_switch(mmc
, &mmc
->ios
);
2956 mmc
->ops
->set_ios(mmc
, &mmc
->ios
);
2958 if ((host_flags
& SDHCI_PV_ENABLED
) &&
2959 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)) {
2960 spin_lock_irqsave(&host
->lock
, flags
);
2961 sdhci_enable_preset_value(host
, true);
2962 spin_unlock_irqrestore(&host
->lock
, flags
);
2965 if ((mmc
->caps2
& MMC_CAP2_HS400_ES
) &&
2966 mmc
->ops
->hs400_enhanced_strobe
)
2967 mmc
->ops
->hs400_enhanced_strobe(mmc
, &mmc
->ios
);
2970 spin_lock_irqsave(&host
->lock
, flags
);
2972 host
->runtime_suspended
= false;
2974 /* Enable SDIO IRQ */
2975 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2976 sdhci_enable_sdio_irq_nolock(host
, true);
2978 /* Enable Card Detection */
2979 sdhci_enable_card_detection(host
);
2981 spin_unlock_irqrestore(&host
->lock
, flags
);
2985 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2987 #endif /* CONFIG_PM */
2989 /*****************************************************************************\
2991 * Command Queue Engine (CQE) helpers *
2993 \*****************************************************************************/
2995 void sdhci_cqe_enable(struct mmc_host
*mmc
)
2997 struct sdhci_host
*host
= mmc_priv(mmc
);
2998 unsigned long flags
;
3001 spin_lock_irqsave(&host
->lock
, flags
);
3003 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
3004 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
3005 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
3006 ctrl
|= SDHCI_CTRL_ADMA64
;
3008 ctrl
|= SDHCI_CTRL_ADMA32
;
3009 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
3011 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(host
->sdma_boundary
, 512),
3014 /* Set maximum timeout */
3015 sdhci_writeb(host
, 0xE, SDHCI_TIMEOUT_CONTROL
);
3017 host
->ier
= host
->cqe_ier
;
3019 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
3020 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
3022 host
->cqe_on
= true;
3024 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3025 mmc_hostname(mmc
), host
->ier
,
3026 sdhci_readl(host
, SDHCI_INT_STATUS
));
3029 spin_unlock_irqrestore(&host
->lock
, flags
);
3031 EXPORT_SYMBOL_GPL(sdhci_cqe_enable
);
3033 void sdhci_cqe_disable(struct mmc_host
*mmc
, bool recovery
)
3035 struct sdhci_host
*host
= mmc_priv(mmc
);
3036 unsigned long flags
;
3038 spin_lock_irqsave(&host
->lock
, flags
);
3040 sdhci_set_default_irqs(host
);
3042 host
->cqe_on
= false;
3045 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
3046 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
3049 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3050 mmc_hostname(mmc
), host
->ier
,
3051 sdhci_readl(host
, SDHCI_INT_STATUS
));
3054 spin_unlock_irqrestore(&host
->lock
, flags
);
3056 EXPORT_SYMBOL_GPL(sdhci_cqe_disable
);
3058 bool sdhci_cqe_irq(struct sdhci_host
*host
, u32 intmask
, int *cmd_error
,
3066 if (intmask
& (SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
))
3067 *cmd_error
= -EILSEQ
;
3068 else if (intmask
& SDHCI_INT_TIMEOUT
)
3069 *cmd_error
= -ETIMEDOUT
;
3073 if (intmask
& (SDHCI_INT_DATA_END_BIT
| SDHCI_INT_DATA_CRC
))
3074 *data_error
= -EILSEQ
;
3075 else if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
3076 *data_error
= -ETIMEDOUT
;
3077 else if (intmask
& SDHCI_INT_ADMA_ERROR
)
3082 /* Clear selected interrupts. */
3083 mask
= intmask
& host
->cqe_ier
;
3084 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
3086 if (intmask
& SDHCI_INT_BUS_POWER
)
3087 pr_err("%s: Card is consuming too much power!\n",
3088 mmc_hostname(host
->mmc
));
3090 intmask
&= ~(host
->cqe_ier
| SDHCI_INT_ERROR
);
3092 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
3093 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3094 mmc_hostname(host
->mmc
), intmask
);
3095 sdhci_dumpregs(host
);
3100 EXPORT_SYMBOL_GPL(sdhci_cqe_irq
);
3102 /*****************************************************************************\
3104 * Device allocation/registration *
3106 \*****************************************************************************/
3108 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
3111 struct mmc_host
*mmc
;
3112 struct sdhci_host
*host
;
3114 WARN_ON(dev
== NULL
);
3116 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
3118 return ERR_PTR(-ENOMEM
);
3120 host
= mmc_priv(mmc
);
3122 host
->mmc_host_ops
= sdhci_ops
;
3123 mmc
->ops
= &host
->mmc_host_ops
;
3125 host
->flags
= SDHCI_SIGNALING_330
;
3127 host
->cqe_ier
= SDHCI_CQE_INT_MASK
;
3128 host
->cqe_err_ier
= SDHCI_CQE_INT_ERR_MASK
;
3130 host
->tuning_delay
= -1;
3132 host
->sdma_boundary
= SDHCI_DEFAULT_BOUNDARY_ARG
;
3137 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
3139 static int sdhci_set_dma_mask(struct sdhci_host
*host
)
3141 struct mmc_host
*mmc
= host
->mmc
;
3142 struct device
*dev
= mmc_dev(mmc
);
3145 if (host
->quirks2
& SDHCI_QUIRK2_BROKEN_64_BIT_DMA
)
3146 host
->flags
&= ~SDHCI_USE_64_BIT_DMA
;
3148 /* Try 64-bit mask if hardware is capable of it */
3149 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
3150 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(64));
3152 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3154 host
->flags
&= ~SDHCI_USE_64_BIT_DMA
;
3158 /* 32-bit mask as default & fallback */
3160 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
3162 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3169 void __sdhci_read_caps(struct sdhci_host
*host
, u16
*ver
, u32
*caps
, u32
*caps1
)
3172 u64 dt_caps_mask
= 0;
3175 if (host
->read_caps
)
3178 host
->read_caps
= true;
3181 host
->quirks
= debug_quirks
;
3184 host
->quirks2
= debug_quirks2
;
3186 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3188 of_property_read_u64(mmc_dev(host
->mmc
)->of_node
,
3189 "sdhci-caps-mask", &dt_caps_mask
);
3190 of_property_read_u64(mmc_dev(host
->mmc
)->of_node
,
3191 "sdhci-caps", &dt_caps
);
3193 v
= ver
? *ver
: sdhci_readw(host
, SDHCI_HOST_VERSION
);
3194 host
->version
= (v
& SDHCI_SPEC_VER_MASK
) >> SDHCI_SPEC_VER_SHIFT
;
3196 if (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
)
3202 host
->caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
3203 host
->caps
&= ~lower_32_bits(dt_caps_mask
);
3204 host
->caps
|= lower_32_bits(dt_caps
);
3207 if (host
->version
< SDHCI_SPEC_300
)
3211 host
->caps1
= *caps1
;
3213 host
->caps1
= sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
3214 host
->caps1
&= ~upper_32_bits(dt_caps_mask
);
3215 host
->caps1
|= upper_32_bits(dt_caps
);
3218 EXPORT_SYMBOL_GPL(__sdhci_read_caps
);
3220 int sdhci_setup_host(struct sdhci_host
*host
)
3222 struct mmc_host
*mmc
;
3223 u32 max_current_caps
;
3224 unsigned int ocr_avail
;
3225 unsigned int override_timeout_clk
;
3229 WARN_ON(host
== NULL
);
3236 * If there are external regulators, get them. Note this must be done
3237 * early before resetting the host and reading the capabilities so that
3238 * the host can take the appropriate action if regulators are not
3241 ret
= mmc_regulator_get_supply(mmc
);
3245 DBG("Version: 0x%08x | Present: 0x%08x\n",
3246 sdhci_readw(host
, SDHCI_HOST_VERSION
),
3247 sdhci_readl(host
, SDHCI_PRESENT_STATE
));
3248 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3249 sdhci_readl(host
, SDHCI_CAPABILITIES
),
3250 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
3252 sdhci_read_caps(host
);
3254 override_timeout_clk
= host
->timeout_clk
;
3256 if (host
->version
> SDHCI_SPEC_300
) {
3257 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3258 mmc_hostname(mmc
), host
->version
);
3261 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
3262 host
->flags
|= SDHCI_USE_SDMA
;
3263 else if (!(host
->caps
& SDHCI_CAN_DO_SDMA
))
3264 DBG("Controller doesn't have SDMA capability\n");
3266 host
->flags
|= SDHCI_USE_SDMA
;
3268 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
3269 (host
->flags
& SDHCI_USE_SDMA
)) {
3270 DBG("Disabling DMA as it is marked broken\n");
3271 host
->flags
&= ~SDHCI_USE_SDMA
;
3274 if ((host
->version
>= SDHCI_SPEC_200
) &&
3275 (host
->caps
& SDHCI_CAN_DO_ADMA2
))
3276 host
->flags
|= SDHCI_USE_ADMA
;
3278 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
3279 (host
->flags
& SDHCI_USE_ADMA
)) {
3280 DBG("Disabling ADMA as it is marked broken\n");
3281 host
->flags
&= ~SDHCI_USE_ADMA
;
3285 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3286 * and *must* do 64-bit DMA. A driver has the opportunity to change
3287 * that during the first call to ->enable_dma(). Similarly
3288 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3291 if (host
->caps
& SDHCI_CAN_64BIT
)
3292 host
->flags
|= SDHCI_USE_64_BIT_DMA
;
3294 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
3295 ret
= sdhci_set_dma_mask(host
);
3297 if (!ret
&& host
->ops
->enable_dma
)
3298 ret
= host
->ops
->enable_dma(host
);
3301 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3303 host
->flags
&= ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
3309 /* SDMA does not support 64-bit DMA */
3310 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
3311 host
->flags
&= ~SDHCI_USE_SDMA
;
3313 if (host
->flags
& SDHCI_USE_ADMA
) {
3318 * The DMA descriptor table size is calculated as the maximum
3319 * number of segments times 2, to allow for an alignment
3320 * descriptor for each segment, plus 1 for a nop end descriptor,
3321 * all multipled by the descriptor size.
3323 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
3324 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
3325 SDHCI_ADMA2_64_DESC_SZ
;
3326 host
->desc_sz
= SDHCI_ADMA2_64_DESC_SZ
;
3328 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
3329 SDHCI_ADMA2_32_DESC_SZ
;
3330 host
->desc_sz
= SDHCI_ADMA2_32_DESC_SZ
;
3333 host
->align_buffer_sz
= SDHCI_MAX_SEGS
* SDHCI_ADMA2_ALIGN
;
3334 buf
= dma_alloc_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3335 host
->adma_table_sz
, &dma
, GFP_KERNEL
);
3337 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3339 host
->flags
&= ~SDHCI_USE_ADMA
;
3340 } else if ((dma
+ host
->align_buffer_sz
) &
3341 (SDHCI_ADMA2_DESC_ALIGN
- 1)) {
3342 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3344 host
->flags
&= ~SDHCI_USE_ADMA
;
3345 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3346 host
->adma_table_sz
, buf
, dma
);
3348 host
->align_buffer
= buf
;
3349 host
->align_addr
= dma
;
3351 host
->adma_table
= buf
+ host
->align_buffer_sz
;
3352 host
->adma_addr
= dma
+ host
->align_buffer_sz
;
3357 * If we use DMA, then it's up to the caller to set the DMA
3358 * mask, but PIO does not need the hw shim so we set a new
3359 * mask here in that case.
3361 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
3362 host
->dma_mask
= DMA_BIT_MASK(64);
3363 mmc_dev(mmc
)->dma_mask
= &host
->dma_mask
;
3366 if (host
->version
>= SDHCI_SPEC_300
)
3367 host
->max_clk
= (host
->caps
& SDHCI_CLOCK_V3_BASE_MASK
)
3368 >> SDHCI_CLOCK_BASE_SHIFT
;
3370 host
->max_clk
= (host
->caps
& SDHCI_CLOCK_BASE_MASK
)
3371 >> SDHCI_CLOCK_BASE_SHIFT
;
3373 host
->max_clk
*= 1000000;
3374 if (host
->max_clk
== 0 || host
->quirks
&
3375 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
3376 if (!host
->ops
->get_max_clock
) {
3377 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3382 host
->max_clk
= host
->ops
->get_max_clock(host
);
3386 * In case of Host Controller v3.00, find out whether clock
3387 * multiplier is supported.
3389 host
->clk_mul
= (host
->caps1
& SDHCI_CLOCK_MUL_MASK
) >>
3390 SDHCI_CLOCK_MUL_SHIFT
;
3393 * In case the value in Clock Multiplier is 0, then programmable
3394 * clock mode is not supported, otherwise the actual clock
3395 * multiplier is one more than the value of Clock Multiplier
3396 * in the Capabilities Register.
3402 * Set host parameters.
3404 max_clk
= host
->max_clk
;
3406 if (host
->ops
->get_min_clock
)
3407 mmc
->f_min
= host
->ops
->get_min_clock(host
);
3408 else if (host
->version
>= SDHCI_SPEC_300
) {
3409 if (host
->clk_mul
) {
3410 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
3411 max_clk
= host
->max_clk
* host
->clk_mul
;
3413 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
3415 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
3417 if (!mmc
->f_max
|| mmc
->f_max
> max_clk
)
3418 mmc
->f_max
= max_clk
;
3420 if (!(host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
3421 host
->timeout_clk
= (host
->caps
& SDHCI_TIMEOUT_CLK_MASK
) >>
3422 SDHCI_TIMEOUT_CLK_SHIFT
;
3424 if (host
->caps
& SDHCI_TIMEOUT_CLK_UNIT
)
3425 host
->timeout_clk
*= 1000;
3427 if (host
->timeout_clk
== 0) {
3428 if (!host
->ops
->get_timeout_clock
) {
3429 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3436 DIV_ROUND_UP(host
->ops
->get_timeout_clock(host
),
3440 if (override_timeout_clk
)
3441 host
->timeout_clk
= override_timeout_clk
;
3443 mmc
->max_busy_timeout
= host
->ops
->get_max_timeout_count
?
3444 host
->ops
->get_max_timeout_count(host
) : 1 << 27;
3445 mmc
->max_busy_timeout
/= host
->timeout_clk
;
3448 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
3449 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
3451 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
3452 host
->flags
|= SDHCI_AUTO_CMD12
;
3454 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3455 if ((host
->version
>= SDHCI_SPEC_300
) &&
3456 ((host
->flags
& SDHCI_USE_ADMA
) ||
3457 !(host
->flags
& SDHCI_USE_SDMA
)) &&
3458 !(host
->quirks2
& SDHCI_QUIRK2_ACMD23_BROKEN
)) {
3459 host
->flags
|= SDHCI_AUTO_CMD23
;
3460 DBG("Auto-CMD23 available\n");
3462 DBG("Auto-CMD23 unavailable\n");
3466 * A controller may support 8-bit width, but the board itself
3467 * might not have the pins brought out. Boards that support
3468 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3469 * their platform code before calling sdhci_add_host(), and we
3470 * won't assume 8-bit width for hosts without that CAP.
3472 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
3473 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
3475 if (host
->quirks2
& SDHCI_QUIRK2_HOST_NO_CMD23
)
3476 mmc
->caps
&= ~MMC_CAP_CMD23
;
3478 if (host
->caps
& SDHCI_CAN_DO_HISPD
)
3479 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
3481 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
3482 mmc_card_is_removable(mmc
) &&
3483 mmc_gpio_get_cd(host
->mmc
) < 0)
3484 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
3486 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3487 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
3488 ret
= regulator_enable(mmc
->supply
.vqmmc
);
3489 if (!regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1700000,
3491 host
->caps1
&= ~(SDHCI_SUPPORT_SDR104
|
3492 SDHCI_SUPPORT_SDR50
|
3493 SDHCI_SUPPORT_DDR50
);
3495 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3496 mmc_hostname(mmc
), ret
);
3497 mmc
->supply
.vqmmc
= ERR_PTR(-EINVAL
);
3501 if (host
->quirks2
& SDHCI_QUIRK2_NO_1_8_V
) {
3502 host
->caps1
&= ~(SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3503 SDHCI_SUPPORT_DDR50
);
3506 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3507 if (host
->caps1
& (SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3508 SDHCI_SUPPORT_DDR50
))
3509 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
3511 /* SDR104 supports also implies SDR50 support */
3512 if (host
->caps1
& SDHCI_SUPPORT_SDR104
) {
3513 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
3514 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3515 * field can be promoted to support HS200.
3517 if (!(host
->quirks2
& SDHCI_QUIRK2_BROKEN_HS200
))
3518 mmc
->caps2
|= MMC_CAP2_HS200
;
3519 } else if (host
->caps1
& SDHCI_SUPPORT_SDR50
) {
3520 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
3523 if (host
->quirks2
& SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400
&&
3524 (host
->caps1
& SDHCI_SUPPORT_HS400
))
3525 mmc
->caps2
|= MMC_CAP2_HS400
;
3527 if ((mmc
->caps2
& MMC_CAP2_HSX00_1_2V
) &&
3528 (IS_ERR(mmc
->supply
.vqmmc
) ||
3529 !regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1100000,
3531 mmc
->caps2
&= ~MMC_CAP2_HSX00_1_2V
;
3533 if ((host
->caps1
& SDHCI_SUPPORT_DDR50
) &&
3534 !(host
->quirks2
& SDHCI_QUIRK2_BROKEN_DDR50
))
3535 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
3537 /* Does the host need tuning for SDR50? */
3538 if (host
->caps1
& SDHCI_USE_SDR50_TUNING
)
3539 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
3541 /* Driver Type(s) (A, C, D) supported by the host */
3542 if (host
->caps1
& SDHCI_DRIVER_TYPE_A
)
3543 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
3544 if (host
->caps1
& SDHCI_DRIVER_TYPE_C
)
3545 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
3546 if (host
->caps1
& SDHCI_DRIVER_TYPE_D
)
3547 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
3549 /* Initial value for re-tuning timer count */
3550 host
->tuning_count
= (host
->caps1
& SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
3551 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
3554 * In case Re-tuning Timer is not disabled, the actual value of
3555 * re-tuning timer will be 2 ^ (n - 1).
3557 if (host
->tuning_count
)
3558 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
3560 /* Re-tuning mode supported by the Host Controller */
3561 host
->tuning_mode
= (host
->caps1
& SDHCI_RETUNING_MODE_MASK
) >>
3562 SDHCI_RETUNING_MODE_SHIFT
;
3567 * According to SD Host Controller spec v3.00, if the Host System
3568 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3569 * the value is meaningful only if Voltage Support in the Capabilities
3570 * register is set. The actual current value is 4 times the register
3573 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
3574 if (!max_current_caps
&& !IS_ERR(mmc
->supply
.vmmc
)) {
3575 int curr
= regulator_get_current_limit(mmc
->supply
.vmmc
);
3578 /* convert to SDHCI_MAX_CURRENT format */
3579 curr
= curr
/1000; /* convert to mA */
3580 curr
= curr
/SDHCI_MAX_CURRENT_MULTIPLIER
;
3582 curr
= min_t(u32
, curr
, SDHCI_MAX_CURRENT_LIMIT
);
3584 (curr
<< SDHCI_MAX_CURRENT_330_SHIFT
) |
3585 (curr
<< SDHCI_MAX_CURRENT_300_SHIFT
) |
3586 (curr
<< SDHCI_MAX_CURRENT_180_SHIFT
);
3590 if (host
->caps
& SDHCI_CAN_VDD_330
) {
3591 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
3593 mmc
->max_current_330
= ((max_current_caps
&
3594 SDHCI_MAX_CURRENT_330_MASK
) >>
3595 SDHCI_MAX_CURRENT_330_SHIFT
) *
3596 SDHCI_MAX_CURRENT_MULTIPLIER
;
3598 if (host
->caps
& SDHCI_CAN_VDD_300
) {
3599 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
3601 mmc
->max_current_300
= ((max_current_caps
&
3602 SDHCI_MAX_CURRENT_300_MASK
) >>
3603 SDHCI_MAX_CURRENT_300_SHIFT
) *
3604 SDHCI_MAX_CURRENT_MULTIPLIER
;
3606 if (host
->caps
& SDHCI_CAN_VDD_180
) {
3607 ocr_avail
|= MMC_VDD_165_195
;
3609 mmc
->max_current_180
= ((max_current_caps
&
3610 SDHCI_MAX_CURRENT_180_MASK
) >>
3611 SDHCI_MAX_CURRENT_180_SHIFT
) *
3612 SDHCI_MAX_CURRENT_MULTIPLIER
;
3615 /* If OCR set by host, use it instead. */
3617 ocr_avail
= host
->ocr_mask
;
3619 /* If OCR set by external regulators, give it highest prio. */
3621 ocr_avail
= mmc
->ocr_avail
;
3623 mmc
->ocr_avail
= ocr_avail
;
3624 mmc
->ocr_avail_sdio
= ocr_avail
;
3625 if (host
->ocr_avail_sdio
)
3626 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
3627 mmc
->ocr_avail_sd
= ocr_avail
;
3628 if (host
->ocr_avail_sd
)
3629 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
3630 else /* normal SD controllers don't support 1.8V */
3631 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
3632 mmc
->ocr_avail_mmc
= ocr_avail
;
3633 if (host
->ocr_avail_mmc
)
3634 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
3636 if (mmc
->ocr_avail
== 0) {
3637 pr_err("%s: Hardware doesn't report any support voltages.\n",
3643 if ((mmc
->caps
& (MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
|
3644 MMC_CAP_UHS_SDR50
| MMC_CAP_UHS_SDR104
|
3645 MMC_CAP_UHS_DDR50
| MMC_CAP_1_8V_DDR
)) ||
3646 (mmc
->caps2
& (MMC_CAP2_HS200_1_8V_SDR
| MMC_CAP2_HS400_1_8V
)))
3647 host
->flags
|= SDHCI_SIGNALING_180
;
3649 if (mmc
->caps2
& MMC_CAP2_HSX00_1_2V
)
3650 host
->flags
|= SDHCI_SIGNALING_120
;
3652 spin_lock_init(&host
->lock
);
3655 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3656 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3659 mmc
->max_req_size
= 524288;
3662 * Maximum number of segments. Depends on if the hardware
3663 * can do scatter/gather or not.
3665 if (host
->flags
& SDHCI_USE_ADMA
) {
3666 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3667 } else if (host
->flags
& SDHCI_USE_SDMA
) {
3669 if (swiotlb_max_segment()) {
3670 unsigned int max_req_size
= (1 << IO_TLB_SHIFT
) *
3672 mmc
->max_req_size
= min(mmc
->max_req_size
,
3676 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3680 * Maximum segment size. Could be one segment with the maximum number
3681 * of bytes. When doing hardware scatter/gather, each entry cannot
3682 * be larger than 64 KiB though.
3684 if (host
->flags
& SDHCI_USE_ADMA
) {
3685 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
3686 mmc
->max_seg_size
= 65535;
3688 mmc
->max_seg_size
= 65536;
3690 mmc
->max_seg_size
= mmc
->max_req_size
;
3694 * Maximum block size. This varies from controller to controller and
3695 * is specified in the capabilities register.
3697 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
3698 mmc
->max_blk_size
= 2;
3700 mmc
->max_blk_size
= (host
->caps
& SDHCI_MAX_BLOCK_MASK
) >>
3701 SDHCI_MAX_BLOCK_SHIFT
;
3702 if (mmc
->max_blk_size
>= 3) {
3703 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3705 mmc
->max_blk_size
= 0;
3709 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
3712 * Maximum block count.
3714 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
3719 if (!IS_ERR(mmc
->supply
.vqmmc
))
3720 regulator_disable(mmc
->supply
.vqmmc
);
3722 if (host
->align_buffer
)
3723 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3724 host
->adma_table_sz
, host
->align_buffer
,
3726 host
->adma_table
= NULL
;
3727 host
->align_buffer
= NULL
;
3731 EXPORT_SYMBOL_GPL(sdhci_setup_host
);
3733 void sdhci_cleanup_host(struct sdhci_host
*host
)
3735 struct mmc_host
*mmc
= host
->mmc
;
3737 if (!IS_ERR(mmc
->supply
.vqmmc
))
3738 regulator_disable(mmc
->supply
.vqmmc
);
3740 if (host
->align_buffer
)
3741 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3742 host
->adma_table_sz
, host
->align_buffer
,
3744 host
->adma_table
= NULL
;
3745 host
->align_buffer
= NULL
;
3747 EXPORT_SYMBOL_GPL(sdhci_cleanup_host
);
3749 int __sdhci_add_host(struct sdhci_host
*host
)
3751 struct mmc_host
*mmc
= host
->mmc
;
3757 tasklet_init(&host
->finish_tasklet
,
3758 sdhci_tasklet_finish
, (unsigned long)host
);
3760 timer_setup(&host
->timer
, sdhci_timeout_timer
, 0);
3761 timer_setup(&host
->data_timer
, sdhci_timeout_data_timer
, 0);
3763 init_waitqueue_head(&host
->buf_ready_int
);
3765 sdhci_init(host
, 0);
3767 ret
= request_threaded_irq(host
->irq
, sdhci_irq
, sdhci_thread_irq
,
3768 IRQF_SHARED
, mmc_hostname(mmc
), host
);
3770 pr_err("%s: Failed to request IRQ %d: %d\n",
3771 mmc_hostname(mmc
), host
->irq
, ret
);
3775 ret
= sdhci_led_register(host
);
3777 pr_err("%s: Failed to register LED device: %d\n",
3778 mmc_hostname(mmc
), ret
);
3784 ret
= mmc_add_host(mmc
);
3788 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3789 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
3790 (host
->flags
& SDHCI_USE_ADMA
) ?
3791 (host
->flags
& SDHCI_USE_64_BIT_DMA
) ? "ADMA 64-bit" : "ADMA" :
3792 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
3794 sdhci_enable_card_detection(host
);
3799 sdhci_led_unregister(host
);
3801 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3802 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3803 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3804 free_irq(host
->irq
, host
);
3806 tasklet_kill(&host
->finish_tasklet
);
3810 EXPORT_SYMBOL_GPL(__sdhci_add_host
);
3812 int sdhci_add_host(struct sdhci_host
*host
)
3816 ret
= sdhci_setup_host(host
);
3820 ret
= __sdhci_add_host(host
);
3827 sdhci_cleanup_host(host
);
3831 EXPORT_SYMBOL_GPL(sdhci_add_host
);
3833 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
3835 struct mmc_host
*mmc
= host
->mmc
;
3836 unsigned long flags
;
3839 spin_lock_irqsave(&host
->lock
, flags
);
3841 host
->flags
|= SDHCI_DEVICE_DEAD
;
3843 if (sdhci_has_requests(host
)) {
3844 pr_err("%s: Controller removed during "
3845 " transfer!\n", mmc_hostname(mmc
));
3846 sdhci_error_out_mrqs(host
, -ENOMEDIUM
);
3849 spin_unlock_irqrestore(&host
->lock
, flags
);
3852 sdhci_disable_card_detection(host
);
3854 mmc_remove_host(mmc
);
3856 sdhci_led_unregister(host
);
3859 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3861 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3862 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3863 free_irq(host
->irq
, host
);
3865 del_timer_sync(&host
->timer
);
3866 del_timer_sync(&host
->data_timer
);
3868 tasklet_kill(&host
->finish_tasklet
);
3870 if (!IS_ERR(mmc
->supply
.vqmmc
))
3871 regulator_disable(mmc
->supply
.vqmmc
);
3873 if (host
->align_buffer
)
3874 dma_free_coherent(mmc_dev(mmc
), host
->align_buffer_sz
+
3875 host
->adma_table_sz
, host
->align_buffer
,
3878 host
->adma_table
= NULL
;
3879 host
->align_buffer
= NULL
;
3882 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3884 void sdhci_free_host(struct sdhci_host
*host
)
3886 mmc_free_host(host
->mmc
);
3889 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3891 /*****************************************************************************\
3893 * Driver init/exit *
3895 \*****************************************************************************/
3897 static int __init
sdhci_drv_init(void)
3900 ": Secure Digital Host Controller Interface driver\n");
3901 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3906 static void __exit
sdhci_drv_exit(void)
3910 module_init(sdhci_drv_init
);
3911 module_exit(sdhci_drv_exit
);
3913 module_param(debug_quirks
, uint
, 0444);
3914 module_param(debug_quirks2
, uint
, 0444);
3916 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3917 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3918 MODULE_LICENSE("GPL");
3920 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3921 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");