2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
46 #define MAX_TUNING_LOOP 40
48 static unsigned int debug_quirks
= 0;
49 static unsigned int debug_quirks2
;
51 static void sdhci_finish_data(struct sdhci_host
*);
53 static void sdhci_finish_command(struct sdhci_host
*);
54 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
);
55 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
);
56 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
57 struct mmc_data
*data
);
58 static int sdhci_do_get_cd(struct sdhci_host
*host
);
61 static int sdhci_runtime_pm_get(struct sdhci_host
*host
);
62 static int sdhci_runtime_pm_put(struct sdhci_host
*host
);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
);
66 static inline int sdhci_runtime_pm_get(struct sdhci_host
*host
)
70 static inline int sdhci_runtime_pm_put(struct sdhci_host
*host
)
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
82 static void sdhci_dumpregs(struct sdhci_host
*host
)
84 pr_debug(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host
->mmc
));
87 pr_debug(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
89 sdhci_readw(host
, SDHCI_HOST_VERSION
));
90 pr_debug(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
92 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
93 pr_debug(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host
, SDHCI_ARGUMENT
),
95 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
96 pr_debug(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
98 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
99 pr_debug(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
101 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
102 pr_debug(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
104 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
105 pr_debug(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
107 sdhci_readl(host
, SDHCI_INT_STATUS
));
108 pr_debug(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host
, SDHCI_INT_ENABLE
),
110 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
111 pr_debug(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
113 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
114 pr_debug(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host
, SDHCI_CAPABILITIES
),
116 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
117 pr_debug(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host
, SDHCI_COMMAND
),
119 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
120 pr_debug(DRIVER_NAME
": Host ctl2: 0x%08x\n",
121 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
123 if (host
->flags
& SDHCI_USE_ADMA
) {
124 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
125 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
127 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS_HI
),
128 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
130 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
132 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
135 pr_debug(DRIVER_NAME
": ===========================================\n");
138 /*****************************************************************************\
140 * Low level functions *
142 \*****************************************************************************/
144 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
148 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
149 (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
))
153 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
156 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
157 SDHCI_INT_CARD_INSERT
;
159 host
->ier
&= ~(SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
);
162 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
163 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
166 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
168 sdhci_set_card_detection(host
, true);
171 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
173 sdhci_set_card_detection(host
, false);
176 void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
178 unsigned long timeout
;
180 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
182 if (mask
& SDHCI_RESET_ALL
) {
184 /* Reset-all turns off SD Bus Power */
185 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
186 sdhci_runtime_pm_bus_off(host
);
189 /* Wait max 100 ms */
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host
->mmc
), (int)mask
);
197 sdhci_dumpregs(host
);
204 EXPORT_SYMBOL_GPL(sdhci_reset
);
206 static void sdhci_do_reset(struct sdhci_host
*host
, u8 mask
)
208 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
209 if (!sdhci_do_get_cd(host
))
213 host
->ops
->reset(host
, mask
);
215 if (mask
& SDHCI_RESET_ALL
) {
216 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
217 if (host
->ops
->enable_dma
)
218 host
->ops
->enable_dma(host
);
221 /* Resetting the controller clears many */
222 host
->preset_enabled
= false;
226 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
228 static void sdhci_init(struct sdhci_host
*host
, int soft
)
231 sdhci_do_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
233 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
235 host
->ier
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
236 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
|
237 SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
|
238 SDHCI_INT_TIMEOUT
| SDHCI_INT_DATA_END
|
241 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
242 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
245 /* force clock reconfiguration */
247 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
251 static void sdhci_reinit(struct sdhci_host
*host
)
254 sdhci_enable_card_detection(host
);
257 static void sdhci_activate_led(struct sdhci_host
*host
)
261 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
262 ctrl
|= SDHCI_CTRL_LED
;
263 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
266 static void sdhci_deactivate_led(struct sdhci_host
*host
)
270 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
271 ctrl
&= ~SDHCI_CTRL_LED
;
272 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev
*led
,
277 enum led_brightness brightness
)
279 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
282 spin_lock_irqsave(&host
->lock
, flags
);
284 if (host
->runtime_suspended
)
287 if (brightness
== LED_OFF
)
288 sdhci_deactivate_led(host
);
290 sdhci_activate_led(host
);
292 spin_unlock_irqrestore(&host
->lock
, flags
);
296 /*****************************************************************************\
300 \*****************************************************************************/
302 static void sdhci_read_block_pio(struct sdhci_host
*host
)
305 size_t blksize
, len
, chunk
;
306 u32
uninitialized_var(scratch
);
309 DBG("PIO reading\n");
311 blksize
= host
->data
->blksz
;
314 local_irq_save(flags
);
317 BUG_ON(!sg_miter_next(&host
->sg_miter
));
319 len
= min(host
->sg_miter
.length
, blksize
);
322 host
->sg_miter
.consumed
= len
;
324 buf
= host
->sg_miter
.addr
;
328 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
332 *buf
= scratch
& 0xFF;
341 sg_miter_stop(&host
->sg_miter
);
343 local_irq_restore(flags
);
346 static void sdhci_write_block_pio(struct sdhci_host
*host
)
349 size_t blksize
, len
, chunk
;
353 DBG("PIO writing\n");
355 blksize
= host
->data
->blksz
;
359 local_irq_save(flags
);
362 BUG_ON(!sg_miter_next(&host
->sg_miter
));
364 len
= min(host
->sg_miter
.length
, blksize
);
367 host
->sg_miter
.consumed
= len
;
369 buf
= host
->sg_miter
.addr
;
372 scratch
|= (u32
)*buf
<< (chunk
* 8);
378 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
379 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
386 sg_miter_stop(&host
->sg_miter
);
388 local_irq_restore(flags
);
391 static void sdhci_transfer_pio(struct sdhci_host
*host
)
397 if (host
->blocks
== 0)
400 if (host
->data
->flags
& MMC_DATA_READ
)
401 mask
= SDHCI_DATA_AVAILABLE
;
403 mask
= SDHCI_SPACE_AVAILABLE
;
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
410 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
411 (host
->data
->blocks
== 1))
414 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
415 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
418 if (host
->data
->flags
& MMC_DATA_READ
)
419 sdhci_read_block_pio(host
);
421 sdhci_write_block_pio(host
);
424 if (host
->blocks
== 0)
428 DBG("PIO transfer complete.\n");
431 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
433 local_irq_save(*flags
);
434 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
437 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
439 kunmap_atomic(buffer
);
440 local_irq_restore(*flags
);
443 static void sdhci_adma_write_desc(struct sdhci_host
*host
, void *desc
,
444 dma_addr_t addr
, int len
, unsigned cmd
)
446 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc
->cmd
= cpu_to_le16(cmd
);
450 dma_desc
->len
= cpu_to_le16(len
);
451 dma_desc
->addr_lo
= cpu_to_le32((u32
)addr
);
453 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
454 dma_desc
->addr_hi
= cpu_to_le32((u64
)addr
>> 32);
457 static void sdhci_adma_mark_end(void *desc
)
459 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc
->cmd
|= cpu_to_le16(ADMA2_END
);
465 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
466 struct mmc_data
*data
)
473 dma_addr_t align_addr
;
476 struct scatterlist
*sg
;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data
->flags
& MMC_DATA_READ
)
487 direction
= DMA_FROM_DEVICE
;
489 direction
= DMA_TO_DEVICE
;
491 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
492 host
->align_buffer
, host
->align_buffer_sz
, direction
);
493 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
495 BUG_ON(host
->align_addr
& host
->align_mask
);
497 host
->sg_count
= sdhci_pre_dma_transfer(host
, data
);
498 if (host
->sg_count
< 0)
501 desc
= host
->adma_table
;
502 align
= host
->align_buffer
;
504 align_addr
= host
->align_addr
;
506 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
507 addr
= sg_dma_address(sg
);
508 len
= sg_dma_len(sg
);
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
517 offset
= (host
->align_sz
- (addr
& host
->align_mask
)) &
520 if (data
->flags
& MMC_DATA_WRITE
) {
521 buffer
= sdhci_kmap_atomic(sg
, &flags
);
522 memcpy(align
, buffer
, offset
);
523 sdhci_kunmap_atomic(buffer
, &flags
);
527 sdhci_adma_write_desc(host
, desc
, align_addr
, offset
,
530 BUG_ON(offset
> 65536);
532 align
+= host
->align_sz
;
533 align_addr
+= host
->align_sz
;
535 desc
+= host
->desc_sz
;
544 sdhci_adma_write_desc(host
, desc
, addr
, len
, ADMA2_TRAN_VALID
);
545 desc
+= host
->desc_sz
;
548 * If this triggers then we have a calculation bug
551 WARN_ON((desc
- host
->adma_table
) >= host
->adma_table_sz
);
554 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
556 * Mark the last descriptor as the terminating descriptor
558 if (desc
!= host
->adma_table
) {
559 desc
-= host
->desc_sz
;
560 sdhci_adma_mark_end(desc
);
564 * Add a terminating entry.
567 /* nop, end, valid */
568 sdhci_adma_write_desc(host
, desc
, 0, 0, ADMA2_NOP_END_VALID
);
572 * Resync align buffer as we might have changed it.
574 if (data
->flags
& MMC_DATA_WRITE
) {
575 dma_sync_single_for_device(mmc_dev(host
->mmc
),
576 host
->align_addr
, host
->align_buffer_sz
, direction
);
582 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
583 host
->align_buffer_sz
, direction
);
588 static void sdhci_adma_table_post(struct sdhci_host
*host
,
589 struct mmc_data
*data
)
593 struct scatterlist
*sg
;
600 if (data
->flags
& MMC_DATA_READ
)
601 direction
= DMA_FROM_DEVICE
;
603 direction
= DMA_TO_DEVICE
;
605 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
606 host
->align_buffer_sz
, direction
);
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned
= false;
610 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
)
611 if (sg_dma_address(sg
) & host
->align_mask
) {
612 has_unaligned
= true;
616 if (has_unaligned
&& data
->flags
& MMC_DATA_READ
) {
617 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
618 data
->sg_len
, direction
);
620 align
= host
->align_buffer
;
622 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
623 if (sg_dma_address(sg
) & host
->align_mask
) {
624 size
= host
->align_sz
-
625 (sg_dma_address(sg
) & host
->align_mask
);
627 buffer
= sdhci_kmap_atomic(sg
, &flags
);
628 memcpy(buffer
, align
, size
);
629 sdhci_kunmap_atomic(buffer
, &flags
);
631 align
+= host
->align_sz
;
636 if (data
->host_cookie
== COOKIE_MAPPED
) {
637 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
638 data
->sg_len
, direction
);
639 data
->host_cookie
= COOKIE_UNMAPPED
;
643 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
646 struct mmc_data
*data
= cmd
->data
;
647 unsigned target_timeout
, current_timeout
;
650 * If the host controller provides us with an incorrect timeout
651 * value, just skip the check and use 0xE. The hardware may take
652 * longer to time out, but that's much better than having a too-short
655 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
658 /* Unspecified timeout, assume max */
659 if (!data
&& !cmd
->busy_timeout
)
664 target_timeout
= cmd
->busy_timeout
* 1000;
666 target_timeout
= data
->timeout_ns
/ 1000;
668 target_timeout
+= data
->timeout_clks
/ host
->clock
;
672 * Figure out needed cycles.
673 * We do this in steps in order to fit inside a 32 bit int.
674 * The first step is the minimum timeout, which will have a
675 * minimum resolution of 6 bits:
676 * (1) 2^13*1000 > 2^22,
677 * (2) host->timeout_clk < 2^16
682 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
683 while (current_timeout
< target_timeout
) {
685 current_timeout
<<= 1;
691 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
692 mmc_hostname(host
->mmc
), count
, cmd
->opcode
);
699 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
701 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
702 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
704 if (host
->flags
& SDHCI_REQ_USE_DMA
)
705 host
->ier
= (host
->ier
& ~pio_irqs
) | dma_irqs
;
707 host
->ier
= (host
->ier
& ~dma_irqs
) | pio_irqs
;
709 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
710 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
713 static void sdhci_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
717 if (host
->ops
->set_timeout
) {
718 host
->ops
->set_timeout(host
, cmd
);
720 count
= sdhci_calc_timeout(host
, cmd
);
721 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
725 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
728 struct mmc_data
*data
= cmd
->data
;
733 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
))
734 sdhci_set_timeout(host
, cmd
);
740 BUG_ON(data
->blksz
* data
->blocks
> 524288);
741 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
742 BUG_ON(data
->blocks
> 65535);
745 host
->data_early
= 0;
746 host
->data
->bytes_xfered
= 0;
748 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
749 host
->flags
|= SDHCI_REQ_USE_DMA
;
752 * FIXME: This doesn't account for merging when mapping the
755 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
757 struct scatterlist
*sg
;
760 if (host
->flags
& SDHCI_USE_ADMA
) {
761 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
764 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
768 if (unlikely(broken
)) {
769 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
770 if (sg
->length
& 0x3) {
771 DBG("Reverting to PIO because of "
772 "transfer size (%d)\n",
774 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
782 * The assumption here being that alignment is the same after
783 * translation to device address space.
785 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
787 struct scatterlist
*sg
;
790 if (host
->flags
& SDHCI_USE_ADMA
) {
792 * As we use 3 byte chunks to work around
793 * alignment problems, we need to check this
796 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
799 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
803 if (unlikely(broken
)) {
804 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
805 if (sg
->offset
& 0x3) {
806 DBG("Reverting to PIO because of "
808 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
815 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
816 if (host
->flags
& SDHCI_USE_ADMA
) {
817 ret
= sdhci_adma_table_pre(host
, data
);
820 * This only happens when someone fed
821 * us an invalid request.
824 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
826 sdhci_writel(host
, host
->adma_addr
,
828 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
830 (u64
)host
->adma_addr
>> 32,
831 SDHCI_ADMA_ADDRESS_HI
);
836 sg_cnt
= sdhci_pre_dma_transfer(host
, data
);
839 * This only happens when someone fed
840 * us an invalid request.
843 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
845 WARN_ON(sg_cnt
!= 1);
846 sdhci_writel(host
, sg_dma_address(data
->sg
),
853 * Always adjust the DMA selection as some controllers
854 * (e.g. JMicron) can't do PIO properly when the selection
857 if (host
->version
>= SDHCI_SPEC_200
) {
858 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
859 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
860 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
861 (host
->flags
& SDHCI_USE_ADMA
)) {
862 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
863 ctrl
|= SDHCI_CTRL_ADMA64
;
865 ctrl
|= SDHCI_CTRL_ADMA32
;
867 ctrl
|= SDHCI_CTRL_SDMA
;
869 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
872 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
875 flags
= SG_MITER_ATOMIC
;
876 if (host
->data
->flags
& MMC_DATA_READ
)
877 flags
|= SG_MITER_TO_SG
;
879 flags
|= SG_MITER_FROM_SG
;
880 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
881 host
->blocks
= data
->blocks
;
884 sdhci_set_transfer_irqs(host
);
886 /* Set the DMA boundary value and block size */
887 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
888 data
->blksz
), SDHCI_BLOCK_SIZE
);
889 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
892 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
893 struct mmc_command
*cmd
)
896 struct mmc_data
*data
= cmd
->data
;
900 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD
) {
901 sdhci_writew(host
, 0x0, SDHCI_TRANSFER_MODE
);
903 /* clear Auto CMD settings for no data CMDs */
904 mode
= sdhci_readw(host
, SDHCI_TRANSFER_MODE
);
905 sdhci_writew(host
, mode
& ~(SDHCI_TRNS_AUTO_CMD12
|
906 SDHCI_TRNS_AUTO_CMD23
), SDHCI_TRANSFER_MODE
);
911 WARN_ON(!host
->data
);
913 if (!(host
->quirks2
& SDHCI_QUIRK2_SUPPORT_SINGLE
))
914 mode
= SDHCI_TRNS_BLK_CNT_EN
;
916 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
917 mode
= SDHCI_TRNS_BLK_CNT_EN
| SDHCI_TRNS_MULTI
;
919 * If we are sending CMD23, CMD12 never gets sent
920 * on successful completion (so no Auto-CMD12).
922 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
) &&
923 (cmd
->opcode
!= SD_IO_RW_EXTENDED
))
924 mode
|= SDHCI_TRNS_AUTO_CMD12
;
925 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
926 mode
|= SDHCI_TRNS_AUTO_CMD23
;
927 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
931 if (data
->flags
& MMC_DATA_READ
)
932 mode
|= SDHCI_TRNS_READ
;
933 if (host
->flags
& SDHCI_REQ_USE_DMA
)
934 mode
|= SDHCI_TRNS_DMA
;
936 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
939 static void sdhci_finish_data(struct sdhci_host
*host
)
941 struct mmc_data
*data
;
948 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
949 if (host
->flags
& SDHCI_USE_ADMA
)
950 sdhci_adma_table_post(host
, data
);
952 if (data
->host_cookie
== COOKIE_MAPPED
) {
953 dma_unmap_sg(mmc_dev(host
->mmc
),
954 data
->sg
, data
->sg_len
,
955 (data
->flags
& MMC_DATA_READ
) ?
956 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
957 data
->host_cookie
= COOKIE_UNMAPPED
;
963 * The specification states that the block count register must
964 * be updated, but it does not specify at what point in the
965 * data flow. That makes the register entirely useless to read
966 * back so we have to assume that nothing made it to the card
967 * in the event of an error.
970 data
->bytes_xfered
= 0;
972 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
975 * Need to send CMD12 if -
976 * a) open-ended multiblock transfer (no CMD23)
977 * b) error in multiblock transfer
984 * The controller needs a reset of internal state machines
985 * upon error conditions.
988 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
989 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
992 sdhci_send_command(host
, data
->stop
);
994 tasklet_schedule(&host
->finish_tasklet
);
997 void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
1001 unsigned long timeout
;
1005 /* Wait max 10 ms */
1008 mask
= SDHCI_CMD_INHIBIT
;
1009 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
1010 mask
|= SDHCI_DATA_INHIBIT
;
1012 /* We shouldn't wait for data inihibit for stop commands, even
1013 though they might use busy signaling */
1014 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
1015 mask
&= ~SDHCI_DATA_INHIBIT
;
1017 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
1019 pr_err("%s: Controller never released "
1020 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
1021 sdhci_dumpregs(host
);
1023 tasklet_schedule(&host
->finish_tasklet
);
1031 if (!cmd
->data
&& cmd
->busy_timeout
> 9000)
1032 timeout
+= DIV_ROUND_UP(cmd
->busy_timeout
, 1000) * HZ
+ HZ
;
1035 mod_timer(&host
->timer
, timeout
);
1038 host
->busy_handle
= 0;
1040 sdhci_prepare_data(host
, cmd
);
1042 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
1044 sdhci_set_transfer_mode(host
, cmd
);
1046 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
1047 pr_err("%s: Unsupported response type!\n",
1048 mmc_hostname(host
->mmc
));
1049 cmd
->error
= -EINVAL
;
1050 tasklet_schedule(&host
->finish_tasklet
);
1054 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1055 flags
= SDHCI_CMD_RESP_NONE
;
1056 else if (cmd
->flags
& MMC_RSP_136
)
1057 flags
= SDHCI_CMD_RESP_LONG
;
1058 else if (cmd
->flags
& MMC_RSP_BUSY
)
1059 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1061 flags
= SDHCI_CMD_RESP_SHORT
;
1063 if (cmd
->flags
& MMC_RSP_CRC
)
1064 flags
|= SDHCI_CMD_CRC
;
1065 if (cmd
->flags
& MMC_RSP_OPCODE
)
1066 flags
|= SDHCI_CMD_INDEX
;
1068 /* CMD19 is special in that the Data Present Select should be set */
1069 if (cmd
->data
|| cmd
->opcode
== MMC_SEND_TUNING_BLOCK
||
1070 cmd
->opcode
== MMC_SEND_TUNING_BLOCK_HS200
)
1071 flags
|= SDHCI_CMD_DATA
;
1073 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1075 EXPORT_SYMBOL_GPL(sdhci_send_command
);
1077 static void sdhci_finish_command(struct sdhci_host
*host
)
1081 BUG_ON(host
->cmd
== NULL
);
1083 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1084 if (host
->cmd
->flags
& MMC_RSP_136
) {
1085 /* CRC is stripped so we need to do some shifting. */
1086 for (i
= 0;i
< 4;i
++) {
1087 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1088 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1090 host
->cmd
->resp
[i
] |=
1092 SDHCI_RESPONSE
+ (3-i
)*4-1);
1095 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1099 host
->cmd
->error
= 0;
1101 /* Finished CMD23, now send actual command. */
1102 if (host
->cmd
== host
->mrq
->sbc
) {
1104 sdhci_send_command(host
, host
->mrq
->cmd
);
1107 /* Processed actual command. */
1108 if (host
->data
&& host
->data_early
)
1109 sdhci_finish_data(host
);
1111 if (!host
->cmd
->data
)
1112 tasklet_schedule(&host
->finish_tasklet
);
1118 static u16
sdhci_get_preset_value(struct sdhci_host
*host
)
1122 switch (host
->timing
) {
1123 case MMC_TIMING_UHS_SDR12
:
1124 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1126 case MMC_TIMING_UHS_SDR25
:
1127 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR25
);
1129 case MMC_TIMING_UHS_SDR50
:
1130 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR50
);
1132 case MMC_TIMING_UHS_SDR104
:
1133 case MMC_TIMING_MMC_HS200
:
1134 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR104
);
1136 case MMC_TIMING_UHS_DDR50
:
1137 case MMC_TIMING_MMC_DDR52
:
1138 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_DDR50
);
1140 case MMC_TIMING_MMC_HS400
:
1141 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_HS400
);
1144 pr_warn("%s: Invalid UHS-I mode selected\n",
1145 mmc_hostname(host
->mmc
));
1146 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1152 void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1154 int div
= 0; /* Initialized for compiler warning */
1155 int real_div
= div
, clk_mul
= 1;
1157 unsigned long timeout
;
1158 bool switch_base_clk
= false;
1160 host
->mmc
->actual_clock
= 0;
1162 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1167 if (host
->version
>= SDHCI_SPEC_300
) {
1168 if (host
->preset_enabled
) {
1171 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1172 pre_val
= sdhci_get_preset_value(host
);
1173 div
= (pre_val
& SDHCI_PRESET_SDCLK_FREQ_MASK
)
1174 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT
;
1175 if (host
->clk_mul
&&
1176 (pre_val
& SDHCI_PRESET_CLKGEN_SEL_MASK
)) {
1177 clk
= SDHCI_PROG_CLOCK_MODE
;
1179 clk_mul
= host
->clk_mul
;
1181 real_div
= max_t(int, 1, div
<< 1);
1187 * Check if the Host Controller supports Programmable Clock
1190 if (host
->clk_mul
) {
1191 for (div
= 1; div
<= 1024; div
++) {
1192 if ((host
->max_clk
* host
->clk_mul
/ div
)
1196 if ((host
->max_clk
* host
->clk_mul
/ div
) <= clock
) {
1198 * Set Programmable Clock Mode in the Clock
1201 clk
= SDHCI_PROG_CLOCK_MODE
;
1203 clk_mul
= host
->clk_mul
;
1207 * Divisor can be too small to reach clock
1208 * speed requirement. Then use the base clock.
1210 switch_base_clk
= true;
1214 if (!host
->clk_mul
|| switch_base_clk
) {
1215 /* Version 3.00 divisors must be a multiple of 2. */
1216 if (host
->max_clk
<= clock
)
1219 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1221 if ((host
->max_clk
/ div
) <= clock
)
1227 if ((host
->quirks2
& SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
)
1228 && !div
&& host
->max_clk
<= 25000000)
1232 /* Version 2.00 divisors must be a power of 2. */
1233 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1234 if ((host
->max_clk
/ div
) <= clock
)
1243 host
->mmc
->actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1244 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1245 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1246 << SDHCI_DIVIDER_HI_SHIFT
;
1247 clk
|= SDHCI_CLOCK_INT_EN
;
1248 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1250 /* Wait max 20 ms */
1252 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1253 & SDHCI_CLOCK_INT_STABLE
)) {
1255 pr_err("%s: Internal clock never "
1256 "stabilised.\n", mmc_hostname(host
->mmc
));
1257 sdhci_dumpregs(host
);
1264 clk
|= SDHCI_CLOCK_CARD_EN
;
1265 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1267 EXPORT_SYMBOL_GPL(sdhci_set_clock
);
1269 static void sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1272 struct mmc_host
*mmc
= host
->mmc
;
1275 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1276 spin_unlock_irq(&host
->lock
);
1277 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
1278 spin_lock_irq(&host
->lock
);
1280 if (mode
!= MMC_POWER_OFF
)
1281 sdhci_writeb(host
, SDHCI_POWER_ON
, SDHCI_POWER_CONTROL
);
1283 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1288 if (mode
!= MMC_POWER_OFF
) {
1290 case MMC_VDD_165_195
:
1291 pwr
= SDHCI_POWER_180
;
1295 pwr
= SDHCI_POWER_300
;
1299 pwr
= SDHCI_POWER_330
;
1306 if (host
->pwr
== pwr
)
1312 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1313 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1314 sdhci_runtime_pm_bus_off(host
);
1318 * Spec says that we should clear the power reg before setting
1319 * a new value. Some controllers don't seem to like this though.
1321 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1322 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1325 * At least the Marvell CaFe chip gets confused if we set the
1326 * voltage and set turn on power at the same time, so set the
1329 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1330 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1332 pwr
|= SDHCI_POWER_ON
;
1334 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1336 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1337 sdhci_runtime_pm_bus_on(host
);
1340 * Some controllers need an extra 10ms delay of 10ms before
1341 * they can apply clock after applying power
1343 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1348 /*****************************************************************************\
1352 \*****************************************************************************/
1354 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1356 struct sdhci_host
*host
;
1358 unsigned long flags
;
1360 host
= mmc_priv(mmc
);
1362 sdhci_runtime_pm_get(host
);
1364 /* Firstly check card presence */
1365 present
= sdhci_do_get_cd(host
);
1367 spin_lock_irqsave(&host
->lock
, flags
);
1369 WARN_ON(host
->mrq
!= NULL
);
1371 #ifndef SDHCI_USE_LEDS_CLASS
1372 sdhci_activate_led(host
);
1376 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1377 * requests if Auto-CMD12 is enabled.
1379 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1381 mrq
->data
->stop
= NULL
;
1388 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1389 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1390 tasklet_schedule(&host
->finish_tasklet
);
1392 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1393 sdhci_send_command(host
, mrq
->sbc
);
1395 sdhci_send_command(host
, mrq
->cmd
);
1399 spin_unlock_irqrestore(&host
->lock
, flags
);
1402 void sdhci_set_bus_width(struct sdhci_host
*host
, int width
)
1406 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1407 if (width
== MMC_BUS_WIDTH_8
) {
1408 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1409 if (host
->version
>= SDHCI_SPEC_300
)
1410 ctrl
|= SDHCI_CTRL_8BITBUS
;
1412 if (host
->version
>= SDHCI_SPEC_300
)
1413 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1414 if (width
== MMC_BUS_WIDTH_4
)
1415 ctrl
|= SDHCI_CTRL_4BITBUS
;
1417 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1419 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1421 EXPORT_SYMBOL_GPL(sdhci_set_bus_width
);
1423 void sdhci_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
1427 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1428 /* Select Bus Speed Mode for host */
1429 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1430 if ((timing
== MMC_TIMING_MMC_HS200
) ||
1431 (timing
== MMC_TIMING_UHS_SDR104
))
1432 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1433 else if (timing
== MMC_TIMING_UHS_SDR12
)
1434 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1435 else if (timing
== MMC_TIMING_UHS_SDR25
)
1436 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1437 else if (timing
== MMC_TIMING_UHS_SDR50
)
1438 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1439 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
1440 (timing
== MMC_TIMING_MMC_DDR52
))
1441 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1442 else if (timing
== MMC_TIMING_MMC_HS400
)
1443 ctrl_2
|= SDHCI_CTRL_HS400
; /* Non-standard */
1444 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1446 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling
);
1448 static void sdhci_do_set_ios(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1450 unsigned long flags
;
1452 struct mmc_host
*mmc
= host
->mmc
;
1454 spin_lock_irqsave(&host
->lock
, flags
);
1456 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1457 spin_unlock_irqrestore(&host
->lock
, flags
);
1458 if (!IS_ERR(mmc
->supply
.vmmc
) &&
1459 ios
->power_mode
== MMC_POWER_OFF
)
1460 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1465 * Reset the chip on each power off.
1466 * Should clear out any weird states.
1468 if (ios
->power_mode
== MMC_POWER_OFF
) {
1469 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1473 if (host
->version
>= SDHCI_SPEC_300
&&
1474 (ios
->power_mode
== MMC_POWER_UP
) &&
1475 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
))
1476 sdhci_enable_preset_value(host
, false);
1478 if (!ios
->clock
|| ios
->clock
!= host
->clock
) {
1479 host
->ops
->set_clock(host
, ios
->clock
);
1480 host
->clock
= ios
->clock
;
1482 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
&&
1484 host
->timeout_clk
= host
->mmc
->actual_clock
?
1485 host
->mmc
->actual_clock
/ 1000 :
1487 host
->mmc
->max_busy_timeout
=
1488 host
->ops
->get_max_timeout_count
?
1489 host
->ops
->get_max_timeout_count(host
) :
1491 host
->mmc
->max_busy_timeout
/= host
->timeout_clk
;
1495 sdhci_set_power(host
, ios
->power_mode
, ios
->vdd
);
1497 if (host
->ops
->platform_send_init_74_clocks
)
1498 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1500 host
->ops
->set_bus_width(host
, ios
->bus_width
);
1502 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1504 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1505 ios
->timing
== MMC_TIMING_MMC_HS
)
1506 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1507 ctrl
|= SDHCI_CTRL_HISPD
;
1509 ctrl
&= ~SDHCI_CTRL_HISPD
;
1511 if (host
->version
>= SDHCI_SPEC_300
) {
1514 /* In case of UHS-I modes, set High Speed Enable */
1515 if ((ios
->timing
== MMC_TIMING_MMC_HS400
) ||
1516 (ios
->timing
== MMC_TIMING_MMC_HS200
) ||
1517 (ios
->timing
== MMC_TIMING_MMC_DDR52
) ||
1518 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1519 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1520 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1521 (ios
->timing
== MMC_TIMING_UHS_SDR25
))
1522 ctrl
|= SDHCI_CTRL_HISPD
;
1524 if (!host
->preset_enabled
) {
1525 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1527 * We only need to set Driver Strength if the
1528 * preset value enable is not set.
1530 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1531 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1532 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1533 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1534 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_B
)
1535 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1536 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1537 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1538 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_D
)
1539 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_D
;
1541 pr_warn("%s: invalid driver type, default to "
1542 "driver type B\n", mmc_hostname(mmc
));
1543 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1546 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1549 * According to SDHC Spec v3.00, if the Preset Value
1550 * Enable in the Host Control 2 register is set, we
1551 * need to reset SD Clock Enable before changing High
1552 * Speed Enable to avoid generating clock gliches.
1555 /* Reset SD Clock Enable */
1556 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1557 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1558 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1560 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1562 /* Re-enable SD Clock */
1563 host
->ops
->set_clock(host
, host
->clock
);
1566 /* Reset SD Clock Enable */
1567 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1568 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1569 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1571 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1572 host
->timing
= ios
->timing
;
1574 if (!(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
) &&
1575 ((ios
->timing
== MMC_TIMING_UHS_SDR12
) ||
1576 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1577 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1578 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1579 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1580 (ios
->timing
== MMC_TIMING_MMC_DDR52
))) {
1583 sdhci_enable_preset_value(host
, true);
1584 preset
= sdhci_get_preset_value(host
);
1585 ios
->drv_type
= (preset
& SDHCI_PRESET_DRV_MASK
)
1586 >> SDHCI_PRESET_DRV_SHIFT
;
1589 /* Re-enable SD Clock */
1590 host
->ops
->set_clock(host
, host
->clock
);
1592 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1595 * Some (ENE) controllers go apeshit on some ios operation,
1596 * signalling timeout and CRC errors even on CMD0. Resetting
1597 * it on each ios seems to solve the problem.
1599 if (host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1600 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1603 spin_unlock_irqrestore(&host
->lock
, flags
);
1606 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1608 struct sdhci_host
*host
= mmc_priv(mmc
);
1610 sdhci_runtime_pm_get(host
);
1611 sdhci_do_set_ios(host
, ios
);
1612 sdhci_runtime_pm_put(host
);
1615 static int sdhci_do_get_cd(struct sdhci_host
*host
)
1617 int gpio_cd
= mmc_gpio_get_cd(host
->mmc
);
1619 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1622 /* If nonremovable, assume that the card is always present. */
1623 if (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
)
1627 * Try slot gpio detect, if defined it take precedence
1628 * over build in controller functionality
1630 if (!IS_ERR_VALUE(gpio_cd
))
1633 /* If polling, assume that the card is always present. */
1634 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1637 /* Host native card detect */
1638 return !!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
);
1641 static int sdhci_get_cd(struct mmc_host
*mmc
)
1643 struct sdhci_host
*host
= mmc_priv(mmc
);
1646 sdhci_runtime_pm_get(host
);
1647 ret
= sdhci_do_get_cd(host
);
1648 sdhci_runtime_pm_put(host
);
1652 static int sdhci_check_ro(struct sdhci_host
*host
)
1654 unsigned long flags
;
1657 spin_lock_irqsave(&host
->lock
, flags
);
1659 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1661 else if (host
->ops
->get_ro
)
1662 is_readonly
= host
->ops
->get_ro(host
);
1664 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1665 & SDHCI_WRITE_PROTECT
);
1667 spin_unlock_irqrestore(&host
->lock
, flags
);
1669 /* This quirk needs to be replaced by a callback-function later */
1670 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1671 !is_readonly
: is_readonly
;
1674 #define SAMPLE_COUNT 5
1676 static int sdhci_do_get_ro(struct sdhci_host
*host
)
1680 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1681 return sdhci_check_ro(host
);
1684 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1685 if (sdhci_check_ro(host
)) {
1686 if (++ro_count
> SAMPLE_COUNT
/ 2)
1694 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1696 struct sdhci_host
*host
= mmc_priv(mmc
);
1698 if (host
->ops
&& host
->ops
->hw_reset
)
1699 host
->ops
->hw_reset(host
);
1702 static int sdhci_get_ro(struct mmc_host
*mmc
)
1704 struct sdhci_host
*host
= mmc_priv(mmc
);
1707 sdhci_runtime_pm_get(host
);
1708 ret
= sdhci_do_get_ro(host
);
1709 sdhci_runtime_pm_put(host
);
1713 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1715 if (!(host
->flags
& SDHCI_DEVICE_DEAD
)) {
1717 host
->ier
|= SDHCI_INT_CARD_INT
;
1719 host
->ier
&= ~SDHCI_INT_CARD_INT
;
1721 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
1722 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
1727 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1729 struct sdhci_host
*host
= mmc_priv(mmc
);
1730 unsigned long flags
;
1732 sdhci_runtime_pm_get(host
);
1734 spin_lock_irqsave(&host
->lock
, flags
);
1736 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1738 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1740 sdhci_enable_sdio_irq_nolock(host
, enable
);
1741 spin_unlock_irqrestore(&host
->lock
, flags
);
1743 sdhci_runtime_pm_put(host
);
1746 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host
*host
,
1747 struct mmc_ios
*ios
)
1749 struct mmc_host
*mmc
= host
->mmc
;
1754 * Signal Voltage Switching is only applicable for Host Controllers
1757 if (host
->version
< SDHCI_SPEC_300
)
1760 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1762 switch (ios
->signal_voltage
) {
1763 case MMC_SIGNAL_VOLTAGE_330
:
1764 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1765 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1766 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1768 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1769 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 2700000,
1772 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1778 usleep_range(5000, 5500);
1780 /* 3.3V regulator output should be stable within 5 ms */
1781 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1782 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1785 pr_warn("%s: 3.3V regulator output did not became stable\n",
1789 case MMC_SIGNAL_VOLTAGE_180
:
1790 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1791 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1794 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1801 * Enable 1.8V Signal Enable in the Host Control2
1804 ctrl
|= SDHCI_CTRL_VDD_180
;
1805 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1807 /* Some controller need to do more when switching */
1808 if (host
->ops
->voltage_switch
)
1809 host
->ops
->voltage_switch(host
);
1811 /* 1.8V regulator output should be stable within 5 ms */
1812 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1813 if (ctrl
& SDHCI_CTRL_VDD_180
)
1816 pr_warn("%s: 1.8V regulator output did not became stable\n",
1820 case MMC_SIGNAL_VOLTAGE_120
:
1821 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1822 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 1100000,
1825 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1832 /* No signal voltage switch required */
1837 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1838 struct mmc_ios
*ios
)
1840 struct sdhci_host
*host
= mmc_priv(mmc
);
1843 if (host
->version
< SDHCI_SPEC_300
)
1845 sdhci_runtime_pm_get(host
);
1846 err
= sdhci_do_start_signal_voltage_switch(host
, ios
);
1847 sdhci_runtime_pm_put(host
);
1851 static int sdhci_card_busy(struct mmc_host
*mmc
)
1853 struct sdhci_host
*host
= mmc_priv(mmc
);
1856 sdhci_runtime_pm_get(host
);
1857 /* Check whether DAT[3:0] is 0000 */
1858 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1859 sdhci_runtime_pm_put(host
);
1861 return !(present_state
& SDHCI_DATA_LVL_MASK
);
1864 static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1866 struct sdhci_host
*host
= mmc_priv(mmc
);
1867 unsigned long flags
;
1869 spin_lock_irqsave(&host
->lock
, flags
);
1870 host
->flags
|= SDHCI_HS400_TUNING
;
1871 spin_unlock_irqrestore(&host
->lock
, flags
);
1876 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1878 struct sdhci_host
*host
= mmc_priv(mmc
);
1880 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1882 unsigned long flags
;
1883 unsigned int tuning_count
= 0;
1886 sdhci_runtime_pm_get(host
);
1887 spin_lock_irqsave(&host
->lock
, flags
);
1889 hs400_tuning
= host
->flags
& SDHCI_HS400_TUNING
;
1890 host
->flags
&= ~SDHCI_HS400_TUNING
;
1892 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1893 tuning_count
= host
->tuning_count
;
1896 * The Host Controller needs tuning only in case of SDR104 mode
1897 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1898 * Capabilities register.
1899 * If the Host Controller supports the HS200 mode then the
1900 * tuning function has to be executed.
1902 switch (host
->timing
) {
1903 /* HS400 tuning is done in HS200 mode */
1904 case MMC_TIMING_MMC_HS400
:
1908 case MMC_TIMING_MMC_HS200
:
1910 * Periodic re-tuning for HS400 is not expected to be needed, so
1917 case MMC_TIMING_UHS_SDR104
:
1920 case MMC_TIMING_UHS_SDR50
:
1921 if (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
||
1922 host
->flags
& SDHCI_SDR104_NEEDS_TUNING
)
1930 if (host
->ops
->platform_execute_tuning
) {
1931 spin_unlock_irqrestore(&host
->lock
, flags
);
1932 err
= host
->ops
->platform_execute_tuning(host
, opcode
);
1933 sdhci_runtime_pm_put(host
);
1937 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1938 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1939 if (host
->quirks2
& SDHCI_QUIRK2_TUNING_WORK_AROUND
)
1940 ctrl
|= SDHCI_CTRL_TUNED_CLK
;
1941 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1944 * As per the Host Controller spec v3.00, tuning command
1945 * generates Buffer Read Ready interrupt, so enable that.
1947 * Note: The spec clearly says that when tuning sequence
1948 * is being performed, the controller does not generate
1949 * interrupts other than Buffer Read Ready interrupt. But
1950 * to make sure we don't hit a controller bug, we _only_
1951 * enable Buffer Read Ready interrupt here.
1953 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_INT_ENABLE
);
1954 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_SIGNAL_ENABLE
);
1957 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1958 * of loops reaches 40 times or a timeout of 150ms occurs.
1961 struct mmc_command cmd
= {0};
1962 struct mmc_request mrq
= {NULL
};
1964 cmd
.opcode
= opcode
;
1966 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1971 if (tuning_loop_counter
-- == 0)
1978 * In response to CMD19, the card sends 64 bytes of tuning
1979 * block to the Host Controller. So we set the block size
1982 if (cmd
.opcode
== MMC_SEND_TUNING_BLOCK_HS200
) {
1983 if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
1984 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 128),
1986 else if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
1987 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1990 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1995 * The tuning block is sent by the card to the host controller.
1996 * So we set the TRNS_READ bit in the Transfer Mode register.
1997 * This also takes care of setting DMA Enable and Multi Block
1998 * Select in the same register to 0.
2000 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
2002 sdhci_send_command(host
, &cmd
);
2007 spin_unlock_irqrestore(&host
->lock
, flags
);
2008 /* Wait for Buffer Read Ready interrupt */
2009 wait_event_interruptible_timeout(host
->buf_ready_int
,
2010 (host
->tuning_done
== 1),
2011 msecs_to_jiffies(50));
2012 spin_lock_irqsave(&host
->lock
, flags
);
2014 if (!host
->tuning_done
) {
2015 pr_info(DRIVER_NAME
": Timeout waiting for "
2016 "Buffer Read Ready interrupt during tuning "
2017 "procedure, falling back to fixed sampling "
2019 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2020 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2021 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
2022 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2028 host
->tuning_done
= 0;
2030 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2032 /* eMMC spec does not require a delay between tuning cycles */
2033 if (opcode
== MMC_SEND_TUNING_BLOCK
)
2035 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
2038 * The Host Driver has exhausted the maximum number of loops allowed,
2039 * so use fixed sampling frequency.
2041 if (tuning_loop_counter
< 0) {
2042 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2043 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2045 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
2046 pr_info(DRIVER_NAME
": Tuning procedure"
2047 " failed, falling back to fixed sampling"
2055 * In case tuning fails, host controllers which support
2056 * re-tuning can try tuning again at a later time, when the
2057 * re-tuning timer expires. So for these controllers, we
2058 * return 0. Since there might be other controllers who do not
2059 * have this capability, we return error for them.
2064 host
->mmc
->retune_period
= err
? 0 : tuning_count
;
2066 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2067 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2069 spin_unlock_irqrestore(&host
->lock
, flags
);
2070 sdhci_runtime_pm_put(host
);
2075 static int sdhci_select_drive_strength(struct mmc_card
*card
,
2076 unsigned int max_dtr
, int host_drv
,
2077 int card_drv
, int *drv_type
)
2079 struct sdhci_host
*host
= mmc_priv(card
->host
);
2081 if (!host
->ops
->select_drive_strength
)
2084 return host
->ops
->select_drive_strength(host
, card
, max_dtr
, host_drv
,
2085 card_drv
, drv_type
);
2088 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
)
2090 /* Host Controller v3.00 defines preset value registers */
2091 if (host
->version
< SDHCI_SPEC_300
)
2095 * We only enable or disable Preset Value if they are not already
2096 * enabled or disabled respectively. Otherwise, we bail out.
2098 if (host
->preset_enabled
!= enable
) {
2099 u16 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2102 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
2104 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
2106 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2109 host
->flags
|= SDHCI_PV_ENABLED
;
2111 host
->flags
&= ~SDHCI_PV_ENABLED
;
2113 host
->preset_enabled
= enable
;
2117 static void sdhci_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2120 struct sdhci_host
*host
= mmc_priv(mmc
);
2121 struct mmc_data
*data
= mrq
->data
;
2123 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
2124 if (data
->host_cookie
== COOKIE_GIVEN
||
2125 data
->host_cookie
== COOKIE_MAPPED
)
2126 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2127 data
->flags
& MMC_DATA_WRITE
?
2128 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2129 data
->host_cookie
= COOKIE_UNMAPPED
;
2133 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
2134 struct mmc_data
*data
)
2138 if (data
->host_cookie
== COOKIE_MAPPED
) {
2139 data
->host_cookie
= COOKIE_GIVEN
;
2140 return data
->sg_count
;
2143 WARN_ON(data
->host_cookie
== COOKIE_GIVEN
);
2145 sg_count
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2146 data
->flags
& MMC_DATA_WRITE
?
2147 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2152 data
->sg_count
= sg_count
;
2153 data
->host_cookie
= COOKIE_MAPPED
;
2158 static void sdhci_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2161 struct sdhci_host
*host
= mmc_priv(mmc
);
2163 mrq
->data
->host_cookie
= COOKIE_UNMAPPED
;
2165 if (host
->flags
& SDHCI_REQ_USE_DMA
)
2166 sdhci_pre_dma_transfer(host
, mrq
->data
);
2169 static void sdhci_card_event(struct mmc_host
*mmc
)
2171 struct sdhci_host
*host
= mmc_priv(mmc
);
2172 unsigned long flags
;
2175 /* First check if client has provided their own card event */
2176 if (host
->ops
->card_event
)
2177 host
->ops
->card_event(host
);
2179 present
= sdhci_do_get_cd(host
);
2181 spin_lock_irqsave(&host
->lock
, flags
);
2183 /* Check host->mrq first in case we are runtime suspended */
2184 if (host
->mrq
&& !present
) {
2185 pr_err("%s: Card removed during transfer!\n",
2186 mmc_hostname(host
->mmc
));
2187 pr_err("%s: Resetting controller.\n",
2188 mmc_hostname(host
->mmc
));
2190 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2191 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2193 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2194 tasklet_schedule(&host
->finish_tasklet
);
2197 spin_unlock_irqrestore(&host
->lock
, flags
);
2200 static const struct mmc_host_ops sdhci_ops
= {
2201 .request
= sdhci_request
,
2202 .post_req
= sdhci_post_req
,
2203 .pre_req
= sdhci_pre_req
,
2204 .set_ios
= sdhci_set_ios
,
2205 .get_cd
= sdhci_get_cd
,
2206 .get_ro
= sdhci_get_ro
,
2207 .hw_reset
= sdhci_hw_reset
,
2208 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
2209 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
2210 .prepare_hs400_tuning
= sdhci_prepare_hs400_tuning
,
2211 .execute_tuning
= sdhci_execute_tuning
,
2212 .select_drive_strength
= sdhci_select_drive_strength
,
2213 .card_event
= sdhci_card_event
,
2214 .card_busy
= sdhci_card_busy
,
2217 /*****************************************************************************\
2221 \*****************************************************************************/
2223 static void sdhci_tasklet_finish(unsigned long param
)
2225 struct sdhci_host
*host
;
2226 unsigned long flags
;
2227 struct mmc_request
*mrq
;
2229 host
= (struct sdhci_host
*)param
;
2231 spin_lock_irqsave(&host
->lock
, flags
);
2234 * If this tasklet gets rescheduled while running, it will
2235 * be run again afterwards but without any active request.
2238 spin_unlock_irqrestore(&host
->lock
, flags
);
2242 del_timer(&host
->timer
);
2247 * The controller needs a reset of internal state machines
2248 * upon error conditions.
2250 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
2251 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
2252 (mrq
->sbc
&& mrq
->sbc
->error
) ||
2253 (mrq
->data
&& ((mrq
->data
->error
&& !mrq
->data
->stop
) ||
2254 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
2255 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
2257 /* Some controllers need this kick or reset won't work here */
2258 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
)
2259 /* This is to force an update */
2260 host
->ops
->set_clock(host
, host
->clock
);
2262 /* Spec says we should do both at the same time, but Ricoh
2263 controllers do not like that. */
2264 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2265 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2272 #ifndef SDHCI_USE_LEDS_CLASS
2273 sdhci_deactivate_led(host
);
2277 spin_unlock_irqrestore(&host
->lock
, flags
);
2279 mmc_request_done(host
->mmc
, mrq
);
2280 sdhci_runtime_pm_put(host
);
2283 static void sdhci_timeout_timer(unsigned long data
)
2285 struct sdhci_host
*host
;
2286 unsigned long flags
;
2288 host
= (struct sdhci_host
*)data
;
2290 spin_lock_irqsave(&host
->lock
, flags
);
2293 pr_err("%s: Timeout waiting for hardware "
2294 "interrupt.\n", mmc_hostname(host
->mmc
));
2295 sdhci_dumpregs(host
);
2298 host
->data
->error
= -ETIMEDOUT
;
2299 sdhci_finish_data(host
);
2302 host
->cmd
->error
= -ETIMEDOUT
;
2304 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2306 tasklet_schedule(&host
->finish_tasklet
);
2311 spin_unlock_irqrestore(&host
->lock
, flags
);
2314 /*****************************************************************************\
2316 * Interrupt handling *
2318 \*****************************************************************************/
2320 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
, u32
*mask
)
2322 BUG_ON(intmask
== 0);
2325 pr_err("%s: Got command interrupt 0x%08x even "
2326 "though no command operation was in progress.\n",
2327 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2328 sdhci_dumpregs(host
);
2332 if (intmask
& SDHCI_INT_TIMEOUT
)
2333 host
->cmd
->error
= -ETIMEDOUT
;
2334 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
2336 host
->cmd
->error
= -EILSEQ
;
2338 if (host
->cmd
->error
) {
2339 tasklet_schedule(&host
->finish_tasklet
);
2344 * The host can send and interrupt when the busy state has
2345 * ended, allowing us to wait without wasting CPU cycles.
2346 * Unfortunately this is overloaded on the "data complete"
2347 * interrupt, so we need to take some care when handling
2350 * Note: The 1.0 specification is a bit ambiguous about this
2351 * feature so there might be some problems with older
2354 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
2355 if (host
->cmd
->data
)
2356 DBG("Cannot wait for busy signal when also "
2357 "doing a data transfer");
2358 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
)
2359 && !host
->busy_handle
) {
2360 /* Mark that command complete before busy is ended */
2361 host
->busy_handle
= 1;
2365 /* The controller does not support the end-of-busy IRQ,
2366 * fall through and take the SDHCI_INT_RESPONSE */
2367 } else if ((host
->quirks2
& SDHCI_QUIRK2_STOP_WITH_TC
) &&
2368 host
->cmd
->opcode
== MMC_STOP_TRANSMISSION
&& !host
->data
) {
2369 *mask
&= ~SDHCI_INT_DATA_END
;
2372 if (intmask
& SDHCI_INT_RESPONSE
)
2373 sdhci_finish_command(host
);
2376 #ifdef CONFIG_MMC_DEBUG
2377 static void sdhci_adma_show_error(struct sdhci_host
*host
)
2379 const char *name
= mmc_hostname(host
->mmc
);
2380 void *desc
= host
->adma_table
;
2382 sdhci_dumpregs(host
);
2385 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
2387 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2388 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2389 name
, desc
, le32_to_cpu(dma_desc
->addr_hi
),
2390 le32_to_cpu(dma_desc
->addr_lo
),
2391 le16_to_cpu(dma_desc
->len
),
2392 le16_to_cpu(dma_desc
->cmd
));
2394 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2395 name
, desc
, le32_to_cpu(dma_desc
->addr_lo
),
2396 le16_to_cpu(dma_desc
->len
),
2397 le16_to_cpu(dma_desc
->cmd
));
2399 desc
+= host
->desc_sz
;
2401 if (dma_desc
->cmd
& cpu_to_le16(ADMA2_END
))
2406 static void sdhci_adma_show_error(struct sdhci_host
*host
) { }
2409 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2412 BUG_ON(intmask
== 0);
2414 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2415 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2416 command
= SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
));
2417 if (command
== MMC_SEND_TUNING_BLOCK
||
2418 command
== MMC_SEND_TUNING_BLOCK_HS200
) {
2419 host
->tuning_done
= 1;
2420 wake_up(&host
->buf_ready_int
);
2427 * The "data complete" interrupt is also used to
2428 * indicate that a busy state has ended. See comment
2429 * above in sdhci_cmd_irq().
2431 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2432 if (intmask
& SDHCI_INT_DATA_TIMEOUT
) {
2433 host
->cmd
->error
= -ETIMEDOUT
;
2434 tasklet_schedule(&host
->finish_tasklet
);
2437 if (intmask
& SDHCI_INT_DATA_END
) {
2439 * Some cards handle busy-end interrupt
2440 * before the command completed, so make
2441 * sure we do things in the proper order.
2443 if (host
->busy_handle
)
2444 sdhci_finish_command(host
);
2446 host
->busy_handle
= 1;
2451 pr_err("%s: Got data interrupt 0x%08x even "
2452 "though no data operation was in progress.\n",
2453 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2454 sdhci_dumpregs(host
);
2459 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2460 host
->data
->error
= -ETIMEDOUT
;
2461 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2462 host
->data
->error
= -EILSEQ
;
2463 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2464 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2466 host
->data
->error
= -EILSEQ
;
2467 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2468 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2469 sdhci_adma_show_error(host
);
2470 host
->data
->error
= -EIO
;
2471 if (host
->ops
->adma_workaround
)
2472 host
->ops
->adma_workaround(host
, intmask
);
2475 if (host
->data
->error
)
2476 sdhci_finish_data(host
);
2478 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2479 sdhci_transfer_pio(host
);
2482 * We currently don't do anything fancy with DMA
2483 * boundaries, but as we can't disable the feature
2484 * we need to at least restart the transfer.
2486 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2487 * should return a valid address to continue from, but as
2488 * some controllers are faulty, don't trust them.
2490 if (intmask
& SDHCI_INT_DMA_END
) {
2491 u32 dmastart
, dmanow
;
2492 dmastart
= sg_dma_address(host
->data
->sg
);
2493 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2495 * Force update to the next DMA block boundary.
2498 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2499 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2500 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2501 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2503 mmc_hostname(host
->mmc
), dmastart
,
2504 host
->data
->bytes_xfered
, dmanow
);
2505 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2508 if (intmask
& SDHCI_INT_DATA_END
) {
2511 * Data managed to finish before the
2512 * command completed. Make sure we do
2513 * things in the proper order.
2515 host
->data_early
= 1;
2517 sdhci_finish_data(host
);
2523 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2525 irqreturn_t result
= IRQ_NONE
;
2526 struct sdhci_host
*host
= dev_id
;
2527 u32 intmask
, mask
, unexpected
= 0;
2530 spin_lock(&host
->lock
);
2532 if (host
->runtime_suspended
&& !sdhci_sdio_irq_enabled(host
)) {
2533 spin_unlock(&host
->lock
);
2537 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2538 if (!intmask
|| intmask
== 0xffffffff) {
2544 /* Clear selected interrupts. */
2545 mask
= intmask
& (SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2546 SDHCI_INT_BUS_POWER
);
2547 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
2549 DBG("*** %s got interrupt: 0x%08x\n",
2550 mmc_hostname(host
->mmc
), intmask
);
2552 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2553 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2557 * There is a observation on i.mx esdhc. INSERT
2558 * bit will be immediately set again when it gets
2559 * cleared, if a card is inserted. We have to mask
2560 * the irq to prevent interrupt storm which will
2561 * freeze the system. And the REMOVE gets the
2564 * More testing are needed here to ensure it works
2565 * for other platforms though.
2567 host
->ier
&= ~(SDHCI_INT_CARD_INSERT
|
2568 SDHCI_INT_CARD_REMOVE
);
2569 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
2570 SDHCI_INT_CARD_INSERT
;
2571 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2572 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2574 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2575 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2577 host
->thread_isr
|= intmask
& (SDHCI_INT_CARD_INSERT
|
2578 SDHCI_INT_CARD_REMOVE
);
2579 result
= IRQ_WAKE_THREAD
;
2582 if (intmask
& SDHCI_INT_CMD_MASK
)
2583 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
,
2586 if (intmask
& SDHCI_INT_DATA_MASK
)
2587 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2589 if (intmask
& SDHCI_INT_BUS_POWER
)
2590 pr_err("%s: Card is consuming too much power!\n",
2591 mmc_hostname(host
->mmc
));
2593 if (intmask
& SDHCI_INT_CARD_INT
) {
2594 sdhci_enable_sdio_irq_nolock(host
, false);
2595 host
->thread_isr
|= SDHCI_INT_CARD_INT
;
2596 result
= IRQ_WAKE_THREAD
;
2599 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2600 SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2601 SDHCI_INT_ERROR
| SDHCI_INT_BUS_POWER
|
2602 SDHCI_INT_CARD_INT
);
2605 unexpected
|= intmask
;
2606 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2609 if (result
== IRQ_NONE
)
2610 result
= IRQ_HANDLED
;
2612 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2613 } while (intmask
&& --max_loops
);
2615 spin_unlock(&host
->lock
);
2618 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2619 mmc_hostname(host
->mmc
), unexpected
);
2620 sdhci_dumpregs(host
);
2626 static irqreturn_t
sdhci_thread_irq(int irq
, void *dev_id
)
2628 struct sdhci_host
*host
= dev_id
;
2629 unsigned long flags
;
2632 spin_lock_irqsave(&host
->lock
, flags
);
2633 isr
= host
->thread_isr
;
2634 host
->thread_isr
= 0;
2635 spin_unlock_irqrestore(&host
->lock
, flags
);
2637 if (isr
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2638 sdhci_card_event(host
->mmc
);
2639 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
2642 if (isr
& SDHCI_INT_CARD_INT
) {
2643 sdio_run_irqs(host
->mmc
);
2645 spin_lock_irqsave(&host
->lock
, flags
);
2646 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2647 sdhci_enable_sdio_irq_nolock(host
, true);
2648 spin_unlock_irqrestore(&host
->lock
, flags
);
2651 return isr
? IRQ_HANDLED
: IRQ_NONE
;
2654 /*****************************************************************************\
2658 \*****************************************************************************/
2661 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2664 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2665 | SDHCI_WAKE_ON_INT
;
2667 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2669 /* Avoid fake wake up */
2670 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
2671 val
&= ~(SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
);
2672 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2674 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2676 static void sdhci_disable_irq_wakeups(struct sdhci_host
*host
)
2679 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2680 | SDHCI_WAKE_ON_INT
;
2682 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2684 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2687 int sdhci_suspend_host(struct sdhci_host
*host
)
2689 sdhci_disable_card_detection(host
);
2691 mmc_retune_timer_stop(host
->mmc
);
2692 mmc_retune_needed(host
->mmc
);
2694 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2696 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
2697 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
2698 free_irq(host
->irq
, host
);
2700 sdhci_enable_irq_wakeups(host
);
2701 enable_irq_wake(host
->irq
);
2706 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2708 int sdhci_resume_host(struct sdhci_host
*host
)
2712 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2713 if (host
->ops
->enable_dma
)
2714 host
->ops
->enable_dma(host
);
2717 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2718 ret
= request_threaded_irq(host
->irq
, sdhci_irq
,
2719 sdhci_thread_irq
, IRQF_SHARED
,
2720 mmc_hostname(host
->mmc
), host
);
2724 sdhci_disable_irq_wakeups(host
);
2725 disable_irq_wake(host
->irq
);
2728 if ((host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) &&
2729 (host
->quirks2
& SDHCI_QUIRK2_HOST_OFF_CARD_ON
)) {
2730 /* Card keeps power but host controller does not */
2731 sdhci_init(host
, 0);
2734 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2736 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2740 sdhci_enable_card_detection(host
);
2745 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2747 static int sdhci_runtime_pm_get(struct sdhci_host
*host
)
2749 return pm_runtime_get_sync(host
->mmc
->parent
);
2752 static int sdhci_runtime_pm_put(struct sdhci_host
*host
)
2754 pm_runtime_mark_last_busy(host
->mmc
->parent
);
2755 return pm_runtime_put_autosuspend(host
->mmc
->parent
);
2758 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
2760 if (host
->runtime_suspended
|| host
->bus_on
)
2762 host
->bus_on
= true;
2763 pm_runtime_get_noresume(host
->mmc
->parent
);
2766 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
2768 if (host
->runtime_suspended
|| !host
->bus_on
)
2770 host
->bus_on
= false;
2771 pm_runtime_put_noidle(host
->mmc
->parent
);
2774 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2776 unsigned long flags
;
2778 mmc_retune_timer_stop(host
->mmc
);
2779 mmc_retune_needed(host
->mmc
);
2781 spin_lock_irqsave(&host
->lock
, flags
);
2782 host
->ier
&= SDHCI_INT_CARD_INT
;
2783 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2784 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2785 spin_unlock_irqrestore(&host
->lock
, flags
);
2787 synchronize_hardirq(host
->irq
);
2789 spin_lock_irqsave(&host
->lock
, flags
);
2790 host
->runtime_suspended
= true;
2791 spin_unlock_irqrestore(&host
->lock
, flags
);
2795 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2797 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2799 unsigned long flags
;
2800 int host_flags
= host
->flags
;
2802 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2803 if (host
->ops
->enable_dma
)
2804 host
->ops
->enable_dma(host
);
2807 sdhci_init(host
, 0);
2809 /* Force clock and power re-program */
2812 sdhci_do_start_signal_voltage_switch(host
, &host
->mmc
->ios
);
2813 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2815 if ((host_flags
& SDHCI_PV_ENABLED
) &&
2816 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)) {
2817 spin_lock_irqsave(&host
->lock
, flags
);
2818 sdhci_enable_preset_value(host
, true);
2819 spin_unlock_irqrestore(&host
->lock
, flags
);
2822 spin_lock_irqsave(&host
->lock
, flags
);
2824 host
->runtime_suspended
= false;
2826 /* Enable SDIO IRQ */
2827 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2828 sdhci_enable_sdio_irq_nolock(host
, true);
2830 /* Enable Card Detection */
2831 sdhci_enable_card_detection(host
);
2833 spin_unlock_irqrestore(&host
->lock
, flags
);
2837 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2839 #endif /* CONFIG_PM */
2841 /*****************************************************************************\
2843 * Device allocation/registration *
2845 \*****************************************************************************/
2847 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2850 struct mmc_host
*mmc
;
2851 struct sdhci_host
*host
;
2853 WARN_ON(dev
== NULL
);
2855 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2857 return ERR_PTR(-ENOMEM
);
2859 host
= mmc_priv(mmc
);
2865 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2867 int sdhci_add_host(struct sdhci_host
*host
)
2869 struct mmc_host
*mmc
;
2870 u32 caps
[2] = {0, 0};
2871 u32 max_current_caps
;
2872 unsigned int ocr_avail
;
2873 unsigned int override_timeout_clk
;
2877 WARN_ON(host
== NULL
);
2884 host
->quirks
= debug_quirks
;
2886 host
->quirks2
= debug_quirks2
;
2888 override_timeout_clk
= host
->timeout_clk
;
2890 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
2892 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2893 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2894 >> SDHCI_SPEC_VER_SHIFT
;
2895 if (host
->version
> SDHCI_SPEC_300
) {
2896 pr_err("%s: Unknown controller version (%d). "
2897 "You may experience problems.\n", mmc_hostname(mmc
),
2901 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2902 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2904 if (host
->version
>= SDHCI_SPEC_300
)
2905 caps
[1] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ?
2907 sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
2909 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2910 host
->flags
|= SDHCI_USE_SDMA
;
2911 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2912 DBG("Controller doesn't have SDMA capability\n");
2914 host
->flags
|= SDHCI_USE_SDMA
;
2916 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2917 (host
->flags
& SDHCI_USE_SDMA
)) {
2918 DBG("Disabling DMA as it is marked broken\n");
2919 host
->flags
&= ~SDHCI_USE_SDMA
;
2922 if ((host
->version
>= SDHCI_SPEC_200
) &&
2923 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2924 host
->flags
|= SDHCI_USE_ADMA
;
2926 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2927 (host
->flags
& SDHCI_USE_ADMA
)) {
2928 DBG("Disabling ADMA as it is marked broken\n");
2929 host
->flags
&= ~SDHCI_USE_ADMA
;
2933 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2934 * and *must* do 64-bit DMA. A driver has the opportunity to change
2935 * that during the first call to ->enable_dma(). Similarly
2936 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2939 if (sdhci_readl(host
, SDHCI_CAPABILITIES
) & SDHCI_CAN_64BIT
)
2940 host
->flags
|= SDHCI_USE_64_BIT_DMA
;
2942 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2943 if (host
->ops
->enable_dma
) {
2944 if (host
->ops
->enable_dma(host
)) {
2945 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2948 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2953 /* SDMA does not support 64-bit DMA */
2954 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2955 host
->flags
&= ~SDHCI_USE_SDMA
;
2957 if (host
->flags
& SDHCI_USE_ADMA
) {
2959 * The DMA descriptor table size is calculated as the maximum
2960 * number of segments times 2, to allow for an alignment
2961 * descriptor for each segment, plus 1 for a nop end descriptor,
2962 * all multipled by the descriptor size.
2964 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
2965 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2966 SDHCI_ADMA2_64_DESC_SZ
;
2967 host
->align_buffer_sz
= SDHCI_MAX_SEGS
*
2968 SDHCI_ADMA2_64_ALIGN
;
2969 host
->desc_sz
= SDHCI_ADMA2_64_DESC_SZ
;
2970 host
->align_sz
= SDHCI_ADMA2_64_ALIGN
;
2971 host
->align_mask
= SDHCI_ADMA2_64_ALIGN
- 1;
2973 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2974 SDHCI_ADMA2_32_DESC_SZ
;
2975 host
->align_buffer_sz
= SDHCI_MAX_SEGS
*
2976 SDHCI_ADMA2_32_ALIGN
;
2977 host
->desc_sz
= SDHCI_ADMA2_32_DESC_SZ
;
2978 host
->align_sz
= SDHCI_ADMA2_32_ALIGN
;
2979 host
->align_mask
= SDHCI_ADMA2_32_ALIGN
- 1;
2981 host
->adma_table
= dma_alloc_coherent(mmc_dev(mmc
),
2982 host
->adma_table_sz
,
2985 host
->align_buffer
= kmalloc(host
->align_buffer_sz
, GFP_KERNEL
);
2986 if (!host
->adma_table
|| !host
->align_buffer
) {
2987 if (host
->adma_table
)
2988 dma_free_coherent(mmc_dev(mmc
),
2989 host
->adma_table_sz
,
2992 kfree(host
->align_buffer
);
2993 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2995 host
->flags
&= ~SDHCI_USE_ADMA
;
2996 host
->adma_table
= NULL
;
2997 host
->align_buffer
= NULL
;
2998 } else if (host
->adma_addr
& host
->align_mask
) {
2999 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3001 host
->flags
&= ~SDHCI_USE_ADMA
;
3002 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
3003 host
->adma_table
, host
->adma_addr
);
3004 kfree(host
->align_buffer
);
3005 host
->adma_table
= NULL
;
3006 host
->align_buffer
= NULL
;
3011 * If we use DMA, then it's up to the caller to set the DMA
3012 * mask, but PIO does not need the hw shim so we set a new
3013 * mask here in that case.
3015 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
3016 host
->dma_mask
= DMA_BIT_MASK(64);
3017 mmc_dev(mmc
)->dma_mask
= &host
->dma_mask
;
3020 if (host
->version
>= SDHCI_SPEC_300
)
3021 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
3022 >> SDHCI_CLOCK_BASE_SHIFT
;
3024 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
3025 >> SDHCI_CLOCK_BASE_SHIFT
;
3027 host
->max_clk
*= 1000000;
3028 if (host
->max_clk
== 0 || host
->quirks
&
3029 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
3030 if (!host
->ops
->get_max_clock
) {
3031 pr_err("%s: Hardware doesn't specify base clock "
3032 "frequency.\n", mmc_hostname(mmc
));
3035 host
->max_clk
= host
->ops
->get_max_clock(host
);
3039 * In case of Host Controller v3.00, find out whether clock
3040 * multiplier is supported.
3042 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
3043 SDHCI_CLOCK_MUL_SHIFT
;
3046 * In case the value in Clock Multiplier is 0, then programmable
3047 * clock mode is not supported, otherwise the actual clock
3048 * multiplier is one more than the value of Clock Multiplier
3049 * in the Capabilities Register.
3055 * Set host parameters.
3057 mmc
->ops
= &sdhci_ops
;
3058 max_clk
= host
->max_clk
;
3060 if (host
->ops
->get_min_clock
)
3061 mmc
->f_min
= host
->ops
->get_min_clock(host
);
3062 else if (host
->version
>= SDHCI_SPEC_300
) {
3063 if (host
->clk_mul
) {
3064 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
3065 max_clk
= host
->max_clk
* host
->clk_mul
;
3067 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
3069 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
3071 if (!mmc
->f_max
|| (mmc
->f_max
&& (mmc
->f_max
> max_clk
)))
3072 mmc
->f_max
= max_clk
;
3074 if (!(host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
3075 host
->timeout_clk
= (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >>
3076 SDHCI_TIMEOUT_CLK_SHIFT
;
3077 if (host
->timeout_clk
== 0) {
3078 if (host
->ops
->get_timeout_clock
) {
3080 host
->ops
->get_timeout_clock(host
);
3082 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3088 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
3089 host
->timeout_clk
*= 1000;
3091 mmc
->max_busy_timeout
= host
->ops
->get_max_timeout_count
?
3092 host
->ops
->get_max_timeout_count(host
) : 1 << 27;
3093 mmc
->max_busy_timeout
/= host
->timeout_clk
;
3096 if (override_timeout_clk
)
3097 host
->timeout_clk
= override_timeout_clk
;
3099 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
3100 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
3102 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
3103 host
->flags
|= SDHCI_AUTO_CMD12
;
3105 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3106 if ((host
->version
>= SDHCI_SPEC_300
) &&
3107 ((host
->flags
& SDHCI_USE_ADMA
) ||
3108 !(host
->flags
& SDHCI_USE_SDMA
)) &&
3109 !(host
->quirks2
& SDHCI_QUIRK2_ACMD23_BROKEN
)) {
3110 host
->flags
|= SDHCI_AUTO_CMD23
;
3111 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
3113 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
3117 * A controller may support 8-bit width, but the board itself
3118 * might not have the pins brought out. Boards that support
3119 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3120 * their platform code before calling sdhci_add_host(), and we
3121 * won't assume 8-bit width for hosts without that CAP.
3123 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
3124 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
3126 if (host
->quirks2
& SDHCI_QUIRK2_HOST_NO_CMD23
)
3127 mmc
->caps
&= ~MMC_CAP_CMD23
;
3129 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
3130 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
3132 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
3133 !(mmc
->caps
& MMC_CAP_NONREMOVABLE
) &&
3134 IS_ERR_VALUE(mmc_gpio_get_cd(host
->mmc
)))
3135 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
3137 /* If there are external regulators, get them */
3138 if (mmc_regulator_get_supply(mmc
) == -EPROBE_DEFER
)
3139 return -EPROBE_DEFER
;
3141 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3142 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
3143 ret
= regulator_enable(mmc
->supply
.vqmmc
);
3144 if (!regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1700000,
3146 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
|
3147 SDHCI_SUPPORT_SDR50
|
3148 SDHCI_SUPPORT_DDR50
);
3150 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3151 mmc_hostname(mmc
), ret
);
3152 mmc
->supply
.vqmmc
= ERR_PTR(-EINVAL
);
3156 if (host
->quirks2
& SDHCI_QUIRK2_NO_1_8_V
)
3157 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3158 SDHCI_SUPPORT_DDR50
);
3160 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3161 if (caps
[1] & (SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3162 SDHCI_SUPPORT_DDR50
))
3163 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
3165 /* SDR104 supports also implies SDR50 support */
3166 if (caps
[1] & SDHCI_SUPPORT_SDR104
) {
3167 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
3168 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3169 * field can be promoted to support HS200.
3171 if (!(host
->quirks2
& SDHCI_QUIRK2_BROKEN_HS200
))
3172 mmc
->caps2
|= MMC_CAP2_HS200
;
3173 } else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
3174 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
3176 if (host
->quirks2
& SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400
&&
3177 (caps
[1] & SDHCI_SUPPORT_HS400
))
3178 mmc
->caps2
|= MMC_CAP2_HS400
;
3180 if ((mmc
->caps2
& MMC_CAP2_HSX00_1_2V
) &&
3181 (IS_ERR(mmc
->supply
.vqmmc
) ||
3182 !regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1100000,
3184 mmc
->caps2
&= ~MMC_CAP2_HSX00_1_2V
;
3186 if ((caps
[1] & SDHCI_SUPPORT_DDR50
) &&
3187 !(host
->quirks2
& SDHCI_QUIRK2_BROKEN_DDR50
))
3188 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
3190 /* Does the host need tuning for SDR50? */
3191 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
3192 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
3194 /* Does the host need tuning for SDR104 / HS200? */
3195 if (mmc
->caps2
& MMC_CAP2_HS200
)
3196 host
->flags
|= SDHCI_SDR104_NEEDS_TUNING
;
3198 /* Driver Type(s) (A, C, D) supported by the host */
3199 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
3200 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
3201 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
3202 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
3203 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
3204 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
3206 /* Initial value for re-tuning timer count */
3207 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
3208 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
3211 * In case Re-tuning Timer is not disabled, the actual value of
3212 * re-tuning timer will be 2 ^ (n - 1).
3214 if (host
->tuning_count
)
3215 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
3217 /* Re-tuning mode supported by the Host Controller */
3218 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
3219 SDHCI_RETUNING_MODE_SHIFT
;
3224 * According to SD Host Controller spec v3.00, if the Host System
3225 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3226 * the value is meaningful only if Voltage Support in the Capabilities
3227 * register is set. The actual current value is 4 times the register
3230 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
3231 if (!max_current_caps
&& !IS_ERR(mmc
->supply
.vmmc
)) {
3232 int curr
= regulator_get_current_limit(mmc
->supply
.vmmc
);
3235 /* convert to SDHCI_MAX_CURRENT format */
3236 curr
= curr
/1000; /* convert to mA */
3237 curr
= curr
/SDHCI_MAX_CURRENT_MULTIPLIER
;
3239 curr
= min_t(u32
, curr
, SDHCI_MAX_CURRENT_LIMIT
);
3241 (curr
<< SDHCI_MAX_CURRENT_330_SHIFT
) |
3242 (curr
<< SDHCI_MAX_CURRENT_300_SHIFT
) |
3243 (curr
<< SDHCI_MAX_CURRENT_180_SHIFT
);
3247 if (caps
[0] & SDHCI_CAN_VDD_330
) {
3248 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
3250 mmc
->max_current_330
= ((max_current_caps
&
3251 SDHCI_MAX_CURRENT_330_MASK
) >>
3252 SDHCI_MAX_CURRENT_330_SHIFT
) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER
;
3255 if (caps
[0] & SDHCI_CAN_VDD_300
) {
3256 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
3258 mmc
->max_current_300
= ((max_current_caps
&
3259 SDHCI_MAX_CURRENT_300_MASK
) >>
3260 SDHCI_MAX_CURRENT_300_SHIFT
) *
3261 SDHCI_MAX_CURRENT_MULTIPLIER
;
3263 if (caps
[0] & SDHCI_CAN_VDD_180
) {
3264 ocr_avail
|= MMC_VDD_165_195
;
3266 mmc
->max_current_180
= ((max_current_caps
&
3267 SDHCI_MAX_CURRENT_180_MASK
) >>
3268 SDHCI_MAX_CURRENT_180_SHIFT
) *
3269 SDHCI_MAX_CURRENT_MULTIPLIER
;
3272 /* If OCR set by host, use it instead. */
3274 ocr_avail
= host
->ocr_mask
;
3276 /* If OCR set by external regulators, give it highest prio. */
3278 ocr_avail
= mmc
->ocr_avail
;
3280 mmc
->ocr_avail
= ocr_avail
;
3281 mmc
->ocr_avail_sdio
= ocr_avail
;
3282 if (host
->ocr_avail_sdio
)
3283 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
3284 mmc
->ocr_avail_sd
= ocr_avail
;
3285 if (host
->ocr_avail_sd
)
3286 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
3287 else /* normal SD controllers don't support 1.8V */
3288 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
3289 mmc
->ocr_avail_mmc
= ocr_avail
;
3290 if (host
->ocr_avail_mmc
)
3291 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
3293 if (mmc
->ocr_avail
== 0) {
3294 pr_err("%s: Hardware doesn't report any "
3295 "support voltages.\n", mmc_hostname(mmc
));
3299 spin_lock_init(&host
->lock
);
3302 * Maximum number of segments. Depends on if the hardware
3303 * can do scatter/gather or not.
3305 if (host
->flags
& SDHCI_USE_ADMA
)
3306 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3307 else if (host
->flags
& SDHCI_USE_SDMA
)
3310 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3313 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3314 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3317 mmc
->max_req_size
= 524288;
3320 * Maximum segment size. Could be one segment with the maximum number
3321 * of bytes. When doing hardware scatter/gather, each entry cannot
3322 * be larger than 64 KiB though.
3324 if (host
->flags
& SDHCI_USE_ADMA
) {
3325 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
3326 mmc
->max_seg_size
= 65535;
3328 mmc
->max_seg_size
= 65536;
3330 mmc
->max_seg_size
= mmc
->max_req_size
;
3334 * Maximum block size. This varies from controller to controller and
3335 * is specified in the capabilities register.
3337 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
3338 mmc
->max_blk_size
= 2;
3340 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
3341 SDHCI_MAX_BLOCK_SHIFT
;
3342 if (mmc
->max_blk_size
>= 3) {
3343 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3345 mmc
->max_blk_size
= 0;
3349 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
3352 * Maximum block count.
3354 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
3359 tasklet_init(&host
->finish_tasklet
,
3360 sdhci_tasklet_finish
, (unsigned long)host
);
3362 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
3364 init_waitqueue_head(&host
->buf_ready_int
);
3366 sdhci_init(host
, 0);
3368 ret
= request_threaded_irq(host
->irq
, sdhci_irq
, sdhci_thread_irq
,
3369 IRQF_SHARED
, mmc_hostname(mmc
), host
);
3371 pr_err("%s: Failed to request IRQ %d: %d\n",
3372 mmc_hostname(mmc
), host
->irq
, ret
);
3376 #ifdef CONFIG_MMC_DEBUG
3377 sdhci_dumpregs(host
);
3380 #ifdef SDHCI_USE_LEDS_CLASS
3381 snprintf(host
->led_name
, sizeof(host
->led_name
),
3382 "%s::", mmc_hostname(mmc
));
3383 host
->led
.name
= host
->led_name
;
3384 host
->led
.brightness
= LED_OFF
;
3385 host
->led
.default_trigger
= mmc_hostname(mmc
);
3386 host
->led
.brightness_set
= sdhci_led_control
;
3388 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
3390 pr_err("%s: Failed to register LED device: %d\n",
3391 mmc_hostname(mmc
), ret
);
3400 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3401 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
3402 (host
->flags
& SDHCI_USE_ADMA
) ?
3403 (host
->flags
& SDHCI_USE_64_BIT_DMA
) ? "ADMA 64-bit" : "ADMA" :
3404 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
3406 sdhci_enable_card_detection(host
);
3410 #ifdef SDHCI_USE_LEDS_CLASS
3412 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3413 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3414 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3415 free_irq(host
->irq
, host
);
3418 tasklet_kill(&host
->finish_tasklet
);
3423 EXPORT_SYMBOL_GPL(sdhci_add_host
);
3425 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
3427 struct mmc_host
*mmc
= host
->mmc
;
3428 unsigned long flags
;
3431 spin_lock_irqsave(&host
->lock
, flags
);
3433 host
->flags
|= SDHCI_DEVICE_DEAD
;
3436 pr_err("%s: Controller removed during "
3437 " transfer!\n", mmc_hostname(mmc
));
3439 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
3440 tasklet_schedule(&host
->finish_tasklet
);
3443 spin_unlock_irqrestore(&host
->lock
, flags
);
3446 sdhci_disable_card_detection(host
);
3448 mmc_remove_host(mmc
);
3450 #ifdef SDHCI_USE_LEDS_CLASS
3451 led_classdev_unregister(&host
->led
);
3455 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3457 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3458 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3459 free_irq(host
->irq
, host
);
3461 del_timer_sync(&host
->timer
);
3463 tasklet_kill(&host
->finish_tasklet
);
3465 if (!IS_ERR(mmc
->supply
.vqmmc
))
3466 regulator_disable(mmc
->supply
.vqmmc
);
3468 if (host
->adma_table
)
3469 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
3470 host
->adma_table
, host
->adma_addr
);
3471 kfree(host
->align_buffer
);
3473 host
->adma_table
= NULL
;
3474 host
->align_buffer
= NULL
;
3477 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3479 void sdhci_free_host(struct sdhci_host
*host
)
3481 mmc_free_host(host
->mmc
);
3484 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3486 /*****************************************************************************\
3488 * Driver init/exit *
3490 \*****************************************************************************/
3492 static int __init
sdhci_drv_init(void)
3495 ": Secure Digital Host Controller Interface driver\n");
3496 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3501 static void __exit
sdhci_drv_exit(void)
3505 module_init(sdhci_drv_init
);
3506 module_exit(sdhci_drv_exit
);
3508 module_param(debug_quirks
, uint
, 0444);
3509 module_param(debug_quirks2
, uint
, 0444);
3511 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3512 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3513 MODULE_LICENSE("GPL");
3515 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3516 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");