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mmc: sdhci: move sdhci_pre_dma_transfer()
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_do_get_cd(struct sdhci_host *host);
57
58 #ifdef CONFIG_PM
59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 #else
64 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65 {
66 return 0;
67 }
68 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69 {
70 return 0;
71 }
72 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73 {
74 }
75 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76 {
77 }
78 #endif
79
80 static void sdhci_dumpregs(struct sdhci_host *host)
81 {
82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
83 mmc_hostname(host->mmc));
84
85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
113 sdhci_readl(host, SDHCI_CAPABILITIES),
114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
116 sdhci_readw(host, SDHCI_COMMAND),
117 sdhci_readl(host, SDHCI_MAX_CURRENT));
118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120
121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
132
133 pr_debug(DRIVER_NAME ": ===========================================\n");
134 }
135
136 /*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140 \*****************************************************************************/
141
142 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143 {
144 u32 present;
145
146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
148 return;
149
150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
153
154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
162 }
163
164 static void sdhci_enable_card_detection(struct sdhci_host *host)
165 {
166 sdhci_set_card_detection(host, true);
167 }
168
169 static void sdhci_disable_card_detection(struct sdhci_host *host)
170 {
171 sdhci_set_card_detection(host, false);
172 }
173
174 void sdhci_reset(struct sdhci_host *host, u8 mask)
175 {
176 unsigned long timeout;
177
178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
179
180 if (mask & SDHCI_RESET_ALL) {
181 host->clock = 0;
182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
186
187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
192 if (timeout == 0) {
193 pr_err("%s: Reset 0x%x never completed.\n",
194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
200 }
201 }
202 EXPORT_SYMBOL_GPL(sdhci_reset);
203
204 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205 {
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
207 if (!sdhci_do_get_cd(host))
208 return;
209 }
210
211 host->ops->reset(host, mask);
212
213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
221 }
222 }
223
224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226 static void sdhci_init(struct sdhci_host *host, int soft)
227 {
228 if (soft)
229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
230 else
231 sdhci_do_reset(host, SDHCI_RESET_ALL);
232
233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
247 }
248
249 static void sdhci_reinit(struct sdhci_host *host)
250 {
251 sdhci_init(host, 0);
252 sdhci_enable_card_detection(host);
253 }
254
255 static void sdhci_activate_led(struct sdhci_host *host)
256 {
257 u8 ctrl;
258
259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
260 ctrl |= SDHCI_CTRL_LED;
261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
262 }
263
264 static void sdhci_deactivate_led(struct sdhci_host *host)
265 {
266 u8 ctrl;
267
268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
269 ctrl &= ~SDHCI_CTRL_LED;
270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
271 }
272
273 #ifdef SDHCI_USE_LEDS_CLASS
274 static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276 {
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
282 if (host->runtime_suspended)
283 goto out;
284
285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
289 out:
290 spin_unlock_irqrestore(&host->lock, flags);
291 }
292 #endif
293
294 /*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298 \*****************************************************************************/
299
300 static void sdhci_read_block_pio(struct sdhci_host *host)
301 {
302 unsigned long flags;
303 size_t blksize, len, chunk;
304 u32 uninitialized_var(scratch);
305 u8 *buf;
306
307 DBG("PIO reading\n");
308
309 blksize = host->data->blksz;
310 chunk = 0;
311
312 local_irq_save(flags);
313
314 while (blksize) {
315 BUG_ON(!sg_miter_next(&host->sg_miter));
316
317 len = min(host->sg_miter.length, blksize);
318
319 blksize -= len;
320 host->sg_miter.consumed = len;
321
322 buf = host->sg_miter.addr;
323
324 while (len) {
325 if (chunk == 0) {
326 scratch = sdhci_readl(host, SDHCI_BUFFER);
327 chunk = 4;
328 }
329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
336 }
337 }
338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
342 }
343
344 static void sdhci_write_block_pio(struct sdhci_host *host)
345 {
346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
350
351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
354 chunk = 0;
355 scratch = 0;
356
357 local_irq_save(flags);
358
359 while (blksize) {
360 BUG_ON(!sg_miter_next(&host->sg_miter));
361
362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
368
369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
377 sdhci_writel(host, scratch, SDHCI_BUFFER);
378 chunk = 0;
379 scratch = 0;
380 }
381 }
382 }
383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
387 }
388
389 static void sdhci_transfer_pio(struct sdhci_host *host)
390 {
391 u32 mask;
392
393 BUG_ON(!host->data);
394
395 if (host->blocks == 0)
396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
420
421 host->blocks--;
422 if (host->blocks == 0)
423 break;
424 }
425
426 DBG("PIO transfer complete.\n");
427 }
428
429 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
430 struct mmc_data *data)
431 {
432 int sg_count;
433
434 if (data->host_cookie == COOKIE_MAPPED) {
435 data->host_cookie = COOKIE_GIVEN;
436 return data->sg_count;
437 }
438
439 WARN_ON(data->host_cookie == COOKIE_GIVEN);
440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
449 data->host_cookie = COOKIE_MAPPED;
450
451 return sg_count;
452 }
453
454 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455 {
456 local_irq_save(*flags);
457 return kmap_atomic(sg_page(sg)) + sg->offset;
458 }
459
460 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461 {
462 kunmap_atomic(buffer);
463 local_irq_restore(*flags);
464 }
465
466 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
468 {
469 struct sdhci_adma2_64_desc *dma_desc = desc;
470
471 /* 32-bit and 64-bit descriptors have these members in same position */
472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
478 }
479
480 static void sdhci_adma_mark_end(void *desc)
481 {
482 struct sdhci_adma2_64_desc *dma_desc = desc;
483
484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
486 }
487
488 static int sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data)
490 {
491 struct scatterlist *sg;
492 unsigned long flags;
493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
503 host->sg_count = sdhci_pre_dma_transfer(host, data);
504 if (host->sg_count < 0)
505 return -EINVAL;
506
507 desc = host->adma_table;
508 align = host->align_buffer;
509
510 align_addr = host->align_addr;
511
512 for_each_sg(data->sg, sg, host->sg_count, i) {
513 addr = sg_dma_address(sg);
514 len = sg_dma_len(sg);
515
516 /*
517 * The SDHCI specification states that ADMA addresses must
518 * be 32-bit aligned. If they aren't, then we use a bounce
519 * buffer for the (up to three) bytes that screw up the
520 * alignment.
521 */
522 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
523 SDHCI_ADMA2_MASK;
524 if (offset) {
525 if (data->flags & MMC_DATA_WRITE) {
526 buffer = sdhci_kmap_atomic(sg, &flags);
527 memcpy(align, buffer, offset);
528 sdhci_kunmap_atomic(buffer, &flags);
529 }
530
531 /* tran, valid */
532 sdhci_adma_write_desc(host, desc, align_addr, offset,
533 ADMA2_TRAN_VALID);
534
535 BUG_ON(offset > 65536);
536
537 align += SDHCI_ADMA2_ALIGN;
538 align_addr += SDHCI_ADMA2_ALIGN;
539
540 desc += host->desc_sz;
541
542 addr += offset;
543 len -= offset;
544 }
545
546 BUG_ON(len > 65536);
547
548 if (len) {
549 /* tran, valid */
550 sdhci_adma_write_desc(host, desc, addr, len,
551 ADMA2_TRAN_VALID);
552 desc += host->desc_sz;
553 }
554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
559 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
560 }
561
562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 /* Mark the last descriptor as the terminating descriptor */
564 if (desc != host->adma_table) {
565 desc -= host->desc_sz;
566 sdhci_adma_mark_end(desc);
567 }
568 } else {
569 /* Add a terminating entry - nop, end, valid */
570 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
571 }
572 return 0;
573 }
574
575 static void sdhci_adma_table_post(struct sdhci_host *host,
576 struct mmc_data *data)
577 {
578 struct scatterlist *sg;
579 int i, size;
580 void *align;
581 char *buffer;
582 unsigned long flags;
583
584 if (data->flags & MMC_DATA_READ) {
585 bool has_unaligned = false;
586
587 /* Do a quick scan of the SG list for any unaligned mappings */
588 for_each_sg(data->sg, sg, host->sg_count, i)
589 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
590 has_unaligned = true;
591 break;
592 }
593
594 if (has_unaligned) {
595 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
596 data->sg_len, DMA_FROM_DEVICE);
597
598 align = host->align_buffer;
599
600 for_each_sg(data->sg, sg, host->sg_count, i) {
601 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
602 size = SDHCI_ADMA2_ALIGN -
603 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
604
605 buffer = sdhci_kmap_atomic(sg, &flags);
606 memcpy(buffer, align, size);
607 sdhci_kunmap_atomic(buffer, &flags);
608
609 align += SDHCI_ADMA2_ALIGN;
610 }
611 }
612 }
613 }
614 }
615
616 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
617 {
618 u8 count;
619 struct mmc_data *data = cmd->data;
620 unsigned target_timeout, current_timeout;
621
622 /*
623 * If the host controller provides us with an incorrect timeout
624 * value, just skip the check and use 0xE. The hardware may take
625 * longer to time out, but that's much better than having a too-short
626 * timeout value.
627 */
628 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
629 return 0xE;
630
631 /* Unspecified timeout, assume max */
632 if (!data && !cmd->busy_timeout)
633 return 0xE;
634
635 /* timeout in us */
636 if (!data)
637 target_timeout = cmd->busy_timeout * 1000;
638 else {
639 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
640 if (host->clock && data->timeout_clks) {
641 unsigned long long val;
642
643 /*
644 * data->timeout_clks is in units of clock cycles.
645 * host->clock is in Hz. target_timeout is in us.
646 * Hence, us = 1000000 * cycles / Hz. Round up.
647 */
648 val = 1000000 * data->timeout_clks;
649 if (do_div(val, host->clock))
650 target_timeout++;
651 target_timeout += val;
652 }
653 }
654
655 /*
656 * Figure out needed cycles.
657 * We do this in steps in order to fit inside a 32 bit int.
658 * The first step is the minimum timeout, which will have a
659 * minimum resolution of 6 bits:
660 * (1) 2^13*1000 > 2^22,
661 * (2) host->timeout_clk < 2^16
662 * =>
663 * (1) / (2) > 2^6
664 */
665 count = 0;
666 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
667 while (current_timeout < target_timeout) {
668 count++;
669 current_timeout <<= 1;
670 if (count >= 0xF)
671 break;
672 }
673
674 if (count >= 0xF) {
675 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
676 mmc_hostname(host->mmc), count, cmd->opcode);
677 count = 0xE;
678 }
679
680 return count;
681 }
682
683 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
684 {
685 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
686 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
687
688 if (host->flags & SDHCI_REQ_USE_DMA)
689 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
690 else
691 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
692
693 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
694 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
695 }
696
697 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
698 {
699 u8 count;
700
701 if (host->ops->set_timeout) {
702 host->ops->set_timeout(host, cmd);
703 } else {
704 count = sdhci_calc_timeout(host, cmd);
705 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
706 }
707 }
708
709 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
710 {
711 u8 ctrl;
712 struct mmc_data *data = cmd->data;
713 int ret;
714
715 WARN_ON(host->data);
716
717 if (data || (cmd->flags & MMC_RSP_BUSY))
718 sdhci_set_timeout(host, cmd);
719
720 if (!data)
721 return;
722
723 /* Sanity checks */
724 BUG_ON(data->blksz * data->blocks > 524288);
725 BUG_ON(data->blksz > host->mmc->max_blk_size);
726 BUG_ON(data->blocks > 65535);
727
728 host->data = data;
729 host->data_early = 0;
730 host->data->bytes_xfered = 0;
731
732 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
733 host->flags |= SDHCI_REQ_USE_DMA;
734
735 /*
736 * FIXME: This doesn't account for merging when mapping the
737 * scatterlist.
738 */
739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 int broken, i;
741 struct scatterlist *sg;
742
743 broken = 0;
744 if (host->flags & SDHCI_USE_ADMA) {
745 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
746 broken = 1;
747 } else {
748 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
749 broken = 1;
750 }
751
752 if (unlikely(broken)) {
753 for_each_sg(data->sg, sg, data->sg_len, i) {
754 if (sg->length & 0x3) {
755 DBG("Reverting to PIO because of transfer size (%d)\n",
756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
789 DBG("Reverting to PIO because of bad alignment\n");
790 host->flags &= ~SDHCI_REQ_USE_DMA;
791 break;
792 }
793 }
794 }
795 }
796
797 if (host->flags & SDHCI_REQ_USE_DMA) {
798 if (host->flags & SDHCI_USE_ADMA) {
799 ret = sdhci_adma_table_pre(host, data);
800 if (ret) {
801 /*
802 * This only happens when someone fed
803 * us an invalid request.
804 */
805 WARN_ON(1);
806 host->flags &= ~SDHCI_REQ_USE_DMA;
807 } else {
808 sdhci_writel(host, host->adma_addr,
809 SDHCI_ADMA_ADDRESS);
810 if (host->flags & SDHCI_USE_64_BIT_DMA)
811 sdhci_writel(host,
812 (u64)host->adma_addr >> 32,
813 SDHCI_ADMA_ADDRESS_HI);
814 }
815 } else {
816 int sg_cnt;
817
818 sg_cnt = sdhci_pre_dma_transfer(host, data);
819 if (sg_cnt <= 0) {
820 /*
821 * This only happens when someone fed
822 * us an invalid request.
823 */
824 WARN_ON(1);
825 host->flags &= ~SDHCI_REQ_USE_DMA;
826 } else {
827 WARN_ON(sg_cnt != 1);
828 sdhci_writel(host, sg_dma_address(data->sg),
829 SDHCI_DMA_ADDRESS);
830 }
831 }
832 }
833
834 /*
835 * Always adjust the DMA selection as some controllers
836 * (e.g. JMicron) can't do PIO properly when the selection
837 * is ADMA.
838 */
839 if (host->version >= SDHCI_SPEC_200) {
840 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
841 ctrl &= ~SDHCI_CTRL_DMA_MASK;
842 if ((host->flags & SDHCI_REQ_USE_DMA) &&
843 (host->flags & SDHCI_USE_ADMA)) {
844 if (host->flags & SDHCI_USE_64_BIT_DMA)
845 ctrl |= SDHCI_CTRL_ADMA64;
846 else
847 ctrl |= SDHCI_CTRL_ADMA32;
848 } else {
849 ctrl |= SDHCI_CTRL_SDMA;
850 }
851 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
852 }
853
854 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
855 int flags;
856
857 flags = SG_MITER_ATOMIC;
858 if (host->data->flags & MMC_DATA_READ)
859 flags |= SG_MITER_TO_SG;
860 else
861 flags |= SG_MITER_FROM_SG;
862 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
863 host->blocks = data->blocks;
864 }
865
866 sdhci_set_transfer_irqs(host);
867
868 /* Set the DMA boundary value and block size */
869 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
870 data->blksz), SDHCI_BLOCK_SIZE);
871 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
872 }
873
874 static void sdhci_set_transfer_mode(struct sdhci_host *host,
875 struct mmc_command *cmd)
876 {
877 u16 mode = 0;
878 struct mmc_data *data = cmd->data;
879
880 if (data == NULL) {
881 if (host->quirks2 &
882 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
883 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
884 } else {
885 /* clear Auto CMD settings for no data CMDs */
886 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
887 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
888 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
889 }
890 return;
891 }
892
893 WARN_ON(!host->data);
894
895 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
896 mode = SDHCI_TRNS_BLK_CNT_EN;
897
898 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
899 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
900 /*
901 * If we are sending CMD23, CMD12 never gets sent
902 * on successful completion (so no Auto-CMD12).
903 */
904 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
905 (cmd->opcode != SD_IO_RW_EXTENDED))
906 mode |= SDHCI_TRNS_AUTO_CMD12;
907 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
908 mode |= SDHCI_TRNS_AUTO_CMD23;
909 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
910 }
911 }
912
913 if (data->flags & MMC_DATA_READ)
914 mode |= SDHCI_TRNS_READ;
915 if (host->flags & SDHCI_REQ_USE_DMA)
916 mode |= SDHCI_TRNS_DMA;
917
918 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
919 }
920
921 static void sdhci_finish_data(struct sdhci_host *host)
922 {
923 struct mmc_data *data;
924
925 BUG_ON(!host->data);
926
927 data = host->data;
928 host->data = NULL;
929
930 if (host->flags & SDHCI_REQ_USE_DMA) {
931 if (host->flags & SDHCI_USE_ADMA)
932 sdhci_adma_table_post(host, data);
933
934 if (data->host_cookie == COOKIE_MAPPED) {
935 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
936 (data->flags & MMC_DATA_READ) ?
937 DMA_FROM_DEVICE : DMA_TO_DEVICE);
938 data->host_cookie = COOKIE_UNMAPPED;
939 }
940 }
941
942 /*
943 * The specification states that the block count register must
944 * be updated, but it does not specify at what point in the
945 * data flow. That makes the register entirely useless to read
946 * back so we have to assume that nothing made it to the card
947 * in the event of an error.
948 */
949 if (data->error)
950 data->bytes_xfered = 0;
951 else
952 data->bytes_xfered = data->blksz * data->blocks;
953
954 /*
955 * Need to send CMD12 if -
956 * a) open-ended multiblock transfer (no CMD23)
957 * b) error in multiblock transfer
958 */
959 if (data->stop &&
960 (data->error ||
961 !host->mrq->sbc)) {
962
963 /*
964 * The controller needs a reset of internal state machines
965 * upon error conditions.
966 */
967 if (data->error) {
968 sdhci_do_reset(host, SDHCI_RESET_CMD);
969 sdhci_do_reset(host, SDHCI_RESET_DATA);
970 }
971
972 sdhci_send_command(host, data->stop);
973 } else
974 tasklet_schedule(&host->finish_tasklet);
975 }
976
977 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
978 {
979 int flags;
980 u32 mask;
981 unsigned long timeout;
982
983 WARN_ON(host->cmd);
984
985 /* Initially, a command has no error */
986 cmd->error = 0;
987
988 /* Wait max 10 ms */
989 timeout = 10;
990
991 mask = SDHCI_CMD_INHIBIT;
992 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
993 mask |= SDHCI_DATA_INHIBIT;
994
995 /* We shouldn't wait for data inihibit for stop commands, even
996 though they might use busy signaling */
997 if (host->mrq->data && (cmd == host->mrq->data->stop))
998 mask &= ~SDHCI_DATA_INHIBIT;
999
1000 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1001 if (timeout == 0) {
1002 pr_err("%s: Controller never released inhibit bit(s).\n",
1003 mmc_hostname(host->mmc));
1004 sdhci_dumpregs(host);
1005 cmd->error = -EIO;
1006 tasklet_schedule(&host->finish_tasklet);
1007 return;
1008 }
1009 timeout--;
1010 mdelay(1);
1011 }
1012
1013 timeout = jiffies;
1014 if (!cmd->data && cmd->busy_timeout > 9000)
1015 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1016 else
1017 timeout += 10 * HZ;
1018 mod_timer(&host->timer, timeout);
1019
1020 host->cmd = cmd;
1021 host->busy_handle = 0;
1022
1023 sdhci_prepare_data(host, cmd);
1024
1025 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1026
1027 sdhci_set_transfer_mode(host, cmd);
1028
1029 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1030 pr_err("%s: Unsupported response type!\n",
1031 mmc_hostname(host->mmc));
1032 cmd->error = -EINVAL;
1033 tasklet_schedule(&host->finish_tasklet);
1034 return;
1035 }
1036
1037 if (!(cmd->flags & MMC_RSP_PRESENT))
1038 flags = SDHCI_CMD_RESP_NONE;
1039 else if (cmd->flags & MMC_RSP_136)
1040 flags = SDHCI_CMD_RESP_LONG;
1041 else if (cmd->flags & MMC_RSP_BUSY)
1042 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1043 else
1044 flags = SDHCI_CMD_RESP_SHORT;
1045
1046 if (cmd->flags & MMC_RSP_CRC)
1047 flags |= SDHCI_CMD_CRC;
1048 if (cmd->flags & MMC_RSP_OPCODE)
1049 flags |= SDHCI_CMD_INDEX;
1050
1051 /* CMD19 is special in that the Data Present Select should be set */
1052 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1053 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1054 flags |= SDHCI_CMD_DATA;
1055
1056 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1057 }
1058 EXPORT_SYMBOL_GPL(sdhci_send_command);
1059
1060 static void sdhci_finish_command(struct sdhci_host *host)
1061 {
1062 int i;
1063
1064 BUG_ON(host->cmd == NULL);
1065
1066 if (host->cmd->flags & MMC_RSP_PRESENT) {
1067 if (host->cmd->flags & MMC_RSP_136) {
1068 /* CRC is stripped so we need to do some shifting. */
1069 for (i = 0;i < 4;i++) {
1070 host->cmd->resp[i] = sdhci_readl(host,
1071 SDHCI_RESPONSE + (3-i)*4) << 8;
1072 if (i != 3)
1073 host->cmd->resp[i] |=
1074 sdhci_readb(host,
1075 SDHCI_RESPONSE + (3-i)*4-1);
1076 }
1077 } else {
1078 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1079 }
1080 }
1081
1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1084 host->cmd = NULL;
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else {
1087
1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
1091
1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1094
1095 host->cmd = NULL;
1096 }
1097 }
1098
1099 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1100 {
1101 u16 preset = 0;
1102
1103 switch (host->timing) {
1104 case MMC_TIMING_UHS_SDR12:
1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 break;
1107 case MMC_TIMING_UHS_SDR25:
1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1109 break;
1110 case MMC_TIMING_UHS_SDR50:
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1112 break;
1113 case MMC_TIMING_UHS_SDR104:
1114 case MMC_TIMING_MMC_HS200:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case MMC_TIMING_UHS_DDR50:
1118 case MMC_TIMING_MMC_DDR52:
1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1120 break;
1121 case MMC_TIMING_MMC_HS400:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1123 break;
1124 default:
1125 pr_warn("%s: Invalid UHS-I mode selected\n",
1126 mmc_hostname(host->mmc));
1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1128 break;
1129 }
1130 return preset;
1131 }
1132
1133 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1134 {
1135 int div = 0; /* Initialized for compiler warning */
1136 int real_div = div, clk_mul = 1;
1137 u16 clk = 0;
1138 unsigned long timeout;
1139 bool switch_base_clk = false;
1140
1141 host->mmc->actual_clock = 0;
1142
1143 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1144 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1145 mdelay(1);
1146
1147 if (clock == 0)
1148 return;
1149
1150 if (host->version >= SDHCI_SPEC_300) {
1151 if (host->preset_enabled) {
1152 u16 pre_val;
1153
1154 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1155 pre_val = sdhci_get_preset_value(host);
1156 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1157 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1158 if (host->clk_mul &&
1159 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1160 clk = SDHCI_PROG_CLOCK_MODE;
1161 real_div = div + 1;
1162 clk_mul = host->clk_mul;
1163 } else {
1164 real_div = max_t(int, 1, div << 1);
1165 }
1166 goto clock_set;
1167 }
1168
1169 /*
1170 * Check if the Host Controller supports Programmable Clock
1171 * Mode.
1172 */
1173 if (host->clk_mul) {
1174 for (div = 1; div <= 1024; div++) {
1175 if ((host->max_clk * host->clk_mul / div)
1176 <= clock)
1177 break;
1178 }
1179 if ((host->max_clk * host->clk_mul / div) <= clock) {
1180 /*
1181 * Set Programmable Clock Mode in the Clock
1182 * Control register.
1183 */
1184 clk = SDHCI_PROG_CLOCK_MODE;
1185 real_div = div;
1186 clk_mul = host->clk_mul;
1187 div--;
1188 } else {
1189 /*
1190 * Divisor can be too small to reach clock
1191 * speed requirement. Then use the base clock.
1192 */
1193 switch_base_clk = true;
1194 }
1195 }
1196
1197 if (!host->clk_mul || switch_base_clk) {
1198 /* Version 3.00 divisors must be a multiple of 2. */
1199 if (host->max_clk <= clock)
1200 div = 1;
1201 else {
1202 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1203 div += 2) {
1204 if ((host->max_clk / div) <= clock)
1205 break;
1206 }
1207 }
1208 real_div = div;
1209 div >>= 1;
1210 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1211 && !div && host->max_clk <= 25000000)
1212 div = 1;
1213 }
1214 } else {
1215 /* Version 2.00 divisors must be a power of 2. */
1216 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
1220 real_div = div;
1221 div >>= 1;
1222 }
1223
1224 clock_set:
1225 if (real_div)
1226 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1227 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1228 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1229 << SDHCI_DIVIDER_HI_SHIFT;
1230 clk |= SDHCI_CLOCK_INT_EN;
1231 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1232
1233 /* Wait max 20 ms */
1234 timeout = 20;
1235 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1236 & SDHCI_CLOCK_INT_STABLE)) {
1237 if (timeout == 0) {
1238 pr_err("%s: Internal clock never stabilised.\n",
1239 mmc_hostname(host->mmc));
1240 sdhci_dumpregs(host);
1241 return;
1242 }
1243 timeout--;
1244 mdelay(1);
1245 }
1246
1247 clk |= SDHCI_CLOCK_CARD_EN;
1248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1249 }
1250 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1251
1252 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1253 unsigned short vdd)
1254 {
1255 struct mmc_host *mmc = host->mmc;
1256 u8 pwr = 0;
1257
1258 if (mode != MMC_POWER_OFF) {
1259 switch (1 << vdd) {
1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
1272 WARN(1, "%s: Invalid vdd %#x\n",
1273 mmc_hostname(host->mmc), vdd);
1274 break;
1275 }
1276 }
1277
1278 if (host->pwr == pwr)
1279 return;
1280
1281 host->pwr = pwr;
1282
1283 if (pwr == 0) {
1284 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1285 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1286 sdhci_runtime_pm_bus_off(host);
1287 vdd = 0;
1288 } else {
1289 /*
1290 * Spec says that we should clear the power reg before setting
1291 * a new value. Some controllers don't seem to like this though.
1292 */
1293 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1294 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1295
1296 /*
1297 * At least the Marvell CaFe chip gets confused if we set the
1298 * voltage and set turn on power at the same time, so set the
1299 * voltage first.
1300 */
1301 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1302 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1303
1304 pwr |= SDHCI_POWER_ON;
1305
1306 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1307
1308 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1309 sdhci_runtime_pm_bus_on(host);
1310
1311 /*
1312 * Some controllers need an extra 10ms delay of 10ms before
1313 * they can apply clock after applying power
1314 */
1315 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1316 mdelay(10);
1317 }
1318
1319 if (!IS_ERR(mmc->supply.vmmc)) {
1320 spin_unlock_irq(&host->lock);
1321 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1322 spin_lock_irq(&host->lock);
1323 }
1324 }
1325
1326 /*****************************************************************************\
1327 * *
1328 * MMC callbacks *
1329 * *
1330 \*****************************************************************************/
1331
1332 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1333 {
1334 struct sdhci_host *host;
1335 int present;
1336 unsigned long flags;
1337
1338 host = mmc_priv(mmc);
1339
1340 sdhci_runtime_pm_get(host);
1341
1342 /* Firstly check card presence */
1343 present = mmc->ops->get_cd(mmc);
1344
1345 spin_lock_irqsave(&host->lock, flags);
1346
1347 WARN_ON(host->mrq != NULL);
1348
1349 #ifndef SDHCI_USE_LEDS_CLASS
1350 sdhci_activate_led(host);
1351 #endif
1352
1353 /*
1354 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1355 * requests if Auto-CMD12 is enabled.
1356 */
1357 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1358 if (mrq->stop) {
1359 mrq->data->stop = NULL;
1360 mrq->stop = NULL;
1361 }
1362 }
1363
1364 host->mrq = mrq;
1365
1366 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1367 host->mrq->cmd->error = -ENOMEDIUM;
1368 tasklet_schedule(&host->finish_tasklet);
1369 } else {
1370 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1371 sdhci_send_command(host, mrq->sbc);
1372 else
1373 sdhci_send_command(host, mrq->cmd);
1374 }
1375
1376 mmiowb();
1377 spin_unlock_irqrestore(&host->lock, flags);
1378 }
1379
1380 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1381 {
1382 u8 ctrl;
1383
1384 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1385 if (width == MMC_BUS_WIDTH_8) {
1386 ctrl &= ~SDHCI_CTRL_4BITBUS;
1387 if (host->version >= SDHCI_SPEC_300)
1388 ctrl |= SDHCI_CTRL_8BITBUS;
1389 } else {
1390 if (host->version >= SDHCI_SPEC_300)
1391 ctrl &= ~SDHCI_CTRL_8BITBUS;
1392 if (width == MMC_BUS_WIDTH_4)
1393 ctrl |= SDHCI_CTRL_4BITBUS;
1394 else
1395 ctrl &= ~SDHCI_CTRL_4BITBUS;
1396 }
1397 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1398 }
1399 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1400
1401 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1402 {
1403 u16 ctrl_2;
1404
1405 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1406 /* Select Bus Speed Mode for host */
1407 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1408 if ((timing == MMC_TIMING_MMC_HS200) ||
1409 (timing == MMC_TIMING_UHS_SDR104))
1410 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1411 else if (timing == MMC_TIMING_UHS_SDR12)
1412 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1413 else if (timing == MMC_TIMING_UHS_SDR25)
1414 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1415 else if (timing == MMC_TIMING_UHS_SDR50)
1416 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1417 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1418 (timing == MMC_TIMING_MMC_DDR52))
1419 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1420 else if (timing == MMC_TIMING_MMC_HS400)
1421 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1422 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1423 }
1424 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1425
1426 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1427 {
1428 unsigned long flags;
1429 u8 ctrl;
1430 struct mmc_host *mmc = host->mmc;
1431
1432 spin_lock_irqsave(&host->lock, flags);
1433
1434 if (host->flags & SDHCI_DEVICE_DEAD) {
1435 spin_unlock_irqrestore(&host->lock, flags);
1436 if (!IS_ERR(mmc->supply.vmmc) &&
1437 ios->power_mode == MMC_POWER_OFF)
1438 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1439 return;
1440 }
1441
1442 /*
1443 * Reset the chip on each power off.
1444 * Should clear out any weird states.
1445 */
1446 if (ios->power_mode == MMC_POWER_OFF) {
1447 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1448 sdhci_reinit(host);
1449 }
1450
1451 if (host->version >= SDHCI_SPEC_300 &&
1452 (ios->power_mode == MMC_POWER_UP) &&
1453 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1454 sdhci_enable_preset_value(host, false);
1455
1456 if (!ios->clock || ios->clock != host->clock) {
1457 host->ops->set_clock(host, ios->clock);
1458 host->clock = ios->clock;
1459
1460 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1461 host->clock) {
1462 host->timeout_clk = host->mmc->actual_clock ?
1463 host->mmc->actual_clock / 1000 :
1464 host->clock / 1000;
1465 host->mmc->max_busy_timeout =
1466 host->ops->get_max_timeout_count ?
1467 host->ops->get_max_timeout_count(host) :
1468 1 << 27;
1469 host->mmc->max_busy_timeout /= host->timeout_clk;
1470 }
1471 }
1472
1473 sdhci_set_power(host, ios->power_mode, ios->vdd);
1474
1475 if (host->ops->platform_send_init_74_clocks)
1476 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1477
1478 host->ops->set_bus_width(host, ios->bus_width);
1479
1480 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1481
1482 if ((ios->timing == MMC_TIMING_SD_HS ||
1483 ios->timing == MMC_TIMING_MMC_HS)
1484 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1485 ctrl |= SDHCI_CTRL_HISPD;
1486 else
1487 ctrl &= ~SDHCI_CTRL_HISPD;
1488
1489 if (host->version >= SDHCI_SPEC_300) {
1490 u16 clk, ctrl_2;
1491
1492 /* In case of UHS-I modes, set High Speed Enable */
1493 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1494 (ios->timing == MMC_TIMING_MMC_HS200) ||
1495 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1496 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1497 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1498 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1499 (ios->timing == MMC_TIMING_UHS_SDR25))
1500 ctrl |= SDHCI_CTRL_HISPD;
1501
1502 if (!host->preset_enabled) {
1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1504 /*
1505 * We only need to set Driver Strength if the
1506 * preset value enable is not set.
1507 */
1508 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1509 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1510 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1512 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1513 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1514 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1515 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1516 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1517 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1518 else {
1519 pr_warn("%s: invalid driver type, default to driver type B\n",
1520 mmc_hostname(mmc));
1521 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1522 }
1523
1524 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1525 } else {
1526 /*
1527 * According to SDHC Spec v3.00, if the Preset Value
1528 * Enable in the Host Control 2 register is set, we
1529 * need to reset SD Clock Enable before changing High
1530 * Speed Enable to avoid generating clock gliches.
1531 */
1532
1533 /* Reset SD Clock Enable */
1534 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1535 clk &= ~SDHCI_CLOCK_CARD_EN;
1536 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1537
1538 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1539
1540 /* Re-enable SD Clock */
1541 host->ops->set_clock(host, host->clock);
1542 }
1543
1544 /* Reset SD Clock Enable */
1545 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1546 clk &= ~SDHCI_CLOCK_CARD_EN;
1547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1548
1549 host->ops->set_uhs_signaling(host, ios->timing);
1550 host->timing = ios->timing;
1551
1552 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1553 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1554 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1555 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1557 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1558 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1559 u16 preset;
1560
1561 sdhci_enable_preset_value(host, true);
1562 preset = sdhci_get_preset_value(host);
1563 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1564 >> SDHCI_PRESET_DRV_SHIFT;
1565 }
1566
1567 /* Re-enable SD Clock */
1568 host->ops->set_clock(host, host->clock);
1569 } else
1570 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1571
1572 /*
1573 * Some (ENE) controllers go apeshit on some ios operation,
1574 * signalling timeout and CRC errors even on CMD0. Resetting
1575 * it on each ios seems to solve the problem.
1576 */
1577 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1578 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1579
1580 mmiowb();
1581 spin_unlock_irqrestore(&host->lock, flags);
1582 }
1583
1584 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1585 {
1586 struct sdhci_host *host = mmc_priv(mmc);
1587
1588 sdhci_runtime_pm_get(host);
1589 sdhci_do_set_ios(host, ios);
1590 sdhci_runtime_pm_put(host);
1591 }
1592
1593 static int sdhci_do_get_cd(struct sdhci_host *host)
1594 {
1595 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1596
1597 if (host->flags & SDHCI_DEVICE_DEAD)
1598 return 0;
1599
1600 /* If nonremovable, assume that the card is always present. */
1601 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1602 return 1;
1603
1604 /*
1605 * Try slot gpio detect, if defined it take precedence
1606 * over build in controller functionality
1607 */
1608 if (!IS_ERR_VALUE(gpio_cd))
1609 return !!gpio_cd;
1610
1611 /* If polling, assume that the card is always present. */
1612 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1613 return 1;
1614
1615 /* Host native card detect */
1616 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1617 }
1618
1619 static int sdhci_get_cd(struct mmc_host *mmc)
1620 {
1621 struct sdhci_host *host = mmc_priv(mmc);
1622 int ret;
1623
1624 sdhci_runtime_pm_get(host);
1625 ret = sdhci_do_get_cd(host);
1626 sdhci_runtime_pm_put(host);
1627 return ret;
1628 }
1629
1630 static int sdhci_check_ro(struct sdhci_host *host)
1631 {
1632 unsigned long flags;
1633 int is_readonly;
1634
1635 spin_lock_irqsave(&host->lock, flags);
1636
1637 if (host->flags & SDHCI_DEVICE_DEAD)
1638 is_readonly = 0;
1639 else if (host->ops->get_ro)
1640 is_readonly = host->ops->get_ro(host);
1641 else
1642 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1643 & SDHCI_WRITE_PROTECT);
1644
1645 spin_unlock_irqrestore(&host->lock, flags);
1646
1647 /* This quirk needs to be replaced by a callback-function later */
1648 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1649 !is_readonly : is_readonly;
1650 }
1651
1652 #define SAMPLE_COUNT 5
1653
1654 static int sdhci_do_get_ro(struct sdhci_host *host)
1655 {
1656 int i, ro_count;
1657
1658 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1659 return sdhci_check_ro(host);
1660
1661 ro_count = 0;
1662 for (i = 0; i < SAMPLE_COUNT; i++) {
1663 if (sdhci_check_ro(host)) {
1664 if (++ro_count > SAMPLE_COUNT / 2)
1665 return 1;
1666 }
1667 msleep(30);
1668 }
1669 return 0;
1670 }
1671
1672 static void sdhci_hw_reset(struct mmc_host *mmc)
1673 {
1674 struct sdhci_host *host = mmc_priv(mmc);
1675
1676 if (host->ops && host->ops->hw_reset)
1677 host->ops->hw_reset(host);
1678 }
1679
1680 static int sdhci_get_ro(struct mmc_host *mmc)
1681 {
1682 struct sdhci_host *host = mmc_priv(mmc);
1683 int ret;
1684
1685 sdhci_runtime_pm_get(host);
1686 ret = sdhci_do_get_ro(host);
1687 sdhci_runtime_pm_put(host);
1688 return ret;
1689 }
1690
1691 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1692 {
1693 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1694 if (enable)
1695 host->ier |= SDHCI_INT_CARD_INT;
1696 else
1697 host->ier &= ~SDHCI_INT_CARD_INT;
1698
1699 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1700 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1701 mmiowb();
1702 }
1703 }
1704
1705 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1706 {
1707 struct sdhci_host *host = mmc_priv(mmc);
1708 unsigned long flags;
1709
1710 sdhci_runtime_pm_get(host);
1711
1712 spin_lock_irqsave(&host->lock, flags);
1713 if (enable)
1714 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1715 else
1716 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1717
1718 sdhci_enable_sdio_irq_nolock(host, enable);
1719 spin_unlock_irqrestore(&host->lock, flags);
1720
1721 sdhci_runtime_pm_put(host);
1722 }
1723
1724 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1725 struct mmc_ios *ios)
1726 {
1727 struct mmc_host *mmc = host->mmc;
1728 u16 ctrl;
1729 int ret;
1730
1731 /*
1732 * Signal Voltage Switching is only applicable for Host Controllers
1733 * v3.00 and above.
1734 */
1735 if (host->version < SDHCI_SPEC_300)
1736 return 0;
1737
1738 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1739
1740 switch (ios->signal_voltage) {
1741 case MMC_SIGNAL_VOLTAGE_330:
1742 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1743 ctrl &= ~SDHCI_CTRL_VDD_180;
1744 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1745
1746 if (!IS_ERR(mmc->supply.vqmmc)) {
1747 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1748 3600000);
1749 if (ret) {
1750 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1751 mmc_hostname(mmc));
1752 return -EIO;
1753 }
1754 }
1755 /* Wait for 5ms */
1756 usleep_range(5000, 5500);
1757
1758 /* 3.3V regulator output should be stable within 5 ms */
1759 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1760 if (!(ctrl & SDHCI_CTRL_VDD_180))
1761 return 0;
1762
1763 pr_warn("%s: 3.3V regulator output did not became stable\n",
1764 mmc_hostname(mmc));
1765
1766 return -EAGAIN;
1767 case MMC_SIGNAL_VOLTAGE_180:
1768 if (!IS_ERR(mmc->supply.vqmmc)) {
1769 ret = regulator_set_voltage(mmc->supply.vqmmc,
1770 1700000, 1950000);
1771 if (ret) {
1772 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1773 mmc_hostname(mmc));
1774 return -EIO;
1775 }
1776 }
1777
1778 /*
1779 * Enable 1.8V Signal Enable in the Host Control2
1780 * register
1781 */
1782 ctrl |= SDHCI_CTRL_VDD_180;
1783 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1784
1785 /* Some controller need to do more when switching */
1786 if (host->ops->voltage_switch)
1787 host->ops->voltage_switch(host);
1788
1789 /* 1.8V regulator output should be stable within 5 ms */
1790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1791 if (ctrl & SDHCI_CTRL_VDD_180)
1792 return 0;
1793
1794 pr_warn("%s: 1.8V regulator output did not became stable\n",
1795 mmc_hostname(mmc));
1796
1797 return -EAGAIN;
1798 case MMC_SIGNAL_VOLTAGE_120:
1799 if (!IS_ERR(mmc->supply.vqmmc)) {
1800 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1801 1300000);
1802 if (ret) {
1803 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1804 mmc_hostname(mmc));
1805 return -EIO;
1806 }
1807 }
1808 return 0;
1809 default:
1810 /* No signal voltage switch required */
1811 return 0;
1812 }
1813 }
1814
1815 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1816 struct mmc_ios *ios)
1817 {
1818 struct sdhci_host *host = mmc_priv(mmc);
1819 int err;
1820
1821 if (host->version < SDHCI_SPEC_300)
1822 return 0;
1823 sdhci_runtime_pm_get(host);
1824 err = sdhci_do_start_signal_voltage_switch(host, ios);
1825 sdhci_runtime_pm_put(host);
1826 return err;
1827 }
1828
1829 static int sdhci_card_busy(struct mmc_host *mmc)
1830 {
1831 struct sdhci_host *host = mmc_priv(mmc);
1832 u32 present_state;
1833
1834 sdhci_runtime_pm_get(host);
1835 /* Check whether DAT[3:0] is 0000 */
1836 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1837 sdhci_runtime_pm_put(host);
1838
1839 return !(present_state & SDHCI_DATA_LVL_MASK);
1840 }
1841
1842 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1843 {
1844 struct sdhci_host *host = mmc_priv(mmc);
1845 unsigned long flags;
1846
1847 spin_lock_irqsave(&host->lock, flags);
1848 host->flags |= SDHCI_HS400_TUNING;
1849 spin_unlock_irqrestore(&host->lock, flags);
1850
1851 return 0;
1852 }
1853
1854 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1855 {
1856 struct sdhci_host *host = mmc_priv(mmc);
1857 u16 ctrl;
1858 int tuning_loop_counter = MAX_TUNING_LOOP;
1859 int err = 0;
1860 unsigned long flags;
1861 unsigned int tuning_count = 0;
1862 bool hs400_tuning;
1863
1864 sdhci_runtime_pm_get(host);
1865 spin_lock_irqsave(&host->lock, flags);
1866
1867 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1868 host->flags &= ~SDHCI_HS400_TUNING;
1869
1870 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1871 tuning_count = host->tuning_count;
1872
1873 /*
1874 * The Host Controller needs tuning in case of SDR104 and DDR50
1875 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1876 * the Capabilities register.
1877 * If the Host Controller supports the HS200 mode then the
1878 * tuning function has to be executed.
1879 */
1880 switch (host->timing) {
1881 /* HS400 tuning is done in HS200 mode */
1882 case MMC_TIMING_MMC_HS400:
1883 err = -EINVAL;
1884 goto out_unlock;
1885
1886 case MMC_TIMING_MMC_HS200:
1887 /*
1888 * Periodic re-tuning for HS400 is not expected to be needed, so
1889 * disable it here.
1890 */
1891 if (hs400_tuning)
1892 tuning_count = 0;
1893 break;
1894
1895 case MMC_TIMING_UHS_SDR104:
1896 case MMC_TIMING_UHS_DDR50:
1897 break;
1898
1899 case MMC_TIMING_UHS_SDR50:
1900 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1901 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1902 break;
1903 /* FALLTHROUGH */
1904
1905 default:
1906 goto out_unlock;
1907 }
1908
1909 if (host->ops->platform_execute_tuning) {
1910 spin_unlock_irqrestore(&host->lock, flags);
1911 err = host->ops->platform_execute_tuning(host, opcode);
1912 sdhci_runtime_pm_put(host);
1913 return err;
1914 }
1915
1916 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1917 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1918 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1919 ctrl |= SDHCI_CTRL_TUNED_CLK;
1920 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1921
1922 /*
1923 * As per the Host Controller spec v3.00, tuning command
1924 * generates Buffer Read Ready interrupt, so enable that.
1925 *
1926 * Note: The spec clearly says that when tuning sequence
1927 * is being performed, the controller does not generate
1928 * interrupts other than Buffer Read Ready interrupt. But
1929 * to make sure we don't hit a controller bug, we _only_
1930 * enable Buffer Read Ready interrupt here.
1931 */
1932 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1933 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1934
1935 /*
1936 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1937 * of loops reaches 40 times or a timeout of 150ms occurs.
1938 */
1939 do {
1940 struct mmc_command cmd = {0};
1941 struct mmc_request mrq = {NULL};
1942
1943 cmd.opcode = opcode;
1944 cmd.arg = 0;
1945 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1946 cmd.retries = 0;
1947 cmd.data = NULL;
1948 cmd.error = 0;
1949
1950 if (tuning_loop_counter-- == 0)
1951 break;
1952
1953 mrq.cmd = &cmd;
1954 host->mrq = &mrq;
1955
1956 /*
1957 * In response to CMD19, the card sends 64 bytes of tuning
1958 * block to the Host Controller. So we set the block size
1959 * to 64 here.
1960 */
1961 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1962 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1964 SDHCI_BLOCK_SIZE);
1965 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1966 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1967 SDHCI_BLOCK_SIZE);
1968 } else {
1969 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1970 SDHCI_BLOCK_SIZE);
1971 }
1972
1973 /*
1974 * The tuning block is sent by the card to the host controller.
1975 * So we set the TRNS_READ bit in the Transfer Mode register.
1976 * This also takes care of setting DMA Enable and Multi Block
1977 * Select in the same register to 0.
1978 */
1979 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1980
1981 sdhci_send_command(host, &cmd);
1982
1983 host->cmd = NULL;
1984 host->mrq = NULL;
1985
1986 spin_unlock_irqrestore(&host->lock, flags);
1987 /* Wait for Buffer Read Ready interrupt */
1988 wait_event_interruptible_timeout(host->buf_ready_int,
1989 (host->tuning_done == 1),
1990 msecs_to_jiffies(50));
1991 spin_lock_irqsave(&host->lock, flags);
1992
1993 if (!host->tuning_done) {
1994 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
1995 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1999
2000 err = -EIO;
2001 goto out;
2002 }
2003
2004 host->tuning_done = 0;
2005
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2007
2008 /* eMMC spec does not require a delay between tuning cycles */
2009 if (opcode == MMC_SEND_TUNING_BLOCK)
2010 mdelay(1);
2011 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2012
2013 /*
2014 * The Host Driver has exhausted the maximum number of loops allowed,
2015 * so use fixed sampling frequency.
2016 */
2017 if (tuning_loop_counter < 0) {
2018 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2019 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2020 }
2021 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2022 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2023 err = -EIO;
2024 }
2025
2026 out:
2027 if (tuning_count) {
2028 /*
2029 * In case tuning fails, host controllers which support
2030 * re-tuning can try tuning again at a later time, when the
2031 * re-tuning timer expires. So for these controllers, we
2032 * return 0. Since there might be other controllers who do not
2033 * have this capability, we return error for them.
2034 */
2035 err = 0;
2036 }
2037
2038 host->mmc->retune_period = err ? 0 : tuning_count;
2039
2040 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2041 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2042 out_unlock:
2043 spin_unlock_irqrestore(&host->lock, flags);
2044 sdhci_runtime_pm_put(host);
2045
2046 return err;
2047 }
2048
2049 static int sdhci_select_drive_strength(struct mmc_card *card,
2050 unsigned int max_dtr, int host_drv,
2051 int card_drv, int *drv_type)
2052 {
2053 struct sdhci_host *host = mmc_priv(card->host);
2054
2055 if (!host->ops->select_drive_strength)
2056 return 0;
2057
2058 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2059 card_drv, drv_type);
2060 }
2061
2062 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2063 {
2064 /* Host Controller v3.00 defines preset value registers */
2065 if (host->version < SDHCI_SPEC_300)
2066 return;
2067
2068 /*
2069 * We only enable or disable Preset Value if they are not already
2070 * enabled or disabled respectively. Otherwise, we bail out.
2071 */
2072 if (host->preset_enabled != enable) {
2073 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2074
2075 if (enable)
2076 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2077 else
2078 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2079
2080 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2081
2082 if (enable)
2083 host->flags |= SDHCI_PV_ENABLED;
2084 else
2085 host->flags &= ~SDHCI_PV_ENABLED;
2086
2087 host->preset_enabled = enable;
2088 }
2089 }
2090
2091 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2092 int err)
2093 {
2094 struct sdhci_host *host = mmc_priv(mmc);
2095 struct mmc_data *data = mrq->data;
2096
2097 if (data->host_cookie == COOKIE_GIVEN ||
2098 data->host_cookie == COOKIE_MAPPED)
2099 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2100 data->flags & MMC_DATA_WRITE ?
2101 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2102
2103 data->host_cookie = COOKIE_UNMAPPED;
2104 }
2105
2106 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2107 bool is_first_req)
2108 {
2109 struct sdhci_host *host = mmc_priv(mmc);
2110
2111 mrq->data->host_cookie = COOKIE_UNMAPPED;
2112
2113 if (host->flags & SDHCI_REQ_USE_DMA)
2114 sdhci_pre_dma_transfer(host, mrq->data);
2115 }
2116
2117 static void sdhci_card_event(struct mmc_host *mmc)
2118 {
2119 struct sdhci_host *host = mmc_priv(mmc);
2120 unsigned long flags;
2121 int present;
2122
2123 /* First check if client has provided their own card event */
2124 if (host->ops->card_event)
2125 host->ops->card_event(host);
2126
2127 present = sdhci_do_get_cd(host);
2128
2129 spin_lock_irqsave(&host->lock, flags);
2130
2131 /* Check host->mrq first in case we are runtime suspended */
2132 if (host->mrq && !present) {
2133 pr_err("%s: Card removed during transfer!\n",
2134 mmc_hostname(host->mmc));
2135 pr_err("%s: Resetting controller.\n",
2136 mmc_hostname(host->mmc));
2137
2138 sdhci_do_reset(host, SDHCI_RESET_CMD);
2139 sdhci_do_reset(host, SDHCI_RESET_DATA);
2140
2141 host->mrq->cmd->error = -ENOMEDIUM;
2142 tasklet_schedule(&host->finish_tasklet);
2143 }
2144
2145 spin_unlock_irqrestore(&host->lock, flags);
2146 }
2147
2148 static const struct mmc_host_ops sdhci_ops = {
2149 .request = sdhci_request,
2150 .post_req = sdhci_post_req,
2151 .pre_req = sdhci_pre_req,
2152 .set_ios = sdhci_set_ios,
2153 .get_cd = sdhci_get_cd,
2154 .get_ro = sdhci_get_ro,
2155 .hw_reset = sdhci_hw_reset,
2156 .enable_sdio_irq = sdhci_enable_sdio_irq,
2157 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2158 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2159 .execute_tuning = sdhci_execute_tuning,
2160 .select_drive_strength = sdhci_select_drive_strength,
2161 .card_event = sdhci_card_event,
2162 .card_busy = sdhci_card_busy,
2163 };
2164
2165 /*****************************************************************************\
2166 * *
2167 * Tasklets *
2168 * *
2169 \*****************************************************************************/
2170
2171 static void sdhci_tasklet_finish(unsigned long param)
2172 {
2173 struct sdhci_host *host;
2174 unsigned long flags;
2175 struct mmc_request *mrq;
2176
2177 host = (struct sdhci_host*)param;
2178
2179 spin_lock_irqsave(&host->lock, flags);
2180
2181 /*
2182 * If this tasklet gets rescheduled while running, it will
2183 * be run again afterwards but without any active request.
2184 */
2185 if (!host->mrq) {
2186 spin_unlock_irqrestore(&host->lock, flags);
2187 return;
2188 }
2189
2190 del_timer(&host->timer);
2191
2192 mrq = host->mrq;
2193
2194 /*
2195 * Always unmap the data buffers if they were mapped by
2196 * sdhci_prepare_data() whenever we finish with a request.
2197 * This avoids leaking DMA mappings on error.
2198 */
2199 if (host->flags & SDHCI_REQ_USE_DMA) {
2200 struct mmc_data *data = mrq->data;
2201
2202 if (data && data->host_cookie == COOKIE_MAPPED) {
2203 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2204 (data->flags & MMC_DATA_READ) ?
2205 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2206 data->host_cookie = COOKIE_UNMAPPED;
2207 }
2208 }
2209
2210 /*
2211 * The controller needs a reset of internal state machines
2212 * upon error conditions.
2213 */
2214 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2215 ((mrq->cmd && mrq->cmd->error) ||
2216 (mrq->sbc && mrq->sbc->error) ||
2217 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2218 (mrq->data->stop && mrq->data->stop->error))) ||
2219 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2220
2221 /* Some controllers need this kick or reset won't work here */
2222 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2223 /* This is to force an update */
2224 host->ops->set_clock(host, host->clock);
2225
2226 /* Spec says we should do both at the same time, but Ricoh
2227 controllers do not like that. */
2228 sdhci_do_reset(host, SDHCI_RESET_CMD);
2229 sdhci_do_reset(host, SDHCI_RESET_DATA);
2230 }
2231
2232 host->mrq = NULL;
2233 host->cmd = NULL;
2234 host->data = NULL;
2235
2236 #ifndef SDHCI_USE_LEDS_CLASS
2237 sdhci_deactivate_led(host);
2238 #endif
2239
2240 mmiowb();
2241 spin_unlock_irqrestore(&host->lock, flags);
2242
2243 mmc_request_done(host->mmc, mrq);
2244 sdhci_runtime_pm_put(host);
2245 }
2246
2247 static void sdhci_timeout_timer(unsigned long data)
2248 {
2249 struct sdhci_host *host;
2250 unsigned long flags;
2251
2252 host = (struct sdhci_host*)data;
2253
2254 spin_lock_irqsave(&host->lock, flags);
2255
2256 if (host->mrq) {
2257 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2258 mmc_hostname(host->mmc));
2259 sdhci_dumpregs(host);
2260
2261 if (host->data) {
2262 host->data->error = -ETIMEDOUT;
2263 sdhci_finish_data(host);
2264 } else {
2265 if (host->cmd)
2266 host->cmd->error = -ETIMEDOUT;
2267 else
2268 host->mrq->cmd->error = -ETIMEDOUT;
2269
2270 tasklet_schedule(&host->finish_tasklet);
2271 }
2272 }
2273
2274 mmiowb();
2275 spin_unlock_irqrestore(&host->lock, flags);
2276 }
2277
2278 /*****************************************************************************\
2279 * *
2280 * Interrupt handling *
2281 * *
2282 \*****************************************************************************/
2283
2284 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2285 {
2286 BUG_ON(intmask == 0);
2287
2288 if (!host->cmd) {
2289 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2290 mmc_hostname(host->mmc), (unsigned)intmask);
2291 sdhci_dumpregs(host);
2292 return;
2293 }
2294
2295 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2296 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2297 if (intmask & SDHCI_INT_TIMEOUT)
2298 host->cmd->error = -ETIMEDOUT;
2299 else
2300 host->cmd->error = -EILSEQ;
2301
2302 /*
2303 * If this command initiates a data phase and a response
2304 * CRC error is signalled, the card can start transferring
2305 * data - the card may have received the command without
2306 * error. We must not terminate the mmc_request early.
2307 *
2308 * If the card did not receive the command or returned an
2309 * error which prevented it sending data, the data phase
2310 * will time out.
2311 */
2312 if (host->cmd->data &&
2313 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2314 SDHCI_INT_CRC) {
2315 host->cmd = NULL;
2316 return;
2317 }
2318
2319 tasklet_schedule(&host->finish_tasklet);
2320 return;
2321 }
2322
2323 /*
2324 * The host can send and interrupt when the busy state has
2325 * ended, allowing us to wait without wasting CPU cycles.
2326 * Unfortunately this is overloaded on the "data complete"
2327 * interrupt, so we need to take some care when handling
2328 * it.
2329 *
2330 * Note: The 1.0 specification is a bit ambiguous about this
2331 * feature so there might be some problems with older
2332 * controllers.
2333 */
2334 if (host->cmd->flags & MMC_RSP_BUSY) {
2335 if (host->cmd->data)
2336 DBG("Cannot wait for busy signal when also doing a data transfer");
2337 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2338 && !host->busy_handle) {
2339 /* Mark that command complete before busy is ended */
2340 host->busy_handle = 1;
2341 return;
2342 }
2343
2344 /* The controller does not support the end-of-busy IRQ,
2345 * fall through and take the SDHCI_INT_RESPONSE */
2346 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2347 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2348 *mask &= ~SDHCI_INT_DATA_END;
2349 }
2350
2351 if (intmask & SDHCI_INT_RESPONSE)
2352 sdhci_finish_command(host);
2353 }
2354
2355 #ifdef CONFIG_MMC_DEBUG
2356 static void sdhci_adma_show_error(struct sdhci_host *host)
2357 {
2358 const char *name = mmc_hostname(host->mmc);
2359 void *desc = host->adma_table;
2360
2361 sdhci_dumpregs(host);
2362
2363 while (true) {
2364 struct sdhci_adma2_64_desc *dma_desc = desc;
2365
2366 if (host->flags & SDHCI_USE_64_BIT_DMA)
2367 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2368 name, desc, le32_to_cpu(dma_desc->addr_hi),
2369 le32_to_cpu(dma_desc->addr_lo),
2370 le16_to_cpu(dma_desc->len),
2371 le16_to_cpu(dma_desc->cmd));
2372 else
2373 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2374 name, desc, le32_to_cpu(dma_desc->addr_lo),
2375 le16_to_cpu(dma_desc->len),
2376 le16_to_cpu(dma_desc->cmd));
2377
2378 desc += host->desc_sz;
2379
2380 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2381 break;
2382 }
2383 }
2384 #else
2385 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2386 #endif
2387
2388 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2389 {
2390 u32 command;
2391 BUG_ON(intmask == 0);
2392
2393 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2394 if (intmask & SDHCI_INT_DATA_AVAIL) {
2395 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2396 if (command == MMC_SEND_TUNING_BLOCK ||
2397 command == MMC_SEND_TUNING_BLOCK_HS200) {
2398 host->tuning_done = 1;
2399 wake_up(&host->buf_ready_int);
2400 return;
2401 }
2402 }
2403
2404 if (!host->data) {
2405 /*
2406 * The "data complete" interrupt is also used to
2407 * indicate that a busy state has ended. See comment
2408 * above in sdhci_cmd_irq().
2409 */
2410 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2411 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2412 host->cmd->error = -ETIMEDOUT;
2413 tasklet_schedule(&host->finish_tasklet);
2414 return;
2415 }
2416 if (intmask & SDHCI_INT_DATA_END) {
2417 /*
2418 * Some cards handle busy-end interrupt
2419 * before the command completed, so make
2420 * sure we do things in the proper order.
2421 */
2422 if (host->busy_handle)
2423 sdhci_finish_command(host);
2424 else
2425 host->busy_handle = 1;
2426 return;
2427 }
2428 }
2429
2430 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2431 mmc_hostname(host->mmc), (unsigned)intmask);
2432 sdhci_dumpregs(host);
2433
2434 return;
2435 }
2436
2437 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2438 host->data->error = -ETIMEDOUT;
2439 else if (intmask & SDHCI_INT_DATA_END_BIT)
2440 host->data->error = -EILSEQ;
2441 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2442 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2443 != MMC_BUS_TEST_R)
2444 host->data->error = -EILSEQ;
2445 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2446 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2447 sdhci_adma_show_error(host);
2448 host->data->error = -EIO;
2449 if (host->ops->adma_workaround)
2450 host->ops->adma_workaround(host, intmask);
2451 }
2452
2453 if (host->data->error)
2454 sdhci_finish_data(host);
2455 else {
2456 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2457 sdhci_transfer_pio(host);
2458
2459 /*
2460 * We currently don't do anything fancy with DMA
2461 * boundaries, but as we can't disable the feature
2462 * we need to at least restart the transfer.
2463 *
2464 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2465 * should return a valid address to continue from, but as
2466 * some controllers are faulty, don't trust them.
2467 */
2468 if (intmask & SDHCI_INT_DMA_END) {
2469 u32 dmastart, dmanow;
2470 dmastart = sg_dma_address(host->data->sg);
2471 dmanow = dmastart + host->data->bytes_xfered;
2472 /*
2473 * Force update to the next DMA block boundary.
2474 */
2475 dmanow = (dmanow &
2476 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2477 SDHCI_DEFAULT_BOUNDARY_SIZE;
2478 host->data->bytes_xfered = dmanow - dmastart;
2479 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2480 " next 0x%08x\n",
2481 mmc_hostname(host->mmc), dmastart,
2482 host->data->bytes_xfered, dmanow);
2483 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2484 }
2485
2486 if (intmask & SDHCI_INT_DATA_END) {
2487 if (host->cmd) {
2488 /*
2489 * Data managed to finish before the
2490 * command completed. Make sure we do
2491 * things in the proper order.
2492 */
2493 host->data_early = 1;
2494 } else {
2495 sdhci_finish_data(host);
2496 }
2497 }
2498 }
2499 }
2500
2501 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2502 {
2503 irqreturn_t result = IRQ_NONE;
2504 struct sdhci_host *host = dev_id;
2505 u32 intmask, mask, unexpected = 0;
2506 int max_loops = 16;
2507
2508 spin_lock(&host->lock);
2509
2510 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2511 spin_unlock(&host->lock);
2512 return IRQ_NONE;
2513 }
2514
2515 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2516 if (!intmask || intmask == 0xffffffff) {
2517 result = IRQ_NONE;
2518 goto out;
2519 }
2520
2521 do {
2522 /* Clear selected interrupts. */
2523 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2524 SDHCI_INT_BUS_POWER);
2525 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2526
2527 DBG("*** %s got interrupt: 0x%08x\n",
2528 mmc_hostname(host->mmc), intmask);
2529
2530 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2531 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2532 SDHCI_CARD_PRESENT;
2533
2534 /*
2535 * There is a observation on i.mx esdhc. INSERT
2536 * bit will be immediately set again when it gets
2537 * cleared, if a card is inserted. We have to mask
2538 * the irq to prevent interrupt storm which will
2539 * freeze the system. And the REMOVE gets the
2540 * same situation.
2541 *
2542 * More testing are needed here to ensure it works
2543 * for other platforms though.
2544 */
2545 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2546 SDHCI_INT_CARD_REMOVE);
2547 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2548 SDHCI_INT_CARD_INSERT;
2549 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2550 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2551
2552 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2553 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2554
2555 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2556 SDHCI_INT_CARD_REMOVE);
2557 result = IRQ_WAKE_THREAD;
2558 }
2559
2560 if (intmask & SDHCI_INT_CMD_MASK)
2561 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2562 &intmask);
2563
2564 if (intmask & SDHCI_INT_DATA_MASK)
2565 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2566
2567 if (intmask & SDHCI_INT_BUS_POWER)
2568 pr_err("%s: Card is consuming too much power!\n",
2569 mmc_hostname(host->mmc));
2570
2571 if (intmask & SDHCI_INT_CARD_INT) {
2572 sdhci_enable_sdio_irq_nolock(host, false);
2573 host->thread_isr |= SDHCI_INT_CARD_INT;
2574 result = IRQ_WAKE_THREAD;
2575 }
2576
2577 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2578 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2579 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2580 SDHCI_INT_CARD_INT);
2581
2582 if (intmask) {
2583 unexpected |= intmask;
2584 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2585 }
2586
2587 if (result == IRQ_NONE)
2588 result = IRQ_HANDLED;
2589
2590 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2591 } while (intmask && --max_loops);
2592 out:
2593 spin_unlock(&host->lock);
2594
2595 if (unexpected) {
2596 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2597 mmc_hostname(host->mmc), unexpected);
2598 sdhci_dumpregs(host);
2599 }
2600
2601 return result;
2602 }
2603
2604 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2605 {
2606 struct sdhci_host *host = dev_id;
2607 unsigned long flags;
2608 u32 isr;
2609
2610 spin_lock_irqsave(&host->lock, flags);
2611 isr = host->thread_isr;
2612 host->thread_isr = 0;
2613 spin_unlock_irqrestore(&host->lock, flags);
2614
2615 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2616 sdhci_card_event(host->mmc);
2617 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2618 }
2619
2620 if (isr & SDHCI_INT_CARD_INT) {
2621 sdio_run_irqs(host->mmc);
2622
2623 spin_lock_irqsave(&host->lock, flags);
2624 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2625 sdhci_enable_sdio_irq_nolock(host, true);
2626 spin_unlock_irqrestore(&host->lock, flags);
2627 }
2628
2629 return isr ? IRQ_HANDLED : IRQ_NONE;
2630 }
2631
2632 /*****************************************************************************\
2633 * *
2634 * Suspend/resume *
2635 * *
2636 \*****************************************************************************/
2637
2638 #ifdef CONFIG_PM
2639 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2640 {
2641 u8 val;
2642 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2643 | SDHCI_WAKE_ON_INT;
2644
2645 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2646 val |= mask ;
2647 /* Avoid fake wake up */
2648 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2649 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2650 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2651 }
2652 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2653
2654 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2655 {
2656 u8 val;
2657 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2658 | SDHCI_WAKE_ON_INT;
2659
2660 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2661 val &= ~mask;
2662 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2663 }
2664
2665 int sdhci_suspend_host(struct sdhci_host *host)
2666 {
2667 sdhci_disable_card_detection(host);
2668
2669 mmc_retune_timer_stop(host->mmc);
2670 mmc_retune_needed(host->mmc);
2671
2672 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2673 host->ier = 0;
2674 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2675 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2676 free_irq(host->irq, host);
2677 } else {
2678 sdhci_enable_irq_wakeups(host);
2679 enable_irq_wake(host->irq);
2680 }
2681 return 0;
2682 }
2683
2684 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2685
2686 int sdhci_resume_host(struct sdhci_host *host)
2687 {
2688 int ret = 0;
2689
2690 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2691 if (host->ops->enable_dma)
2692 host->ops->enable_dma(host);
2693 }
2694
2695 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2696 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2697 /* Card keeps power but host controller does not */
2698 sdhci_init(host, 0);
2699 host->pwr = 0;
2700 host->clock = 0;
2701 sdhci_do_set_ios(host, &host->mmc->ios);
2702 } else {
2703 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2704 mmiowb();
2705 }
2706
2707 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2708 ret = request_threaded_irq(host->irq, sdhci_irq,
2709 sdhci_thread_irq, IRQF_SHARED,
2710 mmc_hostname(host->mmc), host);
2711 if (ret)
2712 return ret;
2713 } else {
2714 sdhci_disable_irq_wakeups(host);
2715 disable_irq_wake(host->irq);
2716 }
2717
2718 sdhci_enable_card_detection(host);
2719
2720 return ret;
2721 }
2722
2723 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2724
2725 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2726 {
2727 return pm_runtime_get_sync(host->mmc->parent);
2728 }
2729
2730 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2731 {
2732 pm_runtime_mark_last_busy(host->mmc->parent);
2733 return pm_runtime_put_autosuspend(host->mmc->parent);
2734 }
2735
2736 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2737 {
2738 if (host->bus_on)
2739 return;
2740 host->bus_on = true;
2741 pm_runtime_get_noresume(host->mmc->parent);
2742 }
2743
2744 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2745 {
2746 if (!host->bus_on)
2747 return;
2748 host->bus_on = false;
2749 pm_runtime_put_noidle(host->mmc->parent);
2750 }
2751
2752 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2753 {
2754 unsigned long flags;
2755
2756 mmc_retune_timer_stop(host->mmc);
2757 mmc_retune_needed(host->mmc);
2758
2759 spin_lock_irqsave(&host->lock, flags);
2760 host->ier &= SDHCI_INT_CARD_INT;
2761 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2762 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2763 spin_unlock_irqrestore(&host->lock, flags);
2764
2765 synchronize_hardirq(host->irq);
2766
2767 spin_lock_irqsave(&host->lock, flags);
2768 host->runtime_suspended = true;
2769 spin_unlock_irqrestore(&host->lock, flags);
2770
2771 return 0;
2772 }
2773 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2774
2775 int sdhci_runtime_resume_host(struct sdhci_host *host)
2776 {
2777 unsigned long flags;
2778 int host_flags = host->flags;
2779
2780 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2781 if (host->ops->enable_dma)
2782 host->ops->enable_dma(host);
2783 }
2784
2785 sdhci_init(host, 0);
2786
2787 /* Force clock and power re-program */
2788 host->pwr = 0;
2789 host->clock = 0;
2790 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2791 sdhci_do_set_ios(host, &host->mmc->ios);
2792
2793 if ((host_flags & SDHCI_PV_ENABLED) &&
2794 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2795 spin_lock_irqsave(&host->lock, flags);
2796 sdhci_enable_preset_value(host, true);
2797 spin_unlock_irqrestore(&host->lock, flags);
2798 }
2799
2800 spin_lock_irqsave(&host->lock, flags);
2801
2802 host->runtime_suspended = false;
2803
2804 /* Enable SDIO IRQ */
2805 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2806 sdhci_enable_sdio_irq_nolock(host, true);
2807
2808 /* Enable Card Detection */
2809 sdhci_enable_card_detection(host);
2810
2811 spin_unlock_irqrestore(&host->lock, flags);
2812
2813 return 0;
2814 }
2815 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2816
2817 #endif /* CONFIG_PM */
2818
2819 /*****************************************************************************\
2820 * *
2821 * Device allocation/registration *
2822 * *
2823 \*****************************************************************************/
2824
2825 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2826 size_t priv_size)
2827 {
2828 struct mmc_host *mmc;
2829 struct sdhci_host *host;
2830
2831 WARN_ON(dev == NULL);
2832
2833 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2834 if (!mmc)
2835 return ERR_PTR(-ENOMEM);
2836
2837 host = mmc_priv(mmc);
2838 host->mmc = mmc;
2839 host->mmc_host_ops = sdhci_ops;
2840 mmc->ops = &host->mmc_host_ops;
2841
2842 return host;
2843 }
2844
2845 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2846
2847 int sdhci_add_host(struct sdhci_host *host)
2848 {
2849 struct mmc_host *mmc;
2850 u32 caps[2] = {0, 0};
2851 u32 max_current_caps;
2852 unsigned int ocr_avail;
2853 unsigned int override_timeout_clk;
2854 u32 max_clk;
2855 int ret;
2856
2857 WARN_ON(host == NULL);
2858 if (host == NULL)
2859 return -EINVAL;
2860
2861 mmc = host->mmc;
2862
2863 if (debug_quirks)
2864 host->quirks = debug_quirks;
2865 if (debug_quirks2)
2866 host->quirks2 = debug_quirks2;
2867
2868 override_timeout_clk = host->timeout_clk;
2869
2870 sdhci_do_reset(host, SDHCI_RESET_ALL);
2871
2872 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2873 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2874 >> SDHCI_SPEC_VER_SHIFT;
2875 if (host->version > SDHCI_SPEC_300) {
2876 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2877 mmc_hostname(mmc), host->version);
2878 }
2879
2880 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2881 sdhci_readl(host, SDHCI_CAPABILITIES);
2882
2883 if (host->version >= SDHCI_SPEC_300)
2884 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2885 host->caps1 :
2886 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2887
2888 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2889 host->flags |= SDHCI_USE_SDMA;
2890 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2891 DBG("Controller doesn't have SDMA capability\n");
2892 else
2893 host->flags |= SDHCI_USE_SDMA;
2894
2895 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2896 (host->flags & SDHCI_USE_SDMA)) {
2897 DBG("Disabling DMA as it is marked broken\n");
2898 host->flags &= ~SDHCI_USE_SDMA;
2899 }
2900
2901 if ((host->version >= SDHCI_SPEC_200) &&
2902 (caps[0] & SDHCI_CAN_DO_ADMA2))
2903 host->flags |= SDHCI_USE_ADMA;
2904
2905 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2906 (host->flags & SDHCI_USE_ADMA)) {
2907 DBG("Disabling ADMA as it is marked broken\n");
2908 host->flags &= ~SDHCI_USE_ADMA;
2909 }
2910
2911 /*
2912 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2913 * and *must* do 64-bit DMA. A driver has the opportunity to change
2914 * that during the first call to ->enable_dma(). Similarly
2915 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2916 * implement.
2917 */
2918 if (caps[0] & SDHCI_CAN_64BIT)
2919 host->flags |= SDHCI_USE_64_BIT_DMA;
2920
2921 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2922 if (host->ops->enable_dma) {
2923 if (host->ops->enable_dma(host)) {
2924 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2925 mmc_hostname(mmc));
2926 host->flags &=
2927 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2928 }
2929 }
2930 }
2931
2932 /* SDMA does not support 64-bit DMA */
2933 if (host->flags & SDHCI_USE_64_BIT_DMA)
2934 host->flags &= ~SDHCI_USE_SDMA;
2935
2936 if (host->flags & SDHCI_USE_ADMA) {
2937 dma_addr_t dma;
2938 void *buf;
2939
2940 /*
2941 * The DMA descriptor table size is calculated as the maximum
2942 * number of segments times 2, to allow for an alignment
2943 * descriptor for each segment, plus 1 for a nop end descriptor,
2944 * all multipled by the descriptor size.
2945 */
2946 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2947 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2948 SDHCI_ADMA2_64_DESC_SZ;
2949 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2950 } else {
2951 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2952 SDHCI_ADMA2_32_DESC_SZ;
2953 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2954 }
2955
2956 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2957 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2958 host->adma_table_sz, &dma, GFP_KERNEL);
2959 if (!buf) {
2960 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2961 mmc_hostname(mmc));
2962 host->flags &= ~SDHCI_USE_ADMA;
2963 } else if ((dma + host->align_buffer_sz) &
2964 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2965 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2966 mmc_hostname(mmc));
2967 host->flags &= ~SDHCI_USE_ADMA;
2968 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2969 host->adma_table_sz, buf, dma);
2970 } else {
2971 host->align_buffer = buf;
2972 host->align_addr = dma;
2973
2974 host->adma_table = buf + host->align_buffer_sz;
2975 host->adma_addr = dma + host->align_buffer_sz;
2976 }
2977 }
2978
2979 /*
2980 * If we use DMA, then it's up to the caller to set the DMA
2981 * mask, but PIO does not need the hw shim so we set a new
2982 * mask here in that case.
2983 */
2984 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2985 host->dma_mask = DMA_BIT_MASK(64);
2986 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2987 }
2988
2989 if (host->version >= SDHCI_SPEC_300)
2990 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2991 >> SDHCI_CLOCK_BASE_SHIFT;
2992 else
2993 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2994 >> SDHCI_CLOCK_BASE_SHIFT;
2995
2996 host->max_clk *= 1000000;
2997 if (host->max_clk == 0 || host->quirks &
2998 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2999 if (!host->ops->get_max_clock) {
3000 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3001 mmc_hostname(mmc));
3002 return -ENODEV;
3003 }
3004 host->max_clk = host->ops->get_max_clock(host);
3005 }
3006
3007 /*
3008 * In case of Host Controller v3.00, find out whether clock
3009 * multiplier is supported.
3010 */
3011 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3012 SDHCI_CLOCK_MUL_SHIFT;
3013
3014 /*
3015 * In case the value in Clock Multiplier is 0, then programmable
3016 * clock mode is not supported, otherwise the actual clock
3017 * multiplier is one more than the value of Clock Multiplier
3018 * in the Capabilities Register.
3019 */
3020 if (host->clk_mul)
3021 host->clk_mul += 1;
3022
3023 /*
3024 * Set host parameters.
3025 */
3026 max_clk = host->max_clk;
3027
3028 if (host->ops->get_min_clock)
3029 mmc->f_min = host->ops->get_min_clock(host);
3030 else if (host->version >= SDHCI_SPEC_300) {
3031 if (host->clk_mul) {
3032 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3033 max_clk = host->max_clk * host->clk_mul;
3034 } else
3035 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3036 } else
3037 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3038
3039 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3040 mmc->f_max = max_clk;
3041
3042 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3043 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3044 SDHCI_TIMEOUT_CLK_SHIFT;
3045 if (host->timeout_clk == 0) {
3046 if (host->ops->get_timeout_clock) {
3047 host->timeout_clk =
3048 host->ops->get_timeout_clock(host);
3049 } else {
3050 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3051 mmc_hostname(mmc));
3052 return -ENODEV;
3053 }
3054 }
3055
3056 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3057 host->timeout_clk *= 1000;
3058
3059 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3060 host->ops->get_max_timeout_count(host) : 1 << 27;
3061 mmc->max_busy_timeout /= host->timeout_clk;
3062 }
3063
3064 if (override_timeout_clk)
3065 host->timeout_clk = override_timeout_clk;
3066
3067 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3068 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3069
3070 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3071 host->flags |= SDHCI_AUTO_CMD12;
3072
3073 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3074 if ((host->version >= SDHCI_SPEC_300) &&
3075 ((host->flags & SDHCI_USE_ADMA) ||
3076 !(host->flags & SDHCI_USE_SDMA)) &&
3077 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3078 host->flags |= SDHCI_AUTO_CMD23;
3079 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3080 } else {
3081 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3082 }
3083
3084 /*
3085 * A controller may support 8-bit width, but the board itself
3086 * might not have the pins brought out. Boards that support
3087 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3088 * their platform code before calling sdhci_add_host(), and we
3089 * won't assume 8-bit width for hosts without that CAP.
3090 */
3091 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3092 mmc->caps |= MMC_CAP_4_BIT_DATA;
3093
3094 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3095 mmc->caps &= ~MMC_CAP_CMD23;
3096
3097 if (caps[0] & SDHCI_CAN_DO_HISPD)
3098 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3099
3100 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3101 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3102 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3103 mmc->caps |= MMC_CAP_NEEDS_POLL;
3104
3105 /* If there are external regulators, get them */
3106 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3107 return -EPROBE_DEFER;
3108
3109 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3110 if (!IS_ERR(mmc->supply.vqmmc)) {
3111 ret = regulator_enable(mmc->supply.vqmmc);
3112 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3113 1950000))
3114 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3115 SDHCI_SUPPORT_SDR50 |
3116 SDHCI_SUPPORT_DDR50);
3117 if (ret) {
3118 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3119 mmc_hostname(mmc), ret);
3120 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3121 }
3122 }
3123
3124 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3125 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3126 SDHCI_SUPPORT_DDR50);
3127
3128 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3129 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3130 SDHCI_SUPPORT_DDR50))
3131 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3132
3133 /* SDR104 supports also implies SDR50 support */
3134 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3135 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3136 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3137 * field can be promoted to support HS200.
3138 */
3139 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3140 mmc->caps2 |= MMC_CAP2_HS200;
3141 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3142 mmc->caps |= MMC_CAP_UHS_SDR50;
3143
3144 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3145 (caps[1] & SDHCI_SUPPORT_HS400))
3146 mmc->caps2 |= MMC_CAP2_HS400;
3147
3148 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3149 (IS_ERR(mmc->supply.vqmmc) ||
3150 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3151 1300000)))
3152 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3153
3154 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3155 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3156 mmc->caps |= MMC_CAP_UHS_DDR50;
3157
3158 /* Does the host need tuning for SDR50? */
3159 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3160 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3161
3162 /* Does the host need tuning for SDR104 / HS200? */
3163 if (mmc->caps2 & MMC_CAP2_HS200)
3164 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3165
3166 /* Driver Type(s) (A, C, D) supported by the host */
3167 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3168 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3169 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3170 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3171 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3172 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3173
3174 /* Initial value for re-tuning timer count */
3175 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3176 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3177
3178 /*
3179 * In case Re-tuning Timer is not disabled, the actual value of
3180 * re-tuning timer will be 2 ^ (n - 1).
3181 */
3182 if (host->tuning_count)
3183 host->tuning_count = 1 << (host->tuning_count - 1);
3184
3185 /* Re-tuning mode supported by the Host Controller */
3186 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3187 SDHCI_RETUNING_MODE_SHIFT;
3188
3189 ocr_avail = 0;
3190
3191 /*
3192 * According to SD Host Controller spec v3.00, if the Host System
3193 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3194 * the value is meaningful only if Voltage Support in the Capabilities
3195 * register is set. The actual current value is 4 times the register
3196 * value.
3197 */
3198 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3199 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3200 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3201 if (curr > 0) {
3202
3203 /* convert to SDHCI_MAX_CURRENT format */
3204 curr = curr/1000; /* convert to mA */
3205 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3206
3207 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3208 max_current_caps =
3209 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3210 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3211 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3212 }
3213 }
3214
3215 if (caps[0] & SDHCI_CAN_VDD_330) {
3216 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3217
3218 mmc->max_current_330 = ((max_current_caps &
3219 SDHCI_MAX_CURRENT_330_MASK) >>
3220 SDHCI_MAX_CURRENT_330_SHIFT) *
3221 SDHCI_MAX_CURRENT_MULTIPLIER;
3222 }
3223 if (caps[0] & SDHCI_CAN_VDD_300) {
3224 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3225
3226 mmc->max_current_300 = ((max_current_caps &
3227 SDHCI_MAX_CURRENT_300_MASK) >>
3228 SDHCI_MAX_CURRENT_300_SHIFT) *
3229 SDHCI_MAX_CURRENT_MULTIPLIER;
3230 }
3231 if (caps[0] & SDHCI_CAN_VDD_180) {
3232 ocr_avail |= MMC_VDD_165_195;
3233
3234 mmc->max_current_180 = ((max_current_caps &
3235 SDHCI_MAX_CURRENT_180_MASK) >>
3236 SDHCI_MAX_CURRENT_180_SHIFT) *
3237 SDHCI_MAX_CURRENT_MULTIPLIER;
3238 }
3239
3240 /* If OCR set by host, use it instead. */
3241 if (host->ocr_mask)
3242 ocr_avail = host->ocr_mask;
3243
3244 /* If OCR set by external regulators, give it highest prio. */
3245 if (mmc->ocr_avail)
3246 ocr_avail = mmc->ocr_avail;
3247
3248 mmc->ocr_avail = ocr_avail;
3249 mmc->ocr_avail_sdio = ocr_avail;
3250 if (host->ocr_avail_sdio)
3251 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3252 mmc->ocr_avail_sd = ocr_avail;
3253 if (host->ocr_avail_sd)
3254 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3255 else /* normal SD controllers don't support 1.8V */
3256 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3257 mmc->ocr_avail_mmc = ocr_avail;
3258 if (host->ocr_avail_mmc)
3259 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3260
3261 if (mmc->ocr_avail == 0) {
3262 pr_err("%s: Hardware doesn't report any support voltages.\n",
3263 mmc_hostname(mmc));
3264 return -ENODEV;
3265 }
3266
3267 spin_lock_init(&host->lock);
3268
3269 /*
3270 * Maximum number of segments. Depends on if the hardware
3271 * can do scatter/gather or not.
3272 */
3273 if (host->flags & SDHCI_USE_ADMA)
3274 mmc->max_segs = SDHCI_MAX_SEGS;
3275 else if (host->flags & SDHCI_USE_SDMA)
3276 mmc->max_segs = 1;
3277 else /* PIO */
3278 mmc->max_segs = SDHCI_MAX_SEGS;
3279
3280 /*
3281 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3282 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3283 * is less anyway.
3284 */
3285 mmc->max_req_size = 524288;
3286
3287 /*
3288 * Maximum segment size. Could be one segment with the maximum number
3289 * of bytes. When doing hardware scatter/gather, each entry cannot
3290 * be larger than 64 KiB though.
3291 */
3292 if (host->flags & SDHCI_USE_ADMA) {
3293 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3294 mmc->max_seg_size = 65535;
3295 else
3296 mmc->max_seg_size = 65536;
3297 } else {
3298 mmc->max_seg_size = mmc->max_req_size;
3299 }
3300
3301 /*
3302 * Maximum block size. This varies from controller to controller and
3303 * is specified in the capabilities register.
3304 */
3305 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3306 mmc->max_blk_size = 2;
3307 } else {
3308 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3309 SDHCI_MAX_BLOCK_SHIFT;
3310 if (mmc->max_blk_size >= 3) {
3311 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3312 mmc_hostname(mmc));
3313 mmc->max_blk_size = 0;
3314 }
3315 }
3316
3317 mmc->max_blk_size = 512 << mmc->max_blk_size;
3318
3319 /*
3320 * Maximum block count.
3321 */
3322 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3323
3324 /*
3325 * Init tasklets.
3326 */
3327 tasklet_init(&host->finish_tasklet,
3328 sdhci_tasklet_finish, (unsigned long)host);
3329
3330 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3331
3332 init_waitqueue_head(&host->buf_ready_int);
3333
3334 sdhci_init(host, 0);
3335
3336 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3337 IRQF_SHARED, mmc_hostname(mmc), host);
3338 if (ret) {
3339 pr_err("%s: Failed to request IRQ %d: %d\n",
3340 mmc_hostname(mmc), host->irq, ret);
3341 goto untasklet;
3342 }
3343
3344 #ifdef CONFIG_MMC_DEBUG
3345 sdhci_dumpregs(host);
3346 #endif
3347
3348 #ifdef SDHCI_USE_LEDS_CLASS
3349 snprintf(host->led_name, sizeof(host->led_name),
3350 "%s::", mmc_hostname(mmc));
3351 host->led.name = host->led_name;
3352 host->led.brightness = LED_OFF;
3353 host->led.default_trigger = mmc_hostname(mmc);
3354 host->led.brightness_set = sdhci_led_control;
3355
3356 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3357 if (ret) {
3358 pr_err("%s: Failed to register LED device: %d\n",
3359 mmc_hostname(mmc), ret);
3360 goto reset;
3361 }
3362 #endif
3363
3364 mmiowb();
3365
3366 mmc_add_host(mmc);
3367
3368 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3369 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3370 (host->flags & SDHCI_USE_ADMA) ?
3371 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3372 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3373
3374 sdhci_enable_card_detection(host);
3375
3376 return 0;
3377
3378 #ifdef SDHCI_USE_LEDS_CLASS
3379 reset:
3380 sdhci_do_reset(host, SDHCI_RESET_ALL);
3381 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3382 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3383 free_irq(host->irq, host);
3384 #endif
3385 untasklet:
3386 tasklet_kill(&host->finish_tasklet);
3387
3388 return ret;
3389 }
3390
3391 EXPORT_SYMBOL_GPL(sdhci_add_host);
3392
3393 void sdhci_remove_host(struct sdhci_host *host, int dead)
3394 {
3395 struct mmc_host *mmc = host->mmc;
3396 unsigned long flags;
3397
3398 if (dead) {
3399 spin_lock_irqsave(&host->lock, flags);
3400
3401 host->flags |= SDHCI_DEVICE_DEAD;
3402
3403 if (host->mrq) {
3404 pr_err("%s: Controller removed during "
3405 " transfer!\n", mmc_hostname(mmc));
3406
3407 host->mrq->cmd->error = -ENOMEDIUM;
3408 tasklet_schedule(&host->finish_tasklet);
3409 }
3410
3411 spin_unlock_irqrestore(&host->lock, flags);
3412 }
3413
3414 sdhci_disable_card_detection(host);
3415
3416 mmc_remove_host(mmc);
3417
3418 #ifdef SDHCI_USE_LEDS_CLASS
3419 led_classdev_unregister(&host->led);
3420 #endif
3421
3422 if (!dead)
3423 sdhci_do_reset(host, SDHCI_RESET_ALL);
3424
3425 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3426 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3427 free_irq(host->irq, host);
3428
3429 del_timer_sync(&host->timer);
3430
3431 tasklet_kill(&host->finish_tasklet);
3432
3433 if (!IS_ERR(mmc->supply.vqmmc))
3434 regulator_disable(mmc->supply.vqmmc);
3435
3436 if (host->align_buffer)
3437 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3438 host->adma_table_sz, host->align_buffer,
3439 host->align_addr);
3440
3441 host->adma_table = NULL;
3442 host->align_buffer = NULL;
3443 }
3444
3445 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3446
3447 void sdhci_free_host(struct sdhci_host *host)
3448 {
3449 mmc_free_host(host->mmc);
3450 }
3451
3452 EXPORT_SYMBOL_GPL(sdhci_free_host);
3453
3454 /*****************************************************************************\
3455 * *
3456 * Driver init/exit *
3457 * *
3458 \*****************************************************************************/
3459
3460 static int __init sdhci_drv_init(void)
3461 {
3462 pr_info(DRIVER_NAME
3463 ": Secure Digital Host Controller Interface driver\n");
3464 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3465
3466 return 0;
3467 }
3468
3469 static void __exit sdhci_drv_exit(void)
3470 {
3471 }
3472
3473 module_init(sdhci_drv_init);
3474 module_exit(sdhci_drv_exit);
3475
3476 module_param(debug_quirks, uint, 0444);
3477 module_param(debug_quirks2, uint, 0444);
3478
3479 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3480 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3481 MODULE_LICENSE("GPL");
3482
3483 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3484 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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