]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/mmc/host/sdhci.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: Consolidate emmc tuning blocks
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
32
33 #include "sdhci.h"
34
35 #define DRIVER_NAME "sdhci"
36
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
43 #endif
44
45 #define MAX_TUNING_LOOP 40
46
47 #define ADMA_SIZE ((128 * 2 + 1) * 4)
48
49 static unsigned int debug_quirks = 0;
50 static unsigned int debug_quirks2;
51
52 static void sdhci_finish_data(struct sdhci_host *);
53
54 static void sdhci_finish_command(struct sdhci_host *);
55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
56 static void sdhci_tuning_timer(unsigned long data);
57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
58
59 #ifdef CONFIG_PM_RUNTIME
60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
64 #else
65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66 {
67 return 0;
68 }
69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70 {
71 return 0;
72 }
73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74 {
75 }
76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77 {
78 }
79 #endif
80
81 static void sdhci_dumpregs(struct sdhci_host *host)
82 {
83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
84 mmc_hostname(host->mmc));
85
86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
114 sdhci_readl(host, SDHCI_CAPABILITIES),
115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
117 sdhci_readw(host, SDHCI_COMMAND),
118 sdhci_readl(host, SDHCI_MAX_CURRENT));
119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
121
122 if (host->flags & SDHCI_USE_ADMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
127 pr_debug(DRIVER_NAME ": ===========================================\n");
128 }
129
130 /*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134 \*****************************************************************************/
135
136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137 {
138 u32 present;
139
140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
142 return;
143
144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
147
148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
156 }
157
158 static void sdhci_enable_card_detection(struct sdhci_host *host)
159 {
160 sdhci_set_card_detection(host, true);
161 }
162
163 static void sdhci_disable_card_detection(struct sdhci_host *host)
164 {
165 sdhci_set_card_detection(host, false);
166 }
167
168 void sdhci_reset(struct sdhci_host *host, u8 mask)
169 {
170 unsigned long timeout;
171
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
173
174 if (mask & SDHCI_RESET_ALL) {
175 host->clock = 0;
176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
180
181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
186 if (timeout == 0) {
187 pr_err("%s: Reset 0x%x never completed.\n",
188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
194 }
195 }
196 EXPORT_SYMBOL_GPL(sdhci_reset);
197
198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199 {
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
205
206 host->ops->reset(host, mask);
207
208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
212 }
213
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
216 }
217 }
218
219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
221 static void sdhci_init(struct sdhci_host *host, int soft)
222 {
223 if (soft)
224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225 else
226 sdhci_do_reset(host, SDHCI_RESET_ALL);
227
228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
232 SDHCI_INT_RESPONSE;
233
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
236
237 if (soft) {
238 /* force clock reconfiguration */
239 host->clock = 0;
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
241 }
242 }
243
244 static void sdhci_reinit(struct sdhci_host *host)
245 {
246 sdhci_init(host, 0);
247 /*
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
251 */
252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
254
255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259 }
260 sdhci_enable_card_detection(host);
261 }
262
263 static void sdhci_activate_led(struct sdhci_host *host)
264 {
265 u8 ctrl;
266
267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268 ctrl |= SDHCI_CTRL_LED;
269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
270 }
271
272 static void sdhci_deactivate_led(struct sdhci_host *host)
273 {
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl &= ~SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279 }
280
281 #ifdef SDHCI_USE_LEDS_CLASS
282 static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
284 {
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286 unsigned long flags;
287
288 spin_lock_irqsave(&host->lock, flags);
289
290 if (host->runtime_suspended)
291 goto out;
292
293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
295 else
296 sdhci_activate_led(host);
297 out:
298 spin_unlock_irqrestore(&host->lock, flags);
299 }
300 #endif
301
302 /*****************************************************************************\
303 * *
304 * Core functions *
305 * *
306 \*****************************************************************************/
307
308 static void sdhci_read_block_pio(struct sdhci_host *host)
309 {
310 unsigned long flags;
311 size_t blksize, len, chunk;
312 u32 uninitialized_var(scratch);
313 u8 *buf;
314
315 DBG("PIO reading\n");
316
317 blksize = host->data->blksz;
318 chunk = 0;
319
320 local_irq_save(flags);
321
322 while (blksize) {
323 if (!sg_miter_next(&host->sg_miter))
324 BUG();
325
326 len = min(host->sg_miter.length, blksize);
327
328 blksize -= len;
329 host->sg_miter.consumed = len;
330
331 buf = host->sg_miter.addr;
332
333 while (len) {
334 if (chunk == 0) {
335 scratch = sdhci_readl(host, SDHCI_BUFFER);
336 chunk = 4;
337 }
338
339 *buf = scratch & 0xFF;
340
341 buf++;
342 scratch >>= 8;
343 chunk--;
344 len--;
345 }
346 }
347
348 sg_miter_stop(&host->sg_miter);
349
350 local_irq_restore(flags);
351 }
352
353 static void sdhci_write_block_pio(struct sdhci_host *host)
354 {
355 unsigned long flags;
356 size_t blksize, len, chunk;
357 u32 scratch;
358 u8 *buf;
359
360 DBG("PIO writing\n");
361
362 blksize = host->data->blksz;
363 chunk = 0;
364 scratch = 0;
365
366 local_irq_save(flags);
367
368 while (blksize) {
369 if (!sg_miter_next(&host->sg_miter))
370 BUG();
371
372 len = min(host->sg_miter.length, blksize);
373
374 blksize -= len;
375 host->sg_miter.consumed = len;
376
377 buf = host->sg_miter.addr;
378
379 while (len) {
380 scratch |= (u32)*buf << (chunk * 8);
381
382 buf++;
383 chunk++;
384 len--;
385
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
387 sdhci_writel(host, scratch, SDHCI_BUFFER);
388 chunk = 0;
389 scratch = 0;
390 }
391 }
392 }
393
394 sg_miter_stop(&host->sg_miter);
395
396 local_irq_restore(flags);
397 }
398
399 static void sdhci_transfer_pio(struct sdhci_host *host)
400 {
401 u32 mask;
402
403 BUG_ON(!host->data);
404
405 if (host->blocks == 0)
406 return;
407
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
410 else
411 mask = SDHCI_SPACE_AVAILABLE;
412
413 /*
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
417 */
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
420 mask = ~0;
421
422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424 udelay(100);
425
426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
428 else
429 sdhci_write_block_pio(host);
430
431 host->blocks--;
432 if (host->blocks == 0)
433 break;
434 }
435
436 DBG("PIO transfer complete.\n");
437 }
438
439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440 {
441 local_irq_save(*flags);
442 return kmap_atomic(sg_page(sg)) + sg->offset;
443 }
444
445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446 {
447 kunmap_atomic(buffer);
448 local_irq_restore(*flags);
449 }
450
451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452 {
453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
455
456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
458
459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
461
462 dataddr[0] = cpu_to_le32(addr);
463 }
464
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467 {
468 int direction;
469
470 u8 *desc;
471 u8 *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494 goto fail;
495 BUG_ON(host->align_addr & 0x3);
496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
499 if (host->sg_count == 0)
500 goto unmap_align;
501
502 desc = host->adma_desc;
503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
518 offset = (4 - (addr & 0x3)) & 0x3;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
527 /* tran, valid */
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
529
530 BUG_ON(offset > 65536);
531
532 align += 4;
533 align_addr += 4;
534
535 desc += 8;
536
537 addr += offset;
538 len -= offset;
539 }
540
541 BUG_ON(len > 65536);
542
543 /* tran, valid */
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
545 desc += 8;
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
552 }
553
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
558 if (desc != host->adma_desc) {
559 desc -= 8;
560 desc[0] |= 0x2; /* end */
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
566
567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
569 }
570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
577 }
578
579 return 0;
580
581 unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584 fail:
585 return -EINVAL;
586 }
587
588 static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590 {
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
595 u8 *align;
596 char *buffer;
597 unsigned long flags;
598 bool has_unaligned;
599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
625
626 buffer = sdhci_kmap_atomic(sg, &flags);
627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
631 align += 4;
632 }
633 }
634 }
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
638 }
639
640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
641 {
642 u8 count;
643 struct mmc_data *data = cmd->data;
644 unsigned target_timeout, current_timeout;
645
646 /*
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
650 * timeout value.
651 */
652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
653 return 0xE;
654
655 /* Unspecified timeout, assume max */
656 if (!data && !cmd->busy_timeout)
657 return 0xE;
658
659 /* timeout in us */
660 if (!data)
661 target_timeout = cmd->busy_timeout * 1000;
662 else {
663 target_timeout = data->timeout_ns / 1000;
664 if (host->clock)
665 target_timeout += data->timeout_clks / host->clock;
666 }
667
668 /*
669 * Figure out needed cycles.
670 * We do this in steps in order to fit inside a 32 bit int.
671 * The first step is the minimum timeout, which will have a
672 * minimum resolution of 6 bits:
673 * (1) 2^13*1000 > 2^22,
674 * (2) host->timeout_clk < 2^16
675 * =>
676 * (1) / (2) > 2^6
677 */
678 count = 0;
679 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680 while (current_timeout < target_timeout) {
681 count++;
682 current_timeout <<= 1;
683 if (count >= 0xF)
684 break;
685 }
686
687 if (count >= 0xF) {
688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689 mmc_hostname(host->mmc), count, cmd->opcode);
690 count = 0xE;
691 }
692
693 return count;
694 }
695
696 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
697 {
698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
700
701 if (host->flags & SDHCI_REQ_USE_DMA)
702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
703 else
704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
708 }
709
710 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
711 {
712 u8 count;
713
714 if (host->ops->set_timeout) {
715 host->ops->set_timeout(host, cmd);
716 } else {
717 count = sdhci_calc_timeout(host, cmd);
718 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
719 }
720 }
721
722 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
723 {
724 u8 ctrl;
725 struct mmc_data *data = cmd->data;
726 int ret;
727
728 WARN_ON(host->data);
729
730 if (data || (cmd->flags & MMC_RSP_BUSY))
731 sdhci_set_timeout(host, cmd);
732
733 if (!data)
734 return;
735
736 /* Sanity checks */
737 BUG_ON(data->blksz * data->blocks > 524288);
738 BUG_ON(data->blksz > host->mmc->max_blk_size);
739 BUG_ON(data->blocks > 65535);
740
741 host->data = data;
742 host->data_early = 0;
743 host->data->bytes_xfered = 0;
744
745 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
746 host->flags |= SDHCI_REQ_USE_DMA;
747
748 /*
749 * FIXME: This doesn't account for merging when mapping the
750 * scatterlist.
751 */
752 if (host->flags & SDHCI_REQ_USE_DMA) {
753 int broken, i;
754 struct scatterlist *sg;
755
756 broken = 0;
757 if (host->flags & SDHCI_USE_ADMA) {
758 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
759 broken = 1;
760 } else {
761 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
762 broken = 1;
763 }
764
765 if (unlikely(broken)) {
766 for_each_sg(data->sg, sg, data->sg_len, i) {
767 if (sg->length & 0x3) {
768 DBG("Reverting to PIO because of "
769 "transfer size (%d)\n",
770 sg->length);
771 host->flags &= ~SDHCI_REQ_USE_DMA;
772 break;
773 }
774 }
775 }
776 }
777
778 /*
779 * The assumption here being that alignment is the same after
780 * translation to device address space.
781 */
782 if (host->flags & SDHCI_REQ_USE_DMA) {
783 int broken, i;
784 struct scatterlist *sg;
785
786 broken = 0;
787 if (host->flags & SDHCI_USE_ADMA) {
788 /*
789 * As we use 3 byte chunks to work around
790 * alignment problems, we need to check this
791 * quirk.
792 */
793 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
794 broken = 1;
795 } else {
796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
797 broken = 1;
798 }
799
800 if (unlikely(broken)) {
801 for_each_sg(data->sg, sg, data->sg_len, i) {
802 if (sg->offset & 0x3) {
803 DBG("Reverting to PIO because of "
804 "bad alignment\n");
805 host->flags &= ~SDHCI_REQ_USE_DMA;
806 break;
807 }
808 }
809 }
810 }
811
812 if (host->flags & SDHCI_REQ_USE_DMA) {
813 if (host->flags & SDHCI_USE_ADMA) {
814 ret = sdhci_adma_table_pre(host, data);
815 if (ret) {
816 /*
817 * This only happens when someone fed
818 * us an invalid request.
819 */
820 WARN_ON(1);
821 host->flags &= ~SDHCI_REQ_USE_DMA;
822 } else {
823 sdhci_writel(host, host->adma_addr,
824 SDHCI_ADMA_ADDRESS);
825 }
826 } else {
827 int sg_cnt;
828
829 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
830 data->sg, data->sg_len,
831 (data->flags & MMC_DATA_READ) ?
832 DMA_FROM_DEVICE :
833 DMA_TO_DEVICE);
834 if (sg_cnt == 0) {
835 /*
836 * This only happens when someone fed
837 * us an invalid request.
838 */
839 WARN_ON(1);
840 host->flags &= ~SDHCI_REQ_USE_DMA;
841 } else {
842 WARN_ON(sg_cnt != 1);
843 sdhci_writel(host, sg_dma_address(data->sg),
844 SDHCI_DMA_ADDRESS);
845 }
846 }
847 }
848
849 /*
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
858 (host->flags & SDHCI_USE_ADMA))
859 ctrl |= SDHCI_CTRL_ADMA32;
860 else
861 ctrl |= SDHCI_CTRL_SDMA;
862 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
863 }
864
865 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
866 int flags;
867
868 flags = SG_MITER_ATOMIC;
869 if (host->data->flags & MMC_DATA_READ)
870 flags |= SG_MITER_TO_SG;
871 else
872 flags |= SG_MITER_FROM_SG;
873 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
874 host->blocks = data->blocks;
875 }
876
877 sdhci_set_transfer_irqs(host);
878
879 /* Set the DMA boundary value and block size */
880 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
881 data->blksz), SDHCI_BLOCK_SIZE);
882 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
883 }
884
885 static void sdhci_set_transfer_mode(struct sdhci_host *host,
886 struct mmc_command *cmd)
887 {
888 u16 mode;
889 struct mmc_data *data = cmd->data;
890
891 if (data == NULL) {
892 /* clear Auto CMD settings for no data CMDs */
893 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
894 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
895 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
896 return;
897 }
898
899 WARN_ON(!host->data);
900
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
903 mode |= SDHCI_TRNS_MULTI;
904 /*
905 * If we are sending CMD23, CMD12 never gets sent
906 * on successful completion (so no Auto-CMD12).
907 */
908 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
909 mode |= SDHCI_TRNS_AUTO_CMD12;
910 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
911 mode |= SDHCI_TRNS_AUTO_CMD23;
912 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
913 }
914 }
915
916 if (data->flags & MMC_DATA_READ)
917 mode |= SDHCI_TRNS_READ;
918 if (host->flags & SDHCI_REQ_USE_DMA)
919 mode |= SDHCI_TRNS_DMA;
920
921 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
922 }
923
924 static void sdhci_finish_data(struct sdhci_host *host)
925 {
926 struct mmc_data *data;
927
928 BUG_ON(!host->data);
929
930 data = host->data;
931 host->data = NULL;
932
933 if (host->flags & SDHCI_REQ_USE_DMA) {
934 if (host->flags & SDHCI_USE_ADMA)
935 sdhci_adma_table_post(host, data);
936 else {
937 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
938 data->sg_len, (data->flags & MMC_DATA_READ) ?
939 DMA_FROM_DEVICE : DMA_TO_DEVICE);
940 }
941 }
942
943 /*
944 * The specification states that the block count register must
945 * be updated, but it does not specify at what point in the
946 * data flow. That makes the register entirely useless to read
947 * back so we have to assume that nothing made it to the card
948 * in the event of an error.
949 */
950 if (data->error)
951 data->bytes_xfered = 0;
952 else
953 data->bytes_xfered = data->blksz * data->blocks;
954
955 /*
956 * Need to send CMD12 if -
957 * a) open-ended multiblock transfer (no CMD23)
958 * b) error in multiblock transfer
959 */
960 if (data->stop &&
961 (data->error ||
962 !host->mrq->sbc)) {
963
964 /*
965 * The controller needs a reset of internal state machines
966 * upon error conditions.
967 */
968 if (data->error) {
969 sdhci_do_reset(host, SDHCI_RESET_CMD);
970 sdhci_do_reset(host, SDHCI_RESET_DATA);
971 }
972
973 sdhci_send_command(host, data->stop);
974 } else
975 tasklet_schedule(&host->finish_tasklet);
976 }
977
978 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
979 {
980 int flags;
981 u32 mask;
982 unsigned long timeout;
983
984 WARN_ON(host->cmd);
985
986 /* Wait max 10 ms */
987 timeout = 10;
988
989 mask = SDHCI_CMD_INHIBIT;
990 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
991 mask |= SDHCI_DATA_INHIBIT;
992
993 /* We shouldn't wait for data inihibit for stop commands, even
994 though they might use busy signaling */
995 if (host->mrq->data && (cmd == host->mrq->data->stop))
996 mask &= ~SDHCI_DATA_INHIBIT;
997
998 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
999 if (timeout == 0) {
1000 pr_err("%s: Controller never released "
1001 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1002 sdhci_dumpregs(host);
1003 cmd->error = -EIO;
1004 tasklet_schedule(&host->finish_tasklet);
1005 return;
1006 }
1007 timeout--;
1008 mdelay(1);
1009 }
1010
1011 timeout = jiffies;
1012 if (!cmd->data && cmd->busy_timeout > 9000)
1013 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1014 else
1015 timeout += 10 * HZ;
1016 mod_timer(&host->timer, timeout);
1017
1018 host->cmd = cmd;
1019 host->busy_handle = 0;
1020
1021 sdhci_prepare_data(host, cmd);
1022
1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024
1025 sdhci_set_transfer_mode(host, cmd);
1026
1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1028 pr_err("%s: Unsupported response type!\n",
1029 mmc_hostname(host->mmc));
1030 cmd->error = -EINVAL;
1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
1048
1049 /* CMD19 is special in that the Data Present Select should be set */
1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1052 flags |= SDHCI_CMD_DATA;
1053
1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1055 }
1056 EXPORT_SYMBOL_GPL(sdhci_send_command);
1057
1058 static void sdhci_finish_command(struct sdhci_host *host)
1059 {
1060 int i;
1061
1062 BUG_ON(host->cmd == NULL);
1063
1064 if (host->cmd->flags & MMC_RSP_PRESENT) {
1065 if (host->cmd->flags & MMC_RSP_136) {
1066 /* CRC is stripped so we need to do some shifting. */
1067 for (i = 0;i < 4;i++) {
1068 host->cmd->resp[i] = sdhci_readl(host,
1069 SDHCI_RESPONSE + (3-i)*4) << 8;
1070 if (i != 3)
1071 host->cmd->resp[i] |=
1072 sdhci_readb(host,
1073 SDHCI_RESPONSE + (3-i)*4-1);
1074 }
1075 } else {
1076 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1077 }
1078 }
1079
1080 host->cmd->error = 0;
1081
1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1084 host->cmd = NULL;
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else {
1087
1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
1091
1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1094
1095 host->cmd = NULL;
1096 }
1097 }
1098
1099 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1100 {
1101 u16 preset = 0;
1102
1103 switch (host->timing) {
1104 case MMC_TIMING_UHS_SDR12:
1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 break;
1107 case MMC_TIMING_UHS_SDR25:
1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1109 break;
1110 case MMC_TIMING_UHS_SDR50:
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1112 break;
1113 case MMC_TIMING_UHS_SDR104:
1114 case MMC_TIMING_MMC_HS200:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case MMC_TIMING_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127 }
1128
1129 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130 {
1131 int div = 0; /* Initialized for compiler warning */
1132 int real_div = div, clk_mul = 1;
1133 u16 clk = 0;
1134 unsigned long timeout;
1135
1136 host->mmc->actual_clock = 0;
1137
1138 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1139
1140 if (clock == 0)
1141 return;
1142
1143 if (host->version >= SDHCI_SPEC_300) {
1144 if (host->preset_enabled) {
1145 u16 pre_val;
1146
1147 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1148 pre_val = sdhci_get_preset_value(host);
1149 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1150 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1151 if (host->clk_mul &&
1152 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1153 clk = SDHCI_PROG_CLOCK_MODE;
1154 real_div = div + 1;
1155 clk_mul = host->clk_mul;
1156 } else {
1157 real_div = max_t(int, 1, div << 1);
1158 }
1159 goto clock_set;
1160 }
1161
1162 /*
1163 * Check if the Host Controller supports Programmable Clock
1164 * Mode.
1165 */
1166 if (host->clk_mul) {
1167 for (div = 1; div <= 1024; div++) {
1168 if ((host->max_clk * host->clk_mul / div)
1169 <= clock)
1170 break;
1171 }
1172 /*
1173 * Set Programmable Clock Mode in the Clock
1174 * Control register.
1175 */
1176 clk = SDHCI_PROG_CLOCK_MODE;
1177 real_div = div;
1178 clk_mul = host->clk_mul;
1179 div--;
1180 } else {
1181 /* Version 3.00 divisors must be a multiple of 2. */
1182 if (host->max_clk <= clock)
1183 div = 1;
1184 else {
1185 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1186 div += 2) {
1187 if ((host->max_clk / div) <= clock)
1188 break;
1189 }
1190 }
1191 real_div = div;
1192 div >>= 1;
1193 }
1194 } else {
1195 /* Version 2.00 divisors must be a power of 2. */
1196 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
1200 real_div = div;
1201 div >>= 1;
1202 }
1203
1204 clock_set:
1205 if (real_div)
1206 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1207 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1208 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1209 << SDHCI_DIVIDER_HI_SHIFT;
1210 clk |= SDHCI_CLOCK_INT_EN;
1211 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1212
1213 /* Wait max 20 ms */
1214 timeout = 20;
1215 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1216 & SDHCI_CLOCK_INT_STABLE)) {
1217 if (timeout == 0) {
1218 pr_err("%s: Internal clock never "
1219 "stabilised.\n", mmc_hostname(host->mmc));
1220 sdhci_dumpregs(host);
1221 return;
1222 }
1223 timeout--;
1224 mdelay(1);
1225 }
1226
1227 clk |= SDHCI_CLOCK_CARD_EN;
1228 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1229 }
1230 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1231
1232 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1233 unsigned short vdd)
1234 {
1235 struct mmc_host *mmc = host->mmc;
1236 u8 pwr = 0;
1237
1238 if (!IS_ERR(mmc->supply.vmmc)) {
1239 spin_unlock_irq(&host->lock);
1240 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1241 spin_lock_irq(&host->lock);
1242 return;
1243 }
1244
1245 if (mode != MMC_POWER_OFF) {
1246 switch (1 << vdd) {
1247 case MMC_VDD_165_195:
1248 pwr = SDHCI_POWER_180;
1249 break;
1250 case MMC_VDD_29_30:
1251 case MMC_VDD_30_31:
1252 pwr = SDHCI_POWER_300;
1253 break;
1254 case MMC_VDD_32_33:
1255 case MMC_VDD_33_34:
1256 pwr = SDHCI_POWER_330;
1257 break;
1258 default:
1259 BUG();
1260 }
1261 }
1262
1263 if (host->pwr == pwr)
1264 return;
1265
1266 host->pwr = pwr;
1267
1268 if (pwr == 0) {
1269 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1270 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1271 sdhci_runtime_pm_bus_off(host);
1272 vdd = 0;
1273 } else {
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1280
1281 /*
1282 * At least the Marvell CaFe chip gets confused if we set the
1283 * voltage and set turn on power at the same time, so set the
1284 * voltage first.
1285 */
1286 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1287 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1288
1289 pwr |= SDHCI_POWER_ON;
1290
1291 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1292
1293 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1294 sdhci_runtime_pm_bus_on(host);
1295
1296 /*
1297 * Some controllers need an extra 10ms delay of 10ms before
1298 * they can apply clock after applying power
1299 */
1300 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1301 mdelay(10);
1302 }
1303 }
1304
1305 /*****************************************************************************\
1306 * *
1307 * MMC callbacks *
1308 * *
1309 \*****************************************************************************/
1310
1311 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1312 {
1313 struct sdhci_host *host;
1314 int present;
1315 unsigned long flags;
1316 u32 tuning_opcode;
1317
1318 host = mmc_priv(mmc);
1319
1320 sdhci_runtime_pm_get(host);
1321
1322 spin_lock_irqsave(&host->lock, flags);
1323
1324 WARN_ON(host->mrq != NULL);
1325
1326 #ifndef SDHCI_USE_LEDS_CLASS
1327 sdhci_activate_led(host);
1328 #endif
1329
1330 /*
1331 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1332 * requests if Auto-CMD12 is enabled.
1333 */
1334 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1335 if (mrq->stop) {
1336 mrq->data->stop = NULL;
1337 mrq->stop = NULL;
1338 }
1339 }
1340
1341 host->mrq = mrq;
1342
1343 /*
1344 * Firstly check card presence from cd-gpio. The return could
1345 * be one of the following possibilities:
1346 * negative: cd-gpio is not available
1347 * zero: cd-gpio is used, and card is removed
1348 * one: cd-gpio is used, and card is present
1349 */
1350 present = mmc_gpio_get_cd(host->mmc);
1351 if (present < 0) {
1352 /* If polling, assume that the card is always present. */
1353 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1354 present = 1;
1355 else
1356 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1357 SDHCI_CARD_PRESENT;
1358 }
1359
1360 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1361 host->mrq->cmd->error = -ENOMEDIUM;
1362 tasklet_schedule(&host->finish_tasklet);
1363 } else {
1364 u32 present_state;
1365
1366 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1367 /*
1368 * Check if the re-tuning timer has already expired and there
1369 * is no on-going data transfer. If so, we need to execute
1370 * tuning procedure before sending command.
1371 */
1372 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1373 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1374 if (mmc->card) {
1375 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1376 tuning_opcode =
1377 mmc->card->type == MMC_TYPE_MMC ?
1378 MMC_SEND_TUNING_BLOCK_HS200 :
1379 MMC_SEND_TUNING_BLOCK;
1380
1381 /* Here we need to set the host->mrq to NULL,
1382 * in case the pending finish_tasklet
1383 * finishes it incorrectly.
1384 */
1385 host->mrq = NULL;
1386
1387 spin_unlock_irqrestore(&host->lock, flags);
1388 sdhci_execute_tuning(mmc, tuning_opcode);
1389 spin_lock_irqsave(&host->lock, flags);
1390
1391 /* Restore original mmc_request structure */
1392 host->mrq = mrq;
1393 }
1394 }
1395
1396 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1397 sdhci_send_command(host, mrq->sbc);
1398 else
1399 sdhci_send_command(host, mrq->cmd);
1400 }
1401
1402 mmiowb();
1403 spin_unlock_irqrestore(&host->lock, flags);
1404 }
1405
1406 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1407 {
1408 u8 ctrl;
1409
1410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1411 if (width == MMC_BUS_WIDTH_8) {
1412 ctrl &= ~SDHCI_CTRL_4BITBUS;
1413 if (host->version >= SDHCI_SPEC_300)
1414 ctrl |= SDHCI_CTRL_8BITBUS;
1415 } else {
1416 if (host->version >= SDHCI_SPEC_300)
1417 ctrl &= ~SDHCI_CTRL_8BITBUS;
1418 if (width == MMC_BUS_WIDTH_4)
1419 ctrl |= SDHCI_CTRL_4BITBUS;
1420 else
1421 ctrl &= ~SDHCI_CTRL_4BITBUS;
1422 }
1423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1424 }
1425 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1426
1427 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1428 {
1429 u16 ctrl_2;
1430
1431 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1432 /* Select Bus Speed Mode for host */
1433 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1434 if ((timing == MMC_TIMING_MMC_HS200) ||
1435 (timing == MMC_TIMING_UHS_SDR104))
1436 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1437 else if (timing == MMC_TIMING_UHS_SDR12)
1438 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1439 else if (timing == MMC_TIMING_UHS_SDR25)
1440 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1441 else if (timing == MMC_TIMING_UHS_SDR50)
1442 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1443 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1444 (timing == MMC_TIMING_MMC_DDR52))
1445 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1447 }
1448 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1449
1450 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1451 {
1452 unsigned long flags;
1453 u8 ctrl;
1454 struct mmc_host *mmc = host->mmc;
1455
1456 spin_lock_irqsave(&host->lock, flags);
1457
1458 if (host->flags & SDHCI_DEVICE_DEAD) {
1459 spin_unlock_irqrestore(&host->lock, flags);
1460 if (!IS_ERR(mmc->supply.vmmc) &&
1461 ios->power_mode == MMC_POWER_OFF)
1462 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1463 return;
1464 }
1465
1466 /*
1467 * Reset the chip on each power off.
1468 * Should clear out any weird states.
1469 */
1470 if (ios->power_mode == MMC_POWER_OFF) {
1471 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1472 sdhci_reinit(host);
1473 }
1474
1475 if (host->version >= SDHCI_SPEC_300 &&
1476 (ios->power_mode == MMC_POWER_UP) &&
1477 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1478 sdhci_enable_preset_value(host, false);
1479
1480 if (!ios->clock || ios->clock != host->clock) {
1481 host->ops->set_clock(host, ios->clock);
1482 host->clock = ios->clock;
1483
1484 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1485 host->clock) {
1486 host->timeout_clk = host->mmc->actual_clock ?
1487 host->mmc->actual_clock / 1000 :
1488 host->clock / 1000;
1489 host->mmc->max_busy_timeout =
1490 host->ops->get_max_timeout_count ?
1491 host->ops->get_max_timeout_count(host) :
1492 1 << 27;
1493 host->mmc->max_busy_timeout /= host->timeout_clk;
1494 }
1495 }
1496
1497 sdhci_set_power(host, ios->power_mode, ios->vdd);
1498
1499 if (host->ops->platform_send_init_74_clocks)
1500 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1501
1502 host->ops->set_bus_width(host, ios->bus_width);
1503
1504 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1505
1506 if ((ios->timing == MMC_TIMING_SD_HS ||
1507 ios->timing == MMC_TIMING_MMC_HS)
1508 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1509 ctrl |= SDHCI_CTRL_HISPD;
1510 else
1511 ctrl &= ~SDHCI_CTRL_HISPD;
1512
1513 if (host->version >= SDHCI_SPEC_300) {
1514 u16 clk, ctrl_2;
1515
1516 /* In case of UHS-I modes, set High Speed Enable */
1517 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1518 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1519 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1520 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1521 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1522 (ios->timing == MMC_TIMING_UHS_SDR25))
1523 ctrl |= SDHCI_CTRL_HISPD;
1524
1525 if (!host->preset_enabled) {
1526 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1527 /*
1528 * We only need to set Driver Strength if the
1529 * preset value enable is not set.
1530 */
1531 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1532 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1533 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1534 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1535 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1536 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1537
1538 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1539 } else {
1540 /*
1541 * According to SDHC Spec v3.00, if the Preset Value
1542 * Enable in the Host Control 2 register is set, we
1543 * need to reset SD Clock Enable before changing High
1544 * Speed Enable to avoid generating clock gliches.
1545 */
1546
1547 /* Reset SD Clock Enable */
1548 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1549 clk &= ~SDHCI_CLOCK_CARD_EN;
1550 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1551
1552 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1553
1554 /* Re-enable SD Clock */
1555 host->ops->set_clock(host, host->clock);
1556 }
1557
1558 /* Reset SD Clock Enable */
1559 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1560 clk &= ~SDHCI_CLOCK_CARD_EN;
1561 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1562
1563 host->ops->set_uhs_signaling(host, ios->timing);
1564 host->timing = ios->timing;
1565
1566 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1567 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1568 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1569 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1570 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1571 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1572 u16 preset;
1573
1574 sdhci_enable_preset_value(host, true);
1575 preset = sdhci_get_preset_value(host);
1576 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1577 >> SDHCI_PRESET_DRV_SHIFT;
1578 }
1579
1580 /* Re-enable SD Clock */
1581 host->ops->set_clock(host, host->clock);
1582 } else
1583 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1584
1585 /*
1586 * Some (ENE) controllers go apeshit on some ios operation,
1587 * signalling timeout and CRC errors even on CMD0. Resetting
1588 * it on each ios seems to solve the problem.
1589 */
1590 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1591 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1592
1593 mmiowb();
1594 spin_unlock_irqrestore(&host->lock, flags);
1595 }
1596
1597 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1598 {
1599 struct sdhci_host *host = mmc_priv(mmc);
1600
1601 sdhci_runtime_pm_get(host);
1602 sdhci_do_set_ios(host, ios);
1603 sdhci_runtime_pm_put(host);
1604 }
1605
1606 static int sdhci_do_get_cd(struct sdhci_host *host)
1607 {
1608 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1609
1610 if (host->flags & SDHCI_DEVICE_DEAD)
1611 return 0;
1612
1613 /* If polling/nonremovable, assume that the card is always present. */
1614 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1615 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1616 return 1;
1617
1618 /* Try slot gpio detect */
1619 if (!IS_ERR_VALUE(gpio_cd))
1620 return !!gpio_cd;
1621
1622 /* Host native card detect */
1623 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1624 }
1625
1626 static int sdhci_get_cd(struct mmc_host *mmc)
1627 {
1628 struct sdhci_host *host = mmc_priv(mmc);
1629 int ret;
1630
1631 sdhci_runtime_pm_get(host);
1632 ret = sdhci_do_get_cd(host);
1633 sdhci_runtime_pm_put(host);
1634 return ret;
1635 }
1636
1637 static int sdhci_check_ro(struct sdhci_host *host)
1638 {
1639 unsigned long flags;
1640 int is_readonly;
1641
1642 spin_lock_irqsave(&host->lock, flags);
1643
1644 if (host->flags & SDHCI_DEVICE_DEAD)
1645 is_readonly = 0;
1646 else if (host->ops->get_ro)
1647 is_readonly = host->ops->get_ro(host);
1648 else
1649 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1650 & SDHCI_WRITE_PROTECT);
1651
1652 spin_unlock_irqrestore(&host->lock, flags);
1653
1654 /* This quirk needs to be replaced by a callback-function later */
1655 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1656 !is_readonly : is_readonly;
1657 }
1658
1659 #define SAMPLE_COUNT 5
1660
1661 static int sdhci_do_get_ro(struct sdhci_host *host)
1662 {
1663 int i, ro_count;
1664
1665 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1666 return sdhci_check_ro(host);
1667
1668 ro_count = 0;
1669 for (i = 0; i < SAMPLE_COUNT; i++) {
1670 if (sdhci_check_ro(host)) {
1671 if (++ro_count > SAMPLE_COUNT / 2)
1672 return 1;
1673 }
1674 msleep(30);
1675 }
1676 return 0;
1677 }
1678
1679 static void sdhci_hw_reset(struct mmc_host *mmc)
1680 {
1681 struct sdhci_host *host = mmc_priv(mmc);
1682
1683 if (host->ops && host->ops->hw_reset)
1684 host->ops->hw_reset(host);
1685 }
1686
1687 static int sdhci_get_ro(struct mmc_host *mmc)
1688 {
1689 struct sdhci_host *host = mmc_priv(mmc);
1690 int ret;
1691
1692 sdhci_runtime_pm_get(host);
1693 ret = sdhci_do_get_ro(host);
1694 sdhci_runtime_pm_put(host);
1695 return ret;
1696 }
1697
1698 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1699 {
1700 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1701 if (enable)
1702 host->ier |= SDHCI_INT_CARD_INT;
1703 else
1704 host->ier &= ~SDHCI_INT_CARD_INT;
1705
1706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1708 mmiowb();
1709 }
1710 }
1711
1712 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1713 {
1714 struct sdhci_host *host = mmc_priv(mmc);
1715 unsigned long flags;
1716
1717 sdhci_runtime_pm_get(host);
1718
1719 spin_lock_irqsave(&host->lock, flags);
1720 if (enable)
1721 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1722 else
1723 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1724
1725 sdhci_enable_sdio_irq_nolock(host, enable);
1726 spin_unlock_irqrestore(&host->lock, flags);
1727
1728 sdhci_runtime_pm_put(host);
1729 }
1730
1731 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1732 struct mmc_ios *ios)
1733 {
1734 struct mmc_host *mmc = host->mmc;
1735 u16 ctrl;
1736 int ret;
1737
1738 /*
1739 * Signal Voltage Switching is only applicable for Host Controllers
1740 * v3.00 and above.
1741 */
1742 if (host->version < SDHCI_SPEC_300)
1743 return 0;
1744
1745 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1746
1747 switch (ios->signal_voltage) {
1748 case MMC_SIGNAL_VOLTAGE_330:
1749 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1750 ctrl &= ~SDHCI_CTRL_VDD_180;
1751 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1752
1753 if (!IS_ERR(mmc->supply.vqmmc)) {
1754 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1755 3600000);
1756 if (ret) {
1757 pr_warning("%s: Switching to 3.3V signalling voltage "
1758 " failed\n", mmc_hostname(mmc));
1759 return -EIO;
1760 }
1761 }
1762 /* Wait for 5ms */
1763 usleep_range(5000, 5500);
1764
1765 /* 3.3V regulator output should be stable within 5 ms */
1766 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767 if (!(ctrl & SDHCI_CTRL_VDD_180))
1768 return 0;
1769
1770 pr_warning("%s: 3.3V regulator output did not became stable\n",
1771 mmc_hostname(mmc));
1772
1773 return -EAGAIN;
1774 case MMC_SIGNAL_VOLTAGE_180:
1775 if (!IS_ERR(mmc->supply.vqmmc)) {
1776 ret = regulator_set_voltage(mmc->supply.vqmmc,
1777 1700000, 1950000);
1778 if (ret) {
1779 pr_warning("%s: Switching to 1.8V signalling voltage "
1780 " failed\n", mmc_hostname(mmc));
1781 return -EIO;
1782 }
1783 }
1784
1785 /*
1786 * Enable 1.8V Signal Enable in the Host Control2
1787 * register
1788 */
1789 ctrl |= SDHCI_CTRL_VDD_180;
1790 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1791
1792 /* 1.8V regulator output should be stable within 5 ms */
1793 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1794 if (ctrl & SDHCI_CTRL_VDD_180)
1795 return 0;
1796
1797 pr_warning("%s: 1.8V regulator output did not became stable\n",
1798 mmc_hostname(mmc));
1799
1800 return -EAGAIN;
1801 case MMC_SIGNAL_VOLTAGE_120:
1802 if (!IS_ERR(mmc->supply.vqmmc)) {
1803 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1804 1300000);
1805 if (ret) {
1806 pr_warning("%s: Switching to 1.2V signalling voltage "
1807 " failed\n", mmc_hostname(mmc));
1808 return -EIO;
1809 }
1810 }
1811 return 0;
1812 default:
1813 /* No signal voltage switch required */
1814 return 0;
1815 }
1816 }
1817
1818 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1819 struct mmc_ios *ios)
1820 {
1821 struct sdhci_host *host = mmc_priv(mmc);
1822 int err;
1823
1824 if (host->version < SDHCI_SPEC_300)
1825 return 0;
1826 sdhci_runtime_pm_get(host);
1827 err = sdhci_do_start_signal_voltage_switch(host, ios);
1828 sdhci_runtime_pm_put(host);
1829 return err;
1830 }
1831
1832 static int sdhci_card_busy(struct mmc_host *mmc)
1833 {
1834 struct sdhci_host *host = mmc_priv(mmc);
1835 u32 present_state;
1836
1837 sdhci_runtime_pm_get(host);
1838 /* Check whether DAT[3:0] is 0000 */
1839 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1840 sdhci_runtime_pm_put(host);
1841
1842 return !(present_state & SDHCI_DATA_LVL_MASK);
1843 }
1844
1845 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1846 {
1847 struct sdhci_host *host = mmc_priv(mmc);
1848 u16 ctrl;
1849 int tuning_loop_counter = MAX_TUNING_LOOP;
1850 int err = 0;
1851 unsigned long flags;
1852
1853 sdhci_runtime_pm_get(host);
1854 spin_lock_irqsave(&host->lock, flags);
1855
1856 /*
1857 * The Host Controller needs tuning only in case of SDR104 mode
1858 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1859 * Capabilities register.
1860 * If the Host Controller supports the HS200 mode then the
1861 * tuning function has to be executed.
1862 */
1863 switch (host->timing) {
1864 case MMC_TIMING_MMC_HS200:
1865 case MMC_TIMING_UHS_SDR104:
1866 break;
1867
1868 case MMC_TIMING_UHS_SDR50:
1869 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1870 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1871 break;
1872 /* FALLTHROUGH */
1873
1874 default:
1875 spin_unlock_irqrestore(&host->lock, flags);
1876 sdhci_runtime_pm_put(host);
1877 return 0;
1878 }
1879
1880 if (host->ops->platform_execute_tuning) {
1881 spin_unlock_irqrestore(&host->lock, flags);
1882 err = host->ops->platform_execute_tuning(host, opcode);
1883 sdhci_runtime_pm_put(host);
1884 return err;
1885 }
1886
1887 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1888 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1889 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1890
1891 /*
1892 * As per the Host Controller spec v3.00, tuning command
1893 * generates Buffer Read Ready interrupt, so enable that.
1894 *
1895 * Note: The spec clearly says that when tuning sequence
1896 * is being performed, the controller does not generate
1897 * interrupts other than Buffer Read Ready interrupt. But
1898 * to make sure we don't hit a controller bug, we _only_
1899 * enable Buffer Read Ready interrupt here.
1900 */
1901 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1902 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1903
1904 /*
1905 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1906 * of loops reaches 40 times or a timeout of 150ms occurs.
1907 */
1908 do {
1909 struct mmc_command cmd = {0};
1910 struct mmc_request mrq = {NULL};
1911
1912 cmd.opcode = opcode;
1913 cmd.arg = 0;
1914 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1915 cmd.retries = 0;
1916 cmd.data = NULL;
1917 cmd.error = 0;
1918
1919 if (tuning_loop_counter-- == 0)
1920 break;
1921
1922 mrq.cmd = &cmd;
1923 host->mrq = &mrq;
1924
1925 /*
1926 * In response to CMD19, the card sends 64 bytes of tuning
1927 * block to the Host Controller. So we set the block size
1928 * to 64 here.
1929 */
1930 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1931 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1932 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1933 SDHCI_BLOCK_SIZE);
1934 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1935 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1936 SDHCI_BLOCK_SIZE);
1937 } else {
1938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1939 SDHCI_BLOCK_SIZE);
1940 }
1941
1942 /*
1943 * The tuning block is sent by the card to the host controller.
1944 * So we set the TRNS_READ bit in the Transfer Mode register.
1945 * This also takes care of setting DMA Enable and Multi Block
1946 * Select in the same register to 0.
1947 */
1948 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1949
1950 sdhci_send_command(host, &cmd);
1951
1952 host->cmd = NULL;
1953 host->mrq = NULL;
1954
1955 spin_unlock_irqrestore(&host->lock, flags);
1956 /* Wait for Buffer Read Ready interrupt */
1957 wait_event_interruptible_timeout(host->buf_ready_int,
1958 (host->tuning_done == 1),
1959 msecs_to_jiffies(50));
1960 spin_lock_irqsave(&host->lock, flags);
1961
1962 if (!host->tuning_done) {
1963 pr_info(DRIVER_NAME ": Timeout waiting for "
1964 "Buffer Read Ready interrupt during tuning "
1965 "procedure, falling back to fixed sampling "
1966 "clock\n");
1967 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1968 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1969 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971
1972 err = -EIO;
1973 goto out;
1974 }
1975
1976 host->tuning_done = 0;
1977
1978 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1979
1980 /* eMMC spec does not require a delay between tuning cycles */
1981 if (opcode == MMC_SEND_TUNING_BLOCK)
1982 mdelay(1);
1983 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1984
1985 /*
1986 * The Host Driver has exhausted the maximum number of loops allowed,
1987 * so use fixed sampling frequency.
1988 */
1989 if (tuning_loop_counter < 0) {
1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1992 }
1993 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1994 pr_info(DRIVER_NAME ": Tuning procedure"
1995 " failed, falling back to fixed sampling"
1996 " clock\n");
1997 err = -EIO;
1998 }
1999
2000 out:
2001 /*
2002 * If this is the very first time we are here, we start the retuning
2003 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2004 * flag won't be set, we check this condition before actually starting
2005 * the timer.
2006 */
2007 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2008 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2009 host->flags |= SDHCI_USING_RETUNING_TIMER;
2010 mod_timer(&host->tuning_timer, jiffies +
2011 host->tuning_count * HZ);
2012 /* Tuning mode 1 limits the maximum data length to 4MB */
2013 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2014 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2015 host->flags &= ~SDHCI_NEEDS_RETUNING;
2016 /* Reload the new initial value for timer */
2017 mod_timer(&host->tuning_timer, jiffies +
2018 host->tuning_count * HZ);
2019 }
2020
2021 /*
2022 * In case tuning fails, host controllers which support re-tuning can
2023 * try tuning again at a later time, when the re-tuning timer expires.
2024 * So for these controllers, we return 0. Since there might be other
2025 * controllers who do not have this capability, we return error for
2026 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2027 * a retuning timer to do the retuning for the card.
2028 */
2029 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2030 err = 0;
2031
2032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2034 spin_unlock_irqrestore(&host->lock, flags);
2035 sdhci_runtime_pm_put(host);
2036
2037 return err;
2038 }
2039
2040
2041 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2042 {
2043 /* Host Controller v3.00 defines preset value registers */
2044 if (host->version < SDHCI_SPEC_300)
2045 return;
2046
2047 /*
2048 * We only enable or disable Preset Value if they are not already
2049 * enabled or disabled respectively. Otherwise, we bail out.
2050 */
2051 if (host->preset_enabled != enable) {
2052 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2053
2054 if (enable)
2055 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2056 else
2057 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2058
2059 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2060
2061 if (enable)
2062 host->flags |= SDHCI_PV_ENABLED;
2063 else
2064 host->flags &= ~SDHCI_PV_ENABLED;
2065
2066 host->preset_enabled = enable;
2067 }
2068 }
2069
2070 static void sdhci_card_event(struct mmc_host *mmc)
2071 {
2072 struct sdhci_host *host = mmc_priv(mmc);
2073 unsigned long flags;
2074
2075 /* First check if client has provided their own card event */
2076 if (host->ops->card_event)
2077 host->ops->card_event(host);
2078
2079 spin_lock_irqsave(&host->lock, flags);
2080
2081 /* Check host->mrq first in case we are runtime suspended */
2082 if (host->mrq && !sdhci_do_get_cd(host)) {
2083 pr_err("%s: Card removed during transfer!\n",
2084 mmc_hostname(host->mmc));
2085 pr_err("%s: Resetting controller.\n",
2086 mmc_hostname(host->mmc));
2087
2088 sdhci_do_reset(host, SDHCI_RESET_CMD);
2089 sdhci_do_reset(host, SDHCI_RESET_DATA);
2090
2091 host->mrq->cmd->error = -ENOMEDIUM;
2092 tasklet_schedule(&host->finish_tasklet);
2093 }
2094
2095 spin_unlock_irqrestore(&host->lock, flags);
2096 }
2097
2098 static const struct mmc_host_ops sdhci_ops = {
2099 .request = sdhci_request,
2100 .set_ios = sdhci_set_ios,
2101 .get_cd = sdhci_get_cd,
2102 .get_ro = sdhci_get_ro,
2103 .hw_reset = sdhci_hw_reset,
2104 .enable_sdio_irq = sdhci_enable_sdio_irq,
2105 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2106 .execute_tuning = sdhci_execute_tuning,
2107 .card_event = sdhci_card_event,
2108 .card_busy = sdhci_card_busy,
2109 };
2110
2111 /*****************************************************************************\
2112 * *
2113 * Tasklets *
2114 * *
2115 \*****************************************************************************/
2116
2117 static void sdhci_tasklet_finish(unsigned long param)
2118 {
2119 struct sdhci_host *host;
2120 unsigned long flags;
2121 struct mmc_request *mrq;
2122
2123 host = (struct sdhci_host*)param;
2124
2125 spin_lock_irqsave(&host->lock, flags);
2126
2127 /*
2128 * If this tasklet gets rescheduled while running, it will
2129 * be run again afterwards but without any active request.
2130 */
2131 if (!host->mrq) {
2132 spin_unlock_irqrestore(&host->lock, flags);
2133 return;
2134 }
2135
2136 del_timer(&host->timer);
2137
2138 mrq = host->mrq;
2139
2140 /*
2141 * The controller needs a reset of internal state machines
2142 * upon error conditions.
2143 */
2144 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2145 ((mrq->cmd && mrq->cmd->error) ||
2146 (mrq->data && (mrq->data->error ||
2147 (mrq->data->stop && mrq->data->stop->error))) ||
2148 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2149
2150 /* Some controllers need this kick or reset won't work here */
2151 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2152 /* This is to force an update */
2153 host->ops->set_clock(host, host->clock);
2154
2155 /* Spec says we should do both at the same time, but Ricoh
2156 controllers do not like that. */
2157 sdhci_do_reset(host, SDHCI_RESET_CMD);
2158 sdhci_do_reset(host, SDHCI_RESET_DATA);
2159 }
2160
2161 host->mrq = NULL;
2162 host->cmd = NULL;
2163 host->data = NULL;
2164
2165 #ifndef SDHCI_USE_LEDS_CLASS
2166 sdhci_deactivate_led(host);
2167 #endif
2168
2169 mmiowb();
2170 spin_unlock_irqrestore(&host->lock, flags);
2171
2172 mmc_request_done(host->mmc, mrq);
2173 sdhci_runtime_pm_put(host);
2174 }
2175
2176 static void sdhci_timeout_timer(unsigned long data)
2177 {
2178 struct sdhci_host *host;
2179 unsigned long flags;
2180
2181 host = (struct sdhci_host*)data;
2182
2183 spin_lock_irqsave(&host->lock, flags);
2184
2185 if (host->mrq) {
2186 pr_err("%s: Timeout waiting for hardware "
2187 "interrupt.\n", mmc_hostname(host->mmc));
2188 sdhci_dumpregs(host);
2189
2190 if (host->data) {
2191 host->data->error = -ETIMEDOUT;
2192 sdhci_finish_data(host);
2193 } else {
2194 if (host->cmd)
2195 host->cmd->error = -ETIMEDOUT;
2196 else
2197 host->mrq->cmd->error = -ETIMEDOUT;
2198
2199 tasklet_schedule(&host->finish_tasklet);
2200 }
2201 }
2202
2203 mmiowb();
2204 spin_unlock_irqrestore(&host->lock, flags);
2205 }
2206
2207 static void sdhci_tuning_timer(unsigned long data)
2208 {
2209 struct sdhci_host *host;
2210 unsigned long flags;
2211
2212 host = (struct sdhci_host *)data;
2213
2214 spin_lock_irqsave(&host->lock, flags);
2215
2216 host->flags |= SDHCI_NEEDS_RETUNING;
2217
2218 spin_unlock_irqrestore(&host->lock, flags);
2219 }
2220
2221 /*****************************************************************************\
2222 * *
2223 * Interrupt handling *
2224 * *
2225 \*****************************************************************************/
2226
2227 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2228 {
2229 BUG_ON(intmask == 0);
2230
2231 if (!host->cmd) {
2232 pr_err("%s: Got command interrupt 0x%08x even "
2233 "though no command operation was in progress.\n",
2234 mmc_hostname(host->mmc), (unsigned)intmask);
2235 sdhci_dumpregs(host);
2236 return;
2237 }
2238
2239 if (intmask & SDHCI_INT_TIMEOUT)
2240 host->cmd->error = -ETIMEDOUT;
2241 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2242 SDHCI_INT_INDEX))
2243 host->cmd->error = -EILSEQ;
2244
2245 if (host->cmd->error) {
2246 tasklet_schedule(&host->finish_tasklet);
2247 return;
2248 }
2249
2250 /*
2251 * The host can send and interrupt when the busy state has
2252 * ended, allowing us to wait without wasting CPU cycles.
2253 * Unfortunately this is overloaded on the "data complete"
2254 * interrupt, so we need to take some care when handling
2255 * it.
2256 *
2257 * Note: The 1.0 specification is a bit ambiguous about this
2258 * feature so there might be some problems with older
2259 * controllers.
2260 */
2261 if (host->cmd->flags & MMC_RSP_BUSY) {
2262 if (host->cmd->data)
2263 DBG("Cannot wait for busy signal when also "
2264 "doing a data transfer");
2265 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2266 && !host->busy_handle) {
2267 /* Mark that command complete before busy is ended */
2268 host->busy_handle = 1;
2269 return;
2270 }
2271
2272 /* The controller does not support the end-of-busy IRQ,
2273 * fall through and take the SDHCI_INT_RESPONSE */
2274 }
2275
2276 if (intmask & SDHCI_INT_RESPONSE)
2277 sdhci_finish_command(host);
2278 }
2279
2280 #ifdef CONFIG_MMC_DEBUG
2281 static void sdhci_show_adma_error(struct sdhci_host *host)
2282 {
2283 const char *name = mmc_hostname(host->mmc);
2284 u8 *desc = host->adma_desc;
2285 __le32 *dma;
2286 __le16 *len;
2287 u8 attr;
2288
2289 sdhci_dumpregs(host);
2290
2291 while (true) {
2292 dma = (__le32 *)(desc + 4);
2293 len = (__le16 *)(desc + 2);
2294 attr = *desc;
2295
2296 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2297 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2298
2299 desc += 8;
2300
2301 if (attr & 2)
2302 break;
2303 }
2304 }
2305 #else
2306 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2307 #endif
2308
2309 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2310 {
2311 u32 command;
2312 BUG_ON(intmask == 0);
2313
2314 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2315 if (intmask & SDHCI_INT_DATA_AVAIL) {
2316 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2317 if (command == MMC_SEND_TUNING_BLOCK ||
2318 command == MMC_SEND_TUNING_BLOCK_HS200) {
2319 host->tuning_done = 1;
2320 wake_up(&host->buf_ready_int);
2321 return;
2322 }
2323 }
2324
2325 if (!host->data) {
2326 /*
2327 * The "data complete" interrupt is also used to
2328 * indicate that a busy state has ended. See comment
2329 * above in sdhci_cmd_irq().
2330 */
2331 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2332 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2333 host->cmd->error = -ETIMEDOUT;
2334 tasklet_schedule(&host->finish_tasklet);
2335 return;
2336 }
2337 if (intmask & SDHCI_INT_DATA_END) {
2338 /*
2339 * Some cards handle busy-end interrupt
2340 * before the command completed, so make
2341 * sure we do things in the proper order.
2342 */
2343 if (host->busy_handle)
2344 sdhci_finish_command(host);
2345 else
2346 host->busy_handle = 1;
2347 return;
2348 }
2349 }
2350
2351 pr_err("%s: Got data interrupt 0x%08x even "
2352 "though no data operation was in progress.\n",
2353 mmc_hostname(host->mmc), (unsigned)intmask);
2354 sdhci_dumpregs(host);
2355
2356 return;
2357 }
2358
2359 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2360 host->data->error = -ETIMEDOUT;
2361 else if (intmask & SDHCI_INT_DATA_END_BIT)
2362 host->data->error = -EILSEQ;
2363 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2364 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2365 != MMC_BUS_TEST_R)
2366 host->data->error = -EILSEQ;
2367 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2368 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2369 sdhci_show_adma_error(host);
2370 host->data->error = -EIO;
2371 if (host->ops->adma_workaround)
2372 host->ops->adma_workaround(host, intmask);
2373 }
2374
2375 if (host->data->error)
2376 sdhci_finish_data(host);
2377 else {
2378 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2379 sdhci_transfer_pio(host);
2380
2381 /*
2382 * We currently don't do anything fancy with DMA
2383 * boundaries, but as we can't disable the feature
2384 * we need to at least restart the transfer.
2385 *
2386 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2387 * should return a valid address to continue from, but as
2388 * some controllers are faulty, don't trust them.
2389 */
2390 if (intmask & SDHCI_INT_DMA_END) {
2391 u32 dmastart, dmanow;
2392 dmastart = sg_dma_address(host->data->sg);
2393 dmanow = dmastart + host->data->bytes_xfered;
2394 /*
2395 * Force update to the next DMA block boundary.
2396 */
2397 dmanow = (dmanow &
2398 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2399 SDHCI_DEFAULT_BOUNDARY_SIZE;
2400 host->data->bytes_xfered = dmanow - dmastart;
2401 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2402 " next 0x%08x\n",
2403 mmc_hostname(host->mmc), dmastart,
2404 host->data->bytes_xfered, dmanow);
2405 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2406 }
2407
2408 if (intmask & SDHCI_INT_DATA_END) {
2409 if (host->cmd) {
2410 /*
2411 * Data managed to finish before the
2412 * command completed. Make sure we do
2413 * things in the proper order.
2414 */
2415 host->data_early = 1;
2416 } else {
2417 sdhci_finish_data(host);
2418 }
2419 }
2420 }
2421 }
2422
2423 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2424 {
2425 irqreturn_t result = IRQ_NONE;
2426 struct sdhci_host *host = dev_id;
2427 u32 intmask, mask, unexpected = 0;
2428 int max_loops = 16;
2429
2430 spin_lock(&host->lock);
2431
2432 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2433 spin_unlock(&host->lock);
2434 return IRQ_NONE;
2435 }
2436
2437 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2438 if (!intmask || intmask == 0xffffffff) {
2439 result = IRQ_NONE;
2440 goto out;
2441 }
2442
2443 do {
2444 /* Clear selected interrupts. */
2445 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2446 SDHCI_INT_BUS_POWER);
2447 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2448
2449 DBG("*** %s got interrupt: 0x%08x\n",
2450 mmc_hostname(host->mmc), intmask);
2451
2452 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2453 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2454 SDHCI_CARD_PRESENT;
2455
2456 /*
2457 * There is a observation on i.mx esdhc. INSERT
2458 * bit will be immediately set again when it gets
2459 * cleared, if a card is inserted. We have to mask
2460 * the irq to prevent interrupt storm which will
2461 * freeze the system. And the REMOVE gets the
2462 * same situation.
2463 *
2464 * More testing are needed here to ensure it works
2465 * for other platforms though.
2466 */
2467 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2468 SDHCI_INT_CARD_REMOVE);
2469 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2470 SDHCI_INT_CARD_INSERT;
2471 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2472 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2473
2474 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2475 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2476
2477 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2478 SDHCI_INT_CARD_REMOVE);
2479 result = IRQ_WAKE_THREAD;
2480 }
2481
2482 if (intmask & SDHCI_INT_CMD_MASK)
2483 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2484
2485 if (intmask & SDHCI_INT_DATA_MASK)
2486 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2487
2488 if (intmask & SDHCI_INT_BUS_POWER)
2489 pr_err("%s: Card is consuming too much power!\n",
2490 mmc_hostname(host->mmc));
2491
2492 if (intmask & SDHCI_INT_CARD_INT) {
2493 sdhci_enable_sdio_irq_nolock(host, false);
2494 host->thread_isr |= SDHCI_INT_CARD_INT;
2495 result = IRQ_WAKE_THREAD;
2496 }
2497
2498 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2499 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2500 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2501 SDHCI_INT_CARD_INT);
2502
2503 if (intmask) {
2504 unexpected |= intmask;
2505 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2506 }
2507
2508 if (result == IRQ_NONE)
2509 result = IRQ_HANDLED;
2510
2511 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2512 } while (intmask && --max_loops);
2513 out:
2514 spin_unlock(&host->lock);
2515
2516 if (unexpected) {
2517 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2518 mmc_hostname(host->mmc), unexpected);
2519 sdhci_dumpregs(host);
2520 }
2521
2522 return result;
2523 }
2524
2525 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2526 {
2527 struct sdhci_host *host = dev_id;
2528 unsigned long flags;
2529 u32 isr;
2530
2531 spin_lock_irqsave(&host->lock, flags);
2532 isr = host->thread_isr;
2533 host->thread_isr = 0;
2534 spin_unlock_irqrestore(&host->lock, flags);
2535
2536 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2537 sdhci_card_event(host->mmc);
2538 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2539 }
2540
2541 if (isr & SDHCI_INT_CARD_INT) {
2542 sdio_run_irqs(host->mmc);
2543
2544 spin_lock_irqsave(&host->lock, flags);
2545 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2546 sdhci_enable_sdio_irq_nolock(host, true);
2547 spin_unlock_irqrestore(&host->lock, flags);
2548 }
2549
2550 return isr ? IRQ_HANDLED : IRQ_NONE;
2551 }
2552
2553 /*****************************************************************************\
2554 * *
2555 * Suspend/resume *
2556 * *
2557 \*****************************************************************************/
2558
2559 #ifdef CONFIG_PM
2560 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2561 {
2562 u8 val;
2563 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2564 | SDHCI_WAKE_ON_INT;
2565
2566 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2567 val |= mask ;
2568 /* Avoid fake wake up */
2569 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2570 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2571 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2572 }
2573 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2574
2575 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2576 {
2577 u8 val;
2578 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2579 | SDHCI_WAKE_ON_INT;
2580
2581 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2582 val &= ~mask;
2583 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2584 }
2585
2586 int sdhci_suspend_host(struct sdhci_host *host)
2587 {
2588 sdhci_disable_card_detection(host);
2589
2590 /* Disable tuning since we are suspending */
2591 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2592 del_timer_sync(&host->tuning_timer);
2593 host->flags &= ~SDHCI_NEEDS_RETUNING;
2594 }
2595
2596 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2597 host->ier = 0;
2598 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2599 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2600 free_irq(host->irq, host);
2601 } else {
2602 sdhci_enable_irq_wakeups(host);
2603 enable_irq_wake(host->irq);
2604 }
2605 return 0;
2606 }
2607
2608 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2609
2610 int sdhci_resume_host(struct sdhci_host *host)
2611 {
2612 int ret = 0;
2613
2614 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2615 if (host->ops->enable_dma)
2616 host->ops->enable_dma(host);
2617 }
2618
2619 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2620 ret = request_threaded_irq(host->irq, sdhci_irq,
2621 sdhci_thread_irq, IRQF_SHARED,
2622 mmc_hostname(host->mmc), host);
2623 if (ret)
2624 return ret;
2625 } else {
2626 sdhci_disable_irq_wakeups(host);
2627 disable_irq_wake(host->irq);
2628 }
2629
2630 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2631 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2632 /* Card keeps power but host controller does not */
2633 sdhci_init(host, 0);
2634 host->pwr = 0;
2635 host->clock = 0;
2636 sdhci_do_set_ios(host, &host->mmc->ios);
2637 } else {
2638 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2639 mmiowb();
2640 }
2641
2642 sdhci_enable_card_detection(host);
2643
2644 /* Set the re-tuning expiration flag */
2645 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2646 host->flags |= SDHCI_NEEDS_RETUNING;
2647
2648 return ret;
2649 }
2650
2651 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2652 #endif /* CONFIG_PM */
2653
2654 #ifdef CONFIG_PM_RUNTIME
2655
2656 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2657 {
2658 return pm_runtime_get_sync(host->mmc->parent);
2659 }
2660
2661 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2662 {
2663 pm_runtime_mark_last_busy(host->mmc->parent);
2664 return pm_runtime_put_autosuspend(host->mmc->parent);
2665 }
2666
2667 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2668 {
2669 if (host->runtime_suspended || host->bus_on)
2670 return;
2671 host->bus_on = true;
2672 pm_runtime_get_noresume(host->mmc->parent);
2673 }
2674
2675 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2676 {
2677 if (host->runtime_suspended || !host->bus_on)
2678 return;
2679 host->bus_on = false;
2680 pm_runtime_put_noidle(host->mmc->parent);
2681 }
2682
2683 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2684 {
2685 unsigned long flags;
2686
2687 /* Disable tuning since we are suspending */
2688 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2689 del_timer_sync(&host->tuning_timer);
2690 host->flags &= ~SDHCI_NEEDS_RETUNING;
2691 }
2692
2693 spin_lock_irqsave(&host->lock, flags);
2694 host->ier &= SDHCI_INT_CARD_INT;
2695 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2696 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2697 spin_unlock_irqrestore(&host->lock, flags);
2698
2699 synchronize_hardirq(host->irq);
2700
2701 spin_lock_irqsave(&host->lock, flags);
2702 host->runtime_suspended = true;
2703 spin_unlock_irqrestore(&host->lock, flags);
2704
2705 return 0;
2706 }
2707 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2708
2709 int sdhci_runtime_resume_host(struct sdhci_host *host)
2710 {
2711 unsigned long flags;
2712 int host_flags = host->flags;
2713
2714 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2715 if (host->ops->enable_dma)
2716 host->ops->enable_dma(host);
2717 }
2718
2719 sdhci_init(host, 0);
2720
2721 /* Force clock and power re-program */
2722 host->pwr = 0;
2723 host->clock = 0;
2724 sdhci_do_set_ios(host, &host->mmc->ios);
2725
2726 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2727 if ((host_flags & SDHCI_PV_ENABLED) &&
2728 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2729 spin_lock_irqsave(&host->lock, flags);
2730 sdhci_enable_preset_value(host, true);
2731 spin_unlock_irqrestore(&host->lock, flags);
2732 }
2733
2734 /* Set the re-tuning expiration flag */
2735 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2736 host->flags |= SDHCI_NEEDS_RETUNING;
2737
2738 spin_lock_irqsave(&host->lock, flags);
2739
2740 host->runtime_suspended = false;
2741
2742 /* Enable SDIO IRQ */
2743 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2744 sdhci_enable_sdio_irq_nolock(host, true);
2745
2746 /* Enable Card Detection */
2747 sdhci_enable_card_detection(host);
2748
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
2751 return 0;
2752 }
2753 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2754
2755 #endif
2756
2757 /*****************************************************************************\
2758 * *
2759 * Device allocation/registration *
2760 * *
2761 \*****************************************************************************/
2762
2763 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2764 size_t priv_size)
2765 {
2766 struct mmc_host *mmc;
2767 struct sdhci_host *host;
2768
2769 WARN_ON(dev == NULL);
2770
2771 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2772 if (!mmc)
2773 return ERR_PTR(-ENOMEM);
2774
2775 host = mmc_priv(mmc);
2776 host->mmc = mmc;
2777
2778 return host;
2779 }
2780
2781 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2782
2783 int sdhci_add_host(struct sdhci_host *host)
2784 {
2785 struct mmc_host *mmc;
2786 u32 caps[2] = {0, 0};
2787 u32 max_current_caps;
2788 unsigned int ocr_avail;
2789 int ret;
2790
2791 WARN_ON(host == NULL);
2792 if (host == NULL)
2793 return -EINVAL;
2794
2795 mmc = host->mmc;
2796
2797 if (debug_quirks)
2798 host->quirks = debug_quirks;
2799 if (debug_quirks2)
2800 host->quirks2 = debug_quirks2;
2801
2802 sdhci_do_reset(host, SDHCI_RESET_ALL);
2803
2804 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2805 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2806 >> SDHCI_SPEC_VER_SHIFT;
2807 if (host->version > SDHCI_SPEC_300) {
2808 pr_err("%s: Unknown controller version (%d). "
2809 "You may experience problems.\n", mmc_hostname(mmc),
2810 host->version);
2811 }
2812
2813 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2814 sdhci_readl(host, SDHCI_CAPABILITIES);
2815
2816 if (host->version >= SDHCI_SPEC_300)
2817 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2818 host->caps1 :
2819 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2820
2821 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2822 host->flags |= SDHCI_USE_SDMA;
2823 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2824 DBG("Controller doesn't have SDMA capability\n");
2825 else
2826 host->flags |= SDHCI_USE_SDMA;
2827
2828 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2829 (host->flags & SDHCI_USE_SDMA)) {
2830 DBG("Disabling DMA as it is marked broken\n");
2831 host->flags &= ~SDHCI_USE_SDMA;
2832 }
2833
2834 if ((host->version >= SDHCI_SPEC_200) &&
2835 (caps[0] & SDHCI_CAN_DO_ADMA2))
2836 host->flags |= SDHCI_USE_ADMA;
2837
2838 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2839 (host->flags & SDHCI_USE_ADMA)) {
2840 DBG("Disabling ADMA as it is marked broken\n");
2841 host->flags &= ~SDHCI_USE_ADMA;
2842 }
2843
2844 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2845 if (host->ops->enable_dma) {
2846 if (host->ops->enable_dma(host)) {
2847 pr_warning("%s: No suitable DMA "
2848 "available. Falling back to PIO.\n",
2849 mmc_hostname(mmc));
2850 host->flags &=
2851 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2852 }
2853 }
2854 }
2855
2856 if (host->flags & SDHCI_USE_ADMA) {
2857 /*
2858 * We need to allocate descriptors for all sg entries
2859 * (128) and potentially one alignment transfer for
2860 * each of those entries.
2861 */
2862 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2863 ADMA_SIZE, &host->adma_addr,
2864 GFP_KERNEL);
2865 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2866 if (!host->adma_desc || !host->align_buffer) {
2867 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2868 host->adma_desc, host->adma_addr);
2869 kfree(host->align_buffer);
2870 pr_warning("%s: Unable to allocate ADMA "
2871 "buffers. Falling back to standard DMA.\n",
2872 mmc_hostname(mmc));
2873 host->flags &= ~SDHCI_USE_ADMA;
2874 host->adma_desc = NULL;
2875 host->align_buffer = NULL;
2876 } else if (host->adma_addr & 3) {
2877 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2878 mmc_hostname(mmc));
2879 host->flags &= ~SDHCI_USE_ADMA;
2880 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2881 host->adma_desc, host->adma_addr);
2882 kfree(host->align_buffer);
2883 host->adma_desc = NULL;
2884 host->align_buffer = NULL;
2885 }
2886 }
2887
2888 /*
2889 * If we use DMA, then it's up to the caller to set the DMA
2890 * mask, but PIO does not need the hw shim so we set a new
2891 * mask here in that case.
2892 */
2893 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2894 host->dma_mask = DMA_BIT_MASK(64);
2895 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2896 }
2897
2898 if (host->version >= SDHCI_SPEC_300)
2899 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2900 >> SDHCI_CLOCK_BASE_SHIFT;
2901 else
2902 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2903 >> SDHCI_CLOCK_BASE_SHIFT;
2904
2905 host->max_clk *= 1000000;
2906 if (host->max_clk == 0 || host->quirks &
2907 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2908 if (!host->ops->get_max_clock) {
2909 pr_err("%s: Hardware doesn't specify base clock "
2910 "frequency.\n", mmc_hostname(mmc));
2911 return -ENODEV;
2912 }
2913 host->max_clk = host->ops->get_max_clock(host);
2914 }
2915
2916 /*
2917 * In case of Host Controller v3.00, find out whether clock
2918 * multiplier is supported.
2919 */
2920 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2921 SDHCI_CLOCK_MUL_SHIFT;
2922
2923 /*
2924 * In case the value in Clock Multiplier is 0, then programmable
2925 * clock mode is not supported, otherwise the actual clock
2926 * multiplier is one more than the value of Clock Multiplier
2927 * in the Capabilities Register.
2928 */
2929 if (host->clk_mul)
2930 host->clk_mul += 1;
2931
2932 /*
2933 * Set host parameters.
2934 */
2935 mmc->ops = &sdhci_ops;
2936 mmc->f_max = host->max_clk;
2937 if (host->ops->get_min_clock)
2938 mmc->f_min = host->ops->get_min_clock(host);
2939 else if (host->version >= SDHCI_SPEC_300) {
2940 if (host->clk_mul) {
2941 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2942 mmc->f_max = host->max_clk * host->clk_mul;
2943 } else
2944 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2945 } else
2946 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2947
2948 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2949 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2950 SDHCI_TIMEOUT_CLK_SHIFT;
2951 if (host->timeout_clk == 0) {
2952 if (host->ops->get_timeout_clock) {
2953 host->timeout_clk =
2954 host->ops->get_timeout_clock(host);
2955 } else {
2956 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2957 mmc_hostname(mmc));
2958 return -ENODEV;
2959 }
2960 }
2961
2962 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2963 host->timeout_clk *= 1000;
2964
2965 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2966 host->ops->get_max_timeout_count(host) : 1 << 27;
2967 mmc->max_busy_timeout /= host->timeout_clk;
2968 }
2969
2970 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2971 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2972
2973 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2974 host->flags |= SDHCI_AUTO_CMD12;
2975
2976 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2977 if ((host->version >= SDHCI_SPEC_300) &&
2978 ((host->flags & SDHCI_USE_ADMA) ||
2979 !(host->flags & SDHCI_USE_SDMA))) {
2980 host->flags |= SDHCI_AUTO_CMD23;
2981 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2982 } else {
2983 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2984 }
2985
2986 /*
2987 * A controller may support 8-bit width, but the board itself
2988 * might not have the pins brought out. Boards that support
2989 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2990 * their platform code before calling sdhci_add_host(), and we
2991 * won't assume 8-bit width for hosts without that CAP.
2992 */
2993 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2994 mmc->caps |= MMC_CAP_4_BIT_DATA;
2995
2996 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2997 mmc->caps &= ~MMC_CAP_CMD23;
2998
2999 if (caps[0] & SDHCI_CAN_DO_HISPD)
3000 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3001
3002 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3003 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3004 mmc->caps |= MMC_CAP_NEEDS_POLL;
3005
3006 /* If there are external regulators, get them */
3007 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3008 return -EPROBE_DEFER;
3009
3010 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3011 if (!IS_ERR(mmc->supply.vqmmc)) {
3012 ret = regulator_enable(mmc->supply.vqmmc);
3013 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3014 1950000))
3015 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3016 SDHCI_SUPPORT_SDR50 |
3017 SDHCI_SUPPORT_DDR50);
3018 if (ret) {
3019 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3020 mmc_hostname(mmc), ret);
3021 mmc->supply.vqmmc = NULL;
3022 }
3023 }
3024
3025 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3026 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3027 SDHCI_SUPPORT_DDR50);
3028
3029 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3030 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3031 SDHCI_SUPPORT_DDR50))
3032 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3033
3034 /* SDR104 supports also implies SDR50 support */
3035 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3036 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3037 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3038 * field can be promoted to support HS200.
3039 */
3040 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3041 mmc->caps2 |= MMC_CAP2_HS200;
3042 if (IS_ERR(mmc->supply.vqmmc) ||
3043 !regulator_is_supported_voltage
3044 (mmc->supply.vqmmc, 1100000, 1300000))
3045 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3046 }
3047 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3048 mmc->caps |= MMC_CAP_UHS_SDR50;
3049
3050 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3051 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3052 mmc->caps |= MMC_CAP_UHS_DDR50;
3053
3054 /* Does the host need tuning for SDR50? */
3055 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3056 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3057
3058 /* Does the host need tuning for SDR104 / HS200? */
3059 if (mmc->caps2 & MMC_CAP2_HS200)
3060 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3061
3062 /* Driver Type(s) (A, C, D) supported by the host */
3063 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3064 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3065 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3066 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3067 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3068 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3069
3070 /* Initial value for re-tuning timer count */
3071 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3072 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3073
3074 /*
3075 * In case Re-tuning Timer is not disabled, the actual value of
3076 * re-tuning timer will be 2 ^ (n - 1).
3077 */
3078 if (host->tuning_count)
3079 host->tuning_count = 1 << (host->tuning_count - 1);
3080
3081 /* Re-tuning mode supported by the Host Controller */
3082 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3083 SDHCI_RETUNING_MODE_SHIFT;
3084
3085 ocr_avail = 0;
3086
3087 /*
3088 * According to SD Host Controller spec v3.00, if the Host System
3089 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3090 * the value is meaningful only if Voltage Support in the Capabilities
3091 * register is set. The actual current value is 4 times the register
3092 * value.
3093 */
3094 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3095 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3096 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3097 if (curr > 0) {
3098
3099 /* convert to SDHCI_MAX_CURRENT format */
3100 curr = curr/1000; /* convert to mA */
3101 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3102
3103 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3104 max_current_caps =
3105 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3106 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3107 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3108 }
3109 }
3110
3111 if (caps[0] & SDHCI_CAN_VDD_330) {
3112 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3113
3114 mmc->max_current_330 = ((max_current_caps &
3115 SDHCI_MAX_CURRENT_330_MASK) >>
3116 SDHCI_MAX_CURRENT_330_SHIFT) *
3117 SDHCI_MAX_CURRENT_MULTIPLIER;
3118 }
3119 if (caps[0] & SDHCI_CAN_VDD_300) {
3120 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3121
3122 mmc->max_current_300 = ((max_current_caps &
3123 SDHCI_MAX_CURRENT_300_MASK) >>
3124 SDHCI_MAX_CURRENT_300_SHIFT) *
3125 SDHCI_MAX_CURRENT_MULTIPLIER;
3126 }
3127 if (caps[0] & SDHCI_CAN_VDD_180) {
3128 ocr_avail |= MMC_VDD_165_195;
3129
3130 mmc->max_current_180 = ((max_current_caps &
3131 SDHCI_MAX_CURRENT_180_MASK) >>
3132 SDHCI_MAX_CURRENT_180_SHIFT) *
3133 SDHCI_MAX_CURRENT_MULTIPLIER;
3134 }
3135
3136 /* If OCR set by external regulators, use it instead */
3137 if (mmc->ocr_avail)
3138 ocr_avail = mmc->ocr_avail;
3139
3140 if (host->ocr_mask)
3141 ocr_avail &= host->ocr_mask;
3142
3143 mmc->ocr_avail = ocr_avail;
3144 mmc->ocr_avail_sdio = ocr_avail;
3145 if (host->ocr_avail_sdio)
3146 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3147 mmc->ocr_avail_sd = ocr_avail;
3148 if (host->ocr_avail_sd)
3149 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3150 else /* normal SD controllers don't support 1.8V */
3151 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3152 mmc->ocr_avail_mmc = ocr_avail;
3153 if (host->ocr_avail_mmc)
3154 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3155
3156 if (mmc->ocr_avail == 0) {
3157 pr_err("%s: Hardware doesn't report any "
3158 "support voltages.\n", mmc_hostname(mmc));
3159 return -ENODEV;
3160 }
3161
3162 spin_lock_init(&host->lock);
3163
3164 /*
3165 * Maximum number of segments. Depends on if the hardware
3166 * can do scatter/gather or not.
3167 */
3168 if (host->flags & SDHCI_USE_ADMA)
3169 mmc->max_segs = 128;
3170 else if (host->flags & SDHCI_USE_SDMA)
3171 mmc->max_segs = 1;
3172 else /* PIO */
3173 mmc->max_segs = 128;
3174
3175 /*
3176 * Maximum number of sectors in one transfer. Limited by DMA boundary
3177 * size (512KiB).
3178 */
3179 mmc->max_req_size = 524288;
3180
3181 /*
3182 * Maximum segment size. Could be one segment with the maximum number
3183 * of bytes. When doing hardware scatter/gather, each entry cannot
3184 * be larger than 64 KiB though.
3185 */
3186 if (host->flags & SDHCI_USE_ADMA) {
3187 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3188 mmc->max_seg_size = 65535;
3189 else
3190 mmc->max_seg_size = 65536;
3191 } else {
3192 mmc->max_seg_size = mmc->max_req_size;
3193 }
3194
3195 /*
3196 * Maximum block size. This varies from controller to controller and
3197 * is specified in the capabilities register.
3198 */
3199 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3200 mmc->max_blk_size = 2;
3201 } else {
3202 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3203 SDHCI_MAX_BLOCK_SHIFT;
3204 if (mmc->max_blk_size >= 3) {
3205 pr_warning("%s: Invalid maximum block size, "
3206 "assuming 512 bytes\n", mmc_hostname(mmc));
3207 mmc->max_blk_size = 0;
3208 }
3209 }
3210
3211 mmc->max_blk_size = 512 << mmc->max_blk_size;
3212
3213 /*
3214 * Maximum block count.
3215 */
3216 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3217
3218 /*
3219 * Init tasklets.
3220 */
3221 tasklet_init(&host->finish_tasklet,
3222 sdhci_tasklet_finish, (unsigned long)host);
3223
3224 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3225
3226 if (host->version >= SDHCI_SPEC_300) {
3227 init_waitqueue_head(&host->buf_ready_int);
3228
3229 /* Initialize re-tuning timer */
3230 init_timer(&host->tuning_timer);
3231 host->tuning_timer.data = (unsigned long)host;
3232 host->tuning_timer.function = sdhci_tuning_timer;
3233 }
3234
3235 sdhci_init(host, 0);
3236
3237 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3238 IRQF_SHARED, mmc_hostname(mmc), host);
3239 if (ret) {
3240 pr_err("%s: Failed to request IRQ %d: %d\n",
3241 mmc_hostname(mmc), host->irq, ret);
3242 goto untasklet;
3243 }
3244
3245 #ifdef CONFIG_MMC_DEBUG
3246 sdhci_dumpregs(host);
3247 #endif
3248
3249 #ifdef SDHCI_USE_LEDS_CLASS
3250 snprintf(host->led_name, sizeof(host->led_name),
3251 "%s::", mmc_hostname(mmc));
3252 host->led.name = host->led_name;
3253 host->led.brightness = LED_OFF;
3254 host->led.default_trigger = mmc_hostname(mmc);
3255 host->led.brightness_set = sdhci_led_control;
3256
3257 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3258 if (ret) {
3259 pr_err("%s: Failed to register LED device: %d\n",
3260 mmc_hostname(mmc), ret);
3261 goto reset;
3262 }
3263 #endif
3264
3265 mmiowb();
3266
3267 mmc_add_host(mmc);
3268
3269 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3270 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3271 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3272 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3273
3274 sdhci_enable_card_detection(host);
3275
3276 return 0;
3277
3278 #ifdef SDHCI_USE_LEDS_CLASS
3279 reset:
3280 sdhci_do_reset(host, SDHCI_RESET_ALL);
3281 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3282 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3283 free_irq(host->irq, host);
3284 #endif
3285 untasklet:
3286 tasklet_kill(&host->finish_tasklet);
3287
3288 return ret;
3289 }
3290
3291 EXPORT_SYMBOL_GPL(sdhci_add_host);
3292
3293 void sdhci_remove_host(struct sdhci_host *host, int dead)
3294 {
3295 struct mmc_host *mmc = host->mmc;
3296 unsigned long flags;
3297
3298 if (dead) {
3299 spin_lock_irqsave(&host->lock, flags);
3300
3301 host->flags |= SDHCI_DEVICE_DEAD;
3302
3303 if (host->mrq) {
3304 pr_err("%s: Controller removed during "
3305 " transfer!\n", mmc_hostname(mmc));
3306
3307 host->mrq->cmd->error = -ENOMEDIUM;
3308 tasklet_schedule(&host->finish_tasklet);
3309 }
3310
3311 spin_unlock_irqrestore(&host->lock, flags);
3312 }
3313
3314 sdhci_disable_card_detection(host);
3315
3316 mmc_remove_host(mmc);
3317
3318 #ifdef SDHCI_USE_LEDS_CLASS
3319 led_classdev_unregister(&host->led);
3320 #endif
3321
3322 if (!dead)
3323 sdhci_do_reset(host, SDHCI_RESET_ALL);
3324
3325 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3326 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3327 free_irq(host->irq, host);
3328
3329 del_timer_sync(&host->timer);
3330
3331 tasklet_kill(&host->finish_tasklet);
3332
3333 if (!IS_ERR(mmc->supply.vmmc))
3334 regulator_disable(mmc->supply.vmmc);
3335
3336 if (!IS_ERR(mmc->supply.vqmmc))
3337 regulator_disable(mmc->supply.vqmmc);
3338
3339 if (host->adma_desc)
3340 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3341 host->adma_desc, host->adma_addr);
3342 kfree(host->align_buffer);
3343
3344 host->adma_desc = NULL;
3345 host->align_buffer = NULL;
3346 }
3347
3348 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3349
3350 void sdhci_free_host(struct sdhci_host *host)
3351 {
3352 mmc_free_host(host->mmc);
3353 }
3354
3355 EXPORT_SYMBOL_GPL(sdhci_free_host);
3356
3357 /*****************************************************************************\
3358 * *
3359 * Driver init/exit *
3360 * *
3361 \*****************************************************************************/
3362
3363 static int __init sdhci_drv_init(void)
3364 {
3365 pr_info(DRIVER_NAME
3366 ": Secure Digital Host Controller Interface driver\n");
3367 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3368
3369 return 0;
3370 }
3371
3372 static void __exit sdhci_drv_exit(void)
3373 {
3374 }
3375
3376 module_init(sdhci_drv_init);
3377 module_exit(sdhci_drv_exit);
3378
3379 module_param(debug_quirks, uint, 0444);
3380 module_param(debug_quirks2, uint, 0444);
3381
3382 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3383 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3384 MODULE_LICENSE("GPL");
3385
3386 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3387 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Ubuntu Artful kernel mirror