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Merge branch 'for-4.3-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm into...
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data);
58 static int sdhci_do_get_cd(struct sdhci_host *host);
59
60 #ifdef CONFIG_PM
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 #else
66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 {
68 return 0;
69 }
70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 {
72 return 0;
73 }
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75 {
76 }
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78 {
79 }
80 #endif
81
82 static void sdhci_dumpregs(struct sdhci_host *host)
83 {
84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host->mmc));
86
87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host, SDHCI_CAPABILITIES),
116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host, SDHCI_COMMAND),
119 sdhci_readl(host, SDHCI_MAX_CURRENT));
120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122
123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
134
135 pr_debug(DRIVER_NAME ": ===========================================\n");
136 }
137
138 /*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142 \*****************************************************************************/
143
144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145 {
146 u32 present;
147
148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
150 return;
151
152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155
156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
164 }
165
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168 sdhci_set_card_detection(host, true);
169 }
170
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173 sdhci_set_card_detection(host, false);
174 }
175
176 void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178 unsigned long timeout;
179
180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
181
182 if (mask & SDHCI_RESET_ALL) {
183 host->clock = 0;
184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
188
189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
194 if (timeout == 0) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
202 }
203 }
204 EXPORT_SYMBOL_GPL(sdhci_reset);
205
206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207 {
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209 if (!sdhci_do_get_cd(host))
210 return;
211 }
212
213 host->ops->reset(host, mask);
214
215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
223 }
224 }
225
226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228 static void sdhci_init(struct sdhci_host *host, int soft)
229 {
230 if (soft)
231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
232 else
233 sdhci_do_reset(host, SDHCI_RESET_ALL);
234
235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
249 }
250
251 static void sdhci_reinit(struct sdhci_host *host)
252 {
253 sdhci_init(host, 0);
254 sdhci_enable_card_detection(host);
255 }
256
257 static void sdhci_activate_led(struct sdhci_host *host)
258 {
259 u8 ctrl;
260
261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
262 ctrl |= SDHCI_CTRL_LED;
263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
264 }
265
266 static void sdhci_deactivate_led(struct sdhci_host *host)
267 {
268 u8 ctrl;
269
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl &= ~SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278 {
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
284 if (host->runtime_suspended)
285 goto out;
286
287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
291 out:
292 spin_unlock_irqrestore(&host->lock, flags);
293 }
294 #endif
295
296 /*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300 \*****************************************************************************/
301
302 static void sdhci_read_block_pio(struct sdhci_host *host)
303 {
304 unsigned long flags;
305 size_t blksize, len, chunk;
306 u32 uninitialized_var(scratch);
307 u8 *buf;
308
309 DBG("PIO reading\n");
310
311 blksize = host->data->blksz;
312 chunk = 0;
313
314 local_irq_save(flags);
315
316 while (blksize) {
317 BUG_ON(!sg_miter_next(&host->sg_miter));
318
319 len = min(host->sg_miter.length, blksize);
320
321 blksize -= len;
322 host->sg_miter.consumed = len;
323
324 buf = host->sg_miter.addr;
325
326 while (len) {
327 if (chunk == 0) {
328 scratch = sdhci_readl(host, SDHCI_BUFFER);
329 chunk = 4;
330 }
331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
338 }
339 }
340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
344 }
345
346 static void sdhci_write_block_pio(struct sdhci_host *host)
347 {
348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
352
353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
356 chunk = 0;
357 scratch = 0;
358
359 local_irq_save(flags);
360
361 while (blksize) {
362 BUG_ON(!sg_miter_next(&host->sg_miter));
363
364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
370
371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
379 sdhci_writel(host, scratch, SDHCI_BUFFER);
380 chunk = 0;
381 scratch = 0;
382 }
383 }
384 }
385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
389 }
390
391 static void sdhci_transfer_pio(struct sdhci_host *host)
392 {
393 u32 mask;
394
395 BUG_ON(!host->data);
396
397 if (host->blocks == 0)
398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
422
423 host->blocks--;
424 if (host->blocks == 0)
425 break;
426 }
427
428 DBG("PIO transfer complete.\n");
429 }
430
431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432 {
433 local_irq_save(*flags);
434 return kmap_atomic(sg_page(sg)) + sg->offset;
435 }
436
437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438 {
439 kunmap_atomic(buffer);
440 local_irq_restore(*flags);
441 }
442
443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
445 {
446 struct sdhci_adma2_64_desc *dma_desc = desc;
447
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
455 }
456
457 static void sdhci_adma_mark_end(void *desc)
458 {
459 struct sdhci_adma2_64_desc *dma_desc = desc;
460
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
463 }
464
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467 {
468 int direction;
469
470 void *desc;
471 void *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, host->align_buffer_sz, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494 goto fail;
495 BUG_ON(host->align_addr & host->align_mask);
496
497 host->sg_count = sdhci_pre_dma_transfer(host, data);
498 if (host->sg_count < 0)
499 goto unmap_align;
500
501 desc = host->adma_table;
502 align = host->align_buffer;
503
504 align_addr = host->align_addr;
505
506 for_each_sg(data->sg, sg, host->sg_count, i) {
507 addr = sg_dma_address(sg);
508 len = sg_dma_len(sg);
509
510 /*
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
515 * alignment.
516 */
517 offset = (host->align_sz - (addr & host->align_mask)) &
518 host->align_mask;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 memcpy(align, buffer, offset);
523 sdhci_kunmap_atomic(buffer, &flags);
524 }
525
526 /* tran, valid */
527 sdhci_adma_write_desc(host, desc, align_addr, offset,
528 ADMA2_TRAN_VALID);
529
530 BUG_ON(offset > 65536);
531
532 align += host->align_sz;
533 align_addr += host->align_sz;
534
535 desc += host->desc_sz;
536
537 addr += offset;
538 len -= offset;
539 }
540
541 BUG_ON(len > 65536);
542
543 /* tran, valid */
544 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
545 desc += host->desc_sz;
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
551 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
552 }
553
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
558 if (desc != host->adma_table) {
559 desc -= host->desc_sz;
560 sdhci_adma_mark_end(desc);
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
566
567 /* nop, end, valid */
568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
569 }
570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, host->align_buffer_sz, direction);
577 }
578
579 return 0;
580
581 unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 host->align_buffer_sz, direction);
584 fail:
585 return -EINVAL;
586 }
587
588 static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590 {
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
595 void *align;
596 char *buffer;
597 unsigned long flags;
598 bool has_unaligned;
599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 host->align_buffer_sz, direction);
607
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & host->align_mask) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & host->align_mask) {
624 size = host->align_sz -
625 (sg_dma_address(sg) & host->align_mask);
626
627 buffer = sdhci_kmap_atomic(sg, &flags);
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
631 align += host->align_sz;
632 }
633 }
634 }
635
636 if (data->host_cookie == COOKIE_MAPPED) {
637 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
638 data->sg_len, direction);
639 data->host_cookie = COOKIE_UNMAPPED;
640 }
641 }
642
643 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
644 {
645 u8 count;
646 struct mmc_data *data = cmd->data;
647 unsigned target_timeout, current_timeout;
648
649 /*
650 * If the host controller provides us with an incorrect timeout
651 * value, just skip the check and use 0xE. The hardware may take
652 * longer to time out, but that's much better than having a too-short
653 * timeout value.
654 */
655 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
656 return 0xE;
657
658 /* Unspecified timeout, assume max */
659 if (!data && !cmd->busy_timeout)
660 return 0xE;
661
662 /* timeout in us */
663 if (!data)
664 target_timeout = cmd->busy_timeout * 1000;
665 else {
666 target_timeout = data->timeout_ns / 1000;
667 if (host->clock)
668 target_timeout += data->timeout_clks / host->clock;
669 }
670
671 /*
672 * Figure out needed cycles.
673 * We do this in steps in order to fit inside a 32 bit int.
674 * The first step is the minimum timeout, which will have a
675 * minimum resolution of 6 bits:
676 * (1) 2^13*1000 > 2^22,
677 * (2) host->timeout_clk < 2^16
678 * =>
679 * (1) / (2) > 2^6
680 */
681 count = 0;
682 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
683 while (current_timeout < target_timeout) {
684 count++;
685 current_timeout <<= 1;
686 if (count >= 0xF)
687 break;
688 }
689
690 if (count >= 0xF) {
691 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
692 mmc_hostname(host->mmc), count, cmd->opcode);
693 count = 0xE;
694 }
695
696 return count;
697 }
698
699 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
700 {
701 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
702 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
703
704 if (host->flags & SDHCI_REQ_USE_DMA)
705 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
706 else
707 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
708
709 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
710 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
711 }
712
713 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
714 {
715 u8 count;
716
717 if (host->ops->set_timeout) {
718 host->ops->set_timeout(host, cmd);
719 } else {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 }
723 }
724
725 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
726 {
727 u8 ctrl;
728 struct mmc_data *data = cmd->data;
729 int ret;
730
731 WARN_ON(host->data);
732
733 if (data || (cmd->flags & MMC_RSP_BUSY))
734 sdhci_set_timeout(host, cmd);
735
736 if (!data)
737 return;
738
739 /* Sanity checks */
740 BUG_ON(data->blksz * data->blocks > 524288);
741 BUG_ON(data->blksz > host->mmc->max_blk_size);
742 BUG_ON(data->blocks > 65535);
743
744 host->data = data;
745 host->data_early = 0;
746 host->data->bytes_xfered = 0;
747
748 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
749 host->flags |= SDHCI_REQ_USE_DMA;
750
751 /*
752 * FIXME: This doesn't account for merging when mapping the
753 * scatterlist.
754 */
755 if (host->flags & SDHCI_REQ_USE_DMA) {
756 int broken, i;
757 struct scatterlist *sg;
758
759 broken = 0;
760 if (host->flags & SDHCI_USE_ADMA) {
761 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
762 broken = 1;
763 } else {
764 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
765 broken = 1;
766 }
767
768 if (unlikely(broken)) {
769 for_each_sg(data->sg, sg, data->sg_len, i) {
770 if (sg->length & 0x3) {
771 DBG("Reverting to PIO because of "
772 "transfer size (%d)\n",
773 sg->length);
774 host->flags &= ~SDHCI_REQ_USE_DMA;
775 break;
776 }
777 }
778 }
779 }
780
781 /*
782 * The assumption here being that alignment is the same after
783 * translation to device address space.
784 */
785 if (host->flags & SDHCI_REQ_USE_DMA) {
786 int broken, i;
787 struct scatterlist *sg;
788
789 broken = 0;
790 if (host->flags & SDHCI_USE_ADMA) {
791 /*
792 * As we use 3 byte chunks to work around
793 * alignment problems, we need to check this
794 * quirk.
795 */
796 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
797 broken = 1;
798 } else {
799 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
800 broken = 1;
801 }
802
803 if (unlikely(broken)) {
804 for_each_sg(data->sg, sg, data->sg_len, i) {
805 if (sg->offset & 0x3) {
806 DBG("Reverting to PIO because of "
807 "bad alignment\n");
808 host->flags &= ~SDHCI_REQ_USE_DMA;
809 break;
810 }
811 }
812 }
813 }
814
815 if (host->flags & SDHCI_REQ_USE_DMA) {
816 if (host->flags & SDHCI_USE_ADMA) {
817 ret = sdhci_adma_table_pre(host, data);
818 if (ret) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 sdhci_writel(host, host->adma_addr,
827 SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
832 }
833 } else {
834 int sg_cnt;
835
836 sg_cnt = sdhci_pre_dma_transfer(host, data);
837 if (sg_cnt <= 0) {
838 /*
839 * This only happens when someone fed
840 * us an invalid request.
841 */
842 WARN_ON(1);
843 host->flags &= ~SDHCI_REQ_USE_DMA;
844 } else {
845 WARN_ON(sg_cnt != 1);
846 sdhci_writel(host, sg_dma_address(data->sg),
847 SDHCI_DMA_ADDRESS);
848 }
849 }
850 }
851
852 /*
853 * Always adjust the DMA selection as some controllers
854 * (e.g. JMicron) can't do PIO properly when the selection
855 * is ADMA.
856 */
857 if (host->version >= SDHCI_SPEC_200) {
858 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
859 ctrl &= ~SDHCI_CTRL_DMA_MASK;
860 if ((host->flags & SDHCI_REQ_USE_DMA) &&
861 (host->flags & SDHCI_USE_ADMA)) {
862 if (host->flags & SDHCI_USE_64_BIT_DMA)
863 ctrl |= SDHCI_CTRL_ADMA64;
864 else
865 ctrl |= SDHCI_CTRL_ADMA32;
866 } else {
867 ctrl |= SDHCI_CTRL_SDMA;
868 }
869 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
870 }
871
872 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
873 int flags;
874
875 flags = SG_MITER_ATOMIC;
876 if (host->data->flags & MMC_DATA_READ)
877 flags |= SG_MITER_TO_SG;
878 else
879 flags |= SG_MITER_FROM_SG;
880 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
881 host->blocks = data->blocks;
882 }
883
884 sdhci_set_transfer_irqs(host);
885
886 /* Set the DMA boundary value and block size */
887 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
888 data->blksz), SDHCI_BLOCK_SIZE);
889 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
890 }
891
892 static void sdhci_set_transfer_mode(struct sdhci_host *host,
893 struct mmc_command *cmd)
894 {
895 u16 mode = 0;
896 struct mmc_data *data = cmd->data;
897
898 if (data == NULL) {
899 if (host->quirks2 &
900 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
901 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
902 } else {
903 /* clear Auto CMD settings for no data CMDs */
904 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
905 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
906 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
907 }
908 return;
909 }
910
911 WARN_ON(!host->data);
912
913 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
914 mode = SDHCI_TRNS_BLK_CNT_EN;
915
916 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
917 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
918 /*
919 * If we are sending CMD23, CMD12 never gets sent
920 * on successful completion (so no Auto-CMD12).
921 */
922 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
923 (cmd->opcode != SD_IO_RW_EXTENDED))
924 mode |= SDHCI_TRNS_AUTO_CMD12;
925 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
926 mode |= SDHCI_TRNS_AUTO_CMD23;
927 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
928 }
929 }
930
931 if (data->flags & MMC_DATA_READ)
932 mode |= SDHCI_TRNS_READ;
933 if (host->flags & SDHCI_REQ_USE_DMA)
934 mode |= SDHCI_TRNS_DMA;
935
936 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
937 }
938
939 static void sdhci_finish_data(struct sdhci_host *host)
940 {
941 struct mmc_data *data;
942
943 BUG_ON(!host->data);
944
945 data = host->data;
946 host->data = NULL;
947
948 if (host->flags & SDHCI_REQ_USE_DMA) {
949 if (host->flags & SDHCI_USE_ADMA)
950 sdhci_adma_table_post(host, data);
951 else {
952 if (data->host_cookie == COOKIE_MAPPED) {
953 dma_unmap_sg(mmc_dev(host->mmc),
954 data->sg, data->sg_len,
955 (data->flags & MMC_DATA_READ) ?
956 DMA_FROM_DEVICE : DMA_TO_DEVICE);
957 data->host_cookie = COOKIE_UNMAPPED;
958 }
959 }
960 }
961
962 /*
963 * The specification states that the block count register must
964 * be updated, but it does not specify at what point in the
965 * data flow. That makes the register entirely useless to read
966 * back so we have to assume that nothing made it to the card
967 * in the event of an error.
968 */
969 if (data->error)
970 data->bytes_xfered = 0;
971 else
972 data->bytes_xfered = data->blksz * data->blocks;
973
974 /*
975 * Need to send CMD12 if -
976 * a) open-ended multiblock transfer (no CMD23)
977 * b) error in multiblock transfer
978 */
979 if (data->stop &&
980 (data->error ||
981 !host->mrq->sbc)) {
982
983 /*
984 * The controller needs a reset of internal state machines
985 * upon error conditions.
986 */
987 if (data->error) {
988 sdhci_do_reset(host, SDHCI_RESET_CMD);
989 sdhci_do_reset(host, SDHCI_RESET_DATA);
990 }
991
992 sdhci_send_command(host, data->stop);
993 } else
994 tasklet_schedule(&host->finish_tasklet);
995 }
996
997 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
998 {
999 int flags;
1000 u32 mask;
1001 unsigned long timeout;
1002
1003 WARN_ON(host->cmd);
1004
1005 /* Wait max 10 ms */
1006 timeout = 10;
1007
1008 mask = SDHCI_CMD_INHIBIT;
1009 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1010 mask |= SDHCI_DATA_INHIBIT;
1011
1012 /* We shouldn't wait for data inihibit for stop commands, even
1013 though they might use busy signaling */
1014 if (host->mrq->data && (cmd == host->mrq->data->stop))
1015 mask &= ~SDHCI_DATA_INHIBIT;
1016
1017 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1018 if (timeout == 0) {
1019 pr_err("%s: Controller never released "
1020 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1021 sdhci_dumpregs(host);
1022 cmd->error = -EIO;
1023 tasklet_schedule(&host->finish_tasklet);
1024 return;
1025 }
1026 timeout--;
1027 mdelay(1);
1028 }
1029
1030 timeout = jiffies;
1031 if (!cmd->data && cmd->busy_timeout > 9000)
1032 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1033 else
1034 timeout += 10 * HZ;
1035 mod_timer(&host->timer, timeout);
1036
1037 host->cmd = cmd;
1038 host->busy_handle = 0;
1039
1040 sdhci_prepare_data(host, cmd);
1041
1042 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1043
1044 sdhci_set_transfer_mode(host, cmd);
1045
1046 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1047 pr_err("%s: Unsupported response type!\n",
1048 mmc_hostname(host->mmc));
1049 cmd->error = -EINVAL;
1050 tasklet_schedule(&host->finish_tasklet);
1051 return;
1052 }
1053
1054 if (!(cmd->flags & MMC_RSP_PRESENT))
1055 flags = SDHCI_CMD_RESP_NONE;
1056 else if (cmd->flags & MMC_RSP_136)
1057 flags = SDHCI_CMD_RESP_LONG;
1058 else if (cmd->flags & MMC_RSP_BUSY)
1059 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1060 else
1061 flags = SDHCI_CMD_RESP_SHORT;
1062
1063 if (cmd->flags & MMC_RSP_CRC)
1064 flags |= SDHCI_CMD_CRC;
1065 if (cmd->flags & MMC_RSP_OPCODE)
1066 flags |= SDHCI_CMD_INDEX;
1067
1068 /* CMD19 is special in that the Data Present Select should be set */
1069 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1070 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1071 flags |= SDHCI_CMD_DATA;
1072
1073 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1074 }
1075 EXPORT_SYMBOL_GPL(sdhci_send_command);
1076
1077 static void sdhci_finish_command(struct sdhci_host *host)
1078 {
1079 int i;
1080
1081 BUG_ON(host->cmd == NULL);
1082
1083 if (host->cmd->flags & MMC_RSP_PRESENT) {
1084 if (host->cmd->flags & MMC_RSP_136) {
1085 /* CRC is stripped so we need to do some shifting. */
1086 for (i = 0;i < 4;i++) {
1087 host->cmd->resp[i] = sdhci_readl(host,
1088 SDHCI_RESPONSE + (3-i)*4) << 8;
1089 if (i != 3)
1090 host->cmd->resp[i] |=
1091 sdhci_readb(host,
1092 SDHCI_RESPONSE + (3-i)*4-1);
1093 }
1094 } else {
1095 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1096 }
1097 }
1098
1099 host->cmd->error = 0;
1100
1101 /* Finished CMD23, now send actual command. */
1102 if (host->cmd == host->mrq->sbc) {
1103 host->cmd = NULL;
1104 sdhci_send_command(host, host->mrq->cmd);
1105 } else {
1106
1107 /* Processed actual command. */
1108 if (host->data && host->data_early)
1109 sdhci_finish_data(host);
1110
1111 if (!host->cmd->data)
1112 tasklet_schedule(&host->finish_tasklet);
1113
1114 host->cmd = NULL;
1115 }
1116 }
1117
1118 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1119 {
1120 u16 preset = 0;
1121
1122 switch (host->timing) {
1123 case MMC_TIMING_UHS_SDR12:
1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1125 break;
1126 case MMC_TIMING_UHS_SDR25:
1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1128 break;
1129 case MMC_TIMING_UHS_SDR50:
1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1131 break;
1132 case MMC_TIMING_UHS_SDR104:
1133 case MMC_TIMING_MMC_HS200:
1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1135 break;
1136 case MMC_TIMING_UHS_DDR50:
1137 case MMC_TIMING_MMC_DDR52:
1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1139 break;
1140 case MMC_TIMING_MMC_HS400:
1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1142 break;
1143 default:
1144 pr_warn("%s: Invalid UHS-I mode selected\n",
1145 mmc_hostname(host->mmc));
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1147 break;
1148 }
1149 return preset;
1150 }
1151
1152 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1153 {
1154 int div = 0; /* Initialized for compiler warning */
1155 int real_div = div, clk_mul = 1;
1156 u16 clk = 0;
1157 unsigned long timeout;
1158 bool switch_base_clk = false;
1159
1160 host->mmc->actual_clock = 0;
1161
1162 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1163
1164 if (clock == 0)
1165 return;
1166
1167 if (host->version >= SDHCI_SPEC_300) {
1168 if (host->preset_enabled) {
1169 u16 pre_val;
1170
1171 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1172 pre_val = sdhci_get_preset_value(host);
1173 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1174 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1175 if (host->clk_mul &&
1176 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1177 clk = SDHCI_PROG_CLOCK_MODE;
1178 real_div = div + 1;
1179 clk_mul = host->clk_mul;
1180 } else {
1181 real_div = max_t(int, 1, div << 1);
1182 }
1183 goto clock_set;
1184 }
1185
1186 /*
1187 * Check if the Host Controller supports Programmable Clock
1188 * Mode.
1189 */
1190 if (host->clk_mul) {
1191 for (div = 1; div <= 1024; div++) {
1192 if ((host->max_clk * host->clk_mul / div)
1193 <= clock)
1194 break;
1195 }
1196 if ((host->max_clk * host->clk_mul / div) <= clock) {
1197 /*
1198 * Set Programmable Clock Mode in the Clock
1199 * Control register.
1200 */
1201 clk = SDHCI_PROG_CLOCK_MODE;
1202 real_div = div;
1203 clk_mul = host->clk_mul;
1204 div--;
1205 } else {
1206 /*
1207 * Divisor can be too small to reach clock
1208 * speed requirement. Then use the base clock.
1209 */
1210 switch_base_clk = true;
1211 }
1212 }
1213
1214 if (!host->clk_mul || switch_base_clk) {
1215 /* Version 3.00 divisors must be a multiple of 2. */
1216 if (host->max_clk <= clock)
1217 div = 1;
1218 else {
1219 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1220 div += 2) {
1221 if ((host->max_clk / div) <= clock)
1222 break;
1223 }
1224 }
1225 real_div = div;
1226 div >>= 1;
1227 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1228 && !div && host->max_clk <= 25000000)
1229 div = 1;
1230 }
1231 } else {
1232 /* Version 2.00 divisors must be a power of 2. */
1233 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1234 if ((host->max_clk / div) <= clock)
1235 break;
1236 }
1237 real_div = div;
1238 div >>= 1;
1239 }
1240
1241 clock_set:
1242 if (real_div)
1243 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1244 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1245 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1246 << SDHCI_DIVIDER_HI_SHIFT;
1247 clk |= SDHCI_CLOCK_INT_EN;
1248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1249
1250 /* Wait max 20 ms */
1251 timeout = 20;
1252 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1253 & SDHCI_CLOCK_INT_STABLE)) {
1254 if (timeout == 0) {
1255 pr_err("%s: Internal clock never "
1256 "stabilised.\n", mmc_hostname(host->mmc));
1257 sdhci_dumpregs(host);
1258 return;
1259 }
1260 timeout--;
1261 mdelay(1);
1262 }
1263
1264 clk |= SDHCI_CLOCK_CARD_EN;
1265 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1266 }
1267 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1268
1269 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1270 unsigned short vdd)
1271 {
1272 struct mmc_host *mmc = host->mmc;
1273 u8 pwr = 0;
1274
1275 if (!IS_ERR(mmc->supply.vmmc)) {
1276 spin_unlock_irq(&host->lock);
1277 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1278 spin_lock_irq(&host->lock);
1279
1280 if (mode != MMC_POWER_OFF)
1281 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1282 else
1283 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1284
1285 return;
1286 }
1287
1288 if (mode != MMC_POWER_OFF) {
1289 switch (1 << vdd) {
1290 case MMC_VDD_165_195:
1291 pwr = SDHCI_POWER_180;
1292 break;
1293 case MMC_VDD_29_30:
1294 case MMC_VDD_30_31:
1295 pwr = SDHCI_POWER_300;
1296 break;
1297 case MMC_VDD_32_33:
1298 case MMC_VDD_33_34:
1299 pwr = SDHCI_POWER_330;
1300 break;
1301 default:
1302 BUG();
1303 }
1304 }
1305
1306 if (host->pwr == pwr)
1307 return;
1308
1309 host->pwr = pwr;
1310
1311 if (pwr == 0) {
1312 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1313 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1314 sdhci_runtime_pm_bus_off(host);
1315 vdd = 0;
1316 } else {
1317 /*
1318 * Spec says that we should clear the power reg before setting
1319 * a new value. Some controllers don't seem to like this though.
1320 */
1321 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1322 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1323
1324 /*
1325 * At least the Marvell CaFe chip gets confused if we set the
1326 * voltage and set turn on power at the same time, so set the
1327 * voltage first.
1328 */
1329 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1330 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1331
1332 pwr |= SDHCI_POWER_ON;
1333
1334 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1335
1336 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1337 sdhci_runtime_pm_bus_on(host);
1338
1339 /*
1340 * Some controllers need an extra 10ms delay of 10ms before
1341 * they can apply clock after applying power
1342 */
1343 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1344 mdelay(10);
1345 }
1346 }
1347
1348 /*****************************************************************************\
1349 * *
1350 * MMC callbacks *
1351 * *
1352 \*****************************************************************************/
1353
1354 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1355 {
1356 struct sdhci_host *host;
1357 int present;
1358 unsigned long flags;
1359
1360 host = mmc_priv(mmc);
1361
1362 sdhci_runtime_pm_get(host);
1363
1364 /* Firstly check card presence */
1365 present = sdhci_do_get_cd(host);
1366
1367 spin_lock_irqsave(&host->lock, flags);
1368
1369 WARN_ON(host->mrq != NULL);
1370
1371 #ifndef SDHCI_USE_LEDS_CLASS
1372 sdhci_activate_led(host);
1373 #endif
1374
1375 /*
1376 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1377 * requests if Auto-CMD12 is enabled.
1378 */
1379 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1380 if (mrq->stop) {
1381 mrq->data->stop = NULL;
1382 mrq->stop = NULL;
1383 }
1384 }
1385
1386 host->mrq = mrq;
1387
1388 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1389 host->mrq->cmd->error = -ENOMEDIUM;
1390 tasklet_schedule(&host->finish_tasklet);
1391 } else {
1392 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1393 sdhci_send_command(host, mrq->sbc);
1394 else
1395 sdhci_send_command(host, mrq->cmd);
1396 }
1397
1398 mmiowb();
1399 spin_unlock_irqrestore(&host->lock, flags);
1400 }
1401
1402 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1403 {
1404 u8 ctrl;
1405
1406 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1407 if (width == MMC_BUS_WIDTH_8) {
1408 ctrl &= ~SDHCI_CTRL_4BITBUS;
1409 if (host->version >= SDHCI_SPEC_300)
1410 ctrl |= SDHCI_CTRL_8BITBUS;
1411 } else {
1412 if (host->version >= SDHCI_SPEC_300)
1413 ctrl &= ~SDHCI_CTRL_8BITBUS;
1414 if (width == MMC_BUS_WIDTH_4)
1415 ctrl |= SDHCI_CTRL_4BITBUS;
1416 else
1417 ctrl &= ~SDHCI_CTRL_4BITBUS;
1418 }
1419 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1420 }
1421 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1422
1423 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1424 {
1425 u16 ctrl_2;
1426
1427 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1428 /* Select Bus Speed Mode for host */
1429 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1430 if ((timing == MMC_TIMING_MMC_HS200) ||
1431 (timing == MMC_TIMING_UHS_SDR104))
1432 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1433 else if (timing == MMC_TIMING_UHS_SDR12)
1434 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1435 else if (timing == MMC_TIMING_UHS_SDR25)
1436 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1437 else if (timing == MMC_TIMING_UHS_SDR50)
1438 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1439 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1440 (timing == MMC_TIMING_MMC_DDR52))
1441 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1442 else if (timing == MMC_TIMING_MMC_HS400)
1443 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1444 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1445 }
1446 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1447
1448 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1449 {
1450 unsigned long flags;
1451 u8 ctrl;
1452 struct mmc_host *mmc = host->mmc;
1453
1454 spin_lock_irqsave(&host->lock, flags);
1455
1456 if (host->flags & SDHCI_DEVICE_DEAD) {
1457 spin_unlock_irqrestore(&host->lock, flags);
1458 if (!IS_ERR(mmc->supply.vmmc) &&
1459 ios->power_mode == MMC_POWER_OFF)
1460 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1461 return;
1462 }
1463
1464 /*
1465 * Reset the chip on each power off.
1466 * Should clear out any weird states.
1467 */
1468 if (ios->power_mode == MMC_POWER_OFF) {
1469 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1470 sdhci_reinit(host);
1471 }
1472
1473 if (host->version >= SDHCI_SPEC_300 &&
1474 (ios->power_mode == MMC_POWER_UP) &&
1475 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1476 sdhci_enable_preset_value(host, false);
1477
1478 if (!ios->clock || ios->clock != host->clock) {
1479 host->ops->set_clock(host, ios->clock);
1480 host->clock = ios->clock;
1481
1482 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1483 host->clock) {
1484 host->timeout_clk = host->mmc->actual_clock ?
1485 host->mmc->actual_clock / 1000 :
1486 host->clock / 1000;
1487 host->mmc->max_busy_timeout =
1488 host->ops->get_max_timeout_count ?
1489 host->ops->get_max_timeout_count(host) :
1490 1 << 27;
1491 host->mmc->max_busy_timeout /= host->timeout_clk;
1492 }
1493 }
1494
1495 sdhci_set_power(host, ios->power_mode, ios->vdd);
1496
1497 if (host->ops->platform_send_init_74_clocks)
1498 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1499
1500 host->ops->set_bus_width(host, ios->bus_width);
1501
1502 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1503
1504 if ((ios->timing == MMC_TIMING_SD_HS ||
1505 ios->timing == MMC_TIMING_MMC_HS)
1506 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1507 ctrl |= SDHCI_CTRL_HISPD;
1508 else
1509 ctrl &= ~SDHCI_CTRL_HISPD;
1510
1511 if (host->version >= SDHCI_SPEC_300) {
1512 u16 clk, ctrl_2;
1513
1514 /* In case of UHS-I modes, set High Speed Enable */
1515 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1516 (ios->timing == MMC_TIMING_MMC_HS200) ||
1517 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1518 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1519 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1520 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1521 (ios->timing == MMC_TIMING_UHS_SDR25))
1522 ctrl |= SDHCI_CTRL_HISPD;
1523
1524 if (!host->preset_enabled) {
1525 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1526 /*
1527 * We only need to set Driver Strength if the
1528 * preset value enable is not set.
1529 */
1530 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1531 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1532 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1533 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1534 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1535 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1536 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1537 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1538 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1539 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1540 else {
1541 pr_warn("%s: invalid driver type, default to "
1542 "driver type B\n", mmc_hostname(mmc));
1543 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1544 }
1545
1546 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1547 } else {
1548 /*
1549 * According to SDHC Spec v3.00, if the Preset Value
1550 * Enable in the Host Control 2 register is set, we
1551 * need to reset SD Clock Enable before changing High
1552 * Speed Enable to avoid generating clock gliches.
1553 */
1554
1555 /* Reset SD Clock Enable */
1556 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1557 clk &= ~SDHCI_CLOCK_CARD_EN;
1558 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1559
1560 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1561
1562 /* Re-enable SD Clock */
1563 host->ops->set_clock(host, host->clock);
1564 }
1565
1566 /* Reset SD Clock Enable */
1567 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1568 clk &= ~SDHCI_CLOCK_CARD_EN;
1569 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1570
1571 host->ops->set_uhs_signaling(host, ios->timing);
1572 host->timing = ios->timing;
1573
1574 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1575 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1576 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1577 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1578 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1579 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1580 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1581 u16 preset;
1582
1583 sdhci_enable_preset_value(host, true);
1584 preset = sdhci_get_preset_value(host);
1585 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1586 >> SDHCI_PRESET_DRV_SHIFT;
1587 }
1588
1589 /* Re-enable SD Clock */
1590 host->ops->set_clock(host, host->clock);
1591 } else
1592 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1593
1594 /*
1595 * Some (ENE) controllers go apeshit on some ios operation,
1596 * signalling timeout and CRC errors even on CMD0. Resetting
1597 * it on each ios seems to solve the problem.
1598 */
1599 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1600 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1601
1602 mmiowb();
1603 spin_unlock_irqrestore(&host->lock, flags);
1604 }
1605
1606 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1607 {
1608 struct sdhci_host *host = mmc_priv(mmc);
1609
1610 sdhci_runtime_pm_get(host);
1611 sdhci_do_set_ios(host, ios);
1612 sdhci_runtime_pm_put(host);
1613 }
1614
1615 static int sdhci_do_get_cd(struct sdhci_host *host)
1616 {
1617 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1618
1619 if (host->flags & SDHCI_DEVICE_DEAD)
1620 return 0;
1621
1622 /* If nonremovable, assume that the card is always present. */
1623 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1624 return 1;
1625
1626 /*
1627 * Try slot gpio detect, if defined it take precedence
1628 * over build in controller functionality
1629 */
1630 if (!IS_ERR_VALUE(gpio_cd))
1631 return !!gpio_cd;
1632
1633 /* If polling, assume that the card is always present. */
1634 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1635 return 1;
1636
1637 /* Host native card detect */
1638 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1639 }
1640
1641 static int sdhci_get_cd(struct mmc_host *mmc)
1642 {
1643 struct sdhci_host *host = mmc_priv(mmc);
1644 int ret;
1645
1646 sdhci_runtime_pm_get(host);
1647 ret = sdhci_do_get_cd(host);
1648 sdhci_runtime_pm_put(host);
1649 return ret;
1650 }
1651
1652 static int sdhci_check_ro(struct sdhci_host *host)
1653 {
1654 unsigned long flags;
1655 int is_readonly;
1656
1657 spin_lock_irqsave(&host->lock, flags);
1658
1659 if (host->flags & SDHCI_DEVICE_DEAD)
1660 is_readonly = 0;
1661 else if (host->ops->get_ro)
1662 is_readonly = host->ops->get_ro(host);
1663 else
1664 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1665 & SDHCI_WRITE_PROTECT);
1666
1667 spin_unlock_irqrestore(&host->lock, flags);
1668
1669 /* This quirk needs to be replaced by a callback-function later */
1670 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1671 !is_readonly : is_readonly;
1672 }
1673
1674 #define SAMPLE_COUNT 5
1675
1676 static int sdhci_do_get_ro(struct sdhci_host *host)
1677 {
1678 int i, ro_count;
1679
1680 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1681 return sdhci_check_ro(host);
1682
1683 ro_count = 0;
1684 for (i = 0; i < SAMPLE_COUNT; i++) {
1685 if (sdhci_check_ro(host)) {
1686 if (++ro_count > SAMPLE_COUNT / 2)
1687 return 1;
1688 }
1689 msleep(30);
1690 }
1691 return 0;
1692 }
1693
1694 static void sdhci_hw_reset(struct mmc_host *mmc)
1695 {
1696 struct sdhci_host *host = mmc_priv(mmc);
1697
1698 if (host->ops && host->ops->hw_reset)
1699 host->ops->hw_reset(host);
1700 }
1701
1702 static int sdhci_get_ro(struct mmc_host *mmc)
1703 {
1704 struct sdhci_host *host = mmc_priv(mmc);
1705 int ret;
1706
1707 sdhci_runtime_pm_get(host);
1708 ret = sdhci_do_get_ro(host);
1709 sdhci_runtime_pm_put(host);
1710 return ret;
1711 }
1712
1713 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1714 {
1715 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1716 if (enable)
1717 host->ier |= SDHCI_INT_CARD_INT;
1718 else
1719 host->ier &= ~SDHCI_INT_CARD_INT;
1720
1721 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1722 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1723 mmiowb();
1724 }
1725 }
1726
1727 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1728 {
1729 struct sdhci_host *host = mmc_priv(mmc);
1730 unsigned long flags;
1731
1732 sdhci_runtime_pm_get(host);
1733
1734 spin_lock_irqsave(&host->lock, flags);
1735 if (enable)
1736 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1737 else
1738 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1739
1740 sdhci_enable_sdio_irq_nolock(host, enable);
1741 spin_unlock_irqrestore(&host->lock, flags);
1742
1743 sdhci_runtime_pm_put(host);
1744 }
1745
1746 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1747 struct mmc_ios *ios)
1748 {
1749 struct mmc_host *mmc = host->mmc;
1750 u16 ctrl;
1751 int ret;
1752
1753 /*
1754 * Signal Voltage Switching is only applicable for Host Controllers
1755 * v3.00 and above.
1756 */
1757 if (host->version < SDHCI_SPEC_300)
1758 return 0;
1759
1760 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1761
1762 switch (ios->signal_voltage) {
1763 case MMC_SIGNAL_VOLTAGE_330:
1764 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1765 ctrl &= ~SDHCI_CTRL_VDD_180;
1766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1767
1768 if (!IS_ERR(mmc->supply.vqmmc)) {
1769 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1770 3600000);
1771 if (ret) {
1772 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1773 mmc_hostname(mmc));
1774 return -EIO;
1775 }
1776 }
1777 /* Wait for 5ms */
1778 usleep_range(5000, 5500);
1779
1780 /* 3.3V regulator output should be stable within 5 ms */
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782 if (!(ctrl & SDHCI_CTRL_VDD_180))
1783 return 0;
1784
1785 pr_warn("%s: 3.3V regulator output did not became stable\n",
1786 mmc_hostname(mmc));
1787
1788 return -EAGAIN;
1789 case MMC_SIGNAL_VOLTAGE_180:
1790 if (!IS_ERR(mmc->supply.vqmmc)) {
1791 ret = regulator_set_voltage(mmc->supply.vqmmc,
1792 1700000, 1950000);
1793 if (ret) {
1794 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1795 mmc_hostname(mmc));
1796 return -EIO;
1797 }
1798 }
1799
1800 /*
1801 * Enable 1.8V Signal Enable in the Host Control2
1802 * register
1803 */
1804 ctrl |= SDHCI_CTRL_VDD_180;
1805 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1806
1807 /* Some controller need to do more when switching */
1808 if (host->ops->voltage_switch)
1809 host->ops->voltage_switch(host);
1810
1811 /* 1.8V regulator output should be stable within 5 ms */
1812 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1813 if (ctrl & SDHCI_CTRL_VDD_180)
1814 return 0;
1815
1816 pr_warn("%s: 1.8V regulator output did not became stable\n",
1817 mmc_hostname(mmc));
1818
1819 return -EAGAIN;
1820 case MMC_SIGNAL_VOLTAGE_120:
1821 if (!IS_ERR(mmc->supply.vqmmc)) {
1822 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1823 1300000);
1824 if (ret) {
1825 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1826 mmc_hostname(mmc));
1827 return -EIO;
1828 }
1829 }
1830 return 0;
1831 default:
1832 /* No signal voltage switch required */
1833 return 0;
1834 }
1835 }
1836
1837 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1838 struct mmc_ios *ios)
1839 {
1840 struct sdhci_host *host = mmc_priv(mmc);
1841 int err;
1842
1843 if (host->version < SDHCI_SPEC_300)
1844 return 0;
1845 sdhci_runtime_pm_get(host);
1846 err = sdhci_do_start_signal_voltage_switch(host, ios);
1847 sdhci_runtime_pm_put(host);
1848 return err;
1849 }
1850
1851 static int sdhci_card_busy(struct mmc_host *mmc)
1852 {
1853 struct sdhci_host *host = mmc_priv(mmc);
1854 u32 present_state;
1855
1856 sdhci_runtime_pm_get(host);
1857 /* Check whether DAT[3:0] is 0000 */
1858 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1859 sdhci_runtime_pm_put(host);
1860
1861 return !(present_state & SDHCI_DATA_LVL_MASK);
1862 }
1863
1864 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1865 {
1866 struct sdhci_host *host = mmc_priv(mmc);
1867 unsigned long flags;
1868
1869 spin_lock_irqsave(&host->lock, flags);
1870 host->flags |= SDHCI_HS400_TUNING;
1871 spin_unlock_irqrestore(&host->lock, flags);
1872
1873 return 0;
1874 }
1875
1876 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1877 {
1878 struct sdhci_host *host = mmc_priv(mmc);
1879 u16 ctrl;
1880 int tuning_loop_counter = MAX_TUNING_LOOP;
1881 int err = 0;
1882 unsigned long flags;
1883 unsigned int tuning_count = 0;
1884 bool hs400_tuning;
1885
1886 sdhci_runtime_pm_get(host);
1887 spin_lock_irqsave(&host->lock, flags);
1888
1889 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1890 host->flags &= ~SDHCI_HS400_TUNING;
1891
1892 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1893 tuning_count = host->tuning_count;
1894
1895 /*
1896 * The Host Controller needs tuning only in case of SDR104 mode
1897 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1898 * Capabilities register.
1899 * If the Host Controller supports the HS200 mode then the
1900 * tuning function has to be executed.
1901 */
1902 switch (host->timing) {
1903 /* HS400 tuning is done in HS200 mode */
1904 case MMC_TIMING_MMC_HS400:
1905 err = -EINVAL;
1906 goto out_unlock;
1907
1908 case MMC_TIMING_MMC_HS200:
1909 /*
1910 * Periodic re-tuning for HS400 is not expected to be needed, so
1911 * disable it here.
1912 */
1913 if (hs400_tuning)
1914 tuning_count = 0;
1915 break;
1916
1917 case MMC_TIMING_UHS_SDR104:
1918 break;
1919
1920 case MMC_TIMING_UHS_SDR50:
1921 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1922 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1923 break;
1924 /* FALLTHROUGH */
1925
1926 default:
1927 goto out_unlock;
1928 }
1929
1930 if (host->ops->platform_execute_tuning) {
1931 spin_unlock_irqrestore(&host->lock, flags);
1932 err = host->ops->platform_execute_tuning(host, opcode);
1933 sdhci_runtime_pm_put(host);
1934 return err;
1935 }
1936
1937 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1938 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1939 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1940 ctrl |= SDHCI_CTRL_TUNED_CLK;
1941 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1942
1943 /*
1944 * As per the Host Controller spec v3.00, tuning command
1945 * generates Buffer Read Ready interrupt, so enable that.
1946 *
1947 * Note: The spec clearly says that when tuning sequence
1948 * is being performed, the controller does not generate
1949 * interrupts other than Buffer Read Ready interrupt. But
1950 * to make sure we don't hit a controller bug, we _only_
1951 * enable Buffer Read Ready interrupt here.
1952 */
1953 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1954 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1955
1956 /*
1957 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1958 * of loops reaches 40 times or a timeout of 150ms occurs.
1959 */
1960 do {
1961 struct mmc_command cmd = {0};
1962 struct mmc_request mrq = {NULL};
1963
1964 cmd.opcode = opcode;
1965 cmd.arg = 0;
1966 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1967 cmd.retries = 0;
1968 cmd.data = NULL;
1969 cmd.error = 0;
1970
1971 if (tuning_loop_counter-- == 0)
1972 break;
1973
1974 mrq.cmd = &cmd;
1975 host->mrq = &mrq;
1976
1977 /*
1978 * In response to CMD19, the card sends 64 bytes of tuning
1979 * block to the Host Controller. So we set the block size
1980 * to 64 here.
1981 */
1982 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1983 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1984 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1985 SDHCI_BLOCK_SIZE);
1986 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1987 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1988 SDHCI_BLOCK_SIZE);
1989 } else {
1990 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1991 SDHCI_BLOCK_SIZE);
1992 }
1993
1994 /*
1995 * The tuning block is sent by the card to the host controller.
1996 * So we set the TRNS_READ bit in the Transfer Mode register.
1997 * This also takes care of setting DMA Enable and Multi Block
1998 * Select in the same register to 0.
1999 */
2000 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2001
2002 sdhci_send_command(host, &cmd);
2003
2004 host->cmd = NULL;
2005 host->mrq = NULL;
2006
2007 spin_unlock_irqrestore(&host->lock, flags);
2008 /* Wait for Buffer Read Ready interrupt */
2009 wait_event_interruptible_timeout(host->buf_ready_int,
2010 (host->tuning_done == 1),
2011 msecs_to_jiffies(50));
2012 spin_lock_irqsave(&host->lock, flags);
2013
2014 if (!host->tuning_done) {
2015 pr_info(DRIVER_NAME ": Timeout waiting for "
2016 "Buffer Read Ready interrupt during tuning "
2017 "procedure, falling back to fixed sampling "
2018 "clock\n");
2019 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2020 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2021 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2022 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2023
2024 err = -EIO;
2025 goto out;
2026 }
2027
2028 host->tuning_done = 0;
2029
2030 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2031
2032 /* eMMC spec does not require a delay between tuning cycles */
2033 if (opcode == MMC_SEND_TUNING_BLOCK)
2034 mdelay(1);
2035 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2036
2037 /*
2038 * The Host Driver has exhausted the maximum number of loops allowed,
2039 * so use fixed sampling frequency.
2040 */
2041 if (tuning_loop_counter < 0) {
2042 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2043 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2044 }
2045 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2046 pr_info(DRIVER_NAME ": Tuning procedure"
2047 " failed, falling back to fixed sampling"
2048 " clock\n");
2049 err = -EIO;
2050 }
2051
2052 out:
2053 if (tuning_count) {
2054 /*
2055 * In case tuning fails, host controllers which support
2056 * re-tuning can try tuning again at a later time, when the
2057 * re-tuning timer expires. So for these controllers, we
2058 * return 0. Since there might be other controllers who do not
2059 * have this capability, we return error for them.
2060 */
2061 err = 0;
2062 }
2063
2064 host->mmc->retune_period = err ? 0 : tuning_count;
2065
2066 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2067 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2068 out_unlock:
2069 spin_unlock_irqrestore(&host->lock, flags);
2070 sdhci_runtime_pm_put(host);
2071
2072 return err;
2073 }
2074
2075 static int sdhci_select_drive_strength(struct mmc_card *card,
2076 unsigned int max_dtr, int host_drv,
2077 int card_drv, int *drv_type)
2078 {
2079 struct sdhci_host *host = mmc_priv(card->host);
2080
2081 if (!host->ops->select_drive_strength)
2082 return 0;
2083
2084 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2085 card_drv, drv_type);
2086 }
2087
2088 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2089 {
2090 /* Host Controller v3.00 defines preset value registers */
2091 if (host->version < SDHCI_SPEC_300)
2092 return;
2093
2094 /*
2095 * We only enable or disable Preset Value if they are not already
2096 * enabled or disabled respectively. Otherwise, we bail out.
2097 */
2098 if (host->preset_enabled != enable) {
2099 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2100
2101 if (enable)
2102 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2103 else
2104 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2105
2106 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2107
2108 if (enable)
2109 host->flags |= SDHCI_PV_ENABLED;
2110 else
2111 host->flags &= ~SDHCI_PV_ENABLED;
2112
2113 host->preset_enabled = enable;
2114 }
2115 }
2116
2117 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2118 int err)
2119 {
2120 struct sdhci_host *host = mmc_priv(mmc);
2121 struct mmc_data *data = mrq->data;
2122
2123 if (host->flags & SDHCI_REQ_USE_DMA) {
2124 if (data->host_cookie == COOKIE_GIVEN ||
2125 data->host_cookie == COOKIE_MAPPED)
2126 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2127 data->flags & MMC_DATA_WRITE ?
2128 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2129 data->host_cookie = COOKIE_UNMAPPED;
2130 }
2131 }
2132
2133 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2134 struct mmc_data *data)
2135 {
2136 int sg_count;
2137
2138 if (data->host_cookie == COOKIE_MAPPED) {
2139 data->host_cookie = COOKIE_GIVEN;
2140 return data->sg_count;
2141 }
2142
2143 WARN_ON(data->host_cookie == COOKIE_GIVEN);
2144
2145 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2146 data->flags & MMC_DATA_WRITE ?
2147 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2148
2149 if (sg_count == 0)
2150 return -ENOSPC;
2151
2152 data->sg_count = sg_count;
2153 data->host_cookie = COOKIE_MAPPED;
2154
2155 return sg_count;
2156 }
2157
2158 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2159 bool is_first_req)
2160 {
2161 struct sdhci_host *host = mmc_priv(mmc);
2162
2163 mrq->data->host_cookie = COOKIE_UNMAPPED;
2164
2165 if (host->flags & SDHCI_REQ_USE_DMA)
2166 sdhci_pre_dma_transfer(host, mrq->data);
2167 }
2168
2169 static void sdhci_card_event(struct mmc_host *mmc)
2170 {
2171 struct sdhci_host *host = mmc_priv(mmc);
2172 unsigned long flags;
2173 int present;
2174
2175 /* First check if client has provided their own card event */
2176 if (host->ops->card_event)
2177 host->ops->card_event(host);
2178
2179 present = sdhci_do_get_cd(host);
2180
2181 spin_lock_irqsave(&host->lock, flags);
2182
2183 /* Check host->mrq first in case we are runtime suspended */
2184 if (host->mrq && !present) {
2185 pr_err("%s: Card removed during transfer!\n",
2186 mmc_hostname(host->mmc));
2187 pr_err("%s: Resetting controller.\n",
2188 mmc_hostname(host->mmc));
2189
2190 sdhci_do_reset(host, SDHCI_RESET_CMD);
2191 sdhci_do_reset(host, SDHCI_RESET_DATA);
2192
2193 host->mrq->cmd->error = -ENOMEDIUM;
2194 tasklet_schedule(&host->finish_tasklet);
2195 }
2196
2197 spin_unlock_irqrestore(&host->lock, flags);
2198 }
2199
2200 static const struct mmc_host_ops sdhci_ops = {
2201 .request = sdhci_request,
2202 .post_req = sdhci_post_req,
2203 .pre_req = sdhci_pre_req,
2204 .set_ios = sdhci_set_ios,
2205 .get_cd = sdhci_get_cd,
2206 .get_ro = sdhci_get_ro,
2207 .hw_reset = sdhci_hw_reset,
2208 .enable_sdio_irq = sdhci_enable_sdio_irq,
2209 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2210 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2211 .execute_tuning = sdhci_execute_tuning,
2212 .select_drive_strength = sdhci_select_drive_strength,
2213 .card_event = sdhci_card_event,
2214 .card_busy = sdhci_card_busy,
2215 };
2216
2217 /*****************************************************************************\
2218 * *
2219 * Tasklets *
2220 * *
2221 \*****************************************************************************/
2222
2223 static void sdhci_tasklet_finish(unsigned long param)
2224 {
2225 struct sdhci_host *host;
2226 unsigned long flags;
2227 struct mmc_request *mrq;
2228
2229 host = (struct sdhci_host*)param;
2230
2231 spin_lock_irqsave(&host->lock, flags);
2232
2233 /*
2234 * If this tasklet gets rescheduled while running, it will
2235 * be run again afterwards but without any active request.
2236 */
2237 if (!host->mrq) {
2238 spin_unlock_irqrestore(&host->lock, flags);
2239 return;
2240 }
2241
2242 del_timer(&host->timer);
2243
2244 mrq = host->mrq;
2245
2246 /*
2247 * The controller needs a reset of internal state machines
2248 * upon error conditions.
2249 */
2250 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2251 ((mrq->cmd && mrq->cmd->error) ||
2252 (mrq->sbc && mrq->sbc->error) ||
2253 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2254 (mrq->data->stop && mrq->data->stop->error))) ||
2255 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2256
2257 /* Some controllers need this kick or reset won't work here */
2258 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2259 /* This is to force an update */
2260 host->ops->set_clock(host, host->clock);
2261
2262 /* Spec says we should do both at the same time, but Ricoh
2263 controllers do not like that. */
2264 sdhci_do_reset(host, SDHCI_RESET_CMD);
2265 sdhci_do_reset(host, SDHCI_RESET_DATA);
2266 }
2267
2268 host->mrq = NULL;
2269 host->cmd = NULL;
2270 host->data = NULL;
2271
2272 #ifndef SDHCI_USE_LEDS_CLASS
2273 sdhci_deactivate_led(host);
2274 #endif
2275
2276 mmiowb();
2277 spin_unlock_irqrestore(&host->lock, flags);
2278
2279 mmc_request_done(host->mmc, mrq);
2280 sdhci_runtime_pm_put(host);
2281 }
2282
2283 static void sdhci_timeout_timer(unsigned long data)
2284 {
2285 struct sdhci_host *host;
2286 unsigned long flags;
2287
2288 host = (struct sdhci_host*)data;
2289
2290 spin_lock_irqsave(&host->lock, flags);
2291
2292 if (host->mrq) {
2293 pr_err("%s: Timeout waiting for hardware "
2294 "interrupt.\n", mmc_hostname(host->mmc));
2295 sdhci_dumpregs(host);
2296
2297 if (host->data) {
2298 host->data->error = -ETIMEDOUT;
2299 sdhci_finish_data(host);
2300 } else {
2301 if (host->cmd)
2302 host->cmd->error = -ETIMEDOUT;
2303 else
2304 host->mrq->cmd->error = -ETIMEDOUT;
2305
2306 tasklet_schedule(&host->finish_tasklet);
2307 }
2308 }
2309
2310 mmiowb();
2311 spin_unlock_irqrestore(&host->lock, flags);
2312 }
2313
2314 /*****************************************************************************\
2315 * *
2316 * Interrupt handling *
2317 * *
2318 \*****************************************************************************/
2319
2320 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2321 {
2322 BUG_ON(intmask == 0);
2323
2324 if (!host->cmd) {
2325 pr_err("%s: Got command interrupt 0x%08x even "
2326 "though no command operation was in progress.\n",
2327 mmc_hostname(host->mmc), (unsigned)intmask);
2328 sdhci_dumpregs(host);
2329 return;
2330 }
2331
2332 if (intmask & SDHCI_INT_TIMEOUT)
2333 host->cmd->error = -ETIMEDOUT;
2334 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2335 SDHCI_INT_INDEX))
2336 host->cmd->error = -EILSEQ;
2337
2338 if (host->cmd->error) {
2339 tasklet_schedule(&host->finish_tasklet);
2340 return;
2341 }
2342
2343 /*
2344 * The host can send and interrupt when the busy state has
2345 * ended, allowing us to wait without wasting CPU cycles.
2346 * Unfortunately this is overloaded on the "data complete"
2347 * interrupt, so we need to take some care when handling
2348 * it.
2349 *
2350 * Note: The 1.0 specification is a bit ambiguous about this
2351 * feature so there might be some problems with older
2352 * controllers.
2353 */
2354 if (host->cmd->flags & MMC_RSP_BUSY) {
2355 if (host->cmd->data)
2356 DBG("Cannot wait for busy signal when also "
2357 "doing a data transfer");
2358 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2359 && !host->busy_handle) {
2360 /* Mark that command complete before busy is ended */
2361 host->busy_handle = 1;
2362 return;
2363 }
2364
2365 /* The controller does not support the end-of-busy IRQ,
2366 * fall through and take the SDHCI_INT_RESPONSE */
2367 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2368 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2369 *mask &= ~SDHCI_INT_DATA_END;
2370 }
2371
2372 if (intmask & SDHCI_INT_RESPONSE)
2373 sdhci_finish_command(host);
2374 }
2375
2376 #ifdef CONFIG_MMC_DEBUG
2377 static void sdhci_adma_show_error(struct sdhci_host *host)
2378 {
2379 const char *name = mmc_hostname(host->mmc);
2380 void *desc = host->adma_table;
2381
2382 sdhci_dumpregs(host);
2383
2384 while (true) {
2385 struct sdhci_adma2_64_desc *dma_desc = desc;
2386
2387 if (host->flags & SDHCI_USE_64_BIT_DMA)
2388 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2389 name, desc, le32_to_cpu(dma_desc->addr_hi),
2390 le32_to_cpu(dma_desc->addr_lo),
2391 le16_to_cpu(dma_desc->len),
2392 le16_to_cpu(dma_desc->cmd));
2393 else
2394 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2395 name, desc, le32_to_cpu(dma_desc->addr_lo),
2396 le16_to_cpu(dma_desc->len),
2397 le16_to_cpu(dma_desc->cmd));
2398
2399 desc += host->desc_sz;
2400
2401 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2402 break;
2403 }
2404 }
2405 #else
2406 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2407 #endif
2408
2409 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2410 {
2411 u32 command;
2412 BUG_ON(intmask == 0);
2413
2414 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2415 if (intmask & SDHCI_INT_DATA_AVAIL) {
2416 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2417 if (command == MMC_SEND_TUNING_BLOCK ||
2418 command == MMC_SEND_TUNING_BLOCK_HS200) {
2419 host->tuning_done = 1;
2420 wake_up(&host->buf_ready_int);
2421 return;
2422 }
2423 }
2424
2425 if (!host->data) {
2426 /*
2427 * The "data complete" interrupt is also used to
2428 * indicate that a busy state has ended. See comment
2429 * above in sdhci_cmd_irq().
2430 */
2431 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2432 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2433 host->cmd->error = -ETIMEDOUT;
2434 tasklet_schedule(&host->finish_tasklet);
2435 return;
2436 }
2437 if (intmask & SDHCI_INT_DATA_END) {
2438 /*
2439 * Some cards handle busy-end interrupt
2440 * before the command completed, so make
2441 * sure we do things in the proper order.
2442 */
2443 if (host->busy_handle)
2444 sdhci_finish_command(host);
2445 else
2446 host->busy_handle = 1;
2447 return;
2448 }
2449 }
2450
2451 pr_err("%s: Got data interrupt 0x%08x even "
2452 "though no data operation was in progress.\n",
2453 mmc_hostname(host->mmc), (unsigned)intmask);
2454 sdhci_dumpregs(host);
2455
2456 return;
2457 }
2458
2459 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2460 host->data->error = -ETIMEDOUT;
2461 else if (intmask & SDHCI_INT_DATA_END_BIT)
2462 host->data->error = -EILSEQ;
2463 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2464 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2465 != MMC_BUS_TEST_R)
2466 host->data->error = -EILSEQ;
2467 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2468 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2469 sdhci_adma_show_error(host);
2470 host->data->error = -EIO;
2471 if (host->ops->adma_workaround)
2472 host->ops->adma_workaround(host, intmask);
2473 }
2474
2475 if (host->data->error)
2476 sdhci_finish_data(host);
2477 else {
2478 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2479 sdhci_transfer_pio(host);
2480
2481 /*
2482 * We currently don't do anything fancy with DMA
2483 * boundaries, but as we can't disable the feature
2484 * we need to at least restart the transfer.
2485 *
2486 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2487 * should return a valid address to continue from, but as
2488 * some controllers are faulty, don't trust them.
2489 */
2490 if (intmask & SDHCI_INT_DMA_END) {
2491 u32 dmastart, dmanow;
2492 dmastart = sg_dma_address(host->data->sg);
2493 dmanow = dmastart + host->data->bytes_xfered;
2494 /*
2495 * Force update to the next DMA block boundary.
2496 */
2497 dmanow = (dmanow &
2498 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2499 SDHCI_DEFAULT_BOUNDARY_SIZE;
2500 host->data->bytes_xfered = dmanow - dmastart;
2501 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2502 " next 0x%08x\n",
2503 mmc_hostname(host->mmc), dmastart,
2504 host->data->bytes_xfered, dmanow);
2505 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2506 }
2507
2508 if (intmask & SDHCI_INT_DATA_END) {
2509 if (host->cmd) {
2510 /*
2511 * Data managed to finish before the
2512 * command completed. Make sure we do
2513 * things in the proper order.
2514 */
2515 host->data_early = 1;
2516 } else {
2517 sdhci_finish_data(host);
2518 }
2519 }
2520 }
2521 }
2522
2523 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2524 {
2525 irqreturn_t result = IRQ_NONE;
2526 struct sdhci_host *host = dev_id;
2527 u32 intmask, mask, unexpected = 0;
2528 int max_loops = 16;
2529
2530 spin_lock(&host->lock);
2531
2532 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2533 spin_unlock(&host->lock);
2534 return IRQ_NONE;
2535 }
2536
2537 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2538 if (!intmask || intmask == 0xffffffff) {
2539 result = IRQ_NONE;
2540 goto out;
2541 }
2542
2543 do {
2544 /* Clear selected interrupts. */
2545 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2546 SDHCI_INT_BUS_POWER);
2547 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2548
2549 DBG("*** %s got interrupt: 0x%08x\n",
2550 mmc_hostname(host->mmc), intmask);
2551
2552 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2553 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2554 SDHCI_CARD_PRESENT;
2555
2556 /*
2557 * There is a observation on i.mx esdhc. INSERT
2558 * bit will be immediately set again when it gets
2559 * cleared, if a card is inserted. We have to mask
2560 * the irq to prevent interrupt storm which will
2561 * freeze the system. And the REMOVE gets the
2562 * same situation.
2563 *
2564 * More testing are needed here to ensure it works
2565 * for other platforms though.
2566 */
2567 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2568 SDHCI_INT_CARD_REMOVE);
2569 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2570 SDHCI_INT_CARD_INSERT;
2571 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2572 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2573
2574 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2575 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2576
2577 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2578 SDHCI_INT_CARD_REMOVE);
2579 result = IRQ_WAKE_THREAD;
2580 }
2581
2582 if (intmask & SDHCI_INT_CMD_MASK)
2583 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2584 &intmask);
2585
2586 if (intmask & SDHCI_INT_DATA_MASK)
2587 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2588
2589 if (intmask & SDHCI_INT_BUS_POWER)
2590 pr_err("%s: Card is consuming too much power!\n",
2591 mmc_hostname(host->mmc));
2592
2593 if (intmask & SDHCI_INT_CARD_INT) {
2594 sdhci_enable_sdio_irq_nolock(host, false);
2595 host->thread_isr |= SDHCI_INT_CARD_INT;
2596 result = IRQ_WAKE_THREAD;
2597 }
2598
2599 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2600 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2601 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2602 SDHCI_INT_CARD_INT);
2603
2604 if (intmask) {
2605 unexpected |= intmask;
2606 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2607 }
2608
2609 if (result == IRQ_NONE)
2610 result = IRQ_HANDLED;
2611
2612 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2613 } while (intmask && --max_loops);
2614 out:
2615 spin_unlock(&host->lock);
2616
2617 if (unexpected) {
2618 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2619 mmc_hostname(host->mmc), unexpected);
2620 sdhci_dumpregs(host);
2621 }
2622
2623 return result;
2624 }
2625
2626 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2627 {
2628 struct sdhci_host *host = dev_id;
2629 unsigned long flags;
2630 u32 isr;
2631
2632 spin_lock_irqsave(&host->lock, flags);
2633 isr = host->thread_isr;
2634 host->thread_isr = 0;
2635 spin_unlock_irqrestore(&host->lock, flags);
2636
2637 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2638 sdhci_card_event(host->mmc);
2639 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2640 }
2641
2642 if (isr & SDHCI_INT_CARD_INT) {
2643 sdio_run_irqs(host->mmc);
2644
2645 spin_lock_irqsave(&host->lock, flags);
2646 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2647 sdhci_enable_sdio_irq_nolock(host, true);
2648 spin_unlock_irqrestore(&host->lock, flags);
2649 }
2650
2651 return isr ? IRQ_HANDLED : IRQ_NONE;
2652 }
2653
2654 /*****************************************************************************\
2655 * *
2656 * Suspend/resume *
2657 * *
2658 \*****************************************************************************/
2659
2660 #ifdef CONFIG_PM
2661 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2662 {
2663 u8 val;
2664 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2665 | SDHCI_WAKE_ON_INT;
2666
2667 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2668 val |= mask ;
2669 /* Avoid fake wake up */
2670 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2671 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2672 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2673 }
2674 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2675
2676 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2677 {
2678 u8 val;
2679 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2680 | SDHCI_WAKE_ON_INT;
2681
2682 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2683 val &= ~mask;
2684 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2685 }
2686
2687 int sdhci_suspend_host(struct sdhci_host *host)
2688 {
2689 sdhci_disable_card_detection(host);
2690
2691 mmc_retune_timer_stop(host->mmc);
2692 mmc_retune_needed(host->mmc);
2693
2694 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2695 host->ier = 0;
2696 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2697 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2698 free_irq(host->irq, host);
2699 } else {
2700 sdhci_enable_irq_wakeups(host);
2701 enable_irq_wake(host->irq);
2702 }
2703 return 0;
2704 }
2705
2706 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2707
2708 int sdhci_resume_host(struct sdhci_host *host)
2709 {
2710 int ret = 0;
2711
2712 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2713 if (host->ops->enable_dma)
2714 host->ops->enable_dma(host);
2715 }
2716
2717 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2718 ret = request_threaded_irq(host->irq, sdhci_irq,
2719 sdhci_thread_irq, IRQF_SHARED,
2720 mmc_hostname(host->mmc), host);
2721 if (ret)
2722 return ret;
2723 } else {
2724 sdhci_disable_irq_wakeups(host);
2725 disable_irq_wake(host->irq);
2726 }
2727
2728 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2729 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2730 /* Card keeps power but host controller does not */
2731 sdhci_init(host, 0);
2732 host->pwr = 0;
2733 host->clock = 0;
2734 sdhci_do_set_ios(host, &host->mmc->ios);
2735 } else {
2736 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2737 mmiowb();
2738 }
2739
2740 sdhci_enable_card_detection(host);
2741
2742 return ret;
2743 }
2744
2745 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2746
2747 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2748 {
2749 return pm_runtime_get_sync(host->mmc->parent);
2750 }
2751
2752 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2753 {
2754 pm_runtime_mark_last_busy(host->mmc->parent);
2755 return pm_runtime_put_autosuspend(host->mmc->parent);
2756 }
2757
2758 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2759 {
2760 if (host->runtime_suspended || host->bus_on)
2761 return;
2762 host->bus_on = true;
2763 pm_runtime_get_noresume(host->mmc->parent);
2764 }
2765
2766 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2767 {
2768 if (host->runtime_suspended || !host->bus_on)
2769 return;
2770 host->bus_on = false;
2771 pm_runtime_put_noidle(host->mmc->parent);
2772 }
2773
2774 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2775 {
2776 unsigned long flags;
2777
2778 mmc_retune_timer_stop(host->mmc);
2779 mmc_retune_needed(host->mmc);
2780
2781 spin_lock_irqsave(&host->lock, flags);
2782 host->ier &= SDHCI_INT_CARD_INT;
2783 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2784 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2785 spin_unlock_irqrestore(&host->lock, flags);
2786
2787 synchronize_hardirq(host->irq);
2788
2789 spin_lock_irqsave(&host->lock, flags);
2790 host->runtime_suspended = true;
2791 spin_unlock_irqrestore(&host->lock, flags);
2792
2793 return 0;
2794 }
2795 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2796
2797 int sdhci_runtime_resume_host(struct sdhci_host *host)
2798 {
2799 unsigned long flags;
2800 int host_flags = host->flags;
2801
2802 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2803 if (host->ops->enable_dma)
2804 host->ops->enable_dma(host);
2805 }
2806
2807 sdhci_init(host, 0);
2808
2809 /* Force clock and power re-program */
2810 host->pwr = 0;
2811 host->clock = 0;
2812 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2813 sdhci_do_set_ios(host, &host->mmc->ios);
2814
2815 if ((host_flags & SDHCI_PV_ENABLED) &&
2816 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2817 spin_lock_irqsave(&host->lock, flags);
2818 sdhci_enable_preset_value(host, true);
2819 spin_unlock_irqrestore(&host->lock, flags);
2820 }
2821
2822 spin_lock_irqsave(&host->lock, flags);
2823
2824 host->runtime_suspended = false;
2825
2826 /* Enable SDIO IRQ */
2827 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2828 sdhci_enable_sdio_irq_nolock(host, true);
2829
2830 /* Enable Card Detection */
2831 sdhci_enable_card_detection(host);
2832
2833 spin_unlock_irqrestore(&host->lock, flags);
2834
2835 return 0;
2836 }
2837 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2838
2839 #endif /* CONFIG_PM */
2840
2841 /*****************************************************************************\
2842 * *
2843 * Device allocation/registration *
2844 * *
2845 \*****************************************************************************/
2846
2847 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2848 size_t priv_size)
2849 {
2850 struct mmc_host *mmc;
2851 struct sdhci_host *host;
2852
2853 WARN_ON(dev == NULL);
2854
2855 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2856 if (!mmc)
2857 return ERR_PTR(-ENOMEM);
2858
2859 host = mmc_priv(mmc);
2860 host->mmc = mmc;
2861
2862 return host;
2863 }
2864
2865 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2866
2867 int sdhci_add_host(struct sdhci_host *host)
2868 {
2869 struct mmc_host *mmc;
2870 u32 caps[2] = {0, 0};
2871 u32 max_current_caps;
2872 unsigned int ocr_avail;
2873 unsigned int override_timeout_clk;
2874 u32 max_clk;
2875 int ret;
2876
2877 WARN_ON(host == NULL);
2878 if (host == NULL)
2879 return -EINVAL;
2880
2881 mmc = host->mmc;
2882
2883 if (debug_quirks)
2884 host->quirks = debug_quirks;
2885 if (debug_quirks2)
2886 host->quirks2 = debug_quirks2;
2887
2888 override_timeout_clk = host->timeout_clk;
2889
2890 sdhci_do_reset(host, SDHCI_RESET_ALL);
2891
2892 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2893 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2894 >> SDHCI_SPEC_VER_SHIFT;
2895 if (host->version > SDHCI_SPEC_300) {
2896 pr_err("%s: Unknown controller version (%d). "
2897 "You may experience problems.\n", mmc_hostname(mmc),
2898 host->version);
2899 }
2900
2901 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2902 sdhci_readl(host, SDHCI_CAPABILITIES);
2903
2904 if (host->version >= SDHCI_SPEC_300)
2905 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2906 host->caps1 :
2907 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2908
2909 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2910 host->flags |= SDHCI_USE_SDMA;
2911 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2912 DBG("Controller doesn't have SDMA capability\n");
2913 else
2914 host->flags |= SDHCI_USE_SDMA;
2915
2916 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2917 (host->flags & SDHCI_USE_SDMA)) {
2918 DBG("Disabling DMA as it is marked broken\n");
2919 host->flags &= ~SDHCI_USE_SDMA;
2920 }
2921
2922 if ((host->version >= SDHCI_SPEC_200) &&
2923 (caps[0] & SDHCI_CAN_DO_ADMA2))
2924 host->flags |= SDHCI_USE_ADMA;
2925
2926 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2927 (host->flags & SDHCI_USE_ADMA)) {
2928 DBG("Disabling ADMA as it is marked broken\n");
2929 host->flags &= ~SDHCI_USE_ADMA;
2930 }
2931
2932 /*
2933 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2934 * and *must* do 64-bit DMA. A driver has the opportunity to change
2935 * that during the first call to ->enable_dma(). Similarly
2936 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2937 * implement.
2938 */
2939 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2940 host->flags |= SDHCI_USE_64_BIT_DMA;
2941
2942 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2943 if (host->ops->enable_dma) {
2944 if (host->ops->enable_dma(host)) {
2945 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2946 mmc_hostname(mmc));
2947 host->flags &=
2948 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2949 }
2950 }
2951 }
2952
2953 /* SDMA does not support 64-bit DMA */
2954 if (host->flags & SDHCI_USE_64_BIT_DMA)
2955 host->flags &= ~SDHCI_USE_SDMA;
2956
2957 if (host->flags & SDHCI_USE_ADMA) {
2958 /*
2959 * The DMA descriptor table size is calculated as the maximum
2960 * number of segments times 2, to allow for an alignment
2961 * descriptor for each segment, plus 1 for a nop end descriptor,
2962 * all multipled by the descriptor size.
2963 */
2964 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2965 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2966 SDHCI_ADMA2_64_DESC_SZ;
2967 host->align_buffer_sz = SDHCI_MAX_SEGS *
2968 SDHCI_ADMA2_64_ALIGN;
2969 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2970 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2971 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2972 } else {
2973 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2974 SDHCI_ADMA2_32_DESC_SZ;
2975 host->align_buffer_sz = SDHCI_MAX_SEGS *
2976 SDHCI_ADMA2_32_ALIGN;
2977 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2978 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2979 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2980 }
2981 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2982 host->adma_table_sz,
2983 &host->adma_addr,
2984 GFP_KERNEL);
2985 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2986 if (!host->adma_table || !host->align_buffer) {
2987 if (host->adma_table)
2988 dma_free_coherent(mmc_dev(mmc),
2989 host->adma_table_sz,
2990 host->adma_table,
2991 host->adma_addr);
2992 kfree(host->align_buffer);
2993 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2994 mmc_hostname(mmc));
2995 host->flags &= ~SDHCI_USE_ADMA;
2996 host->adma_table = NULL;
2997 host->align_buffer = NULL;
2998 } else if (host->adma_addr & host->align_mask) {
2999 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3000 mmc_hostname(mmc));
3001 host->flags &= ~SDHCI_USE_ADMA;
3002 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3003 host->adma_table, host->adma_addr);
3004 kfree(host->align_buffer);
3005 host->adma_table = NULL;
3006 host->align_buffer = NULL;
3007 }
3008 }
3009
3010 /*
3011 * If we use DMA, then it's up to the caller to set the DMA
3012 * mask, but PIO does not need the hw shim so we set a new
3013 * mask here in that case.
3014 */
3015 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3016 host->dma_mask = DMA_BIT_MASK(64);
3017 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3018 }
3019
3020 if (host->version >= SDHCI_SPEC_300)
3021 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3022 >> SDHCI_CLOCK_BASE_SHIFT;
3023 else
3024 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3025 >> SDHCI_CLOCK_BASE_SHIFT;
3026
3027 host->max_clk *= 1000000;
3028 if (host->max_clk == 0 || host->quirks &
3029 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3030 if (!host->ops->get_max_clock) {
3031 pr_err("%s: Hardware doesn't specify base clock "
3032 "frequency.\n", mmc_hostname(mmc));
3033 return -ENODEV;
3034 }
3035 host->max_clk = host->ops->get_max_clock(host);
3036 }
3037
3038 /*
3039 * In case of Host Controller v3.00, find out whether clock
3040 * multiplier is supported.
3041 */
3042 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3043 SDHCI_CLOCK_MUL_SHIFT;
3044
3045 /*
3046 * In case the value in Clock Multiplier is 0, then programmable
3047 * clock mode is not supported, otherwise the actual clock
3048 * multiplier is one more than the value of Clock Multiplier
3049 * in the Capabilities Register.
3050 */
3051 if (host->clk_mul)
3052 host->clk_mul += 1;
3053
3054 /*
3055 * Set host parameters.
3056 */
3057 mmc->ops = &sdhci_ops;
3058 max_clk = host->max_clk;
3059
3060 if (host->ops->get_min_clock)
3061 mmc->f_min = host->ops->get_min_clock(host);
3062 else if (host->version >= SDHCI_SPEC_300) {
3063 if (host->clk_mul) {
3064 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3065 max_clk = host->max_clk * host->clk_mul;
3066 } else
3067 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3068 } else
3069 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3070
3071 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3072 mmc->f_max = max_clk;
3073
3074 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3075 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3076 SDHCI_TIMEOUT_CLK_SHIFT;
3077 if (host->timeout_clk == 0) {
3078 if (host->ops->get_timeout_clock) {
3079 host->timeout_clk =
3080 host->ops->get_timeout_clock(host);
3081 } else {
3082 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3083 mmc_hostname(mmc));
3084 return -ENODEV;
3085 }
3086 }
3087
3088 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3089 host->timeout_clk *= 1000;
3090
3091 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3092 host->ops->get_max_timeout_count(host) : 1 << 27;
3093 mmc->max_busy_timeout /= host->timeout_clk;
3094 }
3095
3096 if (override_timeout_clk)
3097 host->timeout_clk = override_timeout_clk;
3098
3099 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3100 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3101
3102 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3103 host->flags |= SDHCI_AUTO_CMD12;
3104
3105 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3106 if ((host->version >= SDHCI_SPEC_300) &&
3107 ((host->flags & SDHCI_USE_ADMA) ||
3108 !(host->flags & SDHCI_USE_SDMA)) &&
3109 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3110 host->flags |= SDHCI_AUTO_CMD23;
3111 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3112 } else {
3113 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3114 }
3115
3116 /*
3117 * A controller may support 8-bit width, but the board itself
3118 * might not have the pins brought out. Boards that support
3119 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3120 * their platform code before calling sdhci_add_host(), and we
3121 * won't assume 8-bit width for hosts without that CAP.
3122 */
3123 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3124 mmc->caps |= MMC_CAP_4_BIT_DATA;
3125
3126 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3127 mmc->caps &= ~MMC_CAP_CMD23;
3128
3129 if (caps[0] & SDHCI_CAN_DO_HISPD)
3130 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3131
3132 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3133 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3134 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3135 mmc->caps |= MMC_CAP_NEEDS_POLL;
3136
3137 /* If there are external regulators, get them */
3138 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3139 return -EPROBE_DEFER;
3140
3141 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3142 if (!IS_ERR(mmc->supply.vqmmc)) {
3143 ret = regulator_enable(mmc->supply.vqmmc);
3144 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3145 1950000))
3146 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3147 SDHCI_SUPPORT_SDR50 |
3148 SDHCI_SUPPORT_DDR50);
3149 if (ret) {
3150 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3151 mmc_hostname(mmc), ret);
3152 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3153 }
3154 }
3155
3156 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3157 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3158 SDHCI_SUPPORT_DDR50);
3159
3160 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3161 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3162 SDHCI_SUPPORT_DDR50))
3163 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3164
3165 /* SDR104 supports also implies SDR50 support */
3166 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3167 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3168 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3169 * field can be promoted to support HS200.
3170 */
3171 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3172 mmc->caps2 |= MMC_CAP2_HS200;
3173 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3174 mmc->caps |= MMC_CAP_UHS_SDR50;
3175
3176 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3177 (caps[1] & SDHCI_SUPPORT_HS400))
3178 mmc->caps2 |= MMC_CAP2_HS400;
3179
3180 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3181 (IS_ERR(mmc->supply.vqmmc) ||
3182 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3183 1300000)))
3184 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3185
3186 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3187 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3188 mmc->caps |= MMC_CAP_UHS_DDR50;
3189
3190 /* Does the host need tuning for SDR50? */
3191 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3192 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3193
3194 /* Does the host need tuning for SDR104 / HS200? */
3195 if (mmc->caps2 & MMC_CAP2_HS200)
3196 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3197
3198 /* Driver Type(s) (A, C, D) supported by the host */
3199 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3200 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3201 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3202 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3203 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3204 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3205
3206 /* Initial value for re-tuning timer count */
3207 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3208 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3209
3210 /*
3211 * In case Re-tuning Timer is not disabled, the actual value of
3212 * re-tuning timer will be 2 ^ (n - 1).
3213 */
3214 if (host->tuning_count)
3215 host->tuning_count = 1 << (host->tuning_count - 1);
3216
3217 /* Re-tuning mode supported by the Host Controller */
3218 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3219 SDHCI_RETUNING_MODE_SHIFT;
3220
3221 ocr_avail = 0;
3222
3223 /*
3224 * According to SD Host Controller spec v3.00, if the Host System
3225 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3226 * the value is meaningful only if Voltage Support in the Capabilities
3227 * register is set. The actual current value is 4 times the register
3228 * value.
3229 */
3230 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3231 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3232 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3233 if (curr > 0) {
3234
3235 /* convert to SDHCI_MAX_CURRENT format */
3236 curr = curr/1000; /* convert to mA */
3237 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3238
3239 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3240 max_current_caps =
3241 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3242 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3243 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3244 }
3245 }
3246
3247 if (caps[0] & SDHCI_CAN_VDD_330) {
3248 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3249
3250 mmc->max_current_330 = ((max_current_caps &
3251 SDHCI_MAX_CURRENT_330_MASK) >>
3252 SDHCI_MAX_CURRENT_330_SHIFT) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER;
3254 }
3255 if (caps[0] & SDHCI_CAN_VDD_300) {
3256 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3257
3258 mmc->max_current_300 = ((max_current_caps &
3259 SDHCI_MAX_CURRENT_300_MASK) >>
3260 SDHCI_MAX_CURRENT_300_SHIFT) *
3261 SDHCI_MAX_CURRENT_MULTIPLIER;
3262 }
3263 if (caps[0] & SDHCI_CAN_VDD_180) {
3264 ocr_avail |= MMC_VDD_165_195;
3265
3266 mmc->max_current_180 = ((max_current_caps &
3267 SDHCI_MAX_CURRENT_180_MASK) >>
3268 SDHCI_MAX_CURRENT_180_SHIFT) *
3269 SDHCI_MAX_CURRENT_MULTIPLIER;
3270 }
3271
3272 /* If OCR set by host, use it instead. */
3273 if (host->ocr_mask)
3274 ocr_avail = host->ocr_mask;
3275
3276 /* If OCR set by external regulators, give it highest prio. */
3277 if (mmc->ocr_avail)
3278 ocr_avail = mmc->ocr_avail;
3279
3280 mmc->ocr_avail = ocr_avail;
3281 mmc->ocr_avail_sdio = ocr_avail;
3282 if (host->ocr_avail_sdio)
3283 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3284 mmc->ocr_avail_sd = ocr_avail;
3285 if (host->ocr_avail_sd)
3286 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3287 else /* normal SD controllers don't support 1.8V */
3288 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3289 mmc->ocr_avail_mmc = ocr_avail;
3290 if (host->ocr_avail_mmc)
3291 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3292
3293 if (mmc->ocr_avail == 0) {
3294 pr_err("%s: Hardware doesn't report any "
3295 "support voltages.\n", mmc_hostname(mmc));
3296 return -ENODEV;
3297 }
3298
3299 spin_lock_init(&host->lock);
3300
3301 /*
3302 * Maximum number of segments. Depends on if the hardware
3303 * can do scatter/gather or not.
3304 */
3305 if (host->flags & SDHCI_USE_ADMA)
3306 mmc->max_segs = SDHCI_MAX_SEGS;
3307 else if (host->flags & SDHCI_USE_SDMA)
3308 mmc->max_segs = 1;
3309 else /* PIO */
3310 mmc->max_segs = SDHCI_MAX_SEGS;
3311
3312 /*
3313 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3314 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3315 * is less anyway.
3316 */
3317 mmc->max_req_size = 524288;
3318
3319 /*
3320 * Maximum segment size. Could be one segment with the maximum number
3321 * of bytes. When doing hardware scatter/gather, each entry cannot
3322 * be larger than 64 KiB though.
3323 */
3324 if (host->flags & SDHCI_USE_ADMA) {
3325 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3326 mmc->max_seg_size = 65535;
3327 else
3328 mmc->max_seg_size = 65536;
3329 } else {
3330 mmc->max_seg_size = mmc->max_req_size;
3331 }
3332
3333 /*
3334 * Maximum block size. This varies from controller to controller and
3335 * is specified in the capabilities register.
3336 */
3337 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3338 mmc->max_blk_size = 2;
3339 } else {
3340 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3341 SDHCI_MAX_BLOCK_SHIFT;
3342 if (mmc->max_blk_size >= 3) {
3343 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3344 mmc_hostname(mmc));
3345 mmc->max_blk_size = 0;
3346 }
3347 }
3348
3349 mmc->max_blk_size = 512 << mmc->max_blk_size;
3350
3351 /*
3352 * Maximum block count.
3353 */
3354 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3355
3356 /*
3357 * Init tasklets.
3358 */
3359 tasklet_init(&host->finish_tasklet,
3360 sdhci_tasklet_finish, (unsigned long)host);
3361
3362 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3363
3364 init_waitqueue_head(&host->buf_ready_int);
3365
3366 sdhci_init(host, 0);
3367
3368 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3369 IRQF_SHARED, mmc_hostname(mmc), host);
3370 if (ret) {
3371 pr_err("%s: Failed to request IRQ %d: %d\n",
3372 mmc_hostname(mmc), host->irq, ret);
3373 goto untasklet;
3374 }
3375
3376 #ifdef CONFIG_MMC_DEBUG
3377 sdhci_dumpregs(host);
3378 #endif
3379
3380 #ifdef SDHCI_USE_LEDS_CLASS
3381 snprintf(host->led_name, sizeof(host->led_name),
3382 "%s::", mmc_hostname(mmc));
3383 host->led.name = host->led_name;
3384 host->led.brightness = LED_OFF;
3385 host->led.default_trigger = mmc_hostname(mmc);
3386 host->led.brightness_set = sdhci_led_control;
3387
3388 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3389 if (ret) {
3390 pr_err("%s: Failed to register LED device: %d\n",
3391 mmc_hostname(mmc), ret);
3392 goto reset;
3393 }
3394 #endif
3395
3396 mmiowb();
3397
3398 mmc_add_host(mmc);
3399
3400 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3401 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3402 (host->flags & SDHCI_USE_ADMA) ?
3403 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3404 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3405
3406 sdhci_enable_card_detection(host);
3407
3408 return 0;
3409
3410 #ifdef SDHCI_USE_LEDS_CLASS
3411 reset:
3412 sdhci_do_reset(host, SDHCI_RESET_ALL);
3413 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3414 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3415 free_irq(host->irq, host);
3416 #endif
3417 untasklet:
3418 tasklet_kill(&host->finish_tasklet);
3419
3420 return ret;
3421 }
3422
3423 EXPORT_SYMBOL_GPL(sdhci_add_host);
3424
3425 void sdhci_remove_host(struct sdhci_host *host, int dead)
3426 {
3427 struct mmc_host *mmc = host->mmc;
3428 unsigned long flags;
3429
3430 if (dead) {
3431 spin_lock_irqsave(&host->lock, flags);
3432
3433 host->flags |= SDHCI_DEVICE_DEAD;
3434
3435 if (host->mrq) {
3436 pr_err("%s: Controller removed during "
3437 " transfer!\n", mmc_hostname(mmc));
3438
3439 host->mrq->cmd->error = -ENOMEDIUM;
3440 tasklet_schedule(&host->finish_tasklet);
3441 }
3442
3443 spin_unlock_irqrestore(&host->lock, flags);
3444 }
3445
3446 sdhci_disable_card_detection(host);
3447
3448 mmc_remove_host(mmc);
3449
3450 #ifdef SDHCI_USE_LEDS_CLASS
3451 led_classdev_unregister(&host->led);
3452 #endif
3453
3454 if (!dead)
3455 sdhci_do_reset(host, SDHCI_RESET_ALL);
3456
3457 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3458 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3459 free_irq(host->irq, host);
3460
3461 del_timer_sync(&host->timer);
3462
3463 tasklet_kill(&host->finish_tasklet);
3464
3465 if (!IS_ERR(mmc->supply.vqmmc))
3466 regulator_disable(mmc->supply.vqmmc);
3467
3468 if (host->adma_table)
3469 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3470 host->adma_table, host->adma_addr);
3471 kfree(host->align_buffer);
3472
3473 host->adma_table = NULL;
3474 host->align_buffer = NULL;
3475 }
3476
3477 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3478
3479 void sdhci_free_host(struct sdhci_host *host)
3480 {
3481 mmc_free_host(host->mmc);
3482 }
3483
3484 EXPORT_SYMBOL_GPL(sdhci_free_host);
3485
3486 /*****************************************************************************\
3487 * *
3488 * Driver init/exit *
3489 * *
3490 \*****************************************************************************/
3491
3492 static int __init sdhci_drv_init(void)
3493 {
3494 pr_info(DRIVER_NAME
3495 ": Secure Digital Host Controller Interface driver\n");
3496 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3497
3498 return 0;
3499 }
3500
3501 static void __exit sdhci_drv_exit(void)
3502 {
3503 }
3504
3505 module_init(sdhci_drv_init);
3506 module_exit(sdhci_drv_exit);
3507
3508 module_param(debug_quirks, uint, 0444);
3509 module_param(debug_quirks2, uint, 0444);
3510
3511 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3512 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3513 MODULE_LICENSE("GPL");
3514
3515 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3516 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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