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[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sh_mmcif.c
1 /*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
19 /*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/mmc/card.h>
52 #include <linux/mmc/core.h>
53 #include <linux/mmc/host.h>
54 #include <linux/mmc/mmc.h>
55 #include <linux/mmc/sdio.h>
56 #include <linux/mmc/sh_mmcif.h>
57 #include <linux/mmc/slot-gpio.h>
58 #include <linux/mod_devicetable.h>
59 #include <linux/mutex.h>
60 #include <linux/pagemap.h>
61 #include <linux/platform_device.h>
62 #include <linux/pm_qos.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/spinlock.h>
65 #include <linux/module.h>
66
67 #define DRIVER_NAME "sh_mmcif"
68 #define DRIVER_VERSION "2010-04-28"
69
70 /* CE_CMD_SET */
71 #define CMD_MASK 0x3f000000
72 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
73 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
74 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
75 #define CMD_SET_RBSY (1 << 21) /* R1b */
76 #define CMD_SET_CCSEN (1 << 20)
77 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
78 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
79 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
80 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
81 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
82 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
83 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
84 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
85 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
86 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
87 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
88 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
89 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
90 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
91 #define CMD_SET_CCSH (1 << 5)
92 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
93 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
94 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
95 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
96
97 /* CE_CMD_CTRL */
98 #define CMD_CTRL_BREAK (1 << 0)
99
100 /* CE_BLOCK_SET */
101 #define BLOCK_SIZE_MASK 0x0000ffff
102
103 /* CE_INT */
104 #define INT_CCSDE (1 << 29)
105 #define INT_CMD12DRE (1 << 26)
106 #define INT_CMD12RBE (1 << 25)
107 #define INT_CMD12CRE (1 << 24)
108 #define INT_DTRANE (1 << 23)
109 #define INT_BUFRE (1 << 22)
110 #define INT_BUFWEN (1 << 21)
111 #define INT_BUFREN (1 << 20)
112 #define INT_CCSRCV (1 << 19)
113 #define INT_RBSYE (1 << 17)
114 #define INT_CRSPE (1 << 16)
115 #define INT_CMDVIO (1 << 15)
116 #define INT_BUFVIO (1 << 14)
117 #define INT_WDATERR (1 << 11)
118 #define INT_RDATERR (1 << 10)
119 #define INT_RIDXERR (1 << 9)
120 #define INT_RSPERR (1 << 8)
121 #define INT_CCSTO (1 << 5)
122 #define INT_CRCSTO (1 << 4)
123 #define INT_WDATTO (1 << 3)
124 #define INT_RDATTO (1 << 2)
125 #define INT_RBSYTO (1 << 1)
126 #define INT_RSPTO (1 << 0)
127 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
128 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
129 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
130 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
131
132 /* CE_INT_MASK */
133 #define MASK_ALL 0x00000000
134 #define MASK_MCCSDE (1 << 29)
135 #define MASK_MCMD12DRE (1 << 26)
136 #define MASK_MCMD12RBE (1 << 25)
137 #define MASK_MCMD12CRE (1 << 24)
138 #define MASK_MDTRANE (1 << 23)
139 #define MASK_MBUFRE (1 << 22)
140 #define MASK_MBUFWEN (1 << 21)
141 #define MASK_MBUFREN (1 << 20)
142 #define MASK_MCCSRCV (1 << 19)
143 #define MASK_MRBSYE (1 << 17)
144 #define MASK_MCRSPE (1 << 16)
145 #define MASK_MCMDVIO (1 << 15)
146 #define MASK_MBUFVIO (1 << 14)
147 #define MASK_MWDATERR (1 << 11)
148 #define MASK_MRDATERR (1 << 10)
149 #define MASK_MRIDXERR (1 << 9)
150 #define MASK_MRSPERR (1 << 8)
151 #define MASK_MCCSTO (1 << 5)
152 #define MASK_MCRCSTO (1 << 4)
153 #define MASK_MWDATTO (1 << 3)
154 #define MASK_MRDATTO (1 << 2)
155 #define MASK_MRBSYTO (1 << 1)
156 #define MASK_MRSPTO (1 << 0)
157
158 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
159 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
160 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
161 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
162
163 /* CE_HOST_STS1 */
164 #define STS1_CMDSEQ (1 << 31)
165
166 /* CE_HOST_STS2 */
167 #define STS2_CRCSTE (1 << 31)
168 #define STS2_CRC16E (1 << 30)
169 #define STS2_AC12CRCE (1 << 29)
170 #define STS2_RSPCRC7E (1 << 28)
171 #define STS2_CRCSTEBE (1 << 27)
172 #define STS2_RDATEBE (1 << 26)
173 #define STS2_AC12REBE (1 << 25)
174 #define STS2_RSPEBE (1 << 24)
175 #define STS2_AC12IDXE (1 << 23)
176 #define STS2_RSPIDXE (1 << 22)
177 #define STS2_CCSTO (1 << 15)
178 #define STS2_RDATTO (1 << 14)
179 #define STS2_DATBSYTO (1 << 13)
180 #define STS2_CRCSTTO (1 << 12)
181 #define STS2_AC12BSYTO (1 << 11)
182 #define STS2_RSPBSYTO (1 << 10)
183 #define STS2_AC12RSPTO (1 << 9)
184 #define STS2_RSPTO (1 << 8)
185 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
186 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
187 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
188 STS2_DATBSYTO | STS2_CRCSTTO | \
189 STS2_AC12BSYTO | STS2_RSPBSYTO | \
190 STS2_AC12RSPTO | STS2_RSPTO)
191
192 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
193 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
194 #define CLKDEV_INIT 400000 /* 400 KHz */
195
196 enum mmcif_state {
197 STATE_IDLE,
198 STATE_REQUEST,
199 STATE_IOS,
200 STATE_TIMEOUT,
201 };
202
203 enum mmcif_wait_for {
204 MMCIF_WAIT_FOR_REQUEST,
205 MMCIF_WAIT_FOR_CMD,
206 MMCIF_WAIT_FOR_MREAD,
207 MMCIF_WAIT_FOR_MWRITE,
208 MMCIF_WAIT_FOR_READ,
209 MMCIF_WAIT_FOR_WRITE,
210 MMCIF_WAIT_FOR_READ_END,
211 MMCIF_WAIT_FOR_WRITE_END,
212 MMCIF_WAIT_FOR_STOP,
213 };
214
215 struct sh_mmcif_host {
216 struct mmc_host *mmc;
217 struct mmc_request *mrq;
218 struct platform_device *pd;
219 struct clk *hclk;
220 unsigned int clk;
221 int bus_width;
222 unsigned char timing;
223 bool sd_error;
224 bool dying;
225 long timeout;
226 void __iomem *addr;
227 u32 *pio_ptr;
228 spinlock_t lock; /* protect sh_mmcif_host::state */
229 enum mmcif_state state;
230 enum mmcif_wait_for wait_for;
231 struct delayed_work timeout_work;
232 size_t blocksize;
233 int sg_idx;
234 int sg_blkidx;
235 bool power;
236 bool card_present;
237 struct mutex thread_lock;
238
239 /* DMA support */
240 struct dma_chan *chan_rx;
241 struct dma_chan *chan_tx;
242 struct completion dma_complete;
243 bool dma_active;
244 };
245
246 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
247 unsigned int reg, u32 val)
248 {
249 writel(val | readl(host->addr + reg), host->addr + reg);
250 }
251
252 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
253 unsigned int reg, u32 val)
254 {
255 writel(~val & readl(host->addr + reg), host->addr + reg);
256 }
257
258 static void mmcif_dma_complete(void *arg)
259 {
260 struct sh_mmcif_host *host = arg;
261 struct mmc_request *mrq = host->mrq;
262
263 dev_dbg(&host->pd->dev, "Command completed\n");
264
265 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
266 dev_name(&host->pd->dev)))
267 return;
268
269 complete(&host->dma_complete);
270 }
271
272 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
273 {
274 struct mmc_data *data = host->mrq->data;
275 struct scatterlist *sg = data->sg;
276 struct dma_async_tx_descriptor *desc = NULL;
277 struct dma_chan *chan = host->chan_rx;
278 dma_cookie_t cookie = -EINVAL;
279 int ret;
280
281 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
282 DMA_FROM_DEVICE);
283 if (ret > 0) {
284 host->dma_active = true;
285 desc = dmaengine_prep_slave_sg(chan, sg, ret,
286 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
287 }
288
289 if (desc) {
290 desc->callback = mmcif_dma_complete;
291 desc->callback_param = host;
292 cookie = dmaengine_submit(desc);
293 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
294 dma_async_issue_pending(chan);
295 }
296 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
297 __func__, data->sg_len, ret, cookie);
298
299 if (!desc) {
300 /* DMA failed, fall back to PIO */
301 if (ret >= 0)
302 ret = -EIO;
303 host->chan_rx = NULL;
304 host->dma_active = false;
305 dma_release_channel(chan);
306 /* Free the Tx channel too */
307 chan = host->chan_tx;
308 if (chan) {
309 host->chan_tx = NULL;
310 dma_release_channel(chan);
311 }
312 dev_warn(&host->pd->dev,
313 "DMA failed: %d, falling back to PIO\n", ret);
314 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
315 }
316
317 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
318 desc, cookie, data->sg_len);
319 }
320
321 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
322 {
323 struct mmc_data *data = host->mrq->data;
324 struct scatterlist *sg = data->sg;
325 struct dma_async_tx_descriptor *desc = NULL;
326 struct dma_chan *chan = host->chan_tx;
327 dma_cookie_t cookie = -EINVAL;
328 int ret;
329
330 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
331 DMA_TO_DEVICE);
332 if (ret > 0) {
333 host->dma_active = true;
334 desc = dmaengine_prep_slave_sg(chan, sg, ret,
335 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
336 }
337
338 if (desc) {
339 desc->callback = mmcif_dma_complete;
340 desc->callback_param = host;
341 cookie = dmaengine_submit(desc);
342 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
343 dma_async_issue_pending(chan);
344 }
345 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
346 __func__, data->sg_len, ret, cookie);
347
348 if (!desc) {
349 /* DMA failed, fall back to PIO */
350 if (ret >= 0)
351 ret = -EIO;
352 host->chan_tx = NULL;
353 host->dma_active = false;
354 dma_release_channel(chan);
355 /* Free the Rx channel too */
356 chan = host->chan_rx;
357 if (chan) {
358 host->chan_rx = NULL;
359 dma_release_channel(chan);
360 }
361 dev_warn(&host->pd->dev,
362 "DMA failed: %d, falling back to PIO\n", ret);
363 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
364 }
365
366 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
367 desc, cookie);
368 }
369
370 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
371 struct sh_mmcif_plat_data *pdata)
372 {
373 struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
374 struct dma_slave_config cfg;
375 dma_cap_mask_t mask;
376 int ret;
377
378 host->dma_active = false;
379
380 if (!pdata)
381 return;
382
383 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
384 return;
385
386 /* We can only either use DMA for both Tx and Rx or not use it at all */
387 dma_cap_zero(mask);
388 dma_cap_set(DMA_SLAVE, mask);
389
390 host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
391 (void *)pdata->slave_id_tx);
392 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
393 host->chan_tx);
394
395 if (!host->chan_tx)
396 return;
397
398 cfg.slave_id = pdata->slave_id_tx;
399 cfg.direction = DMA_MEM_TO_DEV;
400 cfg.dst_addr = res->start + MMCIF_CE_DATA;
401 cfg.src_addr = 0;
402 ret = dmaengine_slave_config(host->chan_tx, &cfg);
403 if (ret < 0)
404 goto ecfgtx;
405
406 host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
407 (void *)pdata->slave_id_rx);
408 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
409 host->chan_rx);
410
411 if (!host->chan_rx)
412 goto erqrx;
413
414 cfg.slave_id = pdata->slave_id_rx;
415 cfg.direction = DMA_DEV_TO_MEM;
416 cfg.dst_addr = 0;
417 cfg.src_addr = res->start + MMCIF_CE_DATA;
418 ret = dmaengine_slave_config(host->chan_rx, &cfg);
419 if (ret < 0)
420 goto ecfgrx;
421
422 return;
423
424 ecfgrx:
425 dma_release_channel(host->chan_rx);
426 host->chan_rx = NULL;
427 erqrx:
428 ecfgtx:
429 dma_release_channel(host->chan_tx);
430 host->chan_tx = NULL;
431 }
432
433 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
434 {
435 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
436 /* Descriptors are freed automatically */
437 if (host->chan_tx) {
438 struct dma_chan *chan = host->chan_tx;
439 host->chan_tx = NULL;
440 dma_release_channel(chan);
441 }
442 if (host->chan_rx) {
443 struct dma_chan *chan = host->chan_rx;
444 host->chan_rx = NULL;
445 dma_release_channel(chan);
446 }
447
448 host->dma_active = false;
449 }
450
451 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
452 {
453 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
454 bool sup_pclk = p ? p->sup_pclk : false;
455
456 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
457 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
458
459 if (!clk)
460 return;
461 if (sup_pclk && clk == host->clk)
462 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
463 else
464 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
465 ((fls(DIV_ROUND_UP(host->clk,
466 clk) - 1) - 1) << 16));
467
468 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
469 }
470
471 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
472 {
473 u32 tmp;
474
475 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
476
477 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
478 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
479 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
480 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
481 /* byte swap on */
482 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
483 }
484
485 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
486 {
487 u32 state1, state2;
488 int ret, timeout;
489
490 host->sd_error = false;
491
492 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
493 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
494 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
495 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
496
497 if (state1 & STS1_CMDSEQ) {
498 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
499 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
500 for (timeout = 10000000; timeout; timeout--) {
501 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
502 & STS1_CMDSEQ))
503 break;
504 mdelay(1);
505 }
506 if (!timeout) {
507 dev_err(&host->pd->dev,
508 "Forced end of command sequence timeout err\n");
509 return -EIO;
510 }
511 sh_mmcif_sync_reset(host);
512 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
513 return -EIO;
514 }
515
516 if (state2 & STS2_CRC_ERR) {
517 dev_dbg(&host->pd->dev, ": CRC error\n");
518 ret = -EIO;
519 } else if (state2 & STS2_TIMEOUT_ERR) {
520 dev_dbg(&host->pd->dev, ": Timeout\n");
521 ret = -ETIMEDOUT;
522 } else {
523 dev_dbg(&host->pd->dev, ": End/Index error\n");
524 ret = -EIO;
525 }
526 return ret;
527 }
528
529 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
530 {
531 struct mmc_data *data = host->mrq->data;
532
533 host->sg_blkidx += host->blocksize;
534
535 /* data->sg->length must be a multiple of host->blocksize? */
536 BUG_ON(host->sg_blkidx > data->sg->length);
537
538 if (host->sg_blkidx == data->sg->length) {
539 host->sg_blkidx = 0;
540 if (++host->sg_idx < data->sg_len)
541 host->pio_ptr = sg_virt(++data->sg);
542 } else {
543 host->pio_ptr = p;
544 }
545
546 return host->sg_idx != data->sg_len;
547 }
548
549 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
550 struct mmc_request *mrq)
551 {
552 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
553 BLOCK_SIZE_MASK) + 3;
554
555 host->wait_for = MMCIF_WAIT_FOR_READ;
556
557 /* buf read enable */
558 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
559 }
560
561 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
562 {
563 struct mmc_data *data = host->mrq->data;
564 u32 *p = sg_virt(data->sg);
565 int i;
566
567 if (host->sd_error) {
568 data->error = sh_mmcif_error_manage(host);
569 return false;
570 }
571
572 for (i = 0; i < host->blocksize / 4; i++)
573 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
574
575 /* buffer read end */
576 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
577 host->wait_for = MMCIF_WAIT_FOR_READ_END;
578
579 return true;
580 }
581
582 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
583 struct mmc_request *mrq)
584 {
585 struct mmc_data *data = mrq->data;
586
587 if (!data->sg_len || !data->sg->length)
588 return;
589
590 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
591 BLOCK_SIZE_MASK;
592
593 host->wait_for = MMCIF_WAIT_FOR_MREAD;
594 host->sg_idx = 0;
595 host->sg_blkidx = 0;
596 host->pio_ptr = sg_virt(data->sg);
597
598 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
599 }
600
601 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
602 {
603 struct mmc_data *data = host->mrq->data;
604 u32 *p = host->pio_ptr;
605 int i;
606
607 if (host->sd_error) {
608 data->error = sh_mmcif_error_manage(host);
609 return false;
610 }
611
612 BUG_ON(!data->sg->length);
613
614 for (i = 0; i < host->blocksize / 4; i++)
615 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
616
617 if (!sh_mmcif_next_block(host, p))
618 return false;
619
620 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
621
622 return true;
623 }
624
625 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
626 struct mmc_request *mrq)
627 {
628 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
629 BLOCK_SIZE_MASK) + 3;
630
631 host->wait_for = MMCIF_WAIT_FOR_WRITE;
632
633 /* buf write enable */
634 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
635 }
636
637 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
638 {
639 struct mmc_data *data = host->mrq->data;
640 u32 *p = sg_virt(data->sg);
641 int i;
642
643 if (host->sd_error) {
644 data->error = sh_mmcif_error_manage(host);
645 return false;
646 }
647
648 for (i = 0; i < host->blocksize / 4; i++)
649 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
650
651 /* buffer write end */
652 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
653 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
654
655 return true;
656 }
657
658 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
659 struct mmc_request *mrq)
660 {
661 struct mmc_data *data = mrq->data;
662
663 if (!data->sg_len || !data->sg->length)
664 return;
665
666 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
667 BLOCK_SIZE_MASK;
668
669 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
670 host->sg_idx = 0;
671 host->sg_blkidx = 0;
672 host->pio_ptr = sg_virt(data->sg);
673
674 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
675 }
676
677 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
678 {
679 struct mmc_data *data = host->mrq->data;
680 u32 *p = host->pio_ptr;
681 int i;
682
683 if (host->sd_error) {
684 data->error = sh_mmcif_error_manage(host);
685 return false;
686 }
687
688 BUG_ON(!data->sg->length);
689
690 for (i = 0; i < host->blocksize / 4; i++)
691 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
692
693 if (!sh_mmcif_next_block(host, p))
694 return false;
695
696 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
697
698 return true;
699 }
700
701 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
702 struct mmc_command *cmd)
703 {
704 if (cmd->flags & MMC_RSP_136) {
705 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
706 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
707 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
708 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
709 } else
710 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
711 }
712
713 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
714 struct mmc_command *cmd)
715 {
716 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
717 }
718
719 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
720 struct mmc_request *mrq)
721 {
722 struct mmc_data *data = mrq->data;
723 struct mmc_command *cmd = mrq->cmd;
724 u32 opc = cmd->opcode;
725 u32 tmp = 0;
726
727 /* Response Type check */
728 switch (mmc_resp_type(cmd)) {
729 case MMC_RSP_NONE:
730 tmp |= CMD_SET_RTYP_NO;
731 break;
732 case MMC_RSP_R1:
733 case MMC_RSP_R1B:
734 case MMC_RSP_R3:
735 tmp |= CMD_SET_RTYP_6B;
736 break;
737 case MMC_RSP_R2:
738 tmp |= CMD_SET_RTYP_17B;
739 break;
740 default:
741 dev_err(&host->pd->dev, "Unsupported response type.\n");
742 break;
743 }
744 switch (opc) {
745 /* RBSY */
746 case MMC_SLEEP_AWAKE:
747 case MMC_SWITCH:
748 case MMC_STOP_TRANSMISSION:
749 case MMC_SET_WRITE_PROT:
750 case MMC_CLR_WRITE_PROT:
751 case MMC_ERASE:
752 tmp |= CMD_SET_RBSY;
753 break;
754 }
755 /* WDAT / DATW */
756 if (data) {
757 tmp |= CMD_SET_WDAT;
758 switch (host->bus_width) {
759 case MMC_BUS_WIDTH_1:
760 tmp |= CMD_SET_DATW_1;
761 break;
762 case MMC_BUS_WIDTH_4:
763 tmp |= CMD_SET_DATW_4;
764 break;
765 case MMC_BUS_WIDTH_8:
766 tmp |= CMD_SET_DATW_8;
767 break;
768 default:
769 dev_err(&host->pd->dev, "Unsupported bus width.\n");
770 break;
771 }
772 switch (host->timing) {
773 case MMC_TIMING_UHS_DDR50:
774 /*
775 * MMC core will only set this timing, if the host
776 * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
777 * implementations with this capability, e.g. sh73a0,
778 * will have to set it in their platform data.
779 */
780 tmp |= CMD_SET_DARS;
781 break;
782 }
783 }
784 /* DWEN */
785 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
786 tmp |= CMD_SET_DWEN;
787 /* CMLTE/CMD12EN */
788 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
789 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
790 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
791 data->blocks << 16);
792 }
793 /* RIDXC[1:0] check bits */
794 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
795 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
796 tmp |= CMD_SET_RIDXC_BITS;
797 /* RCRC7C[1:0] check bits */
798 if (opc == MMC_SEND_OP_COND)
799 tmp |= CMD_SET_CRC7C_BITS;
800 /* RCRC7C[1:0] internal CRC7 */
801 if (opc == MMC_ALL_SEND_CID ||
802 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
803 tmp |= CMD_SET_CRC7C_INTERNAL;
804
805 return (opc << 24) | tmp;
806 }
807
808 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
809 struct mmc_request *mrq, u32 opc)
810 {
811 switch (opc) {
812 case MMC_READ_MULTIPLE_BLOCK:
813 sh_mmcif_multi_read(host, mrq);
814 return 0;
815 case MMC_WRITE_MULTIPLE_BLOCK:
816 sh_mmcif_multi_write(host, mrq);
817 return 0;
818 case MMC_WRITE_BLOCK:
819 sh_mmcif_single_write(host, mrq);
820 return 0;
821 case MMC_READ_SINGLE_BLOCK:
822 case MMC_SEND_EXT_CSD:
823 sh_mmcif_single_read(host, mrq);
824 return 0;
825 default:
826 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
827 return -EINVAL;
828 }
829 }
830
831 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
832 struct mmc_request *mrq)
833 {
834 struct mmc_command *cmd = mrq->cmd;
835 u32 opc = cmd->opcode;
836 u32 mask;
837
838 switch (opc) {
839 /* response busy check */
840 case MMC_SLEEP_AWAKE:
841 case MMC_SWITCH:
842 case MMC_STOP_TRANSMISSION:
843 case MMC_SET_WRITE_PROT:
844 case MMC_CLR_WRITE_PROT:
845 case MMC_ERASE:
846 mask = MASK_START_CMD | MASK_MRBSYE;
847 break;
848 default:
849 mask = MASK_START_CMD | MASK_MCRSPE;
850 break;
851 }
852
853 if (mrq->data) {
854 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
855 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
856 mrq->data->blksz);
857 }
858 opc = sh_mmcif_set_cmd(host, mrq);
859
860 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
861 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
862 /* set arg */
863 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
864 /* set cmd */
865 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
866
867 host->wait_for = MMCIF_WAIT_FOR_CMD;
868 schedule_delayed_work(&host->timeout_work, host->timeout);
869 }
870
871 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
872 struct mmc_request *mrq)
873 {
874 switch (mrq->cmd->opcode) {
875 case MMC_READ_MULTIPLE_BLOCK:
876 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
877 break;
878 case MMC_WRITE_MULTIPLE_BLOCK:
879 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
880 break;
881 default:
882 dev_err(&host->pd->dev, "unsupported stop cmd\n");
883 mrq->stop->error = sh_mmcif_error_manage(host);
884 return;
885 }
886
887 host->wait_for = MMCIF_WAIT_FOR_STOP;
888 }
889
890 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
891 {
892 struct sh_mmcif_host *host = mmc_priv(mmc);
893 unsigned long flags;
894
895 spin_lock_irqsave(&host->lock, flags);
896 if (host->state != STATE_IDLE) {
897 spin_unlock_irqrestore(&host->lock, flags);
898 mrq->cmd->error = -EAGAIN;
899 mmc_request_done(mmc, mrq);
900 return;
901 }
902
903 host->state = STATE_REQUEST;
904 spin_unlock_irqrestore(&host->lock, flags);
905
906 switch (mrq->cmd->opcode) {
907 /* MMCIF does not support SD/SDIO command */
908 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
909 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
910 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
911 break;
912 case MMC_APP_CMD:
913 case SD_IO_RW_DIRECT:
914 host->state = STATE_IDLE;
915 mrq->cmd->error = -ETIMEDOUT;
916 mmc_request_done(mmc, mrq);
917 return;
918 default:
919 break;
920 }
921
922 host->mrq = mrq;
923
924 sh_mmcif_start_cmd(host, mrq);
925 }
926
927 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
928 {
929 int ret = clk_enable(host->hclk);
930
931 if (!ret) {
932 host->clk = clk_get_rate(host->hclk);
933 host->mmc->f_max = host->clk / 2;
934 host->mmc->f_min = host->clk / 512;
935 }
936
937 return ret;
938 }
939
940 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
941 {
942 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
943 struct mmc_host *mmc = host->mmc;
944
945 if (pd && pd->set_pwr)
946 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
947 if (!IS_ERR(mmc->supply.vmmc))
948 /* Errors ignored... */
949 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
950 ios->power_mode ? ios->vdd : 0);
951 }
952
953 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
954 {
955 struct sh_mmcif_host *host = mmc_priv(mmc);
956 unsigned long flags;
957
958 spin_lock_irqsave(&host->lock, flags);
959 if (host->state != STATE_IDLE) {
960 spin_unlock_irqrestore(&host->lock, flags);
961 return;
962 }
963
964 host->state = STATE_IOS;
965 spin_unlock_irqrestore(&host->lock, flags);
966
967 if (ios->power_mode == MMC_POWER_UP) {
968 if (!host->card_present) {
969 /* See if we also get DMA */
970 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
971 host->card_present = true;
972 }
973 sh_mmcif_set_power(host, ios);
974 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
975 /* clock stop */
976 sh_mmcif_clock_control(host, 0);
977 if (ios->power_mode == MMC_POWER_OFF) {
978 if (host->card_present) {
979 sh_mmcif_release_dma(host);
980 host->card_present = false;
981 }
982 }
983 if (host->power) {
984 pm_runtime_put_sync(&host->pd->dev);
985 clk_disable(host->hclk);
986 host->power = false;
987 if (ios->power_mode == MMC_POWER_OFF)
988 sh_mmcif_set_power(host, ios);
989 }
990 host->state = STATE_IDLE;
991 return;
992 }
993
994 if (ios->clock) {
995 if (!host->power) {
996 sh_mmcif_clk_update(host);
997 pm_runtime_get_sync(&host->pd->dev);
998 host->power = true;
999 sh_mmcif_sync_reset(host);
1000 }
1001 sh_mmcif_clock_control(host, ios->clock);
1002 }
1003
1004 host->timing = ios->timing;
1005 host->bus_width = ios->bus_width;
1006 host->state = STATE_IDLE;
1007 }
1008
1009 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1010 {
1011 struct sh_mmcif_host *host = mmc_priv(mmc);
1012 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1013 int ret = mmc_gpio_get_cd(mmc);
1014
1015 if (ret >= 0)
1016 return ret;
1017
1018 if (!p || !p->get_cd)
1019 return -ENOSYS;
1020 else
1021 return p->get_cd(host->pd);
1022 }
1023
1024 static struct mmc_host_ops sh_mmcif_ops = {
1025 .request = sh_mmcif_request,
1026 .set_ios = sh_mmcif_set_ios,
1027 .get_cd = sh_mmcif_get_cd,
1028 };
1029
1030 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1031 {
1032 struct mmc_command *cmd = host->mrq->cmd;
1033 struct mmc_data *data = host->mrq->data;
1034 long time;
1035
1036 if (host->sd_error) {
1037 switch (cmd->opcode) {
1038 case MMC_ALL_SEND_CID:
1039 case MMC_SELECT_CARD:
1040 case MMC_APP_CMD:
1041 cmd->error = -ETIMEDOUT;
1042 break;
1043 default:
1044 cmd->error = sh_mmcif_error_manage(host);
1045 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1046 cmd->opcode, cmd->error);
1047 break;
1048 }
1049 host->sd_error = false;
1050 return false;
1051 }
1052 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1053 cmd->error = 0;
1054 return false;
1055 }
1056
1057 sh_mmcif_get_response(host, cmd);
1058
1059 if (!data)
1060 return false;
1061
1062 /*
1063 * Completion can be signalled from DMA callback and error, so, have to
1064 * reset here, before setting .dma_active
1065 */
1066 init_completion(&host->dma_complete);
1067
1068 if (data->flags & MMC_DATA_READ) {
1069 if (host->chan_rx)
1070 sh_mmcif_start_dma_rx(host);
1071 } else {
1072 if (host->chan_tx)
1073 sh_mmcif_start_dma_tx(host);
1074 }
1075
1076 if (!host->dma_active) {
1077 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1078 return !data->error;
1079 }
1080
1081 /* Running in the IRQ thread, can sleep */
1082 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1083 host->timeout);
1084
1085 if (data->flags & MMC_DATA_READ)
1086 dma_unmap_sg(host->chan_rx->device->dev,
1087 data->sg, data->sg_len,
1088 DMA_FROM_DEVICE);
1089 else
1090 dma_unmap_sg(host->chan_tx->device->dev,
1091 data->sg, data->sg_len,
1092 DMA_TO_DEVICE);
1093
1094 if (host->sd_error) {
1095 dev_err(host->mmc->parent,
1096 "Error IRQ while waiting for DMA completion!\n");
1097 /* Woken up by an error IRQ: abort DMA */
1098 data->error = sh_mmcif_error_manage(host);
1099 } else if (!time) {
1100 data->error = -ETIMEDOUT;
1101 } else if (time < 0) {
1102 data->error = time;
1103 }
1104 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1105 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1106 host->dma_active = false;
1107
1108 if (data->error) {
1109 data->bytes_xfered = 0;
1110 /* Abort DMA */
1111 if (data->flags & MMC_DATA_READ)
1112 dmaengine_terminate_all(host->chan_rx);
1113 else
1114 dmaengine_terminate_all(host->chan_tx);
1115 }
1116
1117 return false;
1118 }
1119
1120 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1121 {
1122 struct sh_mmcif_host *host = dev_id;
1123 struct mmc_request *mrq;
1124 bool wait = false;
1125
1126 cancel_delayed_work_sync(&host->timeout_work);
1127
1128 mutex_lock(&host->thread_lock);
1129
1130 mrq = host->mrq;
1131 if (!mrq) {
1132 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1133 host->state, host->wait_for);
1134 mutex_unlock(&host->thread_lock);
1135 return IRQ_HANDLED;
1136 }
1137
1138 /*
1139 * All handlers return true, if processing continues, and false, if the
1140 * request has to be completed - successfully or not
1141 */
1142 switch (host->wait_for) {
1143 case MMCIF_WAIT_FOR_REQUEST:
1144 /* We're too late, the timeout has already kicked in */
1145 mutex_unlock(&host->thread_lock);
1146 return IRQ_HANDLED;
1147 case MMCIF_WAIT_FOR_CMD:
1148 /* Wait for data? */
1149 wait = sh_mmcif_end_cmd(host);
1150 break;
1151 case MMCIF_WAIT_FOR_MREAD:
1152 /* Wait for more data? */
1153 wait = sh_mmcif_mread_block(host);
1154 break;
1155 case MMCIF_WAIT_FOR_READ:
1156 /* Wait for data end? */
1157 wait = sh_mmcif_read_block(host);
1158 break;
1159 case MMCIF_WAIT_FOR_MWRITE:
1160 /* Wait data to write? */
1161 wait = sh_mmcif_mwrite_block(host);
1162 break;
1163 case MMCIF_WAIT_FOR_WRITE:
1164 /* Wait for data end? */
1165 wait = sh_mmcif_write_block(host);
1166 break;
1167 case MMCIF_WAIT_FOR_STOP:
1168 if (host->sd_error) {
1169 mrq->stop->error = sh_mmcif_error_manage(host);
1170 break;
1171 }
1172 sh_mmcif_get_cmd12response(host, mrq->stop);
1173 mrq->stop->error = 0;
1174 break;
1175 case MMCIF_WAIT_FOR_READ_END:
1176 case MMCIF_WAIT_FOR_WRITE_END:
1177 if (host->sd_error)
1178 mrq->data->error = sh_mmcif_error_manage(host);
1179 break;
1180 default:
1181 BUG();
1182 }
1183
1184 if (wait) {
1185 schedule_delayed_work(&host->timeout_work, host->timeout);
1186 /* Wait for more data */
1187 mutex_unlock(&host->thread_lock);
1188 return IRQ_HANDLED;
1189 }
1190
1191 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1192 struct mmc_data *data = mrq->data;
1193 if (!mrq->cmd->error && data && !data->error)
1194 data->bytes_xfered =
1195 data->blocks * data->blksz;
1196
1197 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1198 sh_mmcif_stop_cmd(host, mrq);
1199 if (!mrq->stop->error) {
1200 schedule_delayed_work(&host->timeout_work, host->timeout);
1201 mutex_unlock(&host->thread_lock);
1202 return IRQ_HANDLED;
1203 }
1204 }
1205 }
1206
1207 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1208 host->state = STATE_IDLE;
1209 host->mrq = NULL;
1210 mmc_request_done(host->mmc, mrq);
1211
1212 mutex_unlock(&host->thread_lock);
1213
1214 return IRQ_HANDLED;
1215 }
1216
1217 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1218 {
1219 struct sh_mmcif_host *host = dev_id;
1220 u32 state;
1221 int err = 0;
1222
1223 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1224
1225 if (state & INT_ERR_STS) {
1226 /* error interrupts - process first */
1227 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1228 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1229 err = 1;
1230 } else if (state & INT_RBSYE) {
1231 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1232 ~(INT_RBSYE | INT_CRSPE));
1233 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1234 } else if (state & INT_CRSPE) {
1235 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1236 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1237 } else if (state & INT_BUFREN) {
1238 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1239 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1240 } else if (state & INT_BUFWEN) {
1241 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1242 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1243 } else if (state & INT_CMD12DRE) {
1244 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1245 ~(INT_CMD12DRE | INT_CMD12RBE |
1246 INT_CMD12CRE | INT_BUFRE));
1247 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1248 } else if (state & INT_BUFRE) {
1249 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1250 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1251 } else if (state & INT_DTRANE) {
1252 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1253 ~(INT_CMD12DRE | INT_CMD12RBE |
1254 INT_CMD12CRE | INT_DTRANE));
1255 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1256 } else if (state & INT_CMD12RBE) {
1257 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1258 ~(INT_CMD12RBE | INT_CMD12CRE));
1259 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1260 } else {
1261 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1262 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1263 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1264 err = 1;
1265 }
1266 if (err) {
1267 host->sd_error = true;
1268 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1269 }
1270 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1271 if (!host->dma_active)
1272 return IRQ_WAKE_THREAD;
1273 else if (host->sd_error)
1274 mmcif_dma_complete(host);
1275 } else {
1276 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1277 }
1278
1279 return IRQ_HANDLED;
1280 }
1281
1282 static void mmcif_timeout_work(struct work_struct *work)
1283 {
1284 struct delayed_work *d = container_of(work, struct delayed_work, work);
1285 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1286 struct mmc_request *mrq = host->mrq;
1287 unsigned long flags;
1288
1289 if (host->dying)
1290 /* Don't run after mmc_remove_host() */
1291 return;
1292
1293 dev_dbg(&host->pd->dev, "Timeout waiting for %u, opcode %u\n",
1294 host->wait_for, mrq->cmd->opcode);
1295
1296 spin_lock_irqsave(&host->lock, flags);
1297 if (host->state == STATE_IDLE) {
1298 spin_unlock_irqrestore(&host->lock, flags);
1299 return;
1300 }
1301
1302 host->state = STATE_TIMEOUT;
1303 spin_unlock_irqrestore(&host->lock, flags);
1304
1305 /*
1306 * Handle races with cancel_delayed_work(), unless
1307 * cancel_delayed_work_sync() is used
1308 */
1309 switch (host->wait_for) {
1310 case MMCIF_WAIT_FOR_CMD:
1311 mrq->cmd->error = sh_mmcif_error_manage(host);
1312 break;
1313 case MMCIF_WAIT_FOR_STOP:
1314 mrq->stop->error = sh_mmcif_error_manage(host);
1315 break;
1316 case MMCIF_WAIT_FOR_MREAD:
1317 case MMCIF_WAIT_FOR_MWRITE:
1318 case MMCIF_WAIT_FOR_READ:
1319 case MMCIF_WAIT_FOR_WRITE:
1320 case MMCIF_WAIT_FOR_READ_END:
1321 case MMCIF_WAIT_FOR_WRITE_END:
1322 mrq->data->error = sh_mmcif_error_manage(host);
1323 break;
1324 default:
1325 BUG();
1326 }
1327
1328 host->state = STATE_IDLE;
1329 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1330 host->mrq = NULL;
1331 mmc_request_done(host->mmc, mrq);
1332 }
1333
1334 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1335 {
1336 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1337 struct mmc_host *mmc = host->mmc;
1338
1339 mmc_regulator_get_supply(mmc);
1340
1341 if (!pd)
1342 return;
1343
1344 if (!mmc->ocr_avail)
1345 mmc->ocr_avail = pd->ocr;
1346 else if (pd->ocr)
1347 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1348 }
1349
1350 static int sh_mmcif_probe(struct platform_device *pdev)
1351 {
1352 int ret = 0, irq[2];
1353 struct mmc_host *mmc;
1354 struct sh_mmcif_host *host;
1355 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1356 struct resource *res;
1357 void __iomem *reg;
1358 const char *name;
1359
1360 irq[0] = platform_get_irq(pdev, 0);
1361 irq[1] = platform_get_irq(pdev, 1);
1362 if (irq[0] < 0) {
1363 dev_err(&pdev->dev, "Get irq error\n");
1364 return -ENXIO;
1365 }
1366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367 if (!res) {
1368 dev_err(&pdev->dev, "platform_get_resource error.\n");
1369 return -ENXIO;
1370 }
1371 reg = ioremap(res->start, resource_size(res));
1372 if (!reg) {
1373 dev_err(&pdev->dev, "ioremap error.\n");
1374 return -ENOMEM;
1375 }
1376
1377 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1378 if (!mmc) {
1379 ret = -ENOMEM;
1380 goto ealloch;
1381 }
1382 host = mmc_priv(mmc);
1383 host->mmc = mmc;
1384 host->addr = reg;
1385 host->timeout = msecs_to_jiffies(1000);
1386
1387 host->pd = pdev;
1388
1389 spin_lock_init(&host->lock);
1390
1391 mmc->ops = &sh_mmcif_ops;
1392 sh_mmcif_init_ocr(host);
1393
1394 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1395 if (pd && pd->caps)
1396 mmc->caps |= pd->caps;
1397 mmc->max_segs = 32;
1398 mmc->max_blk_size = 512;
1399 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1400 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1401 mmc->max_seg_size = mmc->max_req_size;
1402
1403 platform_set_drvdata(pdev, host);
1404
1405 pm_runtime_enable(&pdev->dev);
1406 host->power = false;
1407
1408 host->hclk = clk_get(&pdev->dev, NULL);
1409 if (IS_ERR(host->hclk)) {
1410 ret = PTR_ERR(host->hclk);
1411 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
1412 goto eclkget;
1413 }
1414 ret = sh_mmcif_clk_update(host);
1415 if (ret < 0)
1416 goto eclkupdate;
1417
1418 ret = pm_runtime_resume(&pdev->dev);
1419 if (ret < 0)
1420 goto eresume;
1421
1422 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1423
1424 sh_mmcif_sync_reset(host);
1425 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1426
1427 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1428 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
1429 if (ret) {
1430 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
1431 goto ereqirq0;
1432 }
1433 if (irq[1] >= 0) {
1434 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1435 0, "sh_mmc:int", host);
1436 if (ret) {
1437 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1438 goto ereqirq1;
1439 }
1440 }
1441
1442 if (pd && pd->use_cd_gpio) {
1443 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1444 if (ret < 0)
1445 goto erqcd;
1446 }
1447
1448 mutex_init(&host->thread_lock);
1449
1450 clk_disable(host->hclk);
1451 ret = mmc_add_host(mmc);
1452 if (ret < 0)
1453 goto emmcaddh;
1454
1455 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1456
1457 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1458 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1459 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1460 return ret;
1461
1462 emmcaddh:
1463 erqcd:
1464 if (irq[1] >= 0)
1465 free_irq(irq[1], host);
1466 ereqirq1:
1467 free_irq(irq[0], host);
1468 ereqirq0:
1469 pm_runtime_suspend(&pdev->dev);
1470 eresume:
1471 clk_disable(host->hclk);
1472 eclkupdate:
1473 clk_put(host->hclk);
1474 eclkget:
1475 pm_runtime_disable(&pdev->dev);
1476 mmc_free_host(mmc);
1477 ealloch:
1478 iounmap(reg);
1479 return ret;
1480 }
1481
1482 static int sh_mmcif_remove(struct platform_device *pdev)
1483 {
1484 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1485 int irq[2];
1486
1487 host->dying = true;
1488 clk_enable(host->hclk);
1489 pm_runtime_get_sync(&pdev->dev);
1490
1491 dev_pm_qos_hide_latency_limit(&pdev->dev);
1492
1493 mmc_remove_host(host->mmc);
1494 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1495
1496 /*
1497 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1498 * mmc_remove_host() call above. But swapping order doesn't help either
1499 * (a query on the linux-mmc mailing list didn't bring any replies).
1500 */
1501 cancel_delayed_work_sync(&host->timeout_work);
1502
1503 if (host->addr)
1504 iounmap(host->addr);
1505
1506 irq[0] = platform_get_irq(pdev, 0);
1507 irq[1] = platform_get_irq(pdev, 1);
1508
1509 free_irq(irq[0], host);
1510 if (irq[1] >= 0)
1511 free_irq(irq[1], host);
1512
1513 platform_set_drvdata(pdev, NULL);
1514
1515 clk_disable(host->hclk);
1516 mmc_free_host(host->mmc);
1517 pm_runtime_put_sync(&pdev->dev);
1518 pm_runtime_disable(&pdev->dev);
1519
1520 return 0;
1521 }
1522
1523 #ifdef CONFIG_PM
1524 static int sh_mmcif_suspend(struct device *dev)
1525 {
1526 struct sh_mmcif_host *host = dev_get_drvdata(dev);
1527 int ret = mmc_suspend_host(host->mmc);
1528
1529 if (!ret)
1530 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1531
1532 return ret;
1533 }
1534
1535 static int sh_mmcif_resume(struct device *dev)
1536 {
1537 struct sh_mmcif_host *host = dev_get_drvdata(dev);
1538
1539 return mmc_resume_host(host->mmc);
1540 }
1541 #else
1542 #define sh_mmcif_suspend NULL
1543 #define sh_mmcif_resume NULL
1544 #endif /* CONFIG_PM */
1545
1546 static const struct of_device_id mmcif_of_match[] = {
1547 { .compatible = "renesas,sh-mmcif" },
1548 { }
1549 };
1550 MODULE_DEVICE_TABLE(of, mmcif_of_match);
1551
1552 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1553 .suspend = sh_mmcif_suspend,
1554 .resume = sh_mmcif_resume,
1555 };
1556
1557 static struct platform_driver sh_mmcif_driver = {
1558 .probe = sh_mmcif_probe,
1559 .remove = sh_mmcif_remove,
1560 .driver = {
1561 .name = DRIVER_NAME,
1562 .pm = &sh_mmcif_dev_pm_ops,
1563 .owner = THIS_MODULE,
1564 .of_match_table = mmcif_of_match,
1565 },
1566 };
1567
1568 module_platform_driver(sh_mmcif_driver);
1569
1570 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1571 MODULE_LICENSE("GPL");
1572 MODULE_ALIAS("platform:" DRIVER_NAME);
1573 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
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