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Merge tag 'renesas-fixes4-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sunxi-mmc.c
1 /*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 * (C) Copyright 2017 Sootech SA
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/io.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23
24 #include <linux/clk.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/spinlock.h>
28 #include <linux/scatterlist.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/reset.h>
32 #include <linux/regulator/consumer.h>
33
34 #include <linux/of_address.h>
35 #include <linux/of_gpio.h>
36 #include <linux/of_platform.h>
37
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/sd.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/core.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/slot-gpio.h>
45
46 /* register offset definitions */
47 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
48 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
49 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
50 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
51 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
52 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
53 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
54 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
55 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
56 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
57 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
58 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
59 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
60 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
61 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
62 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
63 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
64 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
65 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
66 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
67 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
68 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
69 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
70 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
71 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
72 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
73 #define SDXC_REG_CHDA (0x90)
74 #define SDXC_REG_CBDA (0x94)
75
76 /* New registers introduced in A64 */
77 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
78 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
79 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
80 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
81 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
82
83 #define mmc_readl(host, reg) \
84 readl((host)->reg_base + SDXC_##reg)
85 #define mmc_writel(host, reg, value) \
86 writel((value), (host)->reg_base + SDXC_##reg)
87
88 /* global control register bits */
89 #define SDXC_SOFT_RESET BIT(0)
90 #define SDXC_FIFO_RESET BIT(1)
91 #define SDXC_DMA_RESET BIT(2)
92 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
93 #define SDXC_DMA_ENABLE_BIT BIT(5)
94 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
95 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
96 #define SDXC_DDR_MODE BIT(10)
97 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
98 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
99 #define SDXC_ACCESS_BY_AHB BIT(31)
100 #define SDXC_ACCESS_BY_DMA (0 << 31)
101 #define SDXC_HARDWARE_RESET \
102 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
103
104 /* clock control bits */
105 #define SDXC_MASK_DATA0 BIT(31)
106 #define SDXC_CARD_CLOCK_ON BIT(16)
107 #define SDXC_LOW_POWER_ON BIT(17)
108
109 /* bus width */
110 #define SDXC_WIDTH1 0
111 #define SDXC_WIDTH4 1
112 #define SDXC_WIDTH8 2
113
114 /* smc command bits */
115 #define SDXC_RESP_EXPIRE BIT(6)
116 #define SDXC_LONG_RESPONSE BIT(7)
117 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
118 #define SDXC_DATA_EXPIRE BIT(9)
119 #define SDXC_WRITE BIT(10)
120 #define SDXC_SEQUENCE_MODE BIT(11)
121 #define SDXC_SEND_AUTO_STOP BIT(12)
122 #define SDXC_WAIT_PRE_OVER BIT(13)
123 #define SDXC_STOP_ABORT_CMD BIT(14)
124 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
125 #define SDXC_UPCLK_ONLY BIT(21)
126 #define SDXC_READ_CEATA_DEV BIT(22)
127 #define SDXC_CCS_EXPIRE BIT(23)
128 #define SDXC_ENABLE_BIT_BOOT BIT(24)
129 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
130 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
131 #define SDXC_BOOT_ABORT BIT(27)
132 #define SDXC_VOLTAGE_SWITCH BIT(28)
133 #define SDXC_USE_HOLD_REGISTER BIT(29)
134 #define SDXC_START BIT(31)
135
136 /* interrupt bits */
137 #define SDXC_RESP_ERROR BIT(1)
138 #define SDXC_COMMAND_DONE BIT(2)
139 #define SDXC_DATA_OVER BIT(3)
140 #define SDXC_TX_DATA_REQUEST BIT(4)
141 #define SDXC_RX_DATA_REQUEST BIT(5)
142 #define SDXC_RESP_CRC_ERROR BIT(6)
143 #define SDXC_DATA_CRC_ERROR BIT(7)
144 #define SDXC_RESP_TIMEOUT BIT(8)
145 #define SDXC_DATA_TIMEOUT BIT(9)
146 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
147 #define SDXC_FIFO_RUN_ERROR BIT(11)
148 #define SDXC_HARD_WARE_LOCKED BIT(12)
149 #define SDXC_START_BIT_ERROR BIT(13)
150 #define SDXC_AUTO_COMMAND_DONE BIT(14)
151 #define SDXC_END_BIT_ERROR BIT(15)
152 #define SDXC_SDIO_INTERRUPT BIT(16)
153 #define SDXC_CARD_INSERT BIT(30)
154 #define SDXC_CARD_REMOVE BIT(31)
155 #define SDXC_INTERRUPT_ERROR_BIT \
156 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
157 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
158 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
159 #define SDXC_INTERRUPT_DONE_BIT \
160 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
161 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
162
163 /* status */
164 #define SDXC_RXWL_FLAG BIT(0)
165 #define SDXC_TXWL_FLAG BIT(1)
166 #define SDXC_FIFO_EMPTY BIT(2)
167 #define SDXC_FIFO_FULL BIT(3)
168 #define SDXC_CARD_PRESENT BIT(8)
169 #define SDXC_CARD_DATA_BUSY BIT(9)
170 #define SDXC_DATA_FSM_BUSY BIT(10)
171 #define SDXC_DMA_REQUEST BIT(31)
172 #define SDXC_FIFO_SIZE 16
173
174 /* Function select */
175 #define SDXC_CEATA_ON (0xceaa << 16)
176 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
177 #define SDXC_SDIO_READ_WAIT BIT(1)
178 #define SDXC_ABORT_READ_DATA BIT(2)
179 #define SDXC_SEND_CCSD BIT(8)
180 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
181 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
182
183 /* IDMA controller bus mod bit field */
184 #define SDXC_IDMAC_SOFT_RESET BIT(0)
185 #define SDXC_IDMAC_FIX_BURST BIT(1)
186 #define SDXC_IDMAC_IDMA_ON BIT(7)
187 #define SDXC_IDMAC_REFETCH_DES BIT(31)
188
189 /* IDMA status bit field */
190 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
191 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
192 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
193 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
194 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
195 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
196 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
197 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
198 #define SDXC_IDMAC_IDLE (0 << 13)
199 #define SDXC_IDMAC_SUSPEND (1 << 13)
200 #define SDXC_IDMAC_DESC_READ (2 << 13)
201 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
202 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
203 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
204 #define SDXC_IDMAC_READ (6 << 13)
205 #define SDXC_IDMAC_WRITE (7 << 13)
206 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
207
208 /*
209 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
210 * Bits 0-12: buf1 size
211 * Bits 13-25: buf2 size
212 * Bits 26-31: not used
213 * Since we only ever set buf1 size, we can simply store it directly.
214 */
215 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
216 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
217 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
218 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
219 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
220 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
221 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
222
223 #define SDXC_CLK_400K 0
224 #define SDXC_CLK_25M 1
225 #define SDXC_CLK_50M 2
226 #define SDXC_CLK_50M_DDR 3
227 #define SDXC_CLK_50M_DDR_8BIT 4
228
229 #define SDXC_2X_TIMING_MODE BIT(31)
230
231 #define SDXC_CAL_START BIT(15)
232 #define SDXC_CAL_DONE BIT(14)
233 #define SDXC_CAL_DL_SHIFT 8
234 #define SDXC_CAL_DL_SW_EN BIT(7)
235 #define SDXC_CAL_DL_SW_SHIFT 0
236 #define SDXC_CAL_DL_MASK 0x3f
237
238 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
239
240 struct sunxi_mmc_clk_delay {
241 u32 output;
242 u32 sample;
243 };
244
245 struct sunxi_idma_des {
246 __le32 config;
247 __le32 buf_size;
248 __le32 buf_addr_ptr1;
249 __le32 buf_addr_ptr2;
250 };
251
252 struct sunxi_mmc_cfg {
253 u32 idma_des_size_bits;
254 const struct sunxi_mmc_clk_delay *clk_delays;
255
256 /* does the IP block support autocalibration? */
257 bool can_calibrate;
258
259 /* Does DATA0 needs to be masked while the clock is updated */
260 bool mask_data0;
261
262 bool needs_new_timings;
263 };
264
265 struct sunxi_mmc_host {
266 struct mmc_host *mmc;
267 struct reset_control *reset;
268 const struct sunxi_mmc_cfg *cfg;
269
270 /* IO mapping base */
271 void __iomem *reg_base;
272
273 /* clock management */
274 struct clk *clk_ahb;
275 struct clk *clk_mmc;
276 struct clk *clk_sample;
277 struct clk *clk_output;
278
279 /* irq */
280 spinlock_t lock;
281 int irq;
282 u32 int_sum;
283 u32 sdio_imask;
284
285 /* dma */
286 dma_addr_t sg_dma;
287 void *sg_cpu;
288 bool wait_dma;
289
290 struct mmc_request *mrq;
291 struct mmc_request *manual_stop_mrq;
292 int ferror;
293
294 /* vqmmc */
295 bool vqmmc_enabled;
296 };
297
298 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
299 {
300 unsigned long expire = jiffies + msecs_to_jiffies(250);
301 u32 rval;
302
303 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
304 do {
305 rval = mmc_readl(host, REG_GCTRL);
306 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
307
308 if (rval & SDXC_HARDWARE_RESET) {
309 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
310 return -EIO;
311 }
312
313 return 0;
314 }
315
316 static int sunxi_mmc_init_host(struct mmc_host *mmc)
317 {
318 u32 rval;
319 struct sunxi_mmc_host *host = mmc_priv(mmc);
320
321 if (sunxi_mmc_reset_host(host))
322 return -EIO;
323
324 /*
325 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
326 *
327 * TODO: sun9i has a larger FIFO and supports higher trigger values
328 */
329 mmc_writel(host, REG_FTRGL, 0x20070008);
330 /* Maximum timeout value */
331 mmc_writel(host, REG_TMOUT, 0xffffffff);
332 /* Unmask SDIO interrupt if needed */
333 mmc_writel(host, REG_IMASK, host->sdio_imask);
334 /* Clear all pending interrupts */
335 mmc_writel(host, REG_RINTR, 0xffffffff);
336 /* Debug register? undocumented */
337 mmc_writel(host, REG_DBGC, 0xdeb);
338 /* Enable CEATA support */
339 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
340 /* Set DMA descriptor list base address */
341 mmc_writel(host, REG_DLBA, host->sg_dma);
342
343 rval = mmc_readl(host, REG_GCTRL);
344 rval |= SDXC_INTERRUPT_ENABLE_BIT;
345 /* Undocumented, but found in Allwinner code */
346 rval &= ~SDXC_ACCESS_DONE_DIRECT;
347 mmc_writel(host, REG_GCTRL, rval);
348
349 return 0;
350 }
351
352 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
353 struct mmc_data *data)
354 {
355 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
356 dma_addr_t next_desc = host->sg_dma;
357 int i, max_len = (1 << host->cfg->idma_des_size_bits);
358
359 for (i = 0; i < data->sg_len; i++) {
360 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
361 SDXC_IDMAC_DES0_OWN |
362 SDXC_IDMAC_DES0_DIC);
363
364 if (data->sg[i].length == max_len)
365 pdes[i].buf_size = 0; /* 0 == max_len */
366 else
367 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
368
369 next_desc += sizeof(struct sunxi_idma_des);
370 pdes[i].buf_addr_ptr1 =
371 cpu_to_le32(sg_dma_address(&data->sg[i]));
372 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
373 }
374
375 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
376 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
377 SDXC_IDMAC_DES0_ER);
378 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
379 pdes[i - 1].buf_addr_ptr2 = 0;
380
381 /*
382 * Avoid the io-store starting the idmac hitting io-mem before the
383 * descriptors hit the main-mem.
384 */
385 wmb();
386 }
387
388 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
389 struct mmc_data *data)
390 {
391 u32 i, dma_len;
392 struct scatterlist *sg;
393
394 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
395 mmc_get_dma_dir(data));
396 if (dma_len == 0) {
397 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
398 return -ENOMEM;
399 }
400
401 for_each_sg(data->sg, sg, data->sg_len, i) {
402 if (sg->offset & 3 || sg->length & 3) {
403 dev_err(mmc_dev(host->mmc),
404 "unaligned scatterlist: os %x length %d\n",
405 sg->offset, sg->length);
406 return -EINVAL;
407 }
408 }
409
410 return 0;
411 }
412
413 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
414 struct mmc_data *data)
415 {
416 u32 rval;
417
418 sunxi_mmc_init_idma_des(host, data);
419
420 rval = mmc_readl(host, REG_GCTRL);
421 rval |= SDXC_DMA_ENABLE_BIT;
422 mmc_writel(host, REG_GCTRL, rval);
423 rval |= SDXC_DMA_RESET;
424 mmc_writel(host, REG_GCTRL, rval);
425
426 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
427
428 if (!(data->flags & MMC_DATA_WRITE))
429 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
430
431 mmc_writel(host, REG_DMAC,
432 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
433 }
434
435 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
436 struct mmc_request *req)
437 {
438 u32 arg, cmd_val, ri;
439 unsigned long expire = jiffies + msecs_to_jiffies(1000);
440
441 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
442 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
443
444 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
445 cmd_val |= SD_IO_RW_DIRECT;
446 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
447 ((req->cmd->arg >> 28) & 0x7);
448 } else {
449 cmd_val |= MMC_STOP_TRANSMISSION;
450 arg = 0;
451 }
452
453 mmc_writel(host, REG_CARG, arg);
454 mmc_writel(host, REG_CMDR, cmd_val);
455
456 do {
457 ri = mmc_readl(host, REG_RINTR);
458 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
459 time_before(jiffies, expire));
460
461 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
462 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
463 if (req->stop)
464 req->stop->resp[0] = -ETIMEDOUT;
465 } else {
466 if (req->stop)
467 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
468 }
469
470 mmc_writel(host, REG_RINTR, 0xffff);
471 }
472
473 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
474 {
475 struct mmc_command *cmd = host->mrq->cmd;
476 struct mmc_data *data = host->mrq->data;
477
478 /* For some cmds timeout is normal with sd/mmc cards */
479 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
480 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
481 cmd->opcode == SD_IO_RW_DIRECT))
482 return;
483
484 dev_dbg(mmc_dev(host->mmc),
485 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
486 host->mmc->index, cmd->opcode,
487 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
488 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
489 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
490 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
491 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
492 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
493 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
494 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
495 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
496 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
497 );
498 }
499
500 /* Called in interrupt context! */
501 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
502 {
503 struct mmc_request *mrq = host->mrq;
504 struct mmc_data *data = mrq->data;
505 u32 rval;
506
507 mmc_writel(host, REG_IMASK, host->sdio_imask);
508 mmc_writel(host, REG_IDIE, 0);
509
510 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
511 sunxi_mmc_dump_errinfo(host);
512 mrq->cmd->error = -ETIMEDOUT;
513
514 if (data) {
515 data->error = -ETIMEDOUT;
516 host->manual_stop_mrq = mrq;
517 }
518
519 if (mrq->stop)
520 mrq->stop->error = -ETIMEDOUT;
521 } else {
522 if (mrq->cmd->flags & MMC_RSP_136) {
523 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
524 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
525 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
526 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
527 } else {
528 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
529 }
530
531 if (data)
532 data->bytes_xfered = data->blocks * data->blksz;
533 }
534
535 if (data) {
536 mmc_writel(host, REG_IDST, 0x337);
537 mmc_writel(host, REG_DMAC, 0);
538 rval = mmc_readl(host, REG_GCTRL);
539 rval |= SDXC_DMA_RESET;
540 mmc_writel(host, REG_GCTRL, rval);
541 rval &= ~SDXC_DMA_ENABLE_BIT;
542 mmc_writel(host, REG_GCTRL, rval);
543 rval |= SDXC_FIFO_RESET;
544 mmc_writel(host, REG_GCTRL, rval);
545 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
546 mmc_get_dma_dir(data));
547 }
548
549 mmc_writel(host, REG_RINTR, 0xffff);
550
551 host->mrq = NULL;
552 host->int_sum = 0;
553 host->wait_dma = false;
554
555 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
556 }
557
558 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
559 {
560 struct sunxi_mmc_host *host = dev_id;
561 struct mmc_request *mrq;
562 u32 msk_int, idma_int;
563 bool finalize = false;
564 bool sdio_int = false;
565 irqreturn_t ret = IRQ_HANDLED;
566
567 spin_lock(&host->lock);
568
569 idma_int = mmc_readl(host, REG_IDST);
570 msk_int = mmc_readl(host, REG_MISTA);
571
572 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
573 host->mrq, msk_int, idma_int);
574
575 mrq = host->mrq;
576 if (mrq) {
577 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
578 host->wait_dma = false;
579
580 host->int_sum |= msk_int;
581
582 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
583 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
584 !(host->int_sum & SDXC_COMMAND_DONE))
585 mmc_writel(host, REG_IMASK,
586 host->sdio_imask | SDXC_COMMAND_DONE);
587 /* Don't wait for dma on error */
588 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
589 finalize = true;
590 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
591 !host->wait_dma)
592 finalize = true;
593 }
594
595 if (msk_int & SDXC_SDIO_INTERRUPT)
596 sdio_int = true;
597
598 mmc_writel(host, REG_RINTR, msk_int);
599 mmc_writel(host, REG_IDST, idma_int);
600
601 if (finalize)
602 ret = sunxi_mmc_finalize_request(host);
603
604 spin_unlock(&host->lock);
605
606 if (finalize && ret == IRQ_HANDLED)
607 mmc_request_done(host->mmc, mrq);
608
609 if (sdio_int)
610 mmc_signal_sdio_irq(host->mmc);
611
612 return ret;
613 }
614
615 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
616 {
617 struct sunxi_mmc_host *host = dev_id;
618 struct mmc_request *mrq;
619 unsigned long iflags;
620
621 spin_lock_irqsave(&host->lock, iflags);
622 mrq = host->manual_stop_mrq;
623 spin_unlock_irqrestore(&host->lock, iflags);
624
625 if (!mrq) {
626 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
627 return IRQ_HANDLED;
628 }
629
630 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
631
632 /*
633 * We will never have more than one outstanding request,
634 * and we do not complete the request until after
635 * we've cleared host->manual_stop_mrq so we do not need to
636 * spin lock this function.
637 * Additionally we have wait states within this function
638 * so having it in a lock is a very bad idea.
639 */
640 sunxi_mmc_send_manual_stop(host, mrq);
641
642 spin_lock_irqsave(&host->lock, iflags);
643 host->manual_stop_mrq = NULL;
644 spin_unlock_irqrestore(&host->lock, iflags);
645
646 mmc_request_done(host->mmc, mrq);
647
648 return IRQ_HANDLED;
649 }
650
651 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
652 {
653 unsigned long expire = jiffies + msecs_to_jiffies(750);
654 u32 rval;
655
656 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
657 oclk_en ? "en" : "dis");
658
659 rval = mmc_readl(host, REG_CLKCR);
660 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
661
662 if (oclk_en)
663 rval |= SDXC_CARD_CLOCK_ON;
664 if (host->cfg->mask_data0)
665 rval |= SDXC_MASK_DATA0;
666
667 mmc_writel(host, REG_CLKCR, rval);
668
669 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
670 mmc_writel(host, REG_CMDR, rval);
671
672 do {
673 rval = mmc_readl(host, REG_CMDR);
674 } while (time_before(jiffies, expire) && (rval & SDXC_START));
675
676 /* clear irq status bits set by the command */
677 mmc_writel(host, REG_RINTR,
678 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
679
680 if (rval & SDXC_START) {
681 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
682 return -EIO;
683 }
684
685 if (host->cfg->mask_data0) {
686 rval = mmc_readl(host, REG_CLKCR);
687 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
688 }
689
690 return 0;
691 }
692
693 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
694 {
695 if (!host->cfg->can_calibrate)
696 return 0;
697
698 /*
699 * FIXME:
700 * This is not clear how the calibration is supposed to work
701 * yet. The best rate have been obtained by simply setting the
702 * delay to 0, as Allwinner does in its BSP.
703 *
704 * The only mode that doesn't have such a delay is HS400, that
705 * is in itself a TODO.
706 */
707 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
708
709 return 0;
710 }
711
712 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
713 struct mmc_ios *ios, u32 rate)
714 {
715 int index;
716
717 if (!host->cfg->clk_delays)
718 return 0;
719
720 /* determine delays */
721 if (rate <= 400000) {
722 index = SDXC_CLK_400K;
723 } else if (rate <= 25000000) {
724 index = SDXC_CLK_25M;
725 } else if (rate <= 52000000) {
726 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
727 ios->timing != MMC_TIMING_MMC_DDR52) {
728 index = SDXC_CLK_50M;
729 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
730 index = SDXC_CLK_50M_DDR_8BIT;
731 } else {
732 index = SDXC_CLK_50M_DDR;
733 }
734 } else {
735 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
736 return -EINVAL;
737 }
738
739 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
740 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
741
742 return 0;
743 }
744
745 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
746 struct mmc_ios *ios)
747 {
748 struct mmc_host *mmc = host->mmc;
749 long rate;
750 u32 rval, clock = ios->clock;
751 int ret;
752
753 ret = sunxi_mmc_oclk_onoff(host, 0);
754 if (ret)
755 return ret;
756
757 /* Our clock is gated now */
758 mmc->actual_clock = 0;
759
760 if (!ios->clock)
761 return 0;
762
763 /* 8 bit DDR requires a higher module clock */
764 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
765 ios->bus_width == MMC_BUS_WIDTH_8)
766 clock <<= 1;
767
768 rate = clk_round_rate(host->clk_mmc, clock);
769 if (rate < 0) {
770 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
771 clock, rate);
772 return rate;
773 }
774 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
775 clock, rate);
776
777 /* setting clock rate */
778 ret = clk_set_rate(host->clk_mmc, rate);
779 if (ret) {
780 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
781 rate, ret);
782 return ret;
783 }
784
785 /* clear internal divider */
786 rval = mmc_readl(host, REG_CLKCR);
787 rval &= ~0xff;
788 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
789 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
790 ios->bus_width == MMC_BUS_WIDTH_8) {
791 rval |= 1;
792 rate >>= 1;
793 }
794 mmc_writel(host, REG_CLKCR, rval);
795
796 if (host->cfg->needs_new_timings) {
797 /* Don't touch the delay bits */
798 rval = mmc_readl(host, REG_SD_NTSR);
799 rval |= SDXC_2X_TIMING_MODE;
800 mmc_writel(host, REG_SD_NTSR, rval);
801 }
802
803 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
804 if (ret)
805 return ret;
806
807 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
808 if (ret)
809 return ret;
810
811 /*
812 * FIXME:
813 *
814 * In HS400 we'll also need to calibrate the data strobe
815 * signal. This should only happen on the MMC2 controller (at
816 * least on the A64).
817 */
818
819 ret = sunxi_mmc_oclk_onoff(host, 1);
820 if (ret)
821 return ret;
822
823 /* And we just enabled our clock back */
824 mmc->actual_clock = rate;
825
826 return 0;
827 }
828
829 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
830 {
831 struct sunxi_mmc_host *host = mmc_priv(mmc);
832 u32 rval;
833
834 /* Set the power state */
835 switch (ios->power_mode) {
836 case MMC_POWER_ON:
837 break;
838
839 case MMC_POWER_UP:
840 if (!IS_ERR(mmc->supply.vmmc)) {
841 host->ferror = mmc_regulator_set_ocr(mmc,
842 mmc->supply.vmmc,
843 ios->vdd);
844 if (host->ferror)
845 return;
846 }
847
848 if (!IS_ERR(mmc->supply.vqmmc)) {
849 host->ferror = regulator_enable(mmc->supply.vqmmc);
850 if (host->ferror) {
851 dev_err(mmc_dev(mmc),
852 "failed to enable vqmmc\n");
853 return;
854 }
855 host->vqmmc_enabled = true;
856 }
857
858 host->ferror = sunxi_mmc_init_host(mmc);
859 if (host->ferror)
860 return;
861
862 dev_dbg(mmc_dev(mmc), "power on!\n");
863 break;
864
865 case MMC_POWER_OFF:
866 dev_dbg(mmc_dev(mmc), "power off!\n");
867 sunxi_mmc_reset_host(host);
868 if (!IS_ERR(mmc->supply.vmmc))
869 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
870
871 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
872 regulator_disable(mmc->supply.vqmmc);
873 host->vqmmc_enabled = false;
874 break;
875 }
876
877 /* set bus width */
878 switch (ios->bus_width) {
879 case MMC_BUS_WIDTH_1:
880 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
881 break;
882 case MMC_BUS_WIDTH_4:
883 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
884 break;
885 case MMC_BUS_WIDTH_8:
886 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
887 break;
888 }
889
890 /* set ddr mode */
891 rval = mmc_readl(host, REG_GCTRL);
892 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
893 ios->timing == MMC_TIMING_MMC_DDR52)
894 rval |= SDXC_DDR_MODE;
895 else
896 rval &= ~SDXC_DDR_MODE;
897 mmc_writel(host, REG_GCTRL, rval);
898
899 /* set up clock */
900 if (ios->power_mode) {
901 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
902 /* Android code had a usleep_range(50000, 55000); here */
903 }
904 }
905
906 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
907 {
908 /* vqmmc regulator is available */
909 if (!IS_ERR(mmc->supply.vqmmc))
910 return mmc_regulator_set_vqmmc(mmc, ios);
911
912 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
913 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
914 return 0;
915
916 return -EINVAL;
917 }
918
919 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
920 {
921 struct sunxi_mmc_host *host = mmc_priv(mmc);
922 unsigned long flags;
923 u32 imask;
924
925 spin_lock_irqsave(&host->lock, flags);
926
927 imask = mmc_readl(host, REG_IMASK);
928 if (enable) {
929 host->sdio_imask = SDXC_SDIO_INTERRUPT;
930 imask |= SDXC_SDIO_INTERRUPT;
931 } else {
932 host->sdio_imask = 0;
933 imask &= ~SDXC_SDIO_INTERRUPT;
934 }
935 mmc_writel(host, REG_IMASK, imask);
936 spin_unlock_irqrestore(&host->lock, flags);
937 }
938
939 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
940 {
941 struct sunxi_mmc_host *host = mmc_priv(mmc);
942 mmc_writel(host, REG_HWRST, 0);
943 udelay(10);
944 mmc_writel(host, REG_HWRST, 1);
945 udelay(300);
946 }
947
948 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
949 {
950 struct sunxi_mmc_host *host = mmc_priv(mmc);
951 struct mmc_command *cmd = mrq->cmd;
952 struct mmc_data *data = mrq->data;
953 unsigned long iflags;
954 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
955 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
956 bool wait_dma = host->wait_dma;
957 int ret;
958
959 /* Check for set_ios errors (should never happen) */
960 if (host->ferror) {
961 mrq->cmd->error = host->ferror;
962 mmc_request_done(mmc, mrq);
963 return;
964 }
965
966 if (data) {
967 ret = sunxi_mmc_map_dma(host, data);
968 if (ret < 0) {
969 dev_err(mmc_dev(mmc), "map DMA failed\n");
970 cmd->error = ret;
971 data->error = ret;
972 mmc_request_done(mmc, mrq);
973 return;
974 }
975 }
976
977 if (cmd->opcode == MMC_GO_IDLE_STATE) {
978 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
979 imask |= SDXC_COMMAND_DONE;
980 }
981
982 if (cmd->flags & MMC_RSP_PRESENT) {
983 cmd_val |= SDXC_RESP_EXPIRE;
984 if (cmd->flags & MMC_RSP_136)
985 cmd_val |= SDXC_LONG_RESPONSE;
986 if (cmd->flags & MMC_RSP_CRC)
987 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
988
989 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
990 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
991
992 if (cmd->data->stop) {
993 imask |= SDXC_AUTO_COMMAND_DONE;
994 cmd_val |= SDXC_SEND_AUTO_STOP;
995 } else {
996 imask |= SDXC_DATA_OVER;
997 }
998
999 if (cmd->data->flags & MMC_DATA_WRITE)
1000 cmd_val |= SDXC_WRITE;
1001 else
1002 wait_dma = true;
1003 } else {
1004 imask |= SDXC_COMMAND_DONE;
1005 }
1006 } else {
1007 imask |= SDXC_COMMAND_DONE;
1008 }
1009
1010 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1011 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1012 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1013
1014 spin_lock_irqsave(&host->lock, iflags);
1015
1016 if (host->mrq || host->manual_stop_mrq) {
1017 spin_unlock_irqrestore(&host->lock, iflags);
1018
1019 if (data)
1020 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1021 mmc_get_dma_dir(data));
1022
1023 dev_err(mmc_dev(mmc), "request already pending\n");
1024 mrq->cmd->error = -EBUSY;
1025 mmc_request_done(mmc, mrq);
1026 return;
1027 }
1028
1029 if (data) {
1030 mmc_writel(host, REG_BLKSZ, data->blksz);
1031 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1032 sunxi_mmc_start_dma(host, data);
1033 }
1034
1035 host->mrq = mrq;
1036 host->wait_dma = wait_dma;
1037 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1038 mmc_writel(host, REG_CARG, cmd->arg);
1039 mmc_writel(host, REG_CMDR, cmd_val);
1040
1041 spin_unlock_irqrestore(&host->lock, iflags);
1042 }
1043
1044 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1045 {
1046 struct sunxi_mmc_host *host = mmc_priv(mmc);
1047
1048 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1049 }
1050
1051 static struct mmc_host_ops sunxi_mmc_ops = {
1052 .request = sunxi_mmc_request,
1053 .set_ios = sunxi_mmc_set_ios,
1054 .get_ro = mmc_gpio_get_ro,
1055 .get_cd = mmc_gpio_get_cd,
1056 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1057 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1058 .hw_reset = sunxi_mmc_hw_reset,
1059 .card_busy = sunxi_mmc_card_busy,
1060 };
1061
1062 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1063 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1064 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1065 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1066 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1067 /* Value from A83T "new timing mode". Works but might not be right. */
1068 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1069 };
1070
1071 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1072 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1073 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1074 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1075 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1076 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1077 };
1078
1079 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1080 .idma_des_size_bits = 13,
1081 .clk_delays = NULL,
1082 .can_calibrate = false,
1083 };
1084
1085 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1086 .idma_des_size_bits = 16,
1087 .clk_delays = NULL,
1088 .can_calibrate = false,
1089 };
1090
1091 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1092 .idma_des_size_bits = 16,
1093 .clk_delays = sunxi_mmc_clk_delays,
1094 .can_calibrate = false,
1095 };
1096
1097 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1098 .idma_des_size_bits = 16,
1099 .clk_delays = sun9i_mmc_clk_delays,
1100 .can_calibrate = false,
1101 };
1102
1103 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1104 .idma_des_size_bits = 16,
1105 .clk_delays = NULL,
1106 .can_calibrate = true,
1107 .mask_data0 = true,
1108 .needs_new_timings = true,
1109 };
1110
1111 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1112 .idma_des_size_bits = 13,
1113 .clk_delays = NULL,
1114 .can_calibrate = true,
1115 };
1116
1117 static const struct of_device_id sunxi_mmc_of_match[] = {
1118 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1119 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1120 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1121 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1122 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1123 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1124 { /* sentinel */ }
1125 };
1126 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1127
1128 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1129 struct platform_device *pdev)
1130 {
1131 int ret;
1132
1133 host->cfg = of_device_get_match_data(&pdev->dev);
1134 if (!host->cfg)
1135 return -EINVAL;
1136
1137 ret = mmc_regulator_get_supply(host->mmc);
1138 if (ret) {
1139 if (ret != -EPROBE_DEFER)
1140 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1141 return ret;
1142 }
1143
1144 host->reg_base = devm_ioremap_resource(&pdev->dev,
1145 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1146 if (IS_ERR(host->reg_base))
1147 return PTR_ERR(host->reg_base);
1148
1149 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1150 if (IS_ERR(host->clk_ahb)) {
1151 dev_err(&pdev->dev, "Could not get ahb clock\n");
1152 return PTR_ERR(host->clk_ahb);
1153 }
1154
1155 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1156 if (IS_ERR(host->clk_mmc)) {
1157 dev_err(&pdev->dev, "Could not get mmc clock\n");
1158 return PTR_ERR(host->clk_mmc);
1159 }
1160
1161 if (host->cfg->clk_delays) {
1162 host->clk_output = devm_clk_get(&pdev->dev, "output");
1163 if (IS_ERR(host->clk_output)) {
1164 dev_err(&pdev->dev, "Could not get output clock\n");
1165 return PTR_ERR(host->clk_output);
1166 }
1167
1168 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1169 if (IS_ERR(host->clk_sample)) {
1170 dev_err(&pdev->dev, "Could not get sample clock\n");
1171 return PTR_ERR(host->clk_sample);
1172 }
1173 }
1174
1175 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1176 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1177 return PTR_ERR(host->reset);
1178
1179 ret = clk_prepare_enable(host->clk_ahb);
1180 if (ret) {
1181 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1182 return ret;
1183 }
1184
1185 ret = clk_prepare_enable(host->clk_mmc);
1186 if (ret) {
1187 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1188 goto error_disable_clk_ahb;
1189 }
1190
1191 ret = clk_prepare_enable(host->clk_output);
1192 if (ret) {
1193 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1194 goto error_disable_clk_mmc;
1195 }
1196
1197 ret = clk_prepare_enable(host->clk_sample);
1198 if (ret) {
1199 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1200 goto error_disable_clk_output;
1201 }
1202
1203 if (!IS_ERR(host->reset)) {
1204 ret = reset_control_deassert(host->reset);
1205 if (ret) {
1206 dev_err(&pdev->dev, "reset err %d\n", ret);
1207 goto error_disable_clk_sample;
1208 }
1209 }
1210
1211 /*
1212 * Sometimes the controller asserts the irq on boot for some reason,
1213 * make sure the controller is in a sane state before enabling irqs.
1214 */
1215 ret = sunxi_mmc_reset_host(host);
1216 if (ret)
1217 goto error_assert_reset;
1218
1219 host->irq = platform_get_irq(pdev, 0);
1220 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1221 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1222
1223 error_assert_reset:
1224 if (!IS_ERR(host->reset))
1225 reset_control_assert(host->reset);
1226 error_disable_clk_sample:
1227 clk_disable_unprepare(host->clk_sample);
1228 error_disable_clk_output:
1229 clk_disable_unprepare(host->clk_output);
1230 error_disable_clk_mmc:
1231 clk_disable_unprepare(host->clk_mmc);
1232 error_disable_clk_ahb:
1233 clk_disable_unprepare(host->clk_ahb);
1234 return ret;
1235 }
1236
1237 static int sunxi_mmc_probe(struct platform_device *pdev)
1238 {
1239 struct sunxi_mmc_host *host;
1240 struct mmc_host *mmc;
1241 int ret;
1242
1243 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1244 if (!mmc) {
1245 dev_err(&pdev->dev, "mmc alloc host failed\n");
1246 return -ENOMEM;
1247 }
1248
1249 host = mmc_priv(mmc);
1250 host->mmc = mmc;
1251 spin_lock_init(&host->lock);
1252
1253 ret = sunxi_mmc_resource_request(host, pdev);
1254 if (ret)
1255 goto error_free_host;
1256
1257 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1258 &host->sg_dma, GFP_KERNEL);
1259 if (!host->sg_cpu) {
1260 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1261 ret = -ENOMEM;
1262 goto error_free_host;
1263 }
1264
1265 mmc->ops = &sunxi_mmc_ops;
1266 mmc->max_blk_count = 8192;
1267 mmc->max_blk_size = 4096;
1268 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1269 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1270 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1271 /* 400kHz ~ 52MHz */
1272 mmc->f_min = 400000;
1273 mmc->f_max = 52000000;
1274 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1275 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1276
1277 if (host->cfg->clk_delays)
1278 mmc->caps |= MMC_CAP_1_8V_DDR;
1279
1280 ret = mmc_of_parse(mmc);
1281 if (ret)
1282 goto error_free_dma;
1283
1284 ret = mmc_add_host(mmc);
1285 if (ret)
1286 goto error_free_dma;
1287
1288 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1289 platform_set_drvdata(pdev, mmc);
1290 return 0;
1291
1292 error_free_dma:
1293 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1294 error_free_host:
1295 mmc_free_host(mmc);
1296 return ret;
1297 }
1298
1299 static int sunxi_mmc_remove(struct platform_device *pdev)
1300 {
1301 struct mmc_host *mmc = platform_get_drvdata(pdev);
1302 struct sunxi_mmc_host *host = mmc_priv(mmc);
1303
1304 mmc_remove_host(mmc);
1305 disable_irq(host->irq);
1306 sunxi_mmc_reset_host(host);
1307
1308 if (!IS_ERR(host->reset))
1309 reset_control_assert(host->reset);
1310
1311 clk_disable_unprepare(host->clk_sample);
1312 clk_disable_unprepare(host->clk_output);
1313 clk_disable_unprepare(host->clk_mmc);
1314 clk_disable_unprepare(host->clk_ahb);
1315
1316 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1317 mmc_free_host(mmc);
1318
1319 return 0;
1320 }
1321
1322 static struct platform_driver sunxi_mmc_driver = {
1323 .driver = {
1324 .name = "sunxi-mmc",
1325 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1326 },
1327 .probe = sunxi_mmc_probe,
1328 .remove = sunxi_mmc_remove,
1329 };
1330 module_platform_driver(sunxi_mmc_driver);
1331
1332 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1335 MODULE_ALIAS("platform:sunxi-mmc");
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