2 * linux/drivers/mmc/imxmmc.c - Motorola i.MX MMCI driver
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
7 * derived from pxamci.c by Russell King
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 * Changed to conform redesigned i.MX scatter gather DMA interface
16 * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17 * Updated for 2.6.14 kernel
19 * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20 * Found and corrected problems in the write path
22 * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23 * The event handling rewritten right way in softirq.
24 * Added many ugly hacks and delays to overcome SDHC
29 #ifdef CONFIG_MMC_DEBUG
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/blkdev.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/protocol.h>
45 #include <linux/delay.h>
50 #include <asm/sizes.h>
51 #include <asm/arch/mmc.h>
52 #include <asm/arch/imx-dma.h>
56 #define DRIVER_NAME "imx-mmc"
58 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
59 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
60 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
70 volatile unsigned int imask
;
71 unsigned int power_mode
;
73 struct imxmmc_platform_data
*pdata
;
75 struct mmc_request
*req
;
76 struct mmc_command
*cmd
;
77 struct mmc_data
*data
;
79 struct timer_list timer
;
80 struct tasklet_struct tasklet
;
81 unsigned int status_reg
;
82 unsigned long pending_events
;
83 /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
85 unsigned int data_cnt
;
86 atomic_t stuck_timeout
;
88 unsigned int dma_nents
;
89 unsigned int dma_size
;
93 unsigned char actual_bus_width
;
96 #define IMXMCI_PEND_IRQ_b 0
97 #define IMXMCI_PEND_DMA_END_b 1
98 #define IMXMCI_PEND_DMA_ERR_b 2
99 #define IMXMCI_PEND_WAIT_RESP_b 3
100 #define IMXMCI_PEND_DMA_DATA_b 4
101 #define IMXMCI_PEND_CPU_DATA_b 5
102 #define IMXMCI_PEND_CARD_XCHG_b 6
103 #define IMXMCI_PEND_SET_INIT_b 7
104 #define IMXMCI_PEND_STARTED_b 8
106 #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
107 #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
108 #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
109 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
110 #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
111 #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
112 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
113 #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
114 #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
116 static void imxmci_stop_clock(struct imxmci_host
*host
)
119 MMC_STR_STP_CLK
&= ~STR_STP_CLK_START_CLK
;
122 MMC_STR_STP_CLK
|= STR_STP_CLK_STOP_CLK
;
124 if(!(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)) {
125 /* Check twice before cut */
126 if(!(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
))
132 dev_dbg(mmc_dev(host
->mmc
), "imxmci_stop_clock blocked, no luck\n");
135 static int imxmci_start_clock(struct imxmci_host
*host
)
137 unsigned int trials
= 0;
138 unsigned int delay_limit
= 128;
141 MMC_STR_STP_CLK
&= ~STR_STP_CLK_STOP_CLK
;
143 clear_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
);
146 * Command start of the clock, this usually succeeds in less
147 * then 6 delay loops, but during card detection (low clockrate)
148 * it takes up to 5000 delay loops and sometimes fails for the first time
150 MMC_STR_STP_CLK
|= STR_STP_CLK_START_CLK
;
153 unsigned int delay
= delay_limit
;
156 if(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)
157 /* Check twice before cut */
158 if(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)
161 if(test_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
))
165 local_irq_save(flags
);
167 * Ensure, that request is not doubled under all possible circumstances.
168 * It is possible, that cock running state is missed, because some other
169 * IRQ or schedule delays this function execution and the clocks has
170 * been already stopped by other means (response processing, SDHC HW)
172 if(!test_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
))
173 MMC_STR_STP_CLK
|= STR_STP_CLK_START_CLK
;
174 local_irq_restore(flags
);
176 } while(++trials
<256);
178 dev_err(mmc_dev(host
->mmc
), "imxmci_start_clock blocked, no luck\n");
183 static void imxmci_softreset(void)
186 MMC_STR_STP_CLK
= 0x8;
187 MMC_STR_STP_CLK
= 0xD;
188 MMC_STR_STP_CLK
= 0x5;
189 MMC_STR_STP_CLK
= 0x5;
190 MMC_STR_STP_CLK
= 0x5;
191 MMC_STR_STP_CLK
= 0x5;
192 MMC_STR_STP_CLK
= 0x5;
193 MMC_STR_STP_CLK
= 0x5;
194 MMC_STR_STP_CLK
= 0x5;
195 MMC_STR_STP_CLK
= 0x5;
202 static int imxmci_busy_wait_for_status(struct imxmci_host
*host
,
203 unsigned int *pstat
, unsigned int stat_mask
,
204 int timeout
, const char *where
)
207 while(!(*pstat
& stat_mask
)) {
209 if(loops
>= timeout
) {
210 dev_dbg(mmc_dev(host
->mmc
), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
211 where
, *pstat
, stat_mask
);
215 *pstat
|= MMC_STATUS
;
220 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
221 if(!(stat_mask
& STATUS_END_CMD_RESP
) || (host
->mmc
->ios
.clock
>=8000000))
222 dev_info(mmc_dev(host
->mmc
), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
223 loops
, where
, *pstat
, stat_mask
);
227 static void imxmci_setup_data(struct imxmci_host
*host
, struct mmc_data
*data
)
229 unsigned int nob
= data
->blocks
;
230 unsigned int blksz
= data
->blksz
;
231 unsigned int datasz
= nob
* blksz
;
234 if (data
->flags
& MMC_DATA_STREAM
)
238 data
->bytes_xfered
= 0;
244 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
245 * We are in big troubles for non-512 byte transfers according to note in the paragraph
246 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
247 * The situation is even more complex in reality. The SDHC in not able to handle wll
248 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
249 * This is required for SCR read at least.
252 host
->dma_size
= datasz
;
253 if (data
->flags
& MMC_DATA_READ
) {
254 host
->dma_dir
= DMA_FROM_DEVICE
;
256 /* Hack to enable read SCR */
262 host
->dma_dir
= DMA_TO_DEVICE
;
265 /* Convert back to virtual address */
266 host
->data_ptr
= (u16
*)(page_address(data
->sg
->page
) + data
->sg
->offset
);
269 clear_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
);
270 set_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
);
275 if (data
->flags
& MMC_DATA_READ
) {
276 host
->dma_dir
= DMA_FROM_DEVICE
;
277 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
278 data
->sg_len
, host
->dma_dir
);
280 imx_dma_setup_sg(host
->dma
, data
->sg
, data
->sg_len
, datasz
,
281 host
->res
->start
+ MMC_BUFFER_ACCESS_OFS
, DMA_MODE_READ
);
283 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
284 CCR(host
->dma
) = CCR_DMOD_LINEAR
| CCR_DSIZ_32
| CCR_SMOD_FIFO
| CCR_SSIZ_16
| CCR_REN
;
286 host
->dma_dir
= DMA_TO_DEVICE
;
288 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
289 data
->sg_len
, host
->dma_dir
);
291 imx_dma_setup_sg(host
->dma
, data
->sg
, data
->sg_len
, datasz
,
292 host
->res
->start
+ MMC_BUFFER_ACCESS_OFS
, DMA_MODE_WRITE
);
294 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
295 CCR(host
->dma
) = CCR_SMOD_LINEAR
| CCR_SSIZ_32
| CCR_DMOD_FIFO
| CCR_DSIZ_16
| CCR_REN
;
298 #if 1 /* This code is there only for consistency checking and can be disabled in future */
300 for(i
=0; i
<host
->dma_nents
; i
++)
301 host
->dma_size
+=data
->sg
[i
].length
;
303 if (datasz
> host
->dma_size
) {
304 dev_err(mmc_dev(host
->mmc
), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
305 datasz
, host
->dma_size
);
309 host
->dma_size
= datasz
;
313 if(host
->actual_bus_width
== MMC_BUS_WIDTH_4
)
314 BLR(host
->dma
) = 0; /* burst 64 byte read / 64 bytes write */
316 BLR(host
->dma
) = 16; /* burst 16 byte read / 16 bytes write */
318 RSSR(host
->dma
) = DMA_REQ_SDHC
;
320 set_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
);
321 clear_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
);
323 /* start DMA engine for read, write is delayed after initial response */
324 if (host
->dma_dir
== DMA_FROM_DEVICE
) {
325 imx_dma_enable(host
->dma
);
329 static void imxmci_start_cmd(struct imxmci_host
*host
, struct mmc_command
*cmd
, unsigned int cmdat
)
334 WARN_ON(host
->cmd
!= NULL
);
337 /* Ensure, that clock are stopped else command programming and start fails */
338 imxmci_stop_clock(host
);
340 if (cmd
->flags
& MMC_RSP_BUSY
)
341 cmdat
|= CMD_DAT_CONT_BUSY
;
343 switch (mmc_resp_type(cmd
)) {
344 case MMC_RSP_R1
: /* short CRC, OPCODE */
345 case MMC_RSP_R1B
:/* short CRC, OPCODE, BUSY */
346 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R1
;
348 case MMC_RSP_R2
: /* long 136 bit + CRC */
349 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R2
;
351 case MMC_RSP_R3
: /* short */
352 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R3
;
354 case MMC_RSP_R6
: /* short CRC */
355 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R6
;
361 if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
) )
362 cmdat
|= CMD_DAT_CONT_INIT
; /* This command needs init */
364 if ( host
->actual_bus_width
== MMC_BUS_WIDTH_4
)
365 cmdat
|= CMD_DAT_CONT_BUS_WIDTH_4
;
367 MMC_CMD
= cmd
->opcode
;
368 MMC_ARGH
= cmd
->arg
>> 16;
369 MMC_ARGL
= cmd
->arg
& 0xffff;
370 MMC_CMD_DAT_CONT
= cmdat
;
372 atomic_set(&host
->stuck_timeout
, 0);
373 set_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
);
376 imask
= IMXMCI_INT_MASK_DEFAULT
;
377 imask
&= ~INT_MASK_END_CMD_RES
;
378 if ( cmdat
& CMD_DAT_CONT_DATA_ENABLE
) {
379 /*imask &= ~INT_MASK_BUF_READY;*/
380 imask
&= ~INT_MASK_DATA_TRAN
;
381 if ( cmdat
& CMD_DAT_CONT_WRITE
)
382 imask
&= ~INT_MASK_WRITE_OP_DONE
;
383 if(test_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
))
384 imask
&= ~INT_MASK_BUF_READY
;
387 spin_lock_irqsave(&host
->lock
, flags
);
389 MMC_INT_MASK
= host
->imask
;
390 spin_unlock_irqrestore(&host
->lock
, flags
);
392 dev_dbg(mmc_dev(host
->mmc
), "CMD%02d (0x%02x) mask set to 0x%04x\n",
393 cmd
->opcode
, cmd
->opcode
, imask
);
395 imxmci_start_clock(host
);
398 static void imxmci_finish_request(struct imxmci_host
*host
, struct mmc_request
*req
)
402 spin_lock_irqsave(&host
->lock
, flags
);
404 host
->pending_events
&= ~(IMXMCI_PEND_WAIT_RESP_m
| IMXMCI_PEND_DMA_END_m
|
405 IMXMCI_PEND_DMA_DATA_m
| IMXMCI_PEND_CPU_DATA_m
);
407 host
->imask
= IMXMCI_INT_MASK_DEFAULT
;
408 MMC_INT_MASK
= host
->imask
;
410 spin_unlock_irqrestore(&host
->lock
, flags
);
415 mmc_request_done(host
->mmc
, req
);
418 static int imxmci_finish_data(struct imxmci_host
*host
, unsigned int stat
)
420 struct mmc_data
*data
= host
->data
;
423 if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)){
424 imx_dma_disable(host
->dma
);
425 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->dma_nents
,
429 if ( stat
& STATUS_ERR_MASK
) {
430 dev_dbg(mmc_dev(host
->mmc
), "request failed. status: 0x%08x\n",stat
);
431 if(stat
& (STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
))
432 data
->error
= MMC_ERR_BADCRC
;
433 else if(stat
& STATUS_TIME_OUT_READ
)
434 data
->error
= MMC_ERR_TIMEOUT
;
436 data
->error
= MMC_ERR_FAILED
;
438 data
->bytes_xfered
= host
->dma_size
;
441 data_error
= data
->error
;
448 static int imxmci_cmd_done(struct imxmci_host
*host
, unsigned int stat
)
450 struct mmc_command
*cmd
= host
->cmd
;
453 struct mmc_data
*data
= host
->data
;
460 if (stat
& STATUS_TIME_OUT_RESP
) {
461 dev_dbg(mmc_dev(host
->mmc
), "CMD TIMEOUT\n");
462 cmd
->error
= MMC_ERR_TIMEOUT
;
463 } else if (stat
& STATUS_RESP_CRC_ERR
&& cmd
->flags
& MMC_RSP_CRC
) {
464 dev_dbg(mmc_dev(host
->mmc
), "cmd crc error\n");
465 cmd
->error
= MMC_ERR_BADCRC
;
468 if(cmd
->flags
& MMC_RSP_PRESENT
) {
469 if(cmd
->flags
& MMC_RSP_136
) {
470 for (i
= 0; i
< 4; i
++) {
471 u32 a
= MMC_RES_FIFO
& 0xffff;
472 u32 b
= MMC_RES_FIFO
& 0xffff;
473 cmd
->resp
[i
] = a
<<16 | b
;
476 a
= MMC_RES_FIFO
& 0xffff;
477 b
= MMC_RES_FIFO
& 0xffff;
478 c
= MMC_RES_FIFO
& 0xffff;
479 cmd
->resp
[0] = a
<<24 | b
<<8 | c
>>8;
483 dev_dbg(mmc_dev(host
->mmc
), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
484 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2], cmd
->resp
[3], cmd
->error
);
486 if (data
&& (cmd
->error
== MMC_ERR_NONE
) && !(stat
& STATUS_ERR_MASK
)) {
487 if (host
->req
->data
->flags
& MMC_DATA_WRITE
) {
489 /* Wait for FIFO to be empty before starting DMA write */
492 if(imxmci_busy_wait_for_status(host
, &stat
,
494 40, "imxmci_cmd_done DMA WR") < 0) {
495 cmd
->error
= MMC_ERR_FIFO
;
496 imxmci_finish_data(host
, stat
);
498 imxmci_finish_request(host
, host
->req
);
499 dev_warn(mmc_dev(host
->mmc
), "STATUS = 0x%04x\n",
504 if(test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)) {
505 imx_dma_enable(host
->dma
);
509 struct mmc_request
*req
;
510 imxmci_stop_clock(host
);
514 imxmci_finish_data(host
, stat
);
517 imxmci_finish_request(host
, req
);
519 dev_warn(mmc_dev(host
->mmc
), "imxmci_cmd_done: no request to finish\n");
526 static int imxmci_data_done(struct imxmci_host
*host
, unsigned int stat
)
528 struct mmc_data
*data
= host
->data
;
534 data_error
= imxmci_finish_data(host
, stat
);
536 if (host
->req
->stop
) {
537 imxmci_stop_clock(host
);
538 imxmci_start_cmd(host
, host
->req
->stop
, 0);
540 struct mmc_request
*req
;
543 imxmci_finish_request(host
, req
);
545 dev_warn(mmc_dev(host
->mmc
), "imxmci_data_done: no request to finish\n");
552 static int imxmci_cpu_driven_data(struct imxmci_host
*host
, unsigned int *pstat
)
558 unsigned int stat
= *pstat
;
560 if(host
->actual_bus_width
!= MMC_BUS_WIDTH_4
)
565 /* This is unfortunately required */
566 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
569 if(host
->dma_dir
== DMA_FROM_DEVICE
) {
570 imxmci_busy_wait_for_status(host
, &stat
,
571 STATUS_APPL_BUFF_FF
| STATUS_DATA_TRANS_DONE
,
572 20, "imxmci_cpu_driven_data read");
574 while((stat
& (STATUS_APPL_BUFF_FF
| STATUS_DATA_TRANS_DONE
)) &&
575 (host
->data_cnt
< host
->dma_size
)) {
576 if(burst_len
>= host
->dma_size
- host
->data_cnt
) {
577 flush_len
= burst_len
;
578 burst_len
= host
->dma_size
- host
->data_cnt
;
579 flush_len
-= burst_len
;
580 host
->data_cnt
= host
->dma_size
;
584 host
->data_cnt
+= burst_len
;
587 for(i
= burst_len
; i
>=2 ; i
-=2) {
588 *(host
->data_ptr
++) = MMC_BUFFER_ACCESS
;
589 udelay(20); /* required for clocks < 8MHz*/
593 *(u8
*)(host
->data_ptr
) = MMC_BUFFER_ACCESS
;
597 /* Flush extra bytes from FIFO */
598 while(flush_len
&& !(stat
& STATUS_DATA_TRANS_DONE
)){
599 i
= MMC_BUFFER_ACCESS
;
601 stat
&= ~STATUS_CRC_READ_ERR
; /* Stupid but required there */
604 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data read burst %d STATUS = 0x%x\n",
608 imxmci_busy_wait_for_status(host
, &stat
,
610 20, "imxmci_cpu_driven_data write");
612 while((stat
& STATUS_APPL_BUFF_FE
) &&
613 (host
->data_cnt
< host
->dma_size
)) {
614 if(burst_len
>= host
->dma_size
- host
->data_cnt
) {
615 burst_len
= host
->dma_size
- host
->data_cnt
;
616 host
->data_cnt
= host
->dma_size
;
619 host
->data_cnt
+= burst_len
;
622 for(i
= burst_len
; i
>0 ; i
-=2)
623 MMC_BUFFER_ACCESS
= *(host
->data_ptr
++);
627 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
637 static void imxmci_dma_irq(int dma
, void *devid
, struct pt_regs
*regs
)
639 struct imxmci_host
*host
= devid
;
640 uint32_t stat
= MMC_STATUS
;
642 atomic_set(&host
->stuck_timeout
, 0);
643 host
->status_reg
= stat
;
644 set_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
);
645 tasklet_schedule(&host
->tasklet
);
648 static irqreturn_t
imxmci_irq(int irq
, void *devid
, struct pt_regs
*regs
)
650 struct imxmci_host
*host
= devid
;
651 uint32_t stat
= MMC_STATUS
;
654 MMC_INT_MASK
= host
->imask
| INT_MASK_SDIO
| INT_MASK_AUTO_CARD_DETECT
;
656 atomic_set(&host
->stuck_timeout
, 0);
657 host
->status_reg
= stat
;
658 set_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
);
659 set_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
);
660 tasklet_schedule(&host
->tasklet
);
662 return IRQ_RETVAL(handled
);;
665 static void imxmci_tasklet_fnc(unsigned long data
)
667 struct imxmci_host
*host
= (struct imxmci_host
*)data
;
669 unsigned int data_dir_mask
= 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
672 if(atomic_read(&host
->stuck_timeout
) > 4) {
676 host
->status_reg
= stat
;
677 if (test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
678 if (test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
))
683 if (test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
))
684 if(test_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
))
691 dev_err(mmc_dev(host
->mmc
), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
692 what
, stat
, MMC_INT_MASK
);
693 dev_err(mmc_dev(host
->mmc
), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
694 MMC_CMD_DAT_CONT
, MMC_BLK_LEN
, MMC_NOB
, CCR(host
->dma
));
695 dev_err(mmc_dev(host
->mmc
), "CMD%d, bus %d-bit, dma_size = 0x%x\n",
696 host
->cmd
?host
->cmd
->opcode
:0, 1<<host
->actual_bus_width
, host
->dma_size
);
699 if(!host
->present
|| timeout
)
700 host
->status_reg
= STATUS_TIME_OUT_RESP
| STATUS_TIME_OUT_READ
|
701 STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
;
703 if(test_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
) || timeout
) {
704 clear_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
);
708 * This is not required in theory, but there is chance to miss some flag
709 * which clears automatically by mask write, FreeScale original code keeps
710 * stat from IRQ time so do I
712 stat
|= host
->status_reg
;
714 if(test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
)) {
715 imxmci_busy_wait_for_status(host
, &stat
,
716 STATUS_END_CMD_RESP
| STATUS_ERR_MASK
,
717 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
720 if(stat
& (STATUS_END_CMD_RESP
| STATUS_ERR_MASK
)) {
721 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
722 imxmci_cmd_done(host
, stat
);
723 if(host
->data
&& (stat
& STATUS_ERR_MASK
))
724 imxmci_data_done(host
, stat
);
727 if(test_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
)) {
729 if(imxmci_cpu_driven_data(host
, &stat
)){
730 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
731 imxmci_cmd_done(host
, stat
);
732 atomic_clear_mask(IMXMCI_PEND_IRQ_m
|IMXMCI_PEND_CPU_DATA_m
,
733 &host
->pending_events
);
734 imxmci_data_done(host
, stat
);
739 if(test_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
) &&
740 !test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
)) {
744 stat
|= host
->status_reg
;
746 if(host
->dma_dir
== DMA_TO_DEVICE
) {
747 data_dir_mask
= STATUS_WRITE_OP_DONE
;
749 data_dir_mask
= STATUS_DATA_TRANS_DONE
;
752 if(stat
& data_dir_mask
) {
753 clear_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
);
754 imxmci_data_done(host
, stat
);
758 if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b
, &host
->pending_events
)) {
761 imxmci_cmd_done(host
, STATUS_TIME_OUT_RESP
);
764 imxmci_data_done(host
, STATUS_TIME_OUT_READ
|
765 STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
);
768 imxmci_finish_request(host
, host
->req
);
770 mmc_detect_change(host
->mmc
, msecs_to_jiffies(100));
775 static void imxmci_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
777 struct imxmci_host
*host
= mmc_priv(mmc
);
780 WARN_ON(host
->req
!= NULL
);
787 imxmci_setup_data(host
, req
->data
);
789 cmdat
|= CMD_DAT_CONT_DATA_ENABLE
;
791 if (req
->data
->flags
& MMC_DATA_WRITE
)
792 cmdat
|= CMD_DAT_CONT_WRITE
;
794 if (req
->data
->flags
& MMC_DATA_STREAM
) {
795 cmdat
|= CMD_DAT_CONT_STREAM_BLOCK
;
799 imxmci_start_cmd(host
, req
->cmd
, cmdat
);
802 #define CLK_RATE 19200000
804 static void imxmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
806 struct imxmci_host
*host
= mmc_priv(mmc
);
809 if( ios
->bus_width
==MMC_BUS_WIDTH_4
) {
810 host
->actual_bus_width
= MMC_BUS_WIDTH_4
;
811 imx_gpio_mode(PB11_PF_SD_DAT3
);
813 host
->actual_bus_width
= MMC_BUS_WIDTH_1
;
814 imx_gpio_mode(GPIO_PORTB
| GPIO_IN
| GPIO_PUEN
| 11);
817 if ( host
->power_mode
!= ios
->power_mode
) {
818 switch (ios
->power_mode
) {
822 set_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
);
827 host
->power_mode
= ios
->power_mode
;
833 /* The prescaler is 5 for PERCLK2 equal to 96MHz
834 * then 96MHz / 5 = 19.2 MHz
836 clk
=imx_get_perclk2();
837 prescaler
=(clk
+(CLK_RATE
*7)/8)/CLK_RATE
;
840 case 1: prescaler
= 0;
842 case 2: prescaler
= 1;
844 case 3: prescaler
= 2;
846 case 4: prescaler
= 4;
849 case 5: prescaler
= 5;
853 dev_dbg(mmc_dev(host
->mmc
), "PERCLK2 %d MHz -> prescaler %d\n",
856 for(clk
=0; clk
<8; clk
++) {
858 x
= CLK_RATE
/ (1<<clk
);
863 MMC_STR_STP_CLK
|= STR_STP_CLK_ENABLE
; /* enable controller */
865 imxmci_stop_clock(host
);
866 MMC_CLK_RATE
= (prescaler
<<3) | clk
;
868 * Under my understanding, clock should not be started there, because it would
869 * initiate SDHC sequencer and send last or random command into card
871 /*imxmci_start_clock(host);*/
873 dev_dbg(mmc_dev(host
->mmc
), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE
);
875 imxmci_stop_clock(host
);
879 static struct mmc_host_ops imxmci_ops
= {
880 .request
= imxmci_request
,
881 .set_ios
= imxmci_set_ios
,
884 static struct resource
*platform_device_resource(struct platform_device
*dev
, unsigned int mask
, int nr
)
888 for (i
= 0; i
< dev
->num_resources
; i
++)
889 if (dev
->resource
[i
].flags
== mask
&& nr
-- == 0)
890 return &dev
->resource
[i
];
894 static int platform_device_irq(struct platform_device
*dev
, int nr
)
898 for (i
= 0; i
< dev
->num_resources
; i
++)
899 if (dev
->resource
[i
].flags
== IORESOURCE_IRQ
&& nr
-- == 0)
900 return dev
->resource
[i
].start
;
904 static void imxmci_check_status(unsigned long data
)
906 struct imxmci_host
*host
= (struct imxmci_host
*)data
;
908 if( host
->pdata
->card_present() != host
->present
) {
910 dev_info(mmc_dev(host
->mmc
), "card %s\n",
911 host
->present
? "inserted" : "removed");
913 set_bit(IMXMCI_PEND_CARD_XCHG_b
, &host
->pending_events
);
914 tasklet_schedule(&host
->tasklet
);
917 if(test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
) ||
918 test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)) {
919 atomic_inc(&host
->stuck_timeout
);
920 if(atomic_read(&host
->stuck_timeout
) > 4)
921 tasklet_schedule(&host
->tasklet
);
923 atomic_set(&host
->stuck_timeout
, 0);
927 mod_timer(&host
->timer
, jiffies
+ (HZ
>>1));
930 static int imxmci_probe(struct platform_device
*pdev
)
932 struct mmc_host
*mmc
;
933 struct imxmci_host
*host
= NULL
;
937 printk(KERN_INFO
"i.MX mmc driver\n");
939 r
= platform_device_resource(pdev
, IORESOURCE_MEM
, 0);
940 irq
= platform_device_irq(pdev
, 0);
941 if (!r
|| irq
== NO_IRQ
)
944 r
= request_mem_region(r
->start
, 0x100, "IMXMCI");
948 mmc
= mmc_alloc_host(sizeof(struct imxmci_host
), &pdev
->dev
);
954 mmc
->ops
= &imxmci_ops
;
956 mmc
->f_max
= CLK_RATE
/2;
957 mmc
->ocr_avail
= MMC_VDD_32_33
;
958 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
960 /* MMC core transfer sizes tunable parameters */
961 mmc
->max_hw_segs
= 64;
962 mmc
->max_phys_segs
= 64;
963 mmc
->max_sectors
= 64; /* default 1 << (PAGE_CACHE_SHIFT - 9) */
964 mmc
->max_seg_size
= 64*512; /* default PAGE_CACHE_SIZE */
966 host
= mmc_priv(mmc
);
968 host
->dma_allocated
= 0;
969 host
->pdata
= pdev
->dev
.platform_data
;
971 spin_lock_init(&host
->lock
);
975 imx_gpio_mode(PB8_PF_SD_DAT0
);
976 imx_gpio_mode(PB9_PF_SD_DAT1
);
977 imx_gpio_mode(PB10_PF_SD_DAT2
);
978 /* Configured as GPIO with pull-up to ensure right MCC card mode */
979 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
980 imx_gpio_mode(GPIO_PORTB
| GPIO_IN
| GPIO_PUEN
| 11);
981 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
982 imx_gpio_mode(PB12_PF_SD_CLK
);
983 imx_gpio_mode(PB13_PF_SD_CMD
);
987 if ( MMC_REV_NO
!= 0x390 ) {
988 dev_err(mmc_dev(host
->mmc
), "wrong rev.no. 0x%08x. aborting.\n",
993 MMC_READ_TO
= 0x2db4; /* recommended in data sheet */
995 host
->imask
= IMXMCI_INT_MASK_DEFAULT
;
996 MMC_INT_MASK
= host
->imask
;
999 if(imx_dma_request_by_prio(&host
->dma
, DRIVER_NAME
, DMA_PRIO_LOW
)<0){
1000 dev_err(mmc_dev(host
->mmc
), "imx_dma_request_by_prio failed\n");
1004 host
->dma_allocated
=1;
1005 imx_dma_setup_handlers(host
->dma
, imxmci_dma_irq
, NULL
, host
);
1007 tasklet_init(&host
->tasklet
, imxmci_tasklet_fnc
, (unsigned long)host
);
1009 host
->pending_events
=0;
1011 ret
= request_irq(host
->irq
, imxmci_irq
, 0, DRIVER_NAME
, host
);
1015 host
->present
= host
->pdata
->card_present();
1016 init_timer(&host
->timer
);
1017 host
->timer
.data
= (unsigned long)host
;
1018 host
->timer
.function
= imxmci_check_status
;
1019 add_timer(&host
->timer
);
1020 mod_timer(&host
->timer
, jiffies
+ (HZ
>>1));
1022 platform_set_drvdata(pdev
, mmc
);
1030 if(host
->dma_allocated
){
1031 imx_dma_free(host
->dma
);
1032 host
->dma_allocated
=0;
1037 release_resource(r
);
1041 static int imxmci_remove(struct platform_device
*pdev
)
1043 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
1045 platform_set_drvdata(pdev
, NULL
);
1048 struct imxmci_host
*host
= mmc_priv(mmc
);
1050 tasklet_disable(&host
->tasklet
);
1052 del_timer_sync(&host
->timer
);
1053 mmc_remove_host(mmc
);
1055 free_irq(host
->irq
, host
);
1056 if(host
->dma_allocated
){
1057 imx_dma_free(host
->dma
);
1058 host
->dma_allocated
=0;
1061 tasklet_kill(&host
->tasklet
);
1063 release_resource(host
->res
);
1071 static int imxmci_suspend(struct platform_device
*dev
, pm_message_t state
)
1073 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
1077 ret
= mmc_suspend_host(mmc
, state
);
1082 static int imxmci_resume(struct platform_device
*dev
)
1084 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
1085 struct imxmci_host
*host
;
1089 host
= mmc_priv(mmc
);
1091 set_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
);
1092 ret
= mmc_resume_host(mmc
);
1098 #define imxmci_suspend NULL
1099 #define imxmci_resume NULL
1100 #endif /* CONFIG_PM */
1102 static struct platform_driver imxmci_driver
= {
1103 .probe
= imxmci_probe
,
1104 .remove
= imxmci_remove
,
1105 .suspend
= imxmci_suspend
,
1106 .resume
= imxmci_resume
,
1108 .name
= DRIVER_NAME
,
1112 static int __init
imxmci_init(void)
1114 return platform_driver_register(&imxmci_driver
);
1117 static void __exit
imxmci_exit(void)
1119 platform_driver_unregister(&imxmci_driver
);
1122 module_init(imxmci_init
);
1123 module_exit(imxmci_exit
);
1125 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1126 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1127 MODULE_LICENSE("GPL");