2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/flash.h>
31 #define FLASH_PAGESIZE 256
34 #define OPCODE_WREN 0x06 /* Write enable */
35 #define OPCODE_RDSR 0x05 /* Read status register */
36 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
37 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
38 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
39 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
40 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
41 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
42 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
44 /* Status Register bits. */
45 #define SR_WIP 1 /* Write in progress */
46 #define SR_WEL 2 /* Write enable latch */
47 /* meaning of other SR_* bits may differ between vendors */
48 #define SR_BP0 4 /* Block protect 0 */
49 #define SR_BP1 8 /* Block protect 1 */
50 #define SR_BP2 0x10 /* Block protect 2 */
51 #define SR_SRWD 0x80 /* SR write protect */
53 /* Define max times to check status register before we give up. */
54 #define MAX_READY_WAIT_COUNT 100000
57 #ifdef CONFIG_M25PXX_USE_FAST_READ
58 #define OPCODE_READ OPCODE_FAST_READ
59 #define FAST_READ_DUMMY_BYTE 1
61 #define OPCODE_READ OPCODE_NORM_READ
62 #define FAST_READ_DUMMY_BYTE 0
65 #ifdef CONFIG_MTD_PARTITIONS
66 #define mtd_has_partitions() (1)
68 #define mtd_has_partitions() (0)
71 /****************************************************************************/
74 struct spi_device
*spi
;
77 unsigned partitioned
:1;
79 u8 command
[CMD_SIZE
+ FAST_READ_DUMMY_BYTE
];
82 static inline struct m25p
*mtd_to_m25p(struct mtd_info
*mtd
)
84 return container_of(mtd
, struct m25p
, mtd
);
87 /****************************************************************************/
90 * Internal helper functions
94 * Read the status register, returning its value in the location
95 * Return the status register value.
96 * Returns negative if error occurred.
98 static int read_sr(struct m25p
*flash
)
101 u8 code
= OPCODE_RDSR
;
104 retval
= spi_write_then_read(flash
->spi
, &code
, 1, &val
, 1);
107 dev_err(&flash
->spi
->dev
, "error %d reading SR\n",
117 * Set write enable latch with Write Enable command.
118 * Returns negative if error occurred.
120 static inline int write_enable(struct m25p
*flash
)
122 u8 code
= OPCODE_WREN
;
124 return spi_write_then_read(flash
->spi
, &code
, 1, NULL
, 0);
129 * Service routine to read status register until ready, or timeout occurs.
130 * Returns non-zero if error.
132 static int wait_till_ready(struct m25p
*flash
)
137 /* one chip guarantees max 5 msec wait here after page writes,
138 * but potentially three seconds (!) after page erase.
140 for (count
= 0; count
< MAX_READY_WAIT_COUNT
; count
++) {
141 if ((sr
= read_sr(flash
)) < 0)
143 else if (!(sr
& SR_WIP
))
146 /* REVISIT sometimes sleeping would be best */
154 * Erase one sector of flash memory at offset ``offset'' which is any
155 * address within the sector which should be erased.
157 * Returns 0 if successful, non-zero otherwise.
159 static int erase_sector(struct m25p
*flash
, u32 offset
)
161 DEBUG(MTD_DEBUG_LEVEL3
, "%s: %s %dKiB at 0x%08x\n",
162 flash
->spi
->dev
.bus_id
, __func__
,
163 flash
->mtd
.erasesize
/ 1024, offset
);
165 /* Wait until finished previous write command. */
166 if (wait_till_ready(flash
))
169 /* Send write enable, then erase commands. */
172 /* Set up command buffer. */
173 flash
->command
[0] = flash
->erase_opcode
;
174 flash
->command
[1] = offset
>> 16;
175 flash
->command
[2] = offset
>> 8;
176 flash
->command
[3] = offset
;
178 spi_write(flash
->spi
, flash
->command
, CMD_SIZE
);
183 /****************************************************************************/
190 * Erase an address range on the flash chip. The address range may extend
191 * one or more erase sectors. Return an error is there is a problem erasing.
193 static int m25p80_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
195 struct m25p
*flash
= mtd_to_m25p(mtd
);
198 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%08x, len %d\n",
199 flash
->spi
->dev
.bus_id
, __func__
, "at",
200 (u32
)instr
->addr
, instr
->len
);
203 if (instr
->addr
+ instr
->len
> flash
->mtd
.size
)
205 if ((instr
->addr
% mtd
->erasesize
) != 0
206 || (instr
->len
% mtd
->erasesize
) != 0) {
213 mutex_lock(&flash
->lock
);
215 /* REVISIT in some cases we could speed up erasing large regions
216 * by using OPCODE_SE instead of OPCODE_BE_4K
219 /* now erase those sectors */
221 if (erase_sector(flash
, addr
)) {
222 instr
->state
= MTD_ERASE_FAILED
;
223 mutex_unlock(&flash
->lock
);
227 addr
+= mtd
->erasesize
;
228 len
-= mtd
->erasesize
;
231 mutex_unlock(&flash
->lock
);
233 instr
->state
= MTD_ERASE_DONE
;
234 mtd_erase_callback(instr
);
240 * Read an address range from the flash chip. The address range
241 * may be any size provided it is within the physical boundaries.
243 static int m25p80_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
244 size_t *retlen
, u_char
*buf
)
246 struct m25p
*flash
= mtd_to_m25p(mtd
);
247 struct spi_transfer t
[2];
248 struct spi_message m
;
250 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%08x, len %zd\n",
251 flash
->spi
->dev
.bus_id
, __func__
, "from",
258 if (from
+ len
> flash
->mtd
.size
)
261 spi_message_init(&m
);
262 memset(t
, 0, (sizeof t
));
265 * OPCODE_FAST_READ (if available) is faster.
266 * Should add 1 byte DUMMY_BYTE.
268 t
[0].tx_buf
= flash
->command
;
269 t
[0].len
= CMD_SIZE
+ FAST_READ_DUMMY_BYTE
;
270 spi_message_add_tail(&t
[0], &m
);
274 spi_message_add_tail(&t
[1], &m
);
276 /* Byte count starts at zero. */
280 mutex_lock(&flash
->lock
);
282 /* Wait till previous write/erase is done. */
283 if (wait_till_ready(flash
)) {
284 /* REVISIT status return?? */
285 mutex_unlock(&flash
->lock
);
289 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
290 * clocks; and at this writing, every chip this driver handles
291 * supports that opcode.
294 /* Set up the write data buffer. */
295 flash
->command
[0] = OPCODE_READ
;
296 flash
->command
[1] = from
>> 16;
297 flash
->command
[2] = from
>> 8;
298 flash
->command
[3] = from
;
300 spi_sync(flash
->spi
, &m
);
302 *retlen
= m
.actual_length
- CMD_SIZE
- FAST_READ_DUMMY_BYTE
;
304 mutex_unlock(&flash
->lock
);
310 * Write an address range to the flash chip. Data must be written in
311 * FLASH_PAGESIZE chunks. The address range may be any size provided
312 * it is within the physical boundaries.
314 static int m25p80_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
315 size_t *retlen
, const u_char
*buf
)
317 struct m25p
*flash
= mtd_to_m25p(mtd
);
318 u32 page_offset
, page_size
;
319 struct spi_transfer t
[2];
320 struct spi_message m
;
322 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%08x, len %zd\n",
323 flash
->spi
->dev
.bus_id
, __func__
, "to",
333 if (to
+ len
> flash
->mtd
.size
)
336 spi_message_init(&m
);
337 memset(t
, 0, (sizeof t
));
339 t
[0].tx_buf
= flash
->command
;
341 spi_message_add_tail(&t
[0], &m
);
344 spi_message_add_tail(&t
[1], &m
);
346 mutex_lock(&flash
->lock
);
348 /* Wait until finished previous write command. */
349 if (wait_till_ready(flash
)) {
350 mutex_unlock(&flash
->lock
);
356 /* Set up the opcode in the write buffer. */
357 flash
->command
[0] = OPCODE_PP
;
358 flash
->command
[1] = to
>> 16;
359 flash
->command
[2] = to
>> 8;
360 flash
->command
[3] = to
;
362 /* what page do we start with? */
363 page_offset
= to
% FLASH_PAGESIZE
;
365 /* do all the bytes fit onto one page? */
366 if (page_offset
+ len
<= FLASH_PAGESIZE
) {
369 spi_sync(flash
->spi
, &m
);
371 *retlen
= m
.actual_length
- CMD_SIZE
;
375 /* the size of data remaining on the first page */
376 page_size
= FLASH_PAGESIZE
- page_offset
;
378 t
[1].len
= page_size
;
379 spi_sync(flash
->spi
, &m
);
381 *retlen
= m
.actual_length
- CMD_SIZE
;
383 /* write everything in PAGESIZE chunks */
384 for (i
= page_size
; i
< len
; i
+= page_size
) {
386 if (page_size
> FLASH_PAGESIZE
)
387 page_size
= FLASH_PAGESIZE
;
389 /* write the next page to flash */
390 flash
->command
[1] = (to
+ i
) >> 16;
391 flash
->command
[2] = (to
+ i
) >> 8;
392 flash
->command
[3] = (to
+ i
);
394 t
[1].tx_buf
= buf
+ i
;
395 t
[1].len
= page_size
;
397 wait_till_ready(flash
);
401 spi_sync(flash
->spi
, &m
);
404 *retlen
+= m
.actual_length
- CMD_SIZE
;
408 mutex_unlock(&flash
->lock
);
414 /****************************************************************************/
417 * SPI device driver setup and teardown
423 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
424 * a high byte of zero plus three data bytes: the manufacturer id,
425 * then a two byte device id.
429 /* The size listed here is what works with OPCODE_SE, which isn't
430 * necessarily called a "sector" by the vendor.
432 unsigned sector_size
;
436 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
440 /* NOTE: double check command sets and memory organization when you add
441 * more flash chips. This current list focusses on newer chips, which
442 * have been converging on command sets which including JEDEC ID.
444 static struct flash_info __devinitdata m25p_data
[] = {
446 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
447 { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K
, },
448 { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K
, },
450 { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K
, },
451 { "at25df641", 0x1f4800, 64 * 1024, 128, SECT_4K
, },
453 { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K
, },
454 { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K
, },
455 { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K
, },
456 { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K
, },
458 /* Spansion -- single (large) sector size only, at least
459 * for the chips listed here (without boot sectors).
461 { "s25sl004a", 0x010212, 64 * 1024, 8, },
462 { "s25sl008a", 0x010213, 64 * 1024, 16, },
463 { "s25sl016a", 0x010214, 64 * 1024, 32, },
464 { "s25sl032a", 0x010215, 64 * 1024, 64, },
465 { "s25sl064a", 0x010216, 64 * 1024, 128, },
467 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
468 { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K
, },
469 { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K
, },
470 { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K
, },
471 { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K
, },
473 /* ST Microelectronics -- newer production may have feature updates */
474 { "m25p05", 0x202010, 32 * 1024, 2, },
475 { "m25p10", 0x202011, 32 * 1024, 4, },
476 { "m25p20", 0x202012, 64 * 1024, 4, },
477 { "m25p40", 0x202013, 64 * 1024, 8, },
478 { "m25p80", 0, 64 * 1024, 16, },
479 { "m25p16", 0x202015, 64 * 1024, 32, },
480 { "m25p32", 0x202016, 64 * 1024, 64, },
481 { "m25p64", 0x202017, 64 * 1024, 128, },
482 { "m25p128", 0x202018, 256 * 1024, 64, },
484 { "m45pe80", 0x204014, 64 * 1024, 16, },
485 { "m45pe16", 0x204015, 64 * 1024, 32, },
487 { "m25pe80", 0x208014, 64 * 1024, 16, },
488 { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K
, },
490 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
491 { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K
, },
492 { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K
, },
493 { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K
, },
494 { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K
, },
495 { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K
, },
496 { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K
, },
497 { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K
, },
500 static struct flash_info
*__devinit
jedec_probe(struct spi_device
*spi
)
503 u8 code
= OPCODE_RDID
;
506 struct flash_info
*info
;
508 /* JEDEC also defines an optional "extended device information"
509 * string for after vendor-specific data, after the three bytes
510 * we use here. Supporting some chips might require using it.
512 tmp
= spi_write_then_read(spi
, &code
, 1, id
, 3);
514 DEBUG(MTD_DEBUG_LEVEL0
, "%s: error %d reading JEDEC ID\n",
515 spi
->dev
.bus_id
, tmp
);
524 for (tmp
= 0, info
= m25p_data
;
525 tmp
< ARRAY_SIZE(m25p_data
);
527 if (info
->jedec_id
== jedec
)
530 dev_err(&spi
->dev
, "unrecognized JEDEC id %06x\n", jedec
);
536 * board specific setup should have ensured the SPI clock used here
537 * matches what the READ command supports, at least until this driver
538 * understands FAST_READ (for clocks over 25 MHz).
540 static int __devinit
m25p_probe(struct spi_device
*spi
)
542 struct flash_platform_data
*data
;
544 struct flash_info
*info
;
547 /* Platform data helps sort out which chip type we have, as
548 * well as how this board partitions it. If we don't have
549 * a chip ID, try the JEDEC id commands; they'll work for most
550 * newer chips, even if we don't recognize the particular chip.
552 data
= spi
->dev
.platform_data
;
553 if (data
&& data
->type
) {
554 for (i
= 0, info
= m25p_data
;
555 i
< ARRAY_SIZE(m25p_data
);
557 if (strcmp(data
->type
, info
->name
) == 0)
561 /* unrecognized chip? */
562 if (i
== ARRAY_SIZE(m25p_data
)) {
563 DEBUG(MTD_DEBUG_LEVEL0
, "%s: unrecognized id %s\n",
564 spi
->dev
.bus_id
, data
->type
);
567 /* recognized; is that chip really what's there? */
568 } else if (info
->jedec_id
) {
569 struct flash_info
*chip
= jedec_probe(spi
);
571 if (!chip
|| chip
!= info
) {
572 dev_warn(&spi
->dev
, "found %s, expected %s\n",
573 chip
? chip
->name
: "UNKNOWN",
579 info
= jedec_probe(spi
);
584 flash
= kzalloc(sizeof *flash
, GFP_KERNEL
);
589 mutex_init(&flash
->lock
);
590 dev_set_drvdata(&spi
->dev
, flash
);
592 if (data
&& data
->name
)
593 flash
->mtd
.name
= data
->name
;
595 flash
->mtd
.name
= spi
->dev
.bus_id
;
597 flash
->mtd
.type
= MTD_NORFLASH
;
598 flash
->mtd
.writesize
= 1;
599 flash
->mtd
.flags
= MTD_CAP_NORFLASH
;
600 flash
->mtd
.size
= info
->sector_size
* info
->n_sectors
;
601 flash
->mtd
.erase
= m25p80_erase
;
602 flash
->mtd
.read
= m25p80_read
;
603 flash
->mtd
.write
= m25p80_write
;
605 /* prefer "small sector" erase if possible */
606 if (info
->flags
& SECT_4K
) {
607 flash
->erase_opcode
= OPCODE_BE_4K
;
608 flash
->mtd
.erasesize
= 4096;
610 flash
->erase_opcode
= OPCODE_SE
;
611 flash
->mtd
.erasesize
= info
->sector_size
;
614 dev_info(&spi
->dev
, "%s (%d Kbytes)\n", info
->name
,
615 flash
->mtd
.size
/ 1024);
617 DEBUG(MTD_DEBUG_LEVEL2
,
618 "mtd .name = %s, .size = 0x%.8x (%uMiB) "
619 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
621 flash
->mtd
.size
, flash
->mtd
.size
/ (1024*1024),
622 flash
->mtd
.erasesize
, flash
->mtd
.erasesize
/ 1024,
623 flash
->mtd
.numeraseregions
);
625 if (flash
->mtd
.numeraseregions
)
626 for (i
= 0; i
< flash
->mtd
.numeraseregions
; i
++)
627 DEBUG(MTD_DEBUG_LEVEL2
,
628 "mtd.eraseregions[%d] = { .offset = 0x%.8x, "
629 ".erasesize = 0x%.8x (%uKiB), "
630 ".numblocks = %d }\n",
631 i
, flash
->mtd
.eraseregions
[i
].offset
,
632 flash
->mtd
.eraseregions
[i
].erasesize
,
633 flash
->mtd
.eraseregions
[i
].erasesize
/ 1024,
634 flash
->mtd
.eraseregions
[i
].numblocks
);
637 /* partitions should match sector boundaries; and it may be good to
638 * use readonly partitions for writeprotected sectors (BP2..BP0).
640 if (mtd_has_partitions()) {
641 struct mtd_partition
*parts
= NULL
;
644 #ifdef CONFIG_MTD_CMDLINE_PARTS
645 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
647 nr_parts
= parse_mtd_partitions(&flash
->mtd
,
648 part_probes
, &parts
, 0);
651 if (nr_parts
<= 0 && data
&& data
->parts
) {
653 nr_parts
= data
->nr_parts
;
657 for (i
= 0; i
< nr_parts
; i
++) {
658 DEBUG(MTD_DEBUG_LEVEL2
, "partitions[%d] = "
659 "{.name = %s, .offset = 0x%.8x, "
660 ".size = 0x%.8x (%uKiB) }\n",
664 parts
[i
].size
/ 1024);
666 flash
->partitioned
= 1;
667 return add_mtd_partitions(&flash
->mtd
, parts
, nr_parts
);
669 } else if (data
->nr_parts
)
670 dev_warn(&spi
->dev
, "ignoring %d default partitions on %s\n",
671 data
->nr_parts
, data
->name
);
673 return add_mtd_device(&flash
->mtd
) == 1 ? -ENODEV
: 0;
677 static int __devexit
m25p_remove(struct spi_device
*spi
)
679 struct m25p
*flash
= dev_get_drvdata(&spi
->dev
);
682 /* Clean up MTD stuff. */
683 if (mtd_has_partitions() && flash
->partitioned
)
684 status
= del_mtd_partitions(&flash
->mtd
);
686 status
= del_mtd_device(&flash
->mtd
);
693 static struct spi_driver m25p80_driver
= {
696 .bus
= &spi_bus_type
,
697 .owner
= THIS_MODULE
,
700 .remove
= __devexit_p(m25p_remove
),
702 /* REVISIT: many of these chips have deep power-down modes, which
703 * should clearly be entered on suspend() to minimize power use.
704 * And also when they're otherwise idle...
709 static int m25p80_init(void)
711 return spi_register_driver(&m25p80_driver
);
715 static void m25p80_exit(void)
717 spi_unregister_driver(&m25p80_driver
);
721 module_init(m25p80_init
);
722 module_exit(m25p80_exit
);
724 MODULE_LICENSE("GPL");
725 MODULE_AUTHOR("Mike Lavender");
726 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");