3 * Copyright 2017 Free Electrons
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Derived from the atmel_nand.c driver which contained the following
10 * Copyright 2003 Rick Bronson
12 * Derived from drivers/mtd/nand/autcpu12.c
13 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
15 * Derived from drivers/mtd/spia.c
16 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * Copyright 2012 ATMEL, Hong Xu
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
36 * A few words about the naming convention in this file. This convention
37 * applies to structure and function names.
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43 * (at91sam9 and avr32 SoCs)
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45 * (sama5 SoCs and later)
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47 * that is available in the HSMC block
48 * - <soc>_nand_: all SoC specific structures/functions
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio.h>
56 #include <linux/gpio/consumer.h>
57 #include <linux/interrupt.h>
58 #include <linux/mfd/syscon.h>
59 #include <linux/mfd/syscon/atmel-matrix.h>
60 #include <linux/mfd/syscon/atmel-smc.h>
61 #include <linux/module.h>
62 #include <linux/mtd/nand.h>
63 #include <linux/of_address.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_platform.h>
66 #include <linux/iopoll.h>
67 #include <linux/platform_device.h>
68 #include <linux/regmap.h>
72 #define ATMEL_HSMC_NFC_CFG 0x0
73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
77 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
79 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
80 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
84 #define ATMEL_HSMC_NFC_CTRL 0x4
85 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
86 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
88 #define ATMEL_HSMC_NFC_SR 0x8
89 #define ATMEL_HSMC_NFC_IER 0xc
90 #define ATMEL_HSMC_NFC_IDR 0x10
91 #define ATMEL_HSMC_NFC_IMR 0x14
92 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
93 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
94 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
95 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
96 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
97 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
98 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
99 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
100 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
101 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
102 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
103 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
104 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
105 ATMEL_HSMC_NFC_SR_UNDEF | \
106 ATMEL_HSMC_NFC_SR_AWB | \
107 ATMEL_HSMC_NFC_SR_NFCASE)
108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
110 #define ATMEL_HSMC_NFC_ADDR 0x18
111 #define ATMEL_HSMC_NFC_BANK 0x1c
113 #define ATMEL_NFC_MAX_RB_ID 7
115 #define ATMEL_NFC_SRAM_SIZE 0x2400
117 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
118 #define ATMEL_NFC_VCMD2 BIT(18)
119 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
120 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
121 #define ATMEL_NFC_DATAEN BIT(25)
122 #define ATMEL_NFC_NFCWR BIT(26)
124 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
126 #define ATMEL_NAND_ALE_OFFSET BIT(21)
127 #define ATMEL_NAND_CLE_OFFSET BIT(22)
129 #define DEFAULT_TIMEOUT_MS 1000
130 #define MIN_DMA_LEN 128
132 enum atmel_nand_rb_type
{
134 ATMEL_NAND_NATIVE_RB
,
138 struct atmel_nand_rb
{
139 enum atmel_nand_rb_type type
;
141 struct gpio_desc
*gpio
;
146 struct atmel_nand_cs
{
148 struct atmel_nand_rb rb
;
149 struct gpio_desc
*csgpio
;
155 struct atmel_smc_cs_conf smcconf
;
159 struct list_head node
;
161 struct nand_chip base
;
162 struct atmel_nand_cs
*activecs
;
163 struct atmel_pmecc_user
*pmecc
;
164 struct gpio_desc
*cdgpio
;
166 struct atmel_nand_cs cs
[];
169 static inline struct atmel_nand
*to_atmel_nand(struct nand_chip
*chip
)
171 return container_of(chip
, struct atmel_nand
, base
);
174 enum atmel_nfc_data_xfer
{
177 ATMEL_NFC_WRITE_DATA
,
180 struct atmel_nfc_op
{
186 enum atmel_nfc_data_xfer data
;
191 struct atmel_nand_controller
;
192 struct atmel_nand_controller_caps
;
194 struct atmel_nand_controller_ops
{
195 int (*probe
)(struct platform_device
*pdev
,
196 const struct atmel_nand_controller_caps
*caps
);
197 int (*remove
)(struct atmel_nand_controller
*nc
);
198 void (*nand_init
)(struct atmel_nand_controller
*nc
,
199 struct atmel_nand
*nand
);
200 int (*ecc_init
)(struct atmel_nand
*nand
);
201 int (*setup_data_interface
)(struct atmel_nand
*nand
, int csline
,
202 const struct nand_data_interface
*conf
);
205 struct atmel_nand_controller_caps
{
207 bool legacy_of_bindings
;
210 const struct atmel_nand_controller_ops
*ops
;
213 struct atmel_nand_controller
{
214 struct nand_hw_control base
;
215 const struct atmel_nand_controller_caps
*caps
;
218 struct dma_chan
*dmac
;
219 struct atmel_pmecc
*pmecc
;
220 struct list_head chips
;
224 static inline struct atmel_nand_controller
*
225 to_nand_controller(struct nand_hw_control
*ctl
)
227 return container_of(ctl
, struct atmel_nand_controller
, base
);
230 struct atmel_smc_nand_controller
{
231 struct atmel_nand_controller base
;
232 struct regmap
*matrix
;
233 unsigned int ebi_csa_offs
;
236 static inline struct atmel_smc_nand_controller
*
237 to_smc_nand_controller(struct nand_hw_control
*ctl
)
239 return container_of(to_nand_controller(ctl
),
240 struct atmel_smc_nand_controller
, base
);
243 struct atmel_hsmc_nand_controller
{
244 struct atmel_nand_controller base
;
246 struct gen_pool
*pool
;
251 struct atmel_nfc_op op
;
252 struct completion complete
;
255 /* Only used when instantiating from legacy DT bindings. */
259 static inline struct atmel_hsmc_nand_controller
*
260 to_hsmc_nand_controller(struct nand_hw_control
*ctl
)
262 return container_of(to_nand_controller(ctl
),
263 struct atmel_hsmc_nand_controller
, base
);
266 static bool atmel_nfc_op_done(struct atmel_nfc_op
*op
, u32 status
)
268 op
->errors
|= status
& ATMEL_HSMC_NFC_SR_ERRORS
;
269 op
->wait
^= status
& op
->wait
;
271 return !op
->wait
|| op
->errors
;
274 static irqreturn_t
atmel_nfc_interrupt(int irq
, void *data
)
276 struct atmel_hsmc_nand_controller
*nc
= data
;
280 regmap_read(nc
->base
.smc
, ATMEL_HSMC_NFC_SR
, &sr
);
282 rcvd
= sr
& (nc
->op
.wait
| ATMEL_HSMC_NFC_SR_ERRORS
);
283 done
= atmel_nfc_op_done(&nc
->op
, sr
);
286 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_IDR
, rcvd
);
289 complete(&nc
->complete
);
291 return rcvd
? IRQ_HANDLED
: IRQ_NONE
;
294 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller
*nc
, bool poll
,
295 unsigned int timeout_ms
)
300 timeout_ms
= DEFAULT_TIMEOUT_MS
;
305 ret
= regmap_read_poll_timeout(nc
->base
.smc
,
306 ATMEL_HSMC_NFC_SR
, status
,
307 atmel_nfc_op_done(&nc
->op
,
309 0, timeout_ms
* 1000);
311 init_completion(&nc
->complete
);
312 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_IER
,
313 nc
->op
.wait
| ATMEL_HSMC_NFC_SR_ERRORS
);
314 ret
= wait_for_completion_timeout(&nc
->complete
,
315 msecs_to_jiffies(timeout_ms
));
321 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_IDR
, 0xffffffff);
324 if (nc
->op
.errors
& ATMEL_HSMC_NFC_SR_DTOE
) {
325 dev_err(nc
->base
.dev
, "Waiting NAND R/B Timeout\n");
329 if (nc
->op
.errors
& ATMEL_HSMC_NFC_SR_UNDEF
) {
330 dev_err(nc
->base
.dev
, "Access to an undefined area\n");
334 if (nc
->op
.errors
& ATMEL_HSMC_NFC_SR_AWB
) {
335 dev_err(nc
->base
.dev
, "Access while busy\n");
339 if (nc
->op
.errors
& ATMEL_HSMC_NFC_SR_NFCASE
) {
340 dev_err(nc
->base
.dev
, "Wrong access size\n");
347 static void atmel_nand_dma_transfer_finished(void *data
)
349 struct completion
*finished
= data
;
354 static int atmel_nand_dma_transfer(struct atmel_nand_controller
*nc
,
355 void *buf
, dma_addr_t dev_dma
, size_t len
,
356 enum dma_data_direction dir
)
358 DECLARE_COMPLETION_ONSTACK(finished
);
359 dma_addr_t src_dma
, dst_dma
, buf_dma
;
360 struct dma_async_tx_descriptor
*tx
;
363 buf_dma
= dma_map_single(nc
->dev
, buf
, len
, dir
);
364 if (dma_mapping_error(nc
->dev
, dev_dma
)) {
366 "Failed to prepare a buffer for DMA access\n");
370 if (dir
== DMA_FROM_DEVICE
) {
378 tx
= dmaengine_prep_dma_memcpy(nc
->dmac
, dst_dma
, src_dma
, len
,
379 DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
);
381 dev_err(nc
->dev
, "Failed to prepare DMA memcpy\n");
385 tx
->callback
= atmel_nand_dma_transfer_finished
;
386 tx
->callback_param
= &finished
;
388 cookie
= dmaengine_submit(tx
);
389 if (dma_submit_error(cookie
)) {
390 dev_err(nc
->dev
, "Failed to do DMA tx_submit\n");
394 dma_async_issue_pending(nc
->dmac
);
395 wait_for_completion(&finished
);
400 dma_unmap_single(nc
->dev
, buf_dma
, len
, dir
);
403 dev_dbg(nc
->dev
, "Fall back to CPU I/O\n");
408 static u8
atmel_nand_read_byte(struct mtd_info
*mtd
)
410 struct nand_chip
*chip
= mtd_to_nand(mtd
);
411 struct atmel_nand
*nand
= to_atmel_nand(chip
);
413 return ioread8(nand
->activecs
->io
.virt
);
416 static u16
atmel_nand_read_word(struct mtd_info
*mtd
)
418 struct nand_chip
*chip
= mtd_to_nand(mtd
);
419 struct atmel_nand
*nand
= to_atmel_nand(chip
);
421 return ioread16(nand
->activecs
->io
.virt
);
424 static void atmel_nand_write_byte(struct mtd_info
*mtd
, u8 byte
)
426 struct nand_chip
*chip
= mtd_to_nand(mtd
);
427 struct atmel_nand
*nand
= to_atmel_nand(chip
);
429 if (chip
->options
& NAND_BUSWIDTH_16
)
430 iowrite16(byte
| (byte
<< 8), nand
->activecs
->io
.virt
);
432 iowrite8(byte
, nand
->activecs
->io
.virt
);
435 static void atmel_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
437 struct nand_chip
*chip
= mtd_to_nand(mtd
);
438 struct atmel_nand
*nand
= to_atmel_nand(chip
);
439 struct atmel_nand_controller
*nc
;
441 nc
= to_nand_controller(chip
->controller
);
444 * If the controller supports DMA, the buffer address is DMA-able and
445 * len is long enough to make DMA transfers profitable, let's trigger
446 * a DMA transfer. If it fails, fallback to PIO mode.
448 if (nc
->dmac
&& virt_addr_valid(buf
) &&
449 len
>= MIN_DMA_LEN
&&
450 !atmel_nand_dma_transfer(nc
, buf
, nand
->activecs
->io
.dma
, len
,
454 if (chip
->options
& NAND_BUSWIDTH_16
)
455 ioread16_rep(nand
->activecs
->io
.virt
, buf
, len
/ 2);
457 ioread8_rep(nand
->activecs
->io
.virt
, buf
, len
);
460 static void atmel_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
462 struct nand_chip
*chip
= mtd_to_nand(mtd
);
463 struct atmel_nand
*nand
= to_atmel_nand(chip
);
464 struct atmel_nand_controller
*nc
;
466 nc
= to_nand_controller(chip
->controller
);
469 * If the controller supports DMA, the buffer address is DMA-able and
470 * len is long enough to make DMA transfers profitable, let's trigger
471 * a DMA transfer. If it fails, fallback to PIO mode.
473 if (nc
->dmac
&& virt_addr_valid(buf
) &&
474 len
>= MIN_DMA_LEN
&&
475 !atmel_nand_dma_transfer(nc
, (void *)buf
, nand
->activecs
->io
.dma
,
479 if (chip
->options
& NAND_BUSWIDTH_16
)
480 iowrite16_rep(nand
->activecs
->io
.virt
, buf
, len
/ 2);
482 iowrite8_rep(nand
->activecs
->io
.virt
, buf
, len
);
485 static int atmel_nand_dev_ready(struct mtd_info
*mtd
)
487 struct nand_chip
*chip
= mtd_to_nand(mtd
);
488 struct atmel_nand
*nand
= to_atmel_nand(chip
);
490 return gpiod_get_value(nand
->activecs
->rb
.gpio
);
493 static void atmel_nand_select_chip(struct mtd_info
*mtd
, int cs
)
495 struct nand_chip
*chip
= mtd_to_nand(mtd
);
496 struct atmel_nand
*nand
= to_atmel_nand(chip
);
498 if (cs
< 0 || cs
>= nand
->numcs
) {
499 nand
->activecs
= NULL
;
500 chip
->dev_ready
= NULL
;
504 nand
->activecs
= &nand
->cs
[cs
];
506 if (nand
->activecs
->rb
.type
== ATMEL_NAND_GPIO_RB
)
507 chip
->dev_ready
= atmel_nand_dev_ready
;
510 static int atmel_hsmc_nand_dev_ready(struct mtd_info
*mtd
)
512 struct nand_chip
*chip
= mtd_to_nand(mtd
);
513 struct atmel_nand
*nand
= to_atmel_nand(chip
);
514 struct atmel_hsmc_nand_controller
*nc
;
517 nc
= to_hsmc_nand_controller(chip
->controller
);
519 regmap_read(nc
->base
.smc
, ATMEL_HSMC_NFC_SR
, &status
);
521 return status
& ATMEL_HSMC_NFC_SR_RBEDGE(nand
->activecs
->rb
.id
);
524 static void atmel_hsmc_nand_select_chip(struct mtd_info
*mtd
, int cs
)
526 struct nand_chip
*chip
= mtd_to_nand(mtd
);
527 struct atmel_nand
*nand
= to_atmel_nand(chip
);
528 struct atmel_hsmc_nand_controller
*nc
;
530 nc
= to_hsmc_nand_controller(chip
->controller
);
532 atmel_nand_select_chip(mtd
, cs
);
534 if (!nand
->activecs
) {
535 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_CTRL
,
536 ATMEL_HSMC_NFC_CTRL_DIS
);
540 if (nand
->activecs
->rb
.type
== ATMEL_NAND_NATIVE_RB
)
541 chip
->dev_ready
= atmel_hsmc_nand_dev_ready
;
543 regmap_update_bits(nc
->base
.smc
, ATMEL_HSMC_NFC_CFG
,
544 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK
|
545 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK
|
546 ATMEL_HSMC_NFC_CFG_RSPARE
|
547 ATMEL_HSMC_NFC_CFG_WSPARE
,
548 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd
->writesize
) |
549 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd
->oobsize
) |
550 ATMEL_HSMC_NFC_CFG_RSPARE
);
551 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_CTRL
,
552 ATMEL_HSMC_NFC_CTRL_EN
);
555 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller
*nc
, bool poll
)
557 u8
*addrs
= nc
->op
.addrs
;
562 nc
->op
.wait
= ATMEL_HSMC_NFC_SR_CMDDONE
;
564 for (i
= 0; i
< nc
->op
.ncmds
; i
++)
565 op
|= ATMEL_NFC_CMD(i
, nc
->op
.cmds
[i
]);
567 if (nc
->op
.naddrs
== ATMEL_NFC_MAX_ADDR_CYCLES
)
568 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_ADDR
, *addrs
++);
570 op
|= ATMEL_NFC_CSID(nc
->op
.cs
) |
571 ATMEL_NFC_ACYCLE(nc
->op
.naddrs
);
573 if (nc
->op
.ncmds
> 1)
574 op
|= ATMEL_NFC_VCMD2
;
576 addr
= addrs
[0] | (addrs
[1] << 8) | (addrs
[2] << 16) |
579 if (nc
->op
.data
!= ATMEL_NFC_NO_DATA
) {
580 op
|= ATMEL_NFC_DATAEN
;
581 nc
->op
.wait
|= ATMEL_HSMC_NFC_SR_XFRDONE
;
583 if (nc
->op
.data
== ATMEL_NFC_WRITE_DATA
)
584 op
|= ATMEL_NFC_NFCWR
;
587 /* Clear all flags. */
588 regmap_read(nc
->base
.smc
, ATMEL_HSMC_NFC_SR
, &val
);
590 /* Send the command. */
591 regmap_write(nc
->io
, op
, addr
);
593 ret
= atmel_nfc_wait(nc
, poll
, 0);
595 dev_err(nc
->base
.dev
,
596 "Failed to send NAND command (err = %d)!",
599 /* Reset the op state. */
600 memset(&nc
->op
, 0, sizeof(nc
->op
));
605 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info
*mtd
, int dat
,
608 struct nand_chip
*chip
= mtd_to_nand(mtd
);
609 struct atmel_nand
*nand
= to_atmel_nand(chip
);
610 struct atmel_hsmc_nand_controller
*nc
;
612 nc
= to_hsmc_nand_controller(chip
->controller
);
614 if (ctrl
& NAND_ALE
) {
615 if (nc
->op
.naddrs
== ATMEL_NFC_MAX_ADDR_CYCLES
)
618 nc
->op
.addrs
[nc
->op
.naddrs
++] = dat
;
619 } else if (ctrl
& NAND_CLE
) {
620 if (nc
->op
.ncmds
> 1)
623 nc
->op
.cmds
[nc
->op
.ncmds
++] = dat
;
626 if (dat
== NAND_CMD_NONE
) {
627 nc
->op
.cs
= nand
->activecs
->id
;
628 atmel_nfc_exec_op(nc
, true);
632 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
635 struct nand_chip
*chip
= mtd_to_nand(mtd
);
636 struct atmel_nand
*nand
= to_atmel_nand(chip
);
637 struct atmel_nand_controller
*nc
;
639 nc
= to_nand_controller(chip
->controller
);
641 if ((ctrl
& NAND_CTRL_CHANGE
) && nand
->activecs
->csgpio
) {
643 gpiod_set_value(nand
->activecs
->csgpio
, 0);
645 gpiod_set_value(nand
->activecs
->csgpio
, 1);
649 writeb(cmd
, nand
->activecs
->io
.virt
+ nc
->caps
->ale_offs
);
650 else if (ctrl
& NAND_CLE
)
651 writeb(cmd
, nand
->activecs
->io
.virt
+ nc
->caps
->cle_offs
);
654 static void atmel_nfc_copy_to_sram(struct nand_chip
*chip
, const u8
*buf
,
657 struct mtd_info
*mtd
= nand_to_mtd(chip
);
658 struct atmel_hsmc_nand_controller
*nc
;
661 nc
= to_hsmc_nand_controller(chip
->controller
);
664 ret
= atmel_nand_dma_transfer(&nc
->base
, (void *)buf
,
665 nc
->sram
.dma
, mtd
->writesize
,
668 /* Falling back to CPU copy. */
670 memcpy_toio(nc
->sram
.virt
, buf
, mtd
->writesize
);
673 memcpy_toio(nc
->sram
.virt
+ mtd
->writesize
, chip
->oob_poi
,
677 static void atmel_nfc_copy_from_sram(struct nand_chip
*chip
, u8
*buf
,
680 struct mtd_info
*mtd
= nand_to_mtd(chip
);
681 struct atmel_hsmc_nand_controller
*nc
;
684 nc
= to_hsmc_nand_controller(chip
->controller
);
687 ret
= atmel_nand_dma_transfer(&nc
->base
, buf
, nc
->sram
.dma
,
688 mtd
->writesize
, DMA_FROM_DEVICE
);
690 /* Falling back to CPU copy. */
692 memcpy_fromio(buf
, nc
->sram
.virt
, mtd
->writesize
);
695 memcpy_fromio(chip
->oob_poi
, nc
->sram
.virt
+ mtd
->writesize
,
699 static void atmel_nfc_set_op_addr(struct nand_chip
*chip
, int page
, int column
)
701 struct mtd_info
*mtd
= nand_to_mtd(chip
);
702 struct atmel_hsmc_nand_controller
*nc
;
704 nc
= to_hsmc_nand_controller(chip
->controller
);
707 nc
->op
.addrs
[nc
->op
.naddrs
++] = column
;
710 * 2 address cycles for the column offset on large page NANDs.
712 if (mtd
->writesize
> 512)
713 nc
->op
.addrs
[nc
->op
.naddrs
++] = column
>> 8;
717 nc
->op
.addrs
[nc
->op
.naddrs
++] = page
;
718 nc
->op
.addrs
[nc
->op
.naddrs
++] = page
>> 8;
720 if ((mtd
->writesize
> 512 && chip
->chipsize
> SZ_128M
) ||
721 (mtd
->writesize
<= 512 && chip
->chipsize
> SZ_32M
))
722 nc
->op
.addrs
[nc
->op
.naddrs
++] = page
>> 16;
726 static int atmel_nand_pmecc_enable(struct nand_chip
*chip
, int op
, bool raw
)
728 struct atmel_nand
*nand
= to_atmel_nand(chip
);
729 struct atmel_nand_controller
*nc
;
732 nc
= to_nand_controller(chip
->controller
);
737 ret
= atmel_pmecc_enable(nand
->pmecc
, op
);
740 "Failed to enable ECC engine (err = %d)\n", ret
);
745 static void atmel_nand_pmecc_disable(struct nand_chip
*chip
, bool raw
)
747 struct atmel_nand
*nand
= to_atmel_nand(chip
);
750 atmel_pmecc_disable(nand
->pmecc
);
753 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip
*chip
, bool raw
)
755 struct atmel_nand
*nand
= to_atmel_nand(chip
);
756 struct mtd_info
*mtd
= nand_to_mtd(chip
);
757 struct atmel_nand_controller
*nc
;
758 struct mtd_oob_region oobregion
;
762 nc
= to_nand_controller(chip
->controller
);
767 ret
= atmel_pmecc_wait_rdy(nand
->pmecc
);
770 "Failed to transfer NAND page data (err = %d)\n",
775 mtd_ooblayout_ecc(mtd
, 0, &oobregion
);
776 eccbuf
= chip
->oob_poi
+ oobregion
.offset
;
778 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
779 atmel_pmecc_get_generated_eccbytes(nand
->pmecc
, i
,
781 eccbuf
+= chip
->ecc
.bytes
;
787 static int atmel_nand_pmecc_correct_data(struct nand_chip
*chip
, void *buf
,
790 struct atmel_nand
*nand
= to_atmel_nand(chip
);
791 struct mtd_info
*mtd
= nand_to_mtd(chip
);
792 struct atmel_nand_controller
*nc
;
793 struct mtd_oob_region oobregion
;
794 int ret
, i
, max_bitflips
= 0;
795 void *databuf
, *eccbuf
;
797 nc
= to_nand_controller(chip
->controller
);
802 ret
= atmel_pmecc_wait_rdy(nand
->pmecc
);
805 "Failed to read NAND page data (err = %d)\n",
810 mtd_ooblayout_ecc(mtd
, 0, &oobregion
);
811 eccbuf
= chip
->oob_poi
+ oobregion
.offset
;
814 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
815 ret
= atmel_pmecc_correct_sector(nand
->pmecc
, i
, databuf
,
817 if (ret
< 0 && !atmel_pmecc_correct_erased_chunks(nand
->pmecc
))
818 ret
= nand_check_erased_ecc_chunk(databuf
,
826 max_bitflips
= max(ret
, max_bitflips
);
828 mtd
->ecc_stats
.failed
++;
830 databuf
+= chip
->ecc
.size
;
831 eccbuf
+= chip
->ecc
.bytes
;
837 static int atmel_nand_pmecc_write_pg(struct nand_chip
*chip
, const u8
*buf
,
838 bool oob_required
, int page
, bool raw
)
840 struct mtd_info
*mtd
= nand_to_mtd(chip
);
841 struct atmel_nand
*nand
= to_atmel_nand(chip
);
844 ret
= atmel_nand_pmecc_enable(chip
, NAND_ECC_WRITE
, raw
);
848 atmel_nand_write_buf(mtd
, buf
, mtd
->writesize
);
850 ret
= atmel_nand_pmecc_generate_eccbytes(chip
, raw
);
852 atmel_pmecc_disable(nand
->pmecc
);
856 atmel_nand_pmecc_disable(chip
, raw
);
858 atmel_nand_write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
863 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
864 struct nand_chip
*chip
, const u8
*buf
,
865 int oob_required
, int page
)
867 return atmel_nand_pmecc_write_pg(chip
, buf
, oob_required
, page
, false);
870 static int atmel_nand_pmecc_write_page_raw(struct mtd_info
*mtd
,
871 struct nand_chip
*chip
,
872 const u8
*buf
, int oob_required
,
875 return atmel_nand_pmecc_write_pg(chip
, buf
, oob_required
, page
, true);
878 static int atmel_nand_pmecc_read_pg(struct nand_chip
*chip
, u8
*buf
,
879 bool oob_required
, int page
, bool raw
)
881 struct mtd_info
*mtd
= nand_to_mtd(chip
);
884 ret
= atmel_nand_pmecc_enable(chip
, NAND_ECC_READ
, raw
);
888 atmel_nand_read_buf(mtd
, buf
, mtd
->writesize
);
889 atmel_nand_read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
891 ret
= atmel_nand_pmecc_correct_data(chip
, buf
, raw
);
893 atmel_nand_pmecc_disable(chip
, raw
);
898 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
899 struct nand_chip
*chip
, u8
*buf
,
900 int oob_required
, int page
)
902 return atmel_nand_pmecc_read_pg(chip
, buf
, oob_required
, page
, false);
905 static int atmel_nand_pmecc_read_page_raw(struct mtd_info
*mtd
,
906 struct nand_chip
*chip
, u8
*buf
,
907 int oob_required
, int page
)
909 return atmel_nand_pmecc_read_pg(chip
, buf
, oob_required
, page
, true);
912 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip
*chip
,
913 const u8
*buf
, bool oob_required
,
916 struct mtd_info
*mtd
= nand_to_mtd(chip
);
917 struct atmel_nand
*nand
= to_atmel_nand(chip
);
918 struct atmel_hsmc_nand_controller
*nc
;
921 nc
= to_hsmc_nand_controller(chip
->controller
);
923 atmel_nfc_copy_to_sram(chip
, buf
, false);
925 nc
->op
.cmds
[0] = NAND_CMD_SEQIN
;
927 atmel_nfc_set_op_addr(chip
, page
, 0x0);
928 nc
->op
.cs
= nand
->activecs
->id
;
929 nc
->op
.data
= ATMEL_NFC_WRITE_DATA
;
931 ret
= atmel_nand_pmecc_enable(chip
, NAND_ECC_WRITE
, raw
);
935 ret
= atmel_nfc_exec_op(nc
, false);
937 atmel_nand_pmecc_disable(chip
, raw
);
938 dev_err(nc
->base
.dev
,
939 "Failed to transfer NAND page data (err = %d)\n",
944 ret
= atmel_nand_pmecc_generate_eccbytes(chip
, raw
);
946 atmel_nand_pmecc_disable(chip
, raw
);
951 atmel_nand_write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
953 nc
->op
.cmds
[0] = NAND_CMD_PAGEPROG
;
955 nc
->op
.cs
= nand
->activecs
->id
;
956 ret
= atmel_nfc_exec_op(nc
, false);
958 dev_err(nc
->base
.dev
, "Failed to program NAND page (err = %d)\n",
961 status
= chip
->waitfunc(mtd
, chip
);
962 if (status
& NAND_STATUS_FAIL
)
968 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info
*mtd
,
969 struct nand_chip
*chip
,
970 const u8
*buf
, int oob_required
,
973 return atmel_hsmc_nand_pmecc_write_pg(chip
, buf
, oob_required
, page
,
977 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info
*mtd
,
978 struct nand_chip
*chip
,
980 int oob_required
, int page
)
982 return atmel_hsmc_nand_pmecc_write_pg(chip
, buf
, oob_required
, page
,
986 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip
*chip
, u8
*buf
,
987 bool oob_required
, int page
,
990 struct mtd_info
*mtd
= nand_to_mtd(chip
);
991 struct atmel_nand
*nand
= to_atmel_nand(chip
);
992 struct atmel_hsmc_nand_controller
*nc
;
995 nc
= to_hsmc_nand_controller(chip
->controller
);
998 * Optimized read page accessors only work when the NAND R/B pin is
999 * connected to a native SoC R/B pin. If that's not the case, fallback
1000 * to the non-optimized one.
1002 if (nand
->activecs
->rb
.type
!= ATMEL_NAND_NATIVE_RB
) {
1003 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1005 return atmel_nand_pmecc_read_pg(chip
, buf
, oob_required
, page
,
1009 nc
->op
.cmds
[nc
->op
.ncmds
++] = NAND_CMD_READ0
;
1011 if (mtd
->writesize
> 512)
1012 nc
->op
.cmds
[nc
->op
.ncmds
++] = NAND_CMD_READSTART
;
1014 atmel_nfc_set_op_addr(chip
, page
, 0x0);
1015 nc
->op
.cs
= nand
->activecs
->id
;
1016 nc
->op
.data
= ATMEL_NFC_READ_DATA
;
1018 ret
= atmel_nand_pmecc_enable(chip
, NAND_ECC_READ
, raw
);
1022 ret
= atmel_nfc_exec_op(nc
, false);
1024 atmel_nand_pmecc_disable(chip
, raw
);
1025 dev_err(nc
->base
.dev
,
1026 "Failed to load NAND page data (err = %d)\n",
1031 atmel_nfc_copy_from_sram(chip
, buf
, true);
1033 ret
= atmel_nand_pmecc_correct_data(chip
, buf
, raw
);
1035 atmel_nand_pmecc_disable(chip
, raw
);
1040 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info
*mtd
,
1041 struct nand_chip
*chip
, u8
*buf
,
1042 int oob_required
, int page
)
1044 return atmel_hsmc_nand_pmecc_read_pg(chip
, buf
, oob_required
, page
,
1048 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info
*mtd
,
1049 struct nand_chip
*chip
,
1050 u8
*buf
, int oob_required
,
1053 return atmel_hsmc_nand_pmecc_read_pg(chip
, buf
, oob_required
, page
,
1057 static int atmel_nand_pmecc_init(struct nand_chip
*chip
)
1059 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1060 struct atmel_nand
*nand
= to_atmel_nand(chip
);
1061 struct atmel_nand_controller
*nc
;
1062 struct atmel_pmecc_user_req req
;
1064 nc
= to_nand_controller(chip
->controller
);
1067 dev_err(nc
->dev
, "HW ECC not supported\n");
1071 if (nc
->caps
->legacy_of_bindings
) {
1074 if (!of_property_read_u32(nc
->dev
->of_node
, "atmel,pmecc-cap",
1076 chip
->ecc
.strength
= val
;
1078 if (!of_property_read_u32(nc
->dev
->of_node
,
1079 "atmel,pmecc-sector-size",
1081 chip
->ecc
.size
= val
;
1084 if (chip
->ecc
.options
& NAND_ECC_MAXIMIZE
)
1085 req
.ecc
.strength
= ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH
;
1086 else if (chip
->ecc
.strength
)
1087 req
.ecc
.strength
= chip
->ecc
.strength
;
1088 else if (chip
->ecc_strength_ds
)
1089 req
.ecc
.strength
= chip
->ecc_strength_ds
;
1091 req
.ecc
.strength
= ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH
;
1094 req
.ecc
.sectorsize
= chip
->ecc
.size
;
1095 else if (chip
->ecc_step_ds
)
1096 req
.ecc
.sectorsize
= chip
->ecc_step_ds
;
1098 req
.ecc
.sectorsize
= ATMEL_PMECC_SECTOR_SIZE_AUTO
;
1100 req
.pagesize
= mtd
->writesize
;
1101 req
.oobsize
= mtd
->oobsize
;
1103 if (mtd
->writesize
<= 512) {
1105 req
.ecc
.ooboffset
= 0;
1107 req
.ecc
.bytes
= mtd
->oobsize
- 2;
1108 req
.ecc
.ooboffset
= ATMEL_PMECC_OOBOFFSET_AUTO
;
1111 nand
->pmecc
= atmel_pmecc_create_user(nc
->pmecc
, &req
);
1112 if (IS_ERR(nand
->pmecc
))
1113 return PTR_ERR(nand
->pmecc
);
1115 chip
->ecc
.algo
= NAND_ECC_BCH
;
1116 chip
->ecc
.size
= req
.ecc
.sectorsize
;
1117 chip
->ecc
.bytes
= req
.ecc
.bytes
/ req
.ecc
.nsectors
;
1118 chip
->ecc
.strength
= req
.ecc
.strength
;
1120 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1122 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
1127 static int atmel_nand_ecc_init(struct atmel_nand
*nand
)
1129 struct nand_chip
*chip
= &nand
->base
;
1130 struct atmel_nand_controller
*nc
;
1133 nc
= to_nand_controller(chip
->controller
);
1135 switch (chip
->ecc
.mode
) {
1139 * Nothing to do, the core will initialize everything for us.
1144 ret
= atmel_nand_pmecc_init(chip
);
1148 chip
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
1149 chip
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
1150 chip
->ecc
.read_page_raw
= atmel_nand_pmecc_read_page_raw
;
1151 chip
->ecc
.write_page_raw
= atmel_nand_pmecc_write_page_raw
;
1155 /* Other modes are not supported. */
1156 dev_err(nc
->dev
, "Unsupported ECC mode: %d\n",
1164 static int atmel_hsmc_nand_ecc_init(struct atmel_nand
*nand
)
1166 struct nand_chip
*chip
= &nand
->base
;
1169 ret
= atmel_nand_ecc_init(nand
);
1173 if (chip
->ecc
.mode
!= NAND_ECC_HW
)
1176 /* Adjust the ECC operations for the HSMC IP. */
1177 chip
->ecc
.read_page
= atmel_hsmc_nand_pmecc_read_page
;
1178 chip
->ecc
.write_page
= atmel_hsmc_nand_pmecc_write_page
;
1179 chip
->ecc
.read_page_raw
= atmel_hsmc_nand_pmecc_read_page_raw
;
1180 chip
->ecc
.write_page_raw
= atmel_hsmc_nand_pmecc_write_page_raw
;
1181 chip
->ecc
.options
|= NAND_ECC_CUSTOM_PAGE_ACCESS
;
1186 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand
*nand
,
1187 const struct nand_data_interface
*conf
,
1188 struct atmel_smc_cs_conf
*smcconf
)
1190 u32 ncycles
, totalcycles
, timeps
, mckperiodps
;
1191 struct atmel_nand_controller
*nc
;
1194 nc
= to_nand_controller(nand
->base
.controller
);
1196 /* DDR interface not supported. */
1197 if (conf
->type
!= NAND_SDR_IFACE
)
1201 * tRC < 30ns implies EDO mode. This controller does not support this
1204 if (conf
->timings
.sdr
.tRC_min
< 30)
1207 atmel_smc_cs_conf_init(smcconf
);
1209 mckperiodps
= NSEC_PER_SEC
/ clk_get_rate(nc
->mck
);
1210 mckperiodps
*= 1000;
1213 * Set write pulse timing. This one is easy to extract:
1217 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tWP_min
, mckperiodps
);
1218 totalcycles
= ncycles
;
1219 ret
= atmel_smc_cs_conf_set_pulse(smcconf
, ATMEL_SMC_NWE_SHIFT
,
1225 * The write setup timing depends on the operation done on the NAND.
1226 * All operations goes through the same data bus, but the operation
1227 * type depends on the address we are writing to (ALE/CLE address
1229 * Since we have no way to differentiate the different operations at
1230 * the SMC level, we must consider the worst case (the biggest setup
1231 * time among all operation types):
1233 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1235 timeps
= max3(conf
->timings
.sdr
.tCLS_min
, conf
->timings
.sdr
.tCS_min
,
1236 conf
->timings
.sdr
.tALS_min
);
1237 timeps
= max(timeps
, conf
->timings
.sdr
.tDS_min
);
1238 ncycles
= DIV_ROUND_UP(timeps
, mckperiodps
);
1239 ncycles
= ncycles
> totalcycles
? ncycles
- totalcycles
: 0;
1240 totalcycles
+= ncycles
;
1241 ret
= atmel_smc_cs_conf_set_setup(smcconf
, ATMEL_SMC_NWE_SHIFT
,
1247 * As for the write setup timing, the write hold timing depends on the
1248 * operation done on the NAND:
1250 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1252 timeps
= max3(conf
->timings
.sdr
.tCLH_min
, conf
->timings
.sdr
.tCH_min
,
1253 conf
->timings
.sdr
.tALH_min
);
1254 timeps
= max3(timeps
, conf
->timings
.sdr
.tDH_min
,
1255 conf
->timings
.sdr
.tWH_min
);
1256 ncycles
= DIV_ROUND_UP(timeps
, mckperiodps
);
1257 totalcycles
+= ncycles
;
1260 * The write cycle timing is directly matching tWC, but is also
1261 * dependent on the other timings on the setup and hold timings we
1262 * calculated earlier, which gives:
1264 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1266 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tWC_min
, mckperiodps
);
1267 ncycles
= max(totalcycles
, ncycles
);
1268 ret
= atmel_smc_cs_conf_set_cycle(smcconf
, ATMEL_SMC_NWE_SHIFT
,
1274 * We don't want the CS line to be toggled between each byte/word
1275 * transfer to the NAND. The only way to guarantee that is to have the
1276 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1278 * NCS_WR_PULSE = NWE_CYCLE
1280 ret
= atmel_smc_cs_conf_set_pulse(smcconf
, ATMEL_SMC_NCS_WR_SHIFT
,
1286 * As for the write setup timing, the read hold timing depends on the
1287 * operation done on the NAND:
1289 * NRD_HOLD = max(tREH, tRHOH)
1291 timeps
= max(conf
->timings
.sdr
.tREH_min
, conf
->timings
.sdr
.tRHOH_min
);
1292 ncycles
= DIV_ROUND_UP(timeps
, mckperiodps
);
1293 totalcycles
= ncycles
;
1296 * TDF = tRHZ - NRD_HOLD
1298 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tRHZ_max
, mckperiodps
);
1299 ncycles
-= totalcycles
;
1302 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1303 * we might end up with a config that does not fit in the TDF field.
1304 * Just take the max value in this case and hope that the NAND is more
1305 * tolerant than advertised.
1307 if (ncycles
> ATMEL_SMC_MODE_TDF_MAX
)
1308 ncycles
= ATMEL_SMC_MODE_TDF_MAX
;
1309 else if (ncycles
< ATMEL_SMC_MODE_TDF_MIN
)
1310 ncycles
= ATMEL_SMC_MODE_TDF_MIN
;
1312 smcconf
->mode
|= ATMEL_SMC_MODE_TDF(ncycles
) |
1313 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED
;
1316 * Read pulse timing directly matches tRP:
1320 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tRP_min
, mckperiodps
);
1321 totalcycles
+= ncycles
;
1322 ret
= atmel_smc_cs_conf_set_pulse(smcconf
, ATMEL_SMC_NRD_SHIFT
,
1328 * The write cycle timing is directly matching tWC, but is also
1329 * dependent on the setup and hold timings we calculated earlier,
1332 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1334 * NRD_SETUP is always 0.
1336 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tRC_min
, mckperiodps
);
1337 ncycles
= max(totalcycles
, ncycles
);
1338 ret
= atmel_smc_cs_conf_set_cycle(smcconf
, ATMEL_SMC_NRD_SHIFT
,
1344 * We don't want the CS line to be toggled between each byte/word
1345 * transfer from the NAND. The only way to guarantee that is to have
1346 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1348 * NCS_RD_PULSE = NRD_CYCLE
1350 ret
= atmel_smc_cs_conf_set_pulse(smcconf
, ATMEL_SMC_NCS_RD_SHIFT
,
1355 /* Txxx timings are directly matching tXXX ones. */
1356 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tCLR_min
, mckperiodps
);
1357 ret
= atmel_smc_cs_conf_set_timing(smcconf
,
1358 ATMEL_HSMC_TIMINGS_TCLR_SHIFT
,
1363 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tADL_min
, mckperiodps
);
1364 ret
= atmel_smc_cs_conf_set_timing(smcconf
,
1365 ATMEL_HSMC_TIMINGS_TADL_SHIFT
,
1370 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tAR_min
, mckperiodps
);
1371 ret
= atmel_smc_cs_conf_set_timing(smcconf
,
1372 ATMEL_HSMC_TIMINGS_TAR_SHIFT
,
1377 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tRR_min
, mckperiodps
);
1378 ret
= atmel_smc_cs_conf_set_timing(smcconf
,
1379 ATMEL_HSMC_TIMINGS_TRR_SHIFT
,
1384 ncycles
= DIV_ROUND_UP(conf
->timings
.sdr
.tWB_max
, mckperiodps
);
1385 ret
= atmel_smc_cs_conf_set_timing(smcconf
,
1386 ATMEL_HSMC_TIMINGS_TWB_SHIFT
,
1391 /* Attach the CS line to the NFC logic. */
1392 smcconf
->timings
|= ATMEL_HSMC_TIMINGS_NFSEL
;
1394 /* Set the appropriate data bus width. */
1395 if (nand
->base
.options
& NAND_BUSWIDTH_16
)
1396 smcconf
->mode
|= ATMEL_SMC_MODE_DBW_16
;
1398 /* Operate in NRD/NWE READ/WRITEMODE. */
1399 smcconf
->mode
|= ATMEL_SMC_MODE_READMODE_NRD
|
1400 ATMEL_SMC_MODE_WRITEMODE_NWE
;
1405 static int atmel_smc_nand_setup_data_interface(struct atmel_nand
*nand
,
1407 const struct nand_data_interface
*conf
)
1409 struct atmel_nand_controller
*nc
;
1410 struct atmel_smc_cs_conf smcconf
;
1411 struct atmel_nand_cs
*cs
;
1414 nc
= to_nand_controller(nand
->base
.controller
);
1416 ret
= atmel_smc_nand_prepare_smcconf(nand
, conf
, &smcconf
);
1420 if (csline
== NAND_DATA_IFACE_CHECK_ONLY
)
1423 cs
= &nand
->cs
[csline
];
1424 cs
->smcconf
= smcconf
;
1425 atmel_smc_cs_conf_apply(nc
->smc
, cs
->id
, &cs
->smcconf
);
1430 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand
*nand
,
1432 const struct nand_data_interface
*conf
)
1434 struct atmel_nand_controller
*nc
;
1435 struct atmel_smc_cs_conf smcconf
;
1436 struct atmel_nand_cs
*cs
;
1439 nc
= to_nand_controller(nand
->base
.controller
);
1441 ret
= atmel_smc_nand_prepare_smcconf(nand
, conf
, &smcconf
);
1445 if (csline
== NAND_DATA_IFACE_CHECK_ONLY
)
1448 cs
= &nand
->cs
[csline
];
1449 cs
->smcconf
= smcconf
;
1451 if (cs
->rb
.type
== ATMEL_NAND_NATIVE_RB
)
1452 cs
->smcconf
.timings
|= ATMEL_HSMC_TIMINGS_RBNSEL(cs
->rb
.id
);
1454 atmel_hsmc_cs_conf_apply(nc
->smc
, cs
->id
, &cs
->smcconf
);
1459 static int atmel_nand_setup_data_interface(struct mtd_info
*mtd
, int csline
,
1460 const struct nand_data_interface
*conf
)
1462 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1463 struct atmel_nand
*nand
= to_atmel_nand(chip
);
1464 struct atmel_nand_controller
*nc
;
1466 nc
= to_nand_controller(nand
->base
.controller
);
1468 if (csline
>= nand
->numcs
||
1469 (csline
< 0 && csline
!= NAND_DATA_IFACE_CHECK_ONLY
))
1472 return nc
->caps
->ops
->setup_data_interface(nand
, csline
, conf
);
1475 static void atmel_nand_init(struct atmel_nand_controller
*nc
,
1476 struct atmel_nand
*nand
)
1478 struct nand_chip
*chip
= &nand
->base
;
1479 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1481 mtd
->dev
.parent
= nc
->dev
;
1482 nand
->base
.controller
= &nc
->base
;
1484 chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
1485 chip
->read_byte
= atmel_nand_read_byte
;
1486 chip
->read_word
= atmel_nand_read_word
;
1487 chip
->write_byte
= atmel_nand_write_byte
;
1488 chip
->read_buf
= atmel_nand_read_buf
;
1489 chip
->write_buf
= atmel_nand_write_buf
;
1490 chip
->select_chip
= atmel_nand_select_chip
;
1492 if (nc
->mck
&& nc
->caps
->ops
->setup_data_interface
)
1493 chip
->setup_data_interface
= atmel_nand_setup_data_interface
;
1495 /* Some NANDs require a longer delay than the default one (20us). */
1496 chip
->chip_delay
= 40;
1499 * Use a bounce buffer when the buffer passed by the MTD user is not
1503 chip
->options
|= NAND_USE_BOUNCE_BUFFER
;
1505 /* Default to HW ECC if pmecc is available. */
1507 chip
->ecc
.mode
= NAND_ECC_HW
;
1510 static void atmel_smc_nand_init(struct atmel_nand_controller
*nc
,
1511 struct atmel_nand
*nand
)
1513 struct nand_chip
*chip
= &nand
->base
;
1514 struct atmel_smc_nand_controller
*smc_nc
;
1517 atmel_nand_init(nc
, nand
);
1519 smc_nc
= to_smc_nand_controller(chip
->controller
);
1520 if (!smc_nc
->matrix
)
1523 /* Attach the CS to the NAND Flash logic. */
1524 for (i
= 0; i
< nand
->numcs
; i
++)
1525 regmap_update_bits(smc_nc
->matrix
, smc_nc
->ebi_csa_offs
,
1526 BIT(nand
->cs
[i
].id
), BIT(nand
->cs
[i
].id
));
1529 static void atmel_hsmc_nand_init(struct atmel_nand_controller
*nc
,
1530 struct atmel_nand
*nand
)
1532 struct nand_chip
*chip
= &nand
->base
;
1534 atmel_nand_init(nc
, nand
);
1536 /* Overload some methods for the HSMC controller. */
1537 chip
->cmd_ctrl
= atmel_hsmc_nand_cmd_ctrl
;
1538 chip
->select_chip
= atmel_hsmc_nand_select_chip
;
1541 static int atmel_nand_detect(struct atmel_nand
*nand
)
1543 struct nand_chip
*chip
= &nand
->base
;
1544 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1545 struct atmel_nand_controller
*nc
;
1548 nc
= to_nand_controller(chip
->controller
);
1550 ret
= nand_scan_ident(mtd
, nand
->numcs
, NULL
);
1552 dev_err(nc
->dev
, "nand_scan_ident() failed: %d\n", ret
);
1557 static int atmel_nand_unregister(struct atmel_nand
*nand
)
1559 struct nand_chip
*chip
= &nand
->base
;
1560 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1563 ret
= mtd_device_unregister(mtd
);
1568 list_del(&nand
->node
);
1573 static int atmel_nand_register(struct atmel_nand
*nand
)
1575 struct nand_chip
*chip
= &nand
->base
;
1576 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1577 struct atmel_nand_controller
*nc
;
1580 nc
= to_nand_controller(chip
->controller
);
1582 if (nc
->caps
->legacy_of_bindings
|| !nc
->dev
->of_node
) {
1584 * We keep the MTD name unchanged to avoid breaking platforms
1585 * where the MTD cmdline parser is used and the bootloader
1586 * has not been updated to use the new naming scheme.
1588 mtd
->name
= "atmel_nand";
1589 } else if (!mtd
->name
) {
1591 * If the new bindings are used and the bootloader has not been
1592 * updated to pass a new mtdparts parameter on the cmdline, you
1593 * should define the following property in your nand node:
1595 * label = "atmel_nand";
1597 * This way, mtd->name will be set by the core when
1598 * nand_set_flash_node() is called.
1600 mtd
->name
= devm_kasprintf(nc
->dev
, GFP_KERNEL
,
1601 "%s:nand.%d", dev_name(nc
->dev
),
1604 dev_err(nc
->dev
, "Failed to allocate mtd->name\n");
1609 ret
= nand_scan_tail(mtd
);
1611 dev_err(nc
->dev
, "nand_scan_tail() failed: %d\n", ret
);
1615 ret
= mtd_device_register(mtd
, NULL
, 0);
1617 dev_err(nc
->dev
, "Failed to register mtd device: %d\n", ret
);
1622 list_add_tail(&nand
->node
, &nc
->chips
);
1627 static struct atmel_nand
*atmel_nand_create(struct atmel_nand_controller
*nc
,
1628 struct device_node
*np
,
1631 struct atmel_nand
*nand
;
1632 struct gpio_desc
*gpio
;
1635 numcs
= of_property_count_elems_of_size(np
, "reg",
1636 reg_cells
* sizeof(u32
));
1638 dev_err(nc
->dev
, "Missing or invalid reg property\n");
1639 return ERR_PTR(-EINVAL
);
1642 nand
= devm_kzalloc(nc
->dev
,
1643 sizeof(*nand
) + (numcs
* sizeof(*nand
->cs
)),
1646 dev_err(nc
->dev
, "Failed to allocate NAND object\n");
1647 return ERR_PTR(-ENOMEM
);
1650 nand
->numcs
= numcs
;
1652 gpio
= devm_fwnode_get_index_gpiod_from_child(nc
->dev
, "det", 0,
1653 &np
->fwnode
, GPIOD_IN
,
1655 if (IS_ERR(gpio
) && PTR_ERR(gpio
) != -ENOENT
) {
1657 "Failed to get detect gpio (err = %ld)\n",
1659 return ERR_CAST(gpio
);
1663 nand
->cdgpio
= gpio
;
1665 for (i
= 0; i
< numcs
; i
++) {
1666 struct resource res
;
1669 ret
= of_address_to_resource(np
, 0, &res
);
1671 dev_err(nc
->dev
, "Invalid reg property (err = %d)\n",
1673 return ERR_PTR(ret
);
1676 ret
= of_property_read_u32_index(np
, "reg", i
* reg_cells
,
1679 dev_err(nc
->dev
, "Invalid reg property (err = %d)\n",
1681 return ERR_PTR(ret
);
1684 nand
->cs
[i
].id
= val
;
1686 nand
->cs
[i
].io
.dma
= res
.start
;
1687 nand
->cs
[i
].io
.virt
= devm_ioremap_resource(nc
->dev
, &res
);
1688 if (IS_ERR(nand
->cs
[i
].io
.virt
))
1689 return ERR_CAST(nand
->cs
[i
].io
.virt
);
1691 if (!of_property_read_u32(np
, "atmel,rb", &val
)) {
1692 if (val
> ATMEL_NFC_MAX_RB_ID
)
1693 return ERR_PTR(-EINVAL
);
1695 nand
->cs
[i
].rb
.type
= ATMEL_NAND_NATIVE_RB
;
1696 nand
->cs
[i
].rb
.id
= val
;
1698 gpio
= devm_fwnode_get_index_gpiod_from_child(nc
->dev
,
1699 "rb", i
, &np
->fwnode
,
1700 GPIOD_IN
, "nand-rb");
1701 if (IS_ERR(gpio
) && PTR_ERR(gpio
) != -ENOENT
) {
1703 "Failed to get R/B gpio (err = %ld)\n",
1705 return ERR_CAST(gpio
);
1708 if (!IS_ERR(gpio
)) {
1709 nand
->cs
[i
].rb
.type
= ATMEL_NAND_GPIO_RB
;
1710 nand
->cs
[i
].rb
.gpio
= gpio
;
1714 gpio
= devm_fwnode_get_index_gpiod_from_child(nc
->dev
, "cs",
1718 if (IS_ERR(gpio
) && PTR_ERR(gpio
) != -ENOENT
) {
1720 "Failed to get CS gpio (err = %ld)\n",
1722 return ERR_CAST(gpio
);
1726 nand
->cs
[i
].csgpio
= gpio
;
1729 nand_set_flash_node(&nand
->base
, np
);
1735 atmel_nand_controller_add_nand(struct atmel_nand_controller
*nc
,
1736 struct atmel_nand
*nand
)
1740 /* No card inserted, skip this NAND. */
1741 if (nand
->cdgpio
&& gpiod_get_value(nand
->cdgpio
)) {
1742 dev_info(nc
->dev
, "No SmartMedia card inserted.\n");
1746 nc
->caps
->ops
->nand_init(nc
, nand
);
1748 ret
= atmel_nand_detect(nand
);
1752 ret
= nc
->caps
->ops
->ecc_init(nand
);
1756 return atmel_nand_register(nand
);
1760 atmel_nand_controller_remove_nands(struct atmel_nand_controller
*nc
)
1762 struct atmel_nand
*nand
, *tmp
;
1765 list_for_each_entry_safe(nand
, tmp
, &nc
->chips
, node
) {
1766 ret
= atmel_nand_unregister(nand
);
1775 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller
*nc
)
1777 struct device
*dev
= nc
->dev
;
1778 struct platform_device
*pdev
= to_platform_device(dev
);
1779 struct atmel_nand
*nand
;
1780 struct gpio_desc
*gpio
;
1781 struct resource
*res
;
1784 * Legacy bindings only allow connecting a single NAND with a unique CS
1785 * line to the controller.
1787 nand
= devm_kzalloc(nc
->dev
, sizeof(*nand
) + sizeof(*nand
->cs
),
1794 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1795 nand
->cs
[0].io
.virt
= devm_ioremap_resource(dev
, res
);
1796 if (IS_ERR(nand
->cs
[0].io
.virt
))
1797 return PTR_ERR(nand
->cs
[0].io
.virt
);
1799 nand
->cs
[0].io
.dma
= res
->start
;
1802 * The old driver was hardcoding the CS id to 3 for all sama5
1803 * controllers. Since this id is only meaningful for the sama5
1804 * controller we can safely assign this id to 3 no matter the
1806 * If one wants to connect a NAND to a different CS line, he will
1807 * have to use the new bindings.
1812 gpio
= devm_gpiod_get_index_optional(dev
, NULL
, 0, GPIOD_IN
);
1814 dev_err(dev
, "Failed to get R/B gpio (err = %ld)\n",
1816 return PTR_ERR(gpio
);
1820 nand
->cs
[0].rb
.type
= ATMEL_NAND_GPIO_RB
;
1821 nand
->cs
[0].rb
.gpio
= gpio
;
1825 gpio
= devm_gpiod_get_index_optional(dev
, NULL
, 1, GPIOD_OUT_HIGH
);
1827 dev_err(dev
, "Failed to get CS gpio (err = %ld)\n",
1829 return PTR_ERR(gpio
);
1832 nand
->cs
[0].csgpio
= gpio
;
1834 /* Card detect GPIO. */
1835 gpio
= devm_gpiod_get_index_optional(nc
->dev
, NULL
, 2, GPIOD_IN
);
1838 "Failed to get detect gpio (err = %ld)\n",
1840 return PTR_ERR(gpio
);
1843 nand
->cdgpio
= gpio
;
1845 nand_set_flash_node(&nand
->base
, nc
->dev
->of_node
);
1847 return atmel_nand_controller_add_nand(nc
, nand
);
1850 static int atmel_nand_controller_add_nands(struct atmel_nand_controller
*nc
)
1852 struct device_node
*np
, *nand_np
;
1853 struct device
*dev
= nc
->dev
;
1857 /* We do not retrieve the SMC syscon when parsing old DTs. */
1858 if (nc
->caps
->legacy_of_bindings
)
1859 return atmel_nand_controller_legacy_add_nands(nc
);
1863 ret
= of_property_read_u32(np
, "#address-cells", &val
);
1865 dev_err(dev
, "missing #address-cells property\n");
1871 ret
= of_property_read_u32(np
, "#size-cells", &val
);
1873 dev_err(dev
, "missing #address-cells property\n");
1879 for_each_child_of_node(np
, nand_np
) {
1880 struct atmel_nand
*nand
;
1882 nand
= atmel_nand_create(nc
, nand_np
, reg_cells
);
1884 ret
= PTR_ERR(nand
);
1888 ret
= atmel_nand_controller_add_nand(nc
, nand
);
1896 atmel_nand_controller_remove_nands(nc
);
1901 static void atmel_nand_controller_cleanup(struct atmel_nand_controller
*nc
)
1904 dma_release_channel(nc
->dmac
);
1909 static const struct of_device_id atmel_matrix_of_ids
[] = {
1911 .compatible
= "atmel,at91sam9260-matrix",
1912 .data
= (void *)AT91SAM9260_MATRIX_EBICSA
,
1915 .compatible
= "atmel,at91sam9261-matrix",
1916 .data
= (void *)AT91SAM9261_MATRIX_EBICSA
,
1919 .compatible
= "atmel,at91sam9263-matrix",
1920 .data
= (void *)AT91SAM9263_MATRIX_EBI0CSA
,
1923 .compatible
= "atmel,at91sam9rl-matrix",
1924 .data
= (void *)AT91SAM9RL_MATRIX_EBICSA
,
1927 .compatible
= "atmel,at91sam9g45-matrix",
1928 .data
= (void *)AT91SAM9G45_MATRIX_EBICSA
,
1931 .compatible
= "atmel,at91sam9n12-matrix",
1932 .data
= (void *)AT91SAM9N12_MATRIX_EBICSA
,
1935 .compatible
= "atmel,at91sam9x5-matrix",
1936 .data
= (void *)AT91SAM9X5_MATRIX_EBICSA
,
1941 static int atmel_nand_controller_init(struct atmel_nand_controller
*nc
,
1942 struct platform_device
*pdev
,
1943 const struct atmel_nand_controller_caps
*caps
)
1945 struct device
*dev
= &pdev
->dev
;
1946 struct device_node
*np
= dev
->of_node
;
1949 nand_hw_control_init(&nc
->base
);
1950 INIT_LIST_HEAD(&nc
->chips
);
1954 platform_set_drvdata(pdev
, nc
);
1956 nc
->pmecc
= devm_atmel_pmecc_get(dev
);
1957 if (IS_ERR(nc
->pmecc
)) {
1958 ret
= PTR_ERR(nc
->pmecc
);
1959 if (ret
!= -EPROBE_DEFER
)
1960 dev_err(dev
, "Could not get PMECC object (err = %d)\n",
1965 if (nc
->caps
->has_dma
) {
1966 dma_cap_mask_t mask
;
1969 dma_cap_set(DMA_MEMCPY
, mask
);
1971 nc
->dmac
= dma_request_channel(mask
, NULL
, NULL
);
1973 dev_err(nc
->dev
, "Failed to request DMA channel\n");
1976 /* We do not retrieve the SMC syscon when parsing old DTs. */
1977 if (nc
->caps
->legacy_of_bindings
)
1980 nc
->mck
= of_clk_get(dev
->parent
->of_node
, 0);
1981 if (IS_ERR(nc
->mck
)) {
1982 dev_err(dev
, "Failed to retrieve MCK clk\n");
1983 return PTR_ERR(nc
->mck
);
1986 np
= of_parse_phandle(dev
->parent
->of_node
, "atmel,smc", 0);
1988 dev_err(dev
, "Missing or invalid atmel,smc property\n");
1992 nc
->smc
= syscon_node_to_regmap(np
);
1994 if (IS_ERR(nc
->smc
)) {
1995 ret
= PTR_ERR(nc
->smc
);
1996 dev_err(dev
, "Could not get SMC regmap (err = %d)\n", ret
);
2004 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller
*nc
)
2006 struct device
*dev
= nc
->base
.dev
;
2007 const struct of_device_id
*match
;
2008 struct device_node
*np
;
2011 /* We do not retrieve the matrix syscon when parsing old DTs. */
2012 if (nc
->base
.caps
->legacy_of_bindings
)
2015 np
= of_parse_phandle(dev
->parent
->of_node
, "atmel,matrix", 0);
2019 match
= of_match_node(atmel_matrix_of_ids
, np
);
2025 nc
->matrix
= syscon_node_to_regmap(np
);
2027 if (IS_ERR(nc
->matrix
)) {
2028 ret
= PTR_ERR(nc
->matrix
);
2029 dev_err(dev
, "Could not get Matrix regmap (err = %d)\n", ret
);
2033 nc
->ebi_csa_offs
= (unsigned int)match
->data
;
2036 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2037 * add 4 to ->ebi_csa_offs.
2039 if (of_device_is_compatible(dev
->parent
->of_node
,
2040 "atmel,at91sam9263-ebi1"))
2041 nc
->ebi_csa_offs
+= 4;
2047 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller
*nc
)
2049 struct regmap_config regmap_conf
= {
2055 struct device
*dev
= nc
->base
.dev
;
2056 struct device_node
*nand_np
, *nfc_np
;
2057 void __iomem
*iomem
;
2058 struct resource res
;
2061 nand_np
= dev
->of_node
;
2062 nfc_np
= of_find_compatible_node(dev
->of_node
, NULL
,
2063 "atmel,sama5d3-nfc");
2065 nc
->clk
= of_clk_get(nfc_np
, 0);
2066 if (IS_ERR(nc
->clk
)) {
2067 ret
= PTR_ERR(nc
->clk
);
2068 dev_err(dev
, "Failed to retrieve HSMC clock (err = %d)\n",
2073 ret
= clk_prepare_enable(nc
->clk
);
2075 dev_err(dev
, "Failed to enable the HSMC clock (err = %d)\n",
2080 nc
->irq
= of_irq_get(nand_np
, 0);
2083 if (ret
!= -EPROBE_DEFER
)
2084 dev_err(dev
, "Failed to get IRQ number (err = %d)\n",
2089 ret
= of_address_to_resource(nfc_np
, 0, &res
);
2091 dev_err(dev
, "Invalid or missing NFC IO resource (err = %d)\n",
2096 iomem
= devm_ioremap_resource(dev
, &res
);
2097 if (IS_ERR(iomem
)) {
2098 ret
= PTR_ERR(iomem
);
2102 regmap_conf
.name
= "nfc-io";
2103 regmap_conf
.max_register
= resource_size(&res
) - 4;
2104 nc
->io
= devm_regmap_init_mmio(dev
, iomem
, ®map_conf
);
2105 if (IS_ERR(nc
->io
)) {
2106 ret
= PTR_ERR(nc
->io
);
2107 dev_err(dev
, "Could not create NFC IO regmap (err = %d)\n",
2112 ret
= of_address_to_resource(nfc_np
, 1, &res
);
2114 dev_err(dev
, "Invalid or missing HSMC resource (err = %d)\n",
2119 iomem
= devm_ioremap_resource(dev
, &res
);
2120 if (IS_ERR(iomem
)) {
2121 ret
= PTR_ERR(iomem
);
2125 regmap_conf
.name
= "smc";
2126 regmap_conf
.max_register
= resource_size(&res
) - 4;
2127 nc
->base
.smc
= devm_regmap_init_mmio(dev
, iomem
, ®map_conf
);
2128 if (IS_ERR(nc
->base
.smc
)) {
2129 ret
= PTR_ERR(nc
->base
.smc
);
2130 dev_err(dev
, "Could not create NFC IO regmap (err = %d)\n",
2135 ret
= of_address_to_resource(nfc_np
, 2, &res
);
2137 dev_err(dev
, "Invalid or missing SRAM resource (err = %d)\n",
2142 nc
->sram
.virt
= devm_ioremap_resource(dev
, &res
);
2143 if (IS_ERR(nc
->sram
.virt
)) {
2144 ret
= PTR_ERR(nc
->sram
.virt
);
2148 nc
->sram
.dma
= res
.start
;
2151 of_node_put(nfc_np
);
2157 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller
*nc
)
2159 struct device
*dev
= nc
->base
.dev
;
2160 struct device_node
*np
;
2163 np
= of_parse_phandle(dev
->parent
->of_node
, "atmel,smc", 0);
2165 dev_err(dev
, "Missing or invalid atmel,smc property\n");
2169 nc
->irq
= of_irq_get(np
, 0);
2172 if (nc
->irq
!= -EPROBE_DEFER
)
2173 dev_err(dev
, "Failed to get IRQ number (err = %d)\n",
2178 np
= of_parse_phandle(dev
->of_node
, "atmel,nfc-io", 0);
2180 dev_err(dev
, "Missing or invalid atmel,nfc-io property\n");
2184 nc
->io
= syscon_node_to_regmap(np
);
2186 if (IS_ERR(nc
->io
)) {
2187 ret
= PTR_ERR(nc
->io
);
2188 dev_err(dev
, "Could not get NFC IO regmap (err = %d)\n", ret
);
2192 nc
->sram
.pool
= of_gen_pool_get(nc
->base
.dev
->of_node
,
2193 "atmel,nfc-sram", 0);
2194 if (!nc
->sram
.pool
) {
2195 dev_err(nc
->base
.dev
, "Missing SRAM\n");
2199 nc
->sram
.virt
= gen_pool_dma_alloc(nc
->sram
.pool
,
2200 ATMEL_NFC_SRAM_SIZE
,
2202 if (!nc
->sram
.virt
) {
2203 dev_err(nc
->base
.dev
,
2204 "Could not allocate memory from the NFC SRAM pool\n");
2212 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller
*nc
)
2214 struct atmel_hsmc_nand_controller
*hsmc_nc
;
2217 ret
= atmel_nand_controller_remove_nands(nc
);
2221 hsmc_nc
= container_of(nc
, struct atmel_hsmc_nand_controller
, base
);
2222 if (hsmc_nc
->sram
.pool
)
2223 gen_pool_free(hsmc_nc
->sram
.pool
,
2224 (unsigned long)hsmc_nc
->sram
.virt
,
2225 ATMEL_NFC_SRAM_SIZE
);
2228 clk_disable_unprepare(hsmc_nc
->clk
);
2229 clk_put(hsmc_nc
->clk
);
2232 atmel_nand_controller_cleanup(nc
);
2237 static int atmel_hsmc_nand_controller_probe(struct platform_device
*pdev
,
2238 const struct atmel_nand_controller_caps
*caps
)
2240 struct device
*dev
= &pdev
->dev
;
2241 struct atmel_hsmc_nand_controller
*nc
;
2244 nc
= devm_kzalloc(dev
, sizeof(*nc
), GFP_KERNEL
);
2248 ret
= atmel_nand_controller_init(&nc
->base
, pdev
, caps
);
2252 if (caps
->legacy_of_bindings
)
2253 ret
= atmel_hsmc_nand_controller_legacy_init(nc
);
2255 ret
= atmel_hsmc_nand_controller_init(nc
);
2260 /* Make sure all irqs are masked before registering our IRQ handler. */
2261 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_IDR
, 0xffffffff);
2262 ret
= devm_request_irq(dev
, nc
->irq
, atmel_nfc_interrupt
,
2263 IRQF_SHARED
, "nfc", nc
);
2266 "Could not get register NFC interrupt handler (err = %d)\n",
2271 /* Initial NFC configuration. */
2272 regmap_write(nc
->base
.smc
, ATMEL_HSMC_NFC_CFG
,
2273 ATMEL_HSMC_NFC_CFG_DTO_MAX
);
2275 ret
= atmel_nand_controller_add_nands(&nc
->base
);
2282 atmel_hsmc_nand_controller_remove(&nc
->base
);
2287 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops
= {
2288 .probe
= atmel_hsmc_nand_controller_probe
,
2289 .remove
= atmel_hsmc_nand_controller_remove
,
2290 .ecc_init
= atmel_hsmc_nand_ecc_init
,
2291 .nand_init
= atmel_hsmc_nand_init
,
2292 .setup_data_interface
= atmel_hsmc_nand_setup_data_interface
,
2295 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps
= {
2297 .ale_offs
= BIT(21),
2298 .cle_offs
= BIT(22),
2299 .ops
= &atmel_hsmc_nc_ops
,
2302 /* Only used to parse old bindings. */
2303 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps
= {
2305 .ale_offs
= BIT(21),
2306 .cle_offs
= BIT(22),
2307 .ops
= &atmel_hsmc_nc_ops
,
2308 .legacy_of_bindings
= true,
2311 static int atmel_smc_nand_controller_probe(struct platform_device
*pdev
,
2312 const struct atmel_nand_controller_caps
*caps
)
2314 struct device
*dev
= &pdev
->dev
;
2315 struct atmel_smc_nand_controller
*nc
;
2318 nc
= devm_kzalloc(dev
, sizeof(*nc
), GFP_KERNEL
);
2322 ret
= atmel_nand_controller_init(&nc
->base
, pdev
, caps
);
2326 ret
= atmel_smc_nand_controller_init(nc
);
2330 return atmel_nand_controller_add_nands(&nc
->base
);
2334 atmel_smc_nand_controller_remove(struct atmel_nand_controller
*nc
)
2338 ret
= atmel_nand_controller_remove_nands(nc
);
2342 atmel_nand_controller_cleanup(nc
);
2348 * The SMC reg layout of at91rm9200 is completely different which prevents us
2349 * from re-using atmel_smc_nand_setup_data_interface() for the
2350 * ->setup_data_interface() hook.
2351 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2352 * ->setup_data_interface() unassigned.
2354 static const struct atmel_nand_controller_ops at91rm9200_nc_ops
= {
2355 .probe
= atmel_smc_nand_controller_probe
,
2356 .remove
= atmel_smc_nand_controller_remove
,
2357 .ecc_init
= atmel_nand_ecc_init
,
2358 .nand_init
= atmel_smc_nand_init
,
2361 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps
= {
2362 .ale_offs
= BIT(21),
2363 .cle_offs
= BIT(22),
2364 .ops
= &at91rm9200_nc_ops
,
2367 static const struct atmel_nand_controller_ops atmel_smc_nc_ops
= {
2368 .probe
= atmel_smc_nand_controller_probe
,
2369 .remove
= atmel_smc_nand_controller_remove
,
2370 .ecc_init
= atmel_nand_ecc_init
,
2371 .nand_init
= atmel_smc_nand_init
,
2372 .setup_data_interface
= atmel_smc_nand_setup_data_interface
,
2375 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps
= {
2376 .ale_offs
= BIT(21),
2377 .cle_offs
= BIT(22),
2378 .ops
= &atmel_smc_nc_ops
,
2381 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps
= {
2382 .ale_offs
= BIT(22),
2383 .cle_offs
= BIT(21),
2384 .ops
= &atmel_smc_nc_ops
,
2387 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps
= {
2389 .ale_offs
= BIT(21),
2390 .cle_offs
= BIT(22),
2391 .ops
= &atmel_smc_nc_ops
,
2394 /* Only used to parse old bindings. */
2395 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps
= {
2396 .ale_offs
= BIT(21),
2397 .cle_offs
= BIT(22),
2398 .ops
= &atmel_smc_nc_ops
,
2399 .legacy_of_bindings
= true,
2402 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps
= {
2403 .ale_offs
= BIT(22),
2404 .cle_offs
= BIT(21),
2405 .ops
= &atmel_smc_nc_ops
,
2406 .legacy_of_bindings
= true,
2409 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps
= {
2411 .ale_offs
= BIT(21),
2412 .cle_offs
= BIT(22),
2413 .ops
= &atmel_smc_nc_ops
,
2414 .legacy_of_bindings
= true,
2417 static const struct of_device_id atmel_nand_controller_of_ids
[] = {
2419 .compatible
= "atmel,at91rm9200-nand-controller",
2420 .data
= &atmel_rm9200_nc_caps
,
2423 .compatible
= "atmel,at91sam9260-nand-controller",
2424 .data
= &atmel_sam9260_nc_caps
,
2427 .compatible
= "atmel,at91sam9261-nand-controller",
2428 .data
= &atmel_sam9261_nc_caps
,
2431 .compatible
= "atmel,at91sam9g45-nand-controller",
2432 .data
= &atmel_sam9g45_nc_caps
,
2435 .compatible
= "atmel,sama5d3-nand-controller",
2436 .data
= &atmel_sama5_nc_caps
,
2438 /* Support for old/deprecated bindings: */
2440 .compatible
= "atmel,at91rm9200-nand",
2441 .data
= &atmel_rm9200_nand_caps
,
2444 .compatible
= "atmel,sama5d4-nand",
2445 .data
= &atmel_rm9200_nand_caps
,
2448 .compatible
= "atmel,sama5d2-nand",
2449 .data
= &atmel_rm9200_nand_caps
,
2453 MODULE_DEVICE_TABLE(of
, atmel_nand_controller_of_ids
);
2455 static int atmel_nand_controller_probe(struct platform_device
*pdev
)
2457 const struct atmel_nand_controller_caps
*caps
;
2460 caps
= (void *)pdev
->id_entry
->driver_data
;
2462 caps
= of_device_get_match_data(&pdev
->dev
);
2465 dev_err(&pdev
->dev
, "Could not retrieve NFC caps\n");
2469 if (caps
->legacy_of_bindings
) {
2473 * If we are parsing legacy DT props and the DT contains a
2474 * valid NFC node, forward the request to the sama5 logic.
2476 if (of_find_compatible_node(pdev
->dev
.of_node
, NULL
,
2477 "atmel,sama5d3-nfc"))
2478 caps
= &atmel_sama5_nand_caps
;
2481 * Even if the compatible says we are dealing with an
2482 * at91rm9200 controller, the atmel,nand-has-dma specify that
2483 * this controller supports DMA, which means we are in fact
2484 * dealing with an at91sam9g45+ controller.
2486 if (!caps
->has_dma
&&
2487 of_property_read_bool(pdev
->dev
.of_node
,
2488 "atmel,nand-has-dma"))
2489 caps
= &atmel_sam9g45_nand_caps
;
2492 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2493 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2494 * actually dealing with an at91sam9261 controller.
2496 of_property_read_u32(pdev
->dev
.of_node
,
2497 "atmel,nand-addr-offset", &ale_offs
);
2499 caps
= &atmel_sam9261_nand_caps
;
2502 return caps
->ops
->probe(pdev
, caps
);
2505 static int atmel_nand_controller_remove(struct platform_device
*pdev
)
2507 struct atmel_nand_controller
*nc
= platform_get_drvdata(pdev
);
2509 return nc
->caps
->ops
->remove(nc
);
2512 static __maybe_unused
int atmel_nand_controller_resume(struct device
*dev
)
2514 struct atmel_nand_controller
*nc
= dev_get_drvdata(dev
);
2515 struct atmel_nand
*nand
;
2517 list_for_each_entry(nand
, &nc
->chips
, node
) {
2520 for (i
= 0; i
< nand
->numcs
; i
++)
2521 nand_reset(&nand
->base
, i
);
2527 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops
, NULL
,
2528 atmel_nand_controller_resume
);
2530 static struct platform_driver atmel_nand_controller_driver
= {
2532 .name
= "atmel-nand-controller",
2533 .of_match_table
= of_match_ptr(atmel_nand_controller_of_ids
),
2535 .probe
= atmel_nand_controller_probe
,
2536 .remove
= atmel_nand_controller_remove
,
2538 module_platform_driver(atmel_nand_controller_driver
);
2540 MODULE_LICENSE("GPL");
2541 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2542 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2543 MODULE_ALIAS("platform:atmel-nand-controller");